Evaluation element, evaluation element set

Abstract

To obtain an evaluation element that can grasp the state of defects in the formation of the column layer. [Solution] The column layer 12 is formed by connecting p layers 12A to 12E in the depth direction. In this evaluation element T1, in a separate region in a plan view from the column layer 12, p layers (first evaluation individual diffusion region) 22B to 22E and p layers (second evaluation individual diffusion region) 23B to 23E are formed, similar to the aforementioned p layers 12B to 12E, and a p-type connecting layer 24 is formed that connects p layers 22B and 23B on their underside, corresponding to the aforementioned p layer 12A. The same applies to evaluation elements T2 to T4. Therefore, the positional relationship and size relationship of the p layers 12A to 12E constituting the column layer 12 can be indirectly investigated by the resistance values ​​of the above elements T1 to T4.

Description

Technical Field

[0001] The present disclosure relates to an evaluation element used for evaluating a semiconductor device in which an impurity distribution extending in the depth direction is formed, and a set of evaluation elements that is a combination of a plurality of such evaluation elements.

Background Art

[0002] As a structure for increasing the breakdown voltage of a vertical MOSFET used as a power semiconductor device, for example, a super junction structure as described in Patent Document 1 is known. In this structure, columnar layers (column layers: columnar semiconductor regions) of the conductivity type opposite to this (second conductivity type) are provided deep along the film thickness direction and arranged in a large number in a plan view in a semiconductor layer (substrate semiconductor region) of the first conductivity type. For example, a drain layer or the like in a MOSFET can be easily formed by one diffusion or ion implantation, but it is difficult to form such a deep column layer by the same method.

[0003] FIG. 11 is a cross-sectional view showing an example of a structure in which such a column layer (p layer: columnar semiconductor region) 92 is provided in an n-layer (substrate semiconductor region) 91, and FIG. 12 is a process cross-sectional view schematically showing a manufacturing method thereof. In FIG. 11, the n-layer 91 is formed by four epitaxial growths. In FIGS. 11 and 12, only portions corresponding to the n-layer 91 and the column layer 92 are shown, and actually other layers are also formed below the n-layer 91, but since they are not related to the invention of the present application, the description thereof is omitted.

[0004] First, as shown in FIG. 12(a), an n-layer 91A that is the lowermost layer constituting the n-layer 91 is formed, and a p-type impurity introduction layer 93 that is the source of the column layer 92 and into which an impurity serving as an acceptor is introduced at a high concentration is formed on the surface thereof. The impurity introduction layer 93 is locally and shallowly formed only in the vicinity of the surface.

[0005] Next, as shown in Figure 12(b), an n-layer 91B is similarly formed on top of this by epitaxial growth, and an impurity introduction layer 93 is similarly formed on its surface. By repeating this process, as shown in Figure 12(c), n-layers 91A to 91D are stacked, and the impurity introduction layer 93 is provided in this stacked structure as shown.

[0006] By applying heat treatment to the structure shown in Figure 12(c), p-type layers (diffusion layers: individual diffusion regions) 94 are formed as shown in Figure 12(d), where impurities (p-type impurities) diffuse and spread from each of the impurity introduction layers 93. If the diffusion is isotropic, each p-type layer 94 will be circular (the uppermost p-type layer 94 will be semicircular) centered on the diffusion layer before heat treatment. Once sufficient thermal diffusion has occurred, the p-type layers 94 will eventually connect in the film thickness direction, as shown in Figure 12(e), forming a column layer 92. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-311669 [Overview of the project] [Problems that the invention aims to solve]

[0008] In the above manufacturing method, the p-type layers 94 are connected in the film thickness direction to ultimately obtain the column layer 92. However, in some cases, this connection is insufficient, and the desired column layer cannot be obtained. Figure 13 schematically shows two typical examples of such cases. Here, it is assumed that the p-type layers 94 (94A to 94D) corresponding to the state in Figure 12(e) are formed in order from bottom to top.

[0009] In Figure 13(a), diffusion in the third p-type layer 94C from the bottom is insufficient, resulting in a smaller p-type layer 94C. Consequently, the connection between p-type layer 94C and p-type layers 94B and 94D is weak, and an integrated column layer cannot be obtained. In Figure 13(b), although the sizes of p-type layers 94A to 94D are similar, due to misalignment, the position of the second p-type layer 94B from the bottom is different from p-type layers 94A and 94C, and an integrated column layer cannot be obtained either.

[0010] Since this situation can occur in semiconductor devices (such as power MOSFETs) having the structure shown in Figure 11, it was desirable to provide an evaluation element on the same substrate (wafer) as the semiconductor device that could assess the condition of the column layer formation defects.

[0011] This disclosure has been made in view of the aforementioned problems and aims to provide an invention that solves the above problems. [Means for solving the problem]

[0012] This disclosure has the following structure in order to solve the above-mentioned problems. The evaluation element of the present disclosure is an evaluation element for a semiconductor device in which a manufacturing process is used to form a columnar semiconductor region which is a columnar region of the second conductivity type, by forming multiple individual diffusion regions, which are diffusion regions of a second conductivity type opposite to the first conductivity type, at different positions in the depth direction within a substrate semiconductor region of a first conductivity type, and stacking them, thereby connecting the multiple individual diffusion regions in the depth direction, wherein the evaluation element comprises a plurality of first evaluation individual diffusion regions formed at different depths in the substrate semiconductor region, each corresponding to the plurality of individual diffusion regions, and a plurality of individual diffusion regions formed at different depths in the substrate semiconductor region, each corresponding to the plurality of individual diffusion regions. The stacked structure of the first evaluation individual diffusion region comprises a plurality of second evaluation individual diffusion regions formed at spaced-apart locations in a plan view, wherein the first evaluation individual diffusion region and the second evaluation individual diffusion region are formed in equal numbers from the surface side, in a number less than or equal to the total number of stacked individual diffusion regions constituting the columnar semiconductor region, and the bottommost first evaluation individual diffusion region and the bottommost second evaluation individual diffusion region are connected by a connecting layer which is a second conductivity type diffusion region, and measurement terminals are connected to the topmost first evaluation individual diffusion region and the topmost second evaluation individual diffusion region, respectively. The individual diffusion regions, the first evaluation individual diffusion region corresponding to the individual diffusion region, and the second evaluation individual diffusion region are formed by a common process. The connecting layer may be provided below the first individual diffusion region for evaluation located at the bottom and the second individual diffusion region for evaluation located at the bottom. The connecting layer may be provided between the first individual diffusion region for evaluation and the second individual diffusion region for evaluation, at the same depth as the first individual diffusion region for evaluation located at the bottom and the second individual diffusion region for evaluation located at the bottom. The connecting layer may be formed to the same size as the columnar semiconductor region at the very bottom by the same process. The evaluation element set of this disclosure comprises multiple evaluation elements, each having a different number of first evaluation individual diffusion regions and second evaluation individual diffusion regions, provided in a common substrate semiconductor region. The evaluation element set of the present disclosure is provided in a common substrate semiconductor region in which multiple evaluation elements are provided, each having a different horizontal spacing between the first evaluation individual diffusion region located at the bottom and the second evaluation individual diffusion region located at the bottom. The evaluation element set of this disclosure is provided with a plurality of evaluation elements, the terminals of which are connected in series. When a plurality of product chips having the columnar semiconductor region are manufactured in an arrangement on a wafer, the columnar semiconductor region may be formed by replacing a portion of the product chip. When a plurality of product chips having the columnar semiconductor region are manufactured in an arrangement on a wafer, the columnar semiconductor region may be formed on the cutting line between adjacent product chips. [Effects of the Invention]

[0013] As described above, this disclosure provides an evaluation element that can grasp the state of defects in the formation of the column layer. [Brief explanation of the drawing]

[0014] [Figure 1] This is a cross-sectional view showing the structure of an evaluation element and an evaluation element set according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view showing the structure of an evaluation element and evaluation element set according to an embodiment of the present invention when diffusion is insufficient in some individual diffusion regions. [Figure 3] This is a cross-sectional view showing the structure of an evaluation element and evaluation element set according to an embodiment of the present invention when there is misalignment in some individual diffusion regions. [Figure 4] This is a cross-sectional view showing the structure of an evaluation element and evaluation element set according to an embodiment of the present invention when a contamination layer is present. [Figure 5] This is a cross-sectional view showing the configuration in which a defect in a wafer is recognized by an evaluation element according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view showing the structure of a first modified example of an evaluation element and an evaluation element set according to an embodiment of the present invention. [Figure 7] A cross-sectional view showing the structure of a second modification of the evaluation element and the evaluation element set according to an embodiment of the present invention. [Figure 8] A top view showing the structure of a third modification of the evaluation element and the evaluation element set according to an embodiment of the present invention. [Figure 9] A cross-sectional view showing the structure of a third modification of the evaluation element and the evaluation element set according to an embodiment of the present invention. [Figure 10] A plan view showing an example of the configuration of a wafer in which an evaluation element set according to an embodiment of the present invention is mixed with product chips. [Figure 11] A cross-sectional view of a structure in which a columnar semiconductor region is formed in a base semiconductor region. [Figure 12] A process cross-sectional view of a manufacturing method of a structure in which a columnar semiconductor region is formed in a base semiconductor region. [Figure 13] An example of a defective formation of a columnar semiconductor region in a structure in which a columnar semiconductor region is formed in a base semiconductor region.

Embodiments for Carrying Out the Invention

[0015] Hereinafter, an evaluation element according to an embodiment of the present disclosure will be described. FIG. 1 is a cross-sectional view showing the structure of an evaluation element set 1 provided with four types of this evaluation element. This evaluation element set 1 is formed on the same substrate as a semiconductor device manufactured by the manufacturing method of FIG. 12. On the left side in FIG. 1, a column layer (columnar semiconductor region) 12 used in this semiconductor device is shown, and this evaluation element set 1 (evaluation elements T1 to T4) is used to indirectly evaluate this column layer 12 in an n layer (base semiconductor region) 11.

[0016] n-layer 11 is formed by sequential epitaxial growth of n-layers 11B to 11E on n-layer 11A. As shown in Figure 12, p-layers (individual diffusion regions) 12A to 12E are formed by thermal diffusion of impurities from the impurity introduction layer introduced into n-layers 11A to 11E. In this case, the thickness of n-layers 11B to 11E and the size of the impurity introduction layer are assumed to be equal.

[0017] The column layer 12 is formed by the connection of p layers 12A to 12E in the depth direction. As mentioned above, in reality, adjacent p layers 12A to 12E overlap in the film thickness direction as shown in Figure 12(e), but here, for convenience, the size of the p-type layers 12A to 12E after heat treatment is described as being equivalent to the thickness of the n-type layers 11B to 11E (the circles constituting the p-type layers 12A to 12E do not overlap but make point contact). Furthermore, the state of the p-type layers 12A to 12E in Figure 1 is considered the normal state, and it is assumed that the column layer 12 is formed by this.

[0018] In this evaluation element T1, p layers (first evaluation individual diffusion regions) 22B to 22E and p layers (second evaluation individual diffusion regions) 23B to 23E are formed in a region separate from the semiconductor device (column layer 12) in a plan view, similar to the p layers 12B to 12E described above. Corresponding to the p layer 12A, a p-type connecting layer 24 is formed that connects p layers 22B and 23B on their underside. The method of forming each of these p layers is the same as that of p layers 12B to 12E in the column layer 12, and they are formed simultaneously. The relationship between the connecting layer 24 and p layer 12A is also the same.

[0019] Similarly, in evaluation element T2, p layers (first evaluation individual diffusion regions) 32C-32E and p layers (second evaluation individual diffusion regions) 33C-33E are formed, similar to the p layers 12C-12E, and a p-type connecting layer 34 is formed to connect p layers 32C and 33C below, corresponding to the p layer 12A. Similarly, in evaluation element T3, p layers (first evaluation individual diffusion regions) 42D, 42E and p layers (second evaluation individual diffusion regions) 43D, 43E are formed, similar to the p layers 12D, 12E, and a p-type connecting layer 44 is formed to connect p layers 42D and 43D below, corresponding to the p layer 12A. Similarly, in the evaluation element T4, a p-layer (first evaluation individual diffusion region) 52E and a p-layer (second evaluation individual diffusion region) 53E are also formed, similar to the p-layer 12E, and a p-type connecting layer 54 is formed to connect the p-layer 52E and p-layer 53E on their underside, corresponding to the p-layer 12A.

[0020] In Figure 1, the surfaces of the semicircular p layers 22E, 23E, 32E, 33E, 42E, 43E, 52E, and 53E on the surface of the n layer 11 contain p-type p with locally high impurity concentrations. + Layer 61 is formed, and on the surface of n layer 11 (n layer 11E), n-type n with a locally high impurity concentration + Layer 62 is formed. p is formed in layers 22E, 23E, 32E, 33E, 42E, 43E, 52E, 53E. + Wiring is connected to layer 61, each connected to terminals T11, T12, T21, T22, T31, T32, T41, and T42. + Similarly, terminal T0 is connected to layer 62.

[0021] Although the explanation of the planar structure is omitted here, in reality, as will be described later, an interlayer insulating layer is formed on the surface side of the n layer 11E, and pads corresponding to the terminals T11 to T42 and T0 are arranged on top of it.

[0022] This configuration forms element T1, in which p-layers 22E, 22D, 22C, 22B, a connecting layer 24, and p-layers 23B, 23C, 23D, and 23E are connected in series between terminals T11 and T12; element T2, in which p-layers 32E, 32D, 32C, a connecting layer 34, and p-layers 33C, 33D, and 33E are connected in series between terminals T21 and T22; element T3, in which p-layers 42E, 42D, a connecting layer 44, and p-layers 43D and 43E are connected in series between terminals T31 and T32; and element T4, in which p-layer 52E, a connecting layer 54, and p-layer 53E are connected in series between terminals T41 and T42.

[0023] This structure can be manufactured using the same manufacturing process as a semiconductor device (product) that includes a column layer 12, by changing only the mask. Therefore, this evaluation element 1 can be manufactured on the same wafer as the product.

[0024] Here, p-layers 22B and 23B in element T1 and the connecting layer 34 in element T2 are diffusion layers formed separately to evaluate p-layer 12B in column layer 12, and the connecting layer 24 in element T1 is a diffusion layer formed separately to evaluate p-layer 12A. Similarly, p-layers 22C and 23C in element T1, p-layers 32C and 33C in element T2, and the connecting layer 44 in element T3 are diffusion layers formed separately to evaluate p-layer 12C in column layer 12. Similarly, p-layers 22D and 23D in element T1, p-layers 32D and 33D in element T2, p-layers 42D and 43D in element T3, and the connecting layer 44 in element T4 are diffusion layers formed separately to evaluate p-layer 12D in column layer 12. Similarly, p layers 22E and 23E in element T1, p layers 32E and 33E in element T2, p layers 42E and 43E in element T3, and p layers 52E and 53E in element T4 become diffusion layers formed separately to evaluate p layer 12E in column layer 12.

[0025] Therefore, the positional and size relationships of the p-layers (individual diffusion regions) 12A to 12E that constitute the column layer 12 can be indirectly investigated by the resistance values ​​(current-voltage characteristics) of the elements T1 to T4 described above. Figure 2 shows the case in the structure of Figure 1 where diffusion is insufficient in the formation of p-layer 12C, and the size of only p-layer 12C becomes smaller than standard. In this case, p-layers 22C and 23C in element T1, p-layers 32C and 33C in element T2, and the connecting layer 44 in element T3, which correspond to p-layer 12C, become similarly smaller, the gap between them and the p-layers in contact above and below them widens, and the resistance values ​​of elements T1 to T3 become larger than in the normal case (the state in Figure 1 for each element). On the other hand, the situation inside element T4 remains unchanged from the state in Figure 1, so the resistance value of element T4 is the same as in the case of Figure 1. In other words, by using the resistance values ​​of elements T1 to T4 in Figure 1 as reference values ​​(resistance values ​​under normal conditions), abnormalities shown by elements T1 to T3 in Figure 2 can be detected based on their relative magnitudes relative to these reference values. This reference resistance value is determined for each element, with element T1 having the highest value and element T4 having the lowest.

[0026] Figure 3 shows the case where, in the structure of Figure 1, misalignment occurs during patterning when forming p-layer 12B, causing p-layer 12B to be formed shifted to the left in the figure. In this case, p-layers 22B and 23B in element T1, which correspond to p-layer 12B, and the connecting layer 34 in element T2 are similarly shifted, increasing the gap between them and the p-layers they are in contact with above and below, resulting in resistance values ​​of elements T1 and T2 being greater than the aforementioned reference values. On the other hand, the conditions within elements T3 and T4 remain unchanged from the normal case (Figure 1), so the resistance values ​​of elements T3 and T4 are normal.

[0027] Figure 4 shows the case in the structure of Figure 1 where contamination exists on the surface of the n-layer 11C before the formation of the n-layer 11D, and a conductive layer (contamination layer 70) due to the contamination is formed at these interfaces. In this case, the space between elements T1 to T3 (between terminals of different elements) is conductive due to the contamination layer 70 (the resistance value becomes smaller than the aforementioned reference value). On the other hand, element T4, which is formed above the contamination layer 70, is not affected by the contamination layer 70, so its resistance value is normal (reference value). Furthermore, if the resistance value of the contamination layer 70 is particularly low, elements T1 to T3 are short-circuited as a result, so their resistance values ​​become equivalent. On the other hand, elements T1 to T3 and element T4 are insulated (the resistance value between them becomes higher). In this evaluation, the current-voltage characteristics between terminal T0 and other terminals in Figure 1 can also be used.

[0028] Furthermore, the evaluation element described above can be used not only for evaluating the p-layers 12A to 12E that constitute the column layer 12, but also for evaluating defects in the wafer. Figure 5 shows an example of such a configuration. Here, two sets of the element T1 (p-layers 22B to 22E, 23B to 23E, and a connecting layer 24) are provided (element T1 and element T1'), and the horizontal spacing between the p-layers 22B to 22E and the p-layers 23B to 23E (length of the connecting layer 24) is set to be large. In such a case, if a defect 71 such as a slip exists in the element T1 on the left side but not in the element T1' on the right side, the resistance value of the element T1 on the left side will be different from the resistance value of the element on the right side. This makes it possible to recognize the defect 71 in the wafer.

[0029] Figure 6 is a cross-sectional view showing the configuration of evaluation element set 2, which is a first modified example of evaluation element set 1 described above. Here, the column layer 12 and n in Figure 1 are shown. +The description for layer 62 is omitted. In this evaluation element 2, the structure of the bottommost connecting layer differs from that in Figure 1. In the structure of Figure 1, the connecting layer 24 corresponds to the bottommost p-layer 12A in the column layer 12 of element T1, whereas here, below p-layers 22B and 23B, there are p-layers (first evaluation individual diffusion region, second evaluation individual diffusion region) 22A and 23A, similar to p-layer 12A. Therefore, the stacked structure of p-layers 22A to 22E and p-layers 23A to 23E are essentially equivalent to the column layer 12 in Figure 1. Furthermore, p-layers 22A and 23A are connected by a connecting layer 24A of the same size. Similarly, in element T2, p layers 32B and 33B and a connecting layer 34A are provided; in element T3, p layers 42C and 42D and a connecting layer 44A are provided; and in element T4, p layers 52D and 53D and a connecting layer 54A are provided.

[0030] In this structure, all p-layers used in the evaluation element are formed with the same size and formation conditions as p-layer 12A in column layer 12. Therefore, the state of column layer 12 is more strongly reflected in this evaluation element 2, and its evaluation can be performed more rigorously.

[0031] In Figures 1 and 6, the p layers are connected in the film thickness direction by making the size (diameter) of p layers 12A, 22A, etc. equal to the thickness of n layers 11B to 11E (as mentioned above, in reality the size (diameter) of p layers 12A, 22A, etc. is larger than the thickness of n layers 11B to 11E, so adjacent p layers overlap). In the structure of Figure 6, this relationship is also the same for the three bottommost p layers in a single element (p layers 22A, 23A and the connecting layer 24A in element T1). However, in this case, if the connection between p layers 22A and 23A by the connecting layer 24A is insufficient, for example, the resistance evaluation of element T1 cannot be performed properly. For this reason, it is preferable to make the lateral spacing between p layers 22A to 22E and p layers 23A to 23E in element T1 smaller than the thickness of n layers 11B to 11E so that the connection by the connecting layer 24A is reliably achieved. In contrast, in the structure shown in Figure 1, if the connecting layer 24 is sufficiently long in the lateral direction, the lateral spacing between p layers 22B-22E and p layers 23B-23E in element T1 can be wide. The same applies to the lateral spacing of p layers and the connecting layer in other elements.

[0032] Figure 7 is a cross-sectional view showing the configuration of evaluation element set 3, which is a second modified example of evaluation element set 1 described above. Here, three types of elements (elements T1A, T1B, and T1C) with a structure corresponding to element T1 in Figure 1 are formed. In each element, the stacked structure of p layers 22A to p layers 22E and the stacked structure of p layers 23A to 23E are spaced apart in the lateral direction, as in Figure 6, and the bottom layers 22A and 23A are connected by a connecting layer, also as in Figure 6.

[0033] In the structure shown in Figure 6, this connecting layer was a diffusion layer of similar size to p-layer 22A, etc. However, in Figure 7, multiple types of lateral spacing between the stacked structures of p-layers 22A to 22E and p-layers 23A to 23E, or the lateral length of this connecting layer, are set. In the connecting layer 24AA in element T1A, the connecting layer 24AB in element T1B, and the connecting layer 24AC in element T1C, the connecting layer 24AC is the longest and the connecting layer 24AA is the shortest.

[0034] In this structure, the resistance measured at elements T1A to T1C is the sum of the resistance R1 due to the stacked structure of p layers 22A to 22E and p layers 23A to 23E, and the resistance R2 due to the connection between each connecting layer and these p layers 22A and 23A. Here, the resistance R2 depends on the length of the connecting layer (diffusion layer), so it is largest at element T1C and smallest at element T1A, whereas ideally the resistance R1 remains constant at elements T1A to T1C.

[0035] For evaluations such as those shown in Figures 2 and 3, it is appropriate to use the resistance value R1 in this case. In this structure, the resistance values ​​R1 and R2 can be accurately determined from the resistance values ​​of elements T1A to T1C, and the aforementioned evaluations can be performed using only the resistance value R1.

[0036] For example, in the example in Figure 2, only the third p-layer 12C from the bottom is shown to be smaller than the others, but there are also cases where all p-layers are uniformly smaller. In this case, there are two possible causes: (1) insufficient diffusion when the p-layer is formed, or (2) the thickness of the n-layer 11B, etc., is too thick compared to the diffusion length. Such situations can be recognized more accurately using the resistance value R1. It should be noted that providing multiple elements with varying lengths of connecting layers in this way can also be achieved in the evaluation element 1 mentioned above.

[0037] Next, we will describe the method of mounting the above-mentioned evaluation elements on the same wafer as the actual semiconductor device that will become the product. Ideally, it is preferable to use an evaluation element set with multiple types of stacking configurations (elements T1 to T4) as shown in Figures 1 and 6, and with multiple types of connecting layer lengths for each type (elements T1A to T1C) as shown in Figure 7. However, in this case, the number of terminals used (T11, T12, etc.) increases, and the number of corresponding pads also increases, so the total area of ​​such evaluation elements becomes large, which imposes limitations when mounting them on the same wafer as the semiconductor device that will become the product.

[0038] Therefore, it is preferable to have a configuration that allows the above-mentioned evaluation elements to be used more simply. Figure 8 is a top view showing the configuration of a third modified evaluation element set 4 having such a configuration, and Figure 9 is a cross-sectional view of the same in two directions.

[0039] Here, only element T1 in Figure 1 is formed, and 18 elements T1 are connected in series between the left pad 80A and the right pad 80B in Figure 8. Here, the horizontal direction in Figure 1 (the direction in which the two stacked structures are aligned) is considered the y-direction. In Figure 8 (top view), only the surface wiring structure and p-layers 22E and 23E are shown. In Figure 8, the path of the current flowing between pads 80A and pad 80B when pad 80A is considered the positive side is indicated by a dotted arrow, and the resistance value between pads 80A and pad 80B can be measured in the same way as described above.

[0040] Figure 9 shows the cross-sectional view in the AA direction (x direction) (a) and the cross-sectional view in the BB direction (y direction) as shown in Figure 8. Here, an interlayer insulating layer 81 is formed on the surface of the semiconductor layer (n layer 11E and p layers 22E, 23E), and by locally removing the interlayer insulating layer 81 on the p layers 22E, 23E, connection wiring 82 is formed as shown in Figure 9, and as a result, the resistance value of 18 series connections of element T1 is measured as shown in Figure 8. In this case, if there is a defect as shown in Figures 2 and 3 in one element T1 or in the stacked structure of the p layer within it, the resistance value will rise from the standard value, and if there is contamination as shown in Figure 4 in even one place, the resistance value will be lower. Therefore, if the standard resistance value in this configuration is known, the presence or absence of such abnormalities can be easily recognized by the magnitude relationship between the measured resistance value and the standard value. This recognition can be easily performed by automated measurement using a computer or the like.

[0041] In the configuration shown in Figure 8, the two pads 80A and 80B occupy a large area, and the p-layers constituting element T1 can be arranged in a two-dimensional array to provide high density. As a result, the area of ​​the evaluation element set 4 in Figure 8 is small, and it can be placed, for example, on the die line between product chips on a wafer (the cutting line used when cutting each product chip from the wafer).

[0042] On the other hand, when using evaluation element sets 1 and 3, it becomes necessary to provide many pads on the surface corresponding to the number of terminals, requiring a large area. Therefore, the area of ​​the evaluation element region where evaluation element sets 1 and 3 are provided becomes large.

[0043] Figure 10 schematically shows an example of the planar configuration of a wafer W on which the product chip and the evaluation element set described above are provided, taking the above points into consideration. In this example, an actual product chip C1 on which a semiconductor device comprising the column layer 12 is provided, a first evaluation element region C2 on which the evaluation element sets 1, 3, etc. are formed, and a second evaluation element region C3 on which only the evaluation element set 4 is provided are arranged. Here, the first evaluation element region C2 and the product chip C1 are rectangular in shape and of the same size.

[0044] In this case, the first evaluation element region C2 can be provided by replacing a portion of the arrangement of the product chip C1 as shown in the figure, and distributed accordingly, allowing the first evaluation element region C2 to be treated in the same way as the product chip C1. In this case, the product chip C1 and the first evaluation element region C2 can be separated by cutting along the die line (cutting line) D in Figure 10.

[0045] On the other hand, as mentioned above, the area of ​​the second evaluation element region C3 is small, so as shown in Figure 10, it can be placed on the die line D between the product chips C1. Also, as mentioned above, only two pads are provided in the second evaluation element region C3, and only the electrical resistance between them is measured. For this reason, evaluation can be easily performed using a prober or the like with the wafer W in the state shown in Figure 10.

[0046] Subsequently, if, for example, an abnormality is found in the separated product chip C1, the abnormality in the formation of the column layer 12 can be recognized by performing the detailed evaluation described above using the simultaneously separated first evaluation element region C2.

[0047] However, the configuration of the evaluation elements on the wafer can be set as appropriate. For example, in Figure 10, the first evaluation element region C2 may be omitted entirely, and only the second evaluation element region C3 may be provided in the configuration of Figure 10. Conversely, in order to evaluate the column layer formation process 12 in particular detail, a wafer may be used in which only the first evaluation element region C2 is arranged, without any product chips C1.

[0048] In the above example, a p-type column layer (columnar semiconductor region) is formed within an n-layer (substrate semiconductor region), but it is clear that the above configuration is also valid even if the conductivity types of these layers are reversed. Furthermore, it is clear that the number of stacked layers, or the depth and width of the column layer, can be arbitrary.

[0049] Furthermore, in the above example, it was assumed that as n layers 11 were formed on n layer 11A and n layers 11B to 11E were sequentially formed by epitaxial growth, individual diffusion regions (first evaluation individual diffusion region, second evaluation individual diffusion region) were formed based on the impurity introduction layer introduced for each layer. However, it is clear that the above evaluation element is equally effective when columnar semiconductor regions are formed by stacking (connecting) individual diffusion regions. [Explanation of symbols]

[0050] 1-4 Evaluation Element Set 11, 91 n-layer (substrate semiconductor region) 11A~11E, 91A~91D n-layer 12, 92 Columnar layer (columnar semiconductor region) 12A~12E, 94 p layer (individual diffusion regions) 22A-22E, 32B-32E, 42C-42E, 52D, 52E p-layer (individual diffusion regions for first evaluation) 23A-23E, 33B-33E, 43C-43E, 53D, 53E p-layer (individual diffusion regions for second evaluation) 24, 24A, 24AA, 24AB, 24AC, 34, 34A, 44, 44A, 54, 54A connection layer 61 p + layer 62 n + layer 70 Contaminated layer 71 Defects 80A, 80B pads 81 Interlayer insulating layer 82 Connection Wiring 93 Impurity introduction layer C1 Product Chip C2 First evaluation element region C3 Second evaluation element region D die line (cutting line) T1~T4, T1A~T1C Evaluation elements (elements) W wafer

Claims

1. An evaluation element for a semiconductor device, in which a manufacturing process is used to form a columnar semiconductor region which is a columnar region of the second conductivity type, in which multiple individual diffusion regions, which are diffusion regions of the second conductivity type opposite to the first conductivity type, are formed at different positions in the depth direction within a substrate semiconductor region of the first conductivity type, and stacked, thereby connecting the multiple individual diffusion regions in the depth direction, A plurality of first evaluation individual diffusion regions are formed at different depths in the substrate semiconductor region, each corresponding to a plurality of the individual diffusion regions, A plurality of second evaluation individual diffusion regions are formed at different depths within the substrate semiconductor region, corresponding to each of the plurality of individual diffusion regions, and are spaced apart in a plan view from the stacked structure of the plurality of first evaluation individual diffusion regions. It is equipped with, The first evaluation individual diffusion regions and the second evaluation individual diffusion regions are formed from the surface side in a number equal to or less than the total number of stacked individual diffusion regions constituting the columnar semiconductor region. The first individual diffusion region for evaluation located at the bottom and the second individual diffusion region for evaluation located at the bottom are connected by a connecting layer which is the second conductive type diffusion region. An evaluation element characterized in that measurement terminals are connected to the first evaluation individual diffusion region located on the outermost surface and the second evaluation individual diffusion region located on the outermost surface.

2. The evaluation element according to claim 1, characterized in that the individual diffusion regions, the first evaluation individual diffusion region corresponding to the individual diffusion region, and the second evaluation individual diffusion region are formed by a common process.

3. The evaluation element according to claim 1 or 2, characterized in that the connecting layer is provided below the first evaluation individual diffusion region located at the bottom and the second evaluation individual diffusion region located at the bottom.

4. The evaluation element according to claim 1 or 2, characterized in that the connecting layer is provided between the first evaluation individual diffusion region and the second evaluation individual diffusion region, which are located at the bottommost end, and at the same depth as the first evaluation individual diffusion region and which are located at the bottommost end.

5. The evaluation element according to claim 4, characterized in that the connecting layer is formed to the same size as the columnar semiconductor region at the very bottom by the same process.

6. An evaluation element set characterized in that a plurality of evaluation elements according to claim 1 or 2, each having a different number of first evaluation individual diffusion regions and second evaluation individual diffusion regions, are provided in a common substrate semiconductor region.

7. An evaluation element set characterized in that a plurality of evaluation elements according to claim 1 or 2 are provided in a common substrate semiconductor region, wherein the horizontal distance between the first evaluation individual diffusion region located at the bottom and the second evaluation individual diffusion region located at the bottom is different.

8. An evaluation element set characterized in that a plurality of evaluation elements according to claim 1 or 2 are provided with their terminals connected in series.

9. The evaluation element set according to claim 6, characterized in that when a plurality of product chips having the columnar semiconductor region are manufactured in a form arranged on a wafer, a portion of the product chip is replaced to form the evaluation element set.

10. The evaluation element set according to claim 8, characterized in that when a plurality of product chips having the columnar semiconductor region are manufactured in a form arranged on a wafer, the columnar semiconductor region is formed on the cutting line between adjacent product chips.

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