Pseudo-annular through-core metal structure for improved signal transmission and thermal management

Abstract

To minimize signal loss and maximize bandwidth at the desired operating frequency of high-speed signal input / output structures within an IC package. [Solution] The microelectronic integrated circuit package structure 400 includes a core substrate 402. The core substrate has a plurality of outer vias, each extending through a layer of glass. Each outer via 406 has a first lateral width and each has individual annular segments separated at a distance from each other, and one or more inner vias 404 extending through a layer of glass adjacent to the outer vias have a second lateral width, the first lateral width being greater than the second lateral width.

Description

Background Art

[0001] In the fabrication of electronic devices, the packaging of an integrated circuit (IC) is the stage of fabrication in which an IC fabricated on a die or chip containing a semiconductor material is coupled to a support case, i.e., a "package", that protects the IC from physical damage and supports electrical interconnects suitable for further connection to a host component such as a printed circuit board (PCB). In the IC industry, the process of manufacturing a package is often referred to as packaging or assembly.

[0002] As semiconductor IC packaging architectures continue to evolve towards more complex and more compact systems, the high signal input output (HSIO) structures within an IC package require designs, processes, and materials to minimize signal loss and maximize bandwidth at the desired operating frequencies. One of the major signal losses in such HSIO structures is associated with through-hole structures within the substrate core. The core structure can include conductive paths for differential pairs of signal structures, with a ring of ground vias surrounding the signal structure to minimize capacitive losses. This ring of ground via structures forms an effective Faraday cage, but its effectiveness is limited by how close the via structures can be placed to each other.

Brief Description of the Drawings

[0003] The subject matter described herein is illustrated by way of example and not limitation in the accompanying drawings. For the sake of brevity and clarity of explanation, the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, reference numerals may be repeated among the drawings to indicate corresponding or similar elements where appropriate. The drawings are as follows.

[0004] [Figure 1A] This is a top view of an annular through-core conductive structure according to several embodiments. [Figure 1B] This is a top view of an annular through-core conductive structure according to several embodiments.

[0005] [Figure 1C] This is a cross-sectional view of an annular through-core conductive structure according to several embodiments.

[0006] [Figure 2-1] Figures 2A and 2B are cross-sectional views of methods for forming an annular through-core conductive structure according to several embodiments. [Figure 2-2] Figures 2C and 2D are cross-sectional views of a method for forming an annular through-core conductive structure according to several embodiments. [Figure 2-3] Figures 2E and 2F are cross-sectional views of a method for forming an annular through-core conductive structure according to several embodiments. [Figure 2-4] Figure 2G is a cross-sectional view of a method for forming an annular through-core conductive structure according to several embodiments.

[0007] [Figure 3-1] Figures 3A and 3B are cross-sectional views of methods for forming an annular through-core conductive structure according to several embodiments. [Figure 3-2] Figures 3C and 3D are cross-sectional views of methods for forming an annular through-core conductive structure according to several embodiments. [Figure 3-3] Figures 3E and 3F are cross-sectional views of methods for forming an annular through-core conductive structure according to several embodiments.

[0008] [Figure 4] This is a cross-sectional view of an IC package structure having an annular through-core conductive structure according to several embodiments.

[0009] [Figure 5]A flowchart illustrating the process for manufacturing an IC package structure having an annular through-core conductive structure, according to several embodiments, is provided.

[0010] [Figure 6] This is a functional block diagram of an electronic computing device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0011] Embodiments will be described with reference to the attached figures. Specific configurations and arrangements will be shown and discussed in detail, but it should be understood that these are for illustrative purposes only. Those skilled in the art will understand that other configurations and arrangements are possible without departing from the spirit and scope of this specification. It will be obvious to those skilled in the art that the techniques and / or arrangements described herein may be used in a variety of other systems and applications not described in detail herein.

[0012] In the following detailed description, reference will be made to the accompanying drawings, which form part of this specification and illustrate exemplary embodiments. Furthermore, it should be understood that even if other embodiments are utilized, or structural and / or logical modifications are made, this will not deviate from the scope of the claimed subject matter. Also note that directions and references such as up, down, upper, and lower may be used simply to facilitate the description of features in the drawings. Therefore, the following detailed description is not intended to limit the meaning, and the scope of the claimed subject matter is defined solely by the accompanying claims and their equivalents.

[0013] Numerous details are provided in the following description. However, it will be apparent to those skilled in the art that embodiments may be carried out without these specific details. In some examples, well-known methods and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the embodiments. Throughout this specification, any reference to “embodiment,” “one embodiment,” or “several embodiments” means that a particular feature, structure, function, or characteristic described in relation to that embodiment is included in at least one embodiment. Thus, the phrases “in an embodiment,” “in one embodiment,” or “in several embodiments” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, functions, or characteristics may be combined in any preferred manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment in any case, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0014] As used herein and in the attached claims, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context otherwise explicitly indicates. It should also be understood that, as used herein, the terms “and / or” refer to and encompass any and all possible combinations of one or more of the items listed relating to this specification.

[0015] The terms “joined” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between multiple components. It should be understood that these terms are not intended to be synonymous with respect to one another. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. “Joined” may be used to indicate that two or more elements are in direct or indirect (with other elements intervening) physical or electrical contact with one another, and / or that two or more elements cooperate or interact with one another (e.g., causally).

[0016] The terms “over,” “under,” “between,” and “on,” as used herein, refer to the relative position of one component or material to another component or material, where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer may be in direct contact with another material or layer above or below it, or may have one or more intervening materials or layers. Furthermore, one material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer “on” a second material or layer is in direct physical contact with the second material / layer. Similar distinctions are made in the context of component assembly.

[0017] Throughout this description and as used in the claims, a list of items connected by the terms “at least one of” or “one or more of” can mean any combination of the listed words. For example, the phrase “at least one of A, B, or C” could mean A, B, C; A and B, A and C; B and C; or A, B and C.

[0018] Unless otherwise explicitly stated in the context of use, the term "predominantly" means more than 50% or more than half. For example, a composition in which the majority is the first component means that more than half of the composition is the first component (e.g., <50 atomic%). The term "predominantly" means the most or the largest part. For example, a composition that is predominantly the first component means that the composition has more of the first component than any other component.

[0019] The term "package" generally refers to an embedded carrier for one or more dies, where the dies are attached to a package substrate and are encapsulated by protective means together with the interconnections by integrated or wire bonding between the dies and the leads, pins, or bumps located on the outer part of the package substrate. The package may contain a single die or multiple dies that provide a specific function. The package is usually mounted on a printed circuit board to form a larger circuit by interconnecting with other packaged integrated circuits and discrete components.

[0020] The term "dielectric" generally refers to any number of non-conductive materials that make up the structure of the package substrate.

[0021] The term "metallization" generally refers to a metal layer formed above and through the dielectric material of the package substrate. The metal layer is generally patterned to form metal structures such as wiring and bonding pads. The metallization of the package substrate may be limited to a single layer or may be in multiple layers separated by dielectric layers.

[0022] The term "bonding pad" generally refers to a metallization structure that terminates the integrated wiring and vias in an integrated circuit package and die. The term "solder pad" may be used interchangeably with and have the same meaning as "bonding pad".

[0023] The term "solder bump" generally refers to the layer of solder formed on a bonding pad. This layer typically has a rounded shape, hence the name "solder bump."

[0024] The term "substrate" generally refers to a planar platform comprising a dielectric and metallization structure. A substrate encapsulates one or more IC dies in a formable dielectric material and mechanically supports and electrically couples one or more IC dies on a single platform. A substrate generally has solder bumps on both sides for bonding interconnects. One side of the substrate is generally called the "die side" and has solder bumps for chip or die bonding. The opposite side of the substrate is generally called the "land side" and has solder bumps for bonding the package to a printed circuit board.

[0025] The vertical direction is the z-direction, and the descriptions "upper," "lower," "upper," and "downward" are understood to refer to relative positions in the z-dimension in the usual sense. However, it is understood that embodiments are not necessarily limited to the directions or configurations shown in the figures.

[0026] The terms “substantially,” “near,” “approximately,” “almost,” and “about” generally refer to being within ±10% of the target value (unless otherwise specified). Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” describing common objects simply indicates different instances of the same object being referred to, and is not intended to imply that the object described in this way must be in a given order in time, space, ranking, or any other manner.

[0027] Figures labeled "section," "side," and "plan" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, section and side views are taken in the xz plane, and plan views are taken in the xy plane. Typically, a side view in the xz plane is a section view. Where appropriate, the drawing is marked with an axis to indicate the orientation of the figure.

[0028] The embodiments described herein address the problems associated with reducing capacitive losses at a desired operating frequency in HSIO packaging architectures. Through-glass vias (TGVs) can be used to provide a conductive path for differential signal pairs in a substrate core, and a ring of grounded TGVs provides a Faraday cage to reduce capacitive losses. However, the effectiveness of such a Faraday cage is limited by the limitations on how close the grounded TGVs can be placed adjacent to each other. The method described herein utilizes glass core substrate processing to form a grounded structure of segmented annular ring TGVs, thereby minimizing losses and maximizing bandwidth at a desired operating frequency.

[0029] For example, a glass core package structure utilizing a segmented annular structure of grounded TGV described herein enables a loss of less than 1 dB relative to the glass core substrate at 90 GHz. In embodiments, the segmented annular ring TGV ground structure may form a Faraday cage surrounding the HSIO TGV signal structure. This embodiment results in a reduction of signal loss due to the reduction in the spacing between the annular ring ground structures.

[0030] The architectures described herein may be assembled and / or manufactured having one or more of the features or attributes provided according to various embodiments. Multiple different assembly and / or manufacturing methods may be employed to enable the formation of glass core package structures that prevent loss and improve thermal conductivity.

[0031] Figures 1A-1C illustrate an embodiment in which a glass core package structure is formed by creating a segmented annular ring ground structure surrounding a differential signal structure within a glass core substrate, thereby reducing signal loss in the IC package structure. The package structure may be formed using standard IC processing techniques. The manufacturing methods described herein produce improved device performance in advanced 2.5D and 3D packaging.

[0032] Figure 1A is a top view of a portion of the package substrate including the core substrate 102, which may include build-up layers (not shown) on the top and bottom surfaces of the core substrate 102. In one embodiment, the core substrate 102 may comprise a layer of glass. In one embodiment, the core substrate 102 may comprise substantially all glass or a layer of glass. The core substrate 102 may be a solid material having an amorphous crystalline structure. More specifically, the core substrate 102 may be any suitable glass composition having the required mechanical robustness and compatibility with semiconductor packaging fabrication and assembly processes. For example, the core substrate 102 may comprise aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silica, or the like. In some embodiments, the core substrate may contain one or more additives, for example, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn.

[0033] More generally, the core substrate 102 may contain, in addition to silicon and oxygen, one or more of the following: aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In one embodiment, the core substrate 102 may contain at least 23 percent silicon (by weight) and at least 26 percent oxygen (by weight). In some embodiments, the core substrate 102 may further contain at least 5 percent aluminum (by weight).

[0034] In one embodiment, the core substrate 102 may have a thickness (between the first and second surfaces) of approximately 500 microns (500 micrometers) to approximately 1,000 microns (1,000 micrometers), although the thickness may be optimized for a particular application. The core substrate 102 may have a substantially rectangular shape (when viewed from above in a plan view), but other shapes may also be used for the core substrate 102.

[0035] One or more inner vias 106a and 106b are located within the central portion of the core substrate 102. One or more inner vias 106a, 106b may comprise a pair of differential signal structures. In one embodiment, one or more inner vias 106a, 106b include one or more inner through-glass vias (TGVs) 106a, 106b, where one or more inner TGVs extend from the upper surface of the core substrate 102 to the lower surface of the core substrate 102 and may be filled with a conductive material such as copper or a copper alloy. In one embodiment, one or more inner TGVs 106a, 106b have a distance 113 between a first inner TGV 106a and a second inner TGV 106b, where the distance 113 may be 80 to 200 microns. In one embodiment, one or more inner TGVs 106a, 106b include a circular shape and may include a diameter 111 of 80 to 200 microns.

[0036] One or more outer TGVs 104a to 104d may surround one or more inner TGVs 106a, 106b. One or more outer TGVs 104a to 104d may comprise a segmented annular ring surrounding one or more inner TGVs 106a, 106b. In one embodiment, the length 114 of the individual segments of one or more outer TGVs 104a to 104d may be 200 microns to 1000 microns. The distance 115 may be between individual segments of one or more outer TGVs (e.g., between segment 104a and segment 104b).

[0037] The distance 115 between the individual outer TGVs 104a to 104d may include 10 to 50 microns, but may vary depending on the specific design. The inner TGVs 106a, 106b surrounded by the outer TGVs 104a to 104d may constitute a portion of the HSIO device 100, in which the segmented annular through-core metal structure provides improved signal transmission and thermal management to the device performance.

[0038] Figure 1B is a top view of a portion of the IC package structure 100, with the line segment A-A' cut out to show the cross-sectional portion in Figure 1C. Figure 1C shows a cross-sectional view of the package structure 100 through the line segment A-A', including outer TGVs 104a, 104c and inner TGVs 106a, 106b. TGVs 104a, 104c have a lateral width 105 that is greater than the lateral width 109 of the inner TGVs 106a, 106b. In one embodiment, the lateral width 105 of the outer TGVs 104a, 104c may be greater than twice the lateral width 109 of the inner TGVs 106a, 106b. The lateral widths 105 and 109 of the inner TGV 106a, 106b and outer TGV 104a, 104c may be optimized for a particular design, but the lateral width 105 of the outer TGV is generally larger than the lateral width 109 of the inner TGV.

[0039] Figures 2A-2G illustrate a method for forming an IC package device by, for example, utilizing a bottom-up plating process for a glass core through-hole structure to form an annular through-core metal ground structure surrounding a circular through-core metal signal structure. The Faraday cage structure is formed with nearly zero spacing between individual segmented ground TGVs.

[0040] Figure 2A shows a cross-sectional view of a portion of a core substrate 102 having a glass layer. In one embodiment, the core substrate 102 may have a thickness 119 of 500 to 1000 microns. In Figure 2B, a process 160 may be used, in which a plurality of first openings 103 may be formed and a plurality of second openings 107 may be formed. The first lateral width 105 of the first openings 103 may be greater than the second lateral width 109 of the second openings 107. In one embodiment, the first lateral width 105 may include 80 to 200 microns, and the second lateral width 109 may include 80 to 200 microns. In one embodiment, the process 160 may include any suitable etching process to remove the glass, such as a laser removal process. The first opening 103 and the second opening 107 extend through the core substrate 102 between the first surface 120 and the second surface 122 of the core substrate 102.

[0041] Figure 2C shows a cross-sectional view of step 161, where the first layer 118 is formed on the second surface 122 of the core substrate 102, and the second layer 123 is formed on the first layer 118. In one embodiment, the first layer 118 includes an adhesive material, such as a film containing a filler and resin, such as a die mounting film, and may have a thickness of 1 to 3 microns. In one embodiment, the second layer 123 may include a conductive material such as copper or a copper alloy. In one embodiment, the second layer 123 may include a thin copper foil and may have a thickness of 1 to 3 microns.

[0042] Figure 2D shows step 162, in which a portion of the first layer 118 has been removed and a portion of the second layer 123 is exposed. In one embodiment, the first layer 118 may be removed by utilizing a reactive ion etching (RIE) step 162, thereby exposing the second layer 123 between the openings 103 and 107.

[0043] Figure 2E shows the forming step 163, in which the conductive material 124 is formed in the first opening 103 and the second opening 107. In one embodiment, the conductive forming step 163 may include an electroplating step 163. In one embodiment, the conductive material 124 may be formed at a distance above the first surface 120 of the core substrate 102. In one embodiment, the conductive material 124 may include any suitable conductive material, such as copper or a copper alloy.

[0044] Figure 2F shows the planarization step 164, in which excess conductive material 124 above the surface 120 of the core substrate 102 is removed so that the surface of the conductive material 124 is coplanar with the surface of the core substrate 102. In one embodiment, the planarization step 164 may include a chemical mechanical polishing (CMP) step, or any other suitable step may be used to planarize the conductive material 124. Additionally, the first layer 118 and the second layer 123 may be removed from the second surface 122 of the core substrate 102.

[0045] Figure 2G shows a contact formation step 165, where self-aligned patterning and etching steps may be used to form contact structures 121 on the surface of the conductive material 124. In this way, outer TGV structures 104a, 104c may be formed surrounding inner TGV structures 106a, 106b, for example, as shown in Figure 1C. The thermal conductivity within the core substrate 102 is improved due to the outer TGV structures 104a, 104c being larger than the inner TGV structures 106a, 106b. Heat transport in the xy and z directions is improved within the package structure utilizing the TGV structure of the embodiments herein. Additionally, the core substrate 102 exhibits better thermal conductivity because the segmented annular TGV structure replaces more of the glass core substrate 102.

[0046] Figures 3A-3F illustrate a method for forming an IC package device by utilizing an electroplating process following conductive seed deposition within the inner and outer TGVs to form a segmented annular through-core metal ground structure surrounding a circular through-core metal signal structure. The Faraday cage structure is formed with nearly zero spacing between the individual segmented ground TGVs. The segmented annular TGV structure can replace portions of the glass core substrate, thereby improving the thermal conductivity of the glass core substrate.

[0047] Figure 3A shows a cross-sectional view of a portion of a core substrate 102 having a glass layer. In one embodiment, the core substrate 102 may have a thickness of 500 to 1000 microns. In Figure 3B, step 160 may be used, in which a plurality of first openings 103 and a plurality of second openings 107 may be formed. The first lateral width 105 of the first openings 103 may be greater than the second lateral width 109 of the second openings 107. In one embodiment, the first lateral width 105 may include 80 to 200 microns, and the second lateral width 109 may include 80 to 200 microns. In one embodiment, step 160 may include any suitable etching step to remove the glass, such as a laser removal step.

[0048] Figure 3C shows a cross-sectional view of step 166, where the seed layer 130 may be formed on the exposed surface of the substrate 102. In one embodiment, the seed layer 130 may have a thickness of about 10 nm to 10 μm. In one embodiment, the seed layer 130 may contain a conductive material such as copper or a copper alloy.

[0049] Figure 3D shows the forming step 163, in which a conductive material 124 is formed on a seed layer (which may be incorporated) in the first opening 103 and the second opening 107 of the substrate core 102. In one embodiment, the conductive forming step 163 may include an electroplating step 163. In one embodiment, the conductive material 124 may be formed at a distance above the first surface 120 of the core substrate 102. In one embodiment, the conductive material 124 may include any suitable conductive material, such as copper or a copper alloy.

[0050] Figure 3E shows a photoresist step 167, in which a photoresist 129 is formed on the surface of the conductive material 124 and patterned to define the contacts 121 (Figure 3F). In one embodiment, step 167 may include a subtractive etching lithography step 167. In this way, outer TGV structures 104a, 104c and inner TGV structures 106a, 106b may be formed, for example, as shown in Figure 1C.

[0051] Figure 4 shows an IC package structure 400 comprising a core substrate 402, for example, a package structure including a glass layer. The signal TGV structure 406 and the ground TGV structure 404 extend through the substrate core 402. The plan view through line segment A-A'411 may be similar to, for example, the plan view shown in Figure 1A, where the segmented annular structure 404 of the ground TGV surrounds the signal TGV structure 106. The portion of the package structure 400 may be similar to, for example, the portion of the package structure shown in Figure 2G.

[0052] The build-up layer 417 is located on the first and second surfaces 420, 422 of the core substrate 402, where the conductive structure 410 is dispersed within the dielectric material 412. The dielectric material 412 may be formed from epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac epoxy resin, aliphatic epoxy resin, and glycidylamine epoxy resin, or any other resin containing one or more terminal epoxy groups.

[0053] TGV404, 406 extend from a first surface 420 to a second surface 422 through the core substrate 402. TGV404, 406 are coupled to dies 450a, 450b. In some embodiments, dies 450a, 450b may comprise a chiplet structure, which may comprise a system-on-a-chip (SOC) structure component. In one embodiment, the core substrate 402 may include a portion of an interposer. TGV404, 406 may comprise a Faraday cage structure, where the outer TGV406 comprises a segmented annular segment surrounding the inner TGV404. In one embodiment, the outer TGV406 comprises a segmented ground structure, and TGV404 comprises a circular signal structure. In one embodiment, TGV404, 406 improve signal loss in devices utilizing the package structure 400 of the embodiments herein.

[0054] Any number of dies / devices may be bonded to TGV404, 406. The package substrate 444 (equipped with a substrate core 402 and a build-up layer 417) may, in one embodiment, be bonded to a board 144 such as a printed circuit board (PCB). Semiconductor materials (e.g., silicon, gallium, indium, germanium, or variations or combinations thereof) and one or more insulating layers, such as organic build-up films, glass fiber reinforced epoxy, e.g., FR-4, polytetrafluoroethylene (Teflon®), cotton paper reinforced epoxy (CEM-3), phenol-glass (G3), paper phenol (FR-1 or FR-2), polyester glass (CEM-5), or any other dielectric layer may be used for the PCB and / or package substrate 444.

[0055] The package substrate 444 may be manufactured using a bumpless buildup layer (BBUL) process or other techniques. The BBUL process involves forming one or more buildup layers around an element such as a high-density interconnect element or bridge die, as known in the art. Microvia formation processes, such as laser drilling, may form connections between the buildup layer 417 and the die bonding pad 435. The buildup layer 417 may be formed using high-density integrated patterning techniques. In one embodiment, the board 144 may be bonded to the package substrate 444 through a solder structure 449. In one embodiment, a power supply 443, which may include any suitable power supply as known in the art, may be bonded to the dies 450a, 450b via the IC package substrate 444. A solder interconnect structure 432 may bond the dies 450a, 450b to the package substrate 444. In one embodiment, an underfill material 436 may surround the solder structure 432.

[0056] Next, we will describe the operations for assembling and / or manufacturing the aforementioned structure.

[0057] Figure 5 is a flowchart of process 500 for manufacturing a package structure, for example, a package substrate comprising a glass core substrate, the glass core substrate having one or more segmented annular openings surrounding a circular opening. The circular opening may comprise a differential signal structure, and the annular ring structure comprises a ring of grounding structures around the signal circular opening. The segmented annular ring structure comprises a Faraday cage around the signal circular opening. For example, process 500 may be used to manufacture any of the microelectronic IC package structures shown in Figures 1A-1C.

[0058] A glass core substrate comprising a layer of glass is received, as described in Block 502. In one embodiment, the layer of glass may comprise one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica. In one embodiment, the layer of glass may comprise a first surface and a second surface opposite to the first surface.

[0059] As described in Block 504, one or more circular openings may be formed in the glass core substrate to form signal through-holes. In one embodiment, one or more circular openings may be formed by utilizing an etching process or a laser etching process. In one embodiment, one or more circular openings may include a signal TGV. One or more circular openings may have a depth equal to the length of the glass core substrate. In one embodiment, the glass core substrate may have a length of 500 microns to about 1000 microns. In one embodiment, individual circular openings may have a diameter of about 10 to 20 microns, but in other embodiments, they may have a diameter of 80 to 200 microns. The diameter of the circular openings may be optimized for a particular application. The distance between adjacent circular openings may be about 80 to about 200 microns, but may be optimized according to a particular application.

[0060] As described in Block 506, one or more segmented annular openings may be formed within the glass core substrate so as to surround a circular opening. This can be achieved by utilizing a laser glass ablation process. In one embodiment, the length of the annular segments may be 200 to 1000 microns, where the distance between adjacent segments of the segmented annular opening may be 5 to 20 microns, but may vary depending on the specific application.

[0061] As described in Block 508, the segmented annular and circular openings may be filled with a conductive material. In one embodiment, the openings may be filled with a metallic material such as copper or a copper alloy. A plating process may be used to fill the segmented annular and circular openings with a conductive material.

[0062] The build-up layers may be formed on the first and second surfaces of the glass core substrate. One or more dies may be mounted on the build-up layers to form a package structure, for example, as shown in Figure 4. One or more dies may include a central processing unit (CPU) or a field programmable gate array (FPGA), and the dies may include, for example, any suitable logic dies for a particular application. One or more dies may be mounted using any suitable die mounting process known in the art.

[0063] Embodiments of this specification enable, for example, a through-core structure that allows for losses lower than 1 dB when passing through a glass core substrate at 90 GHz. This improvement also allows for a relaxation of build-up material / design rule requirements for the packages described herein. By utilizing the embodiments of this specification, operating frequency or bandwidth targets can be extended. Thermal conductivity within the core substrate can be optimized to address the challenge of limited heat transport in the xy or even z direction in the IC package. Because the segmented annular structure replaces a larger portion of the glass in the glass core substrate with copper, the package structures described herein have superior thermal conductivity.

[0064] Using the bottom-up plating process described herein to form a segmented annular ring of grounding metal around an HSIO through-hole reduces process sensitivity by balancing sidewall, conformal plating, and filler plating to achieve the desired pitch requirements for a particular application.

[0065] Figure 6 illustrates an electronic or computing device 600 in one or more implementations of this specification. The computing device 600 may include a housing 601 on which a plate 602 is disposed on top. The computing device 600 may include several integrated circuit components, which are not limited to a processor 604, at least one communication chip 606A, 606B, volatile memory 608 (e.g., DRAM), non-volatile memory 610 (e.g., ROM), flash memory 612, graphics processor or CPU 614, digital signal processor (not shown), cryptographic processor (not shown), chipset 616, antenna, display (touchscreen display), touchscreen controller, battery, audio codec (not shown), video codec (not shown), power amplifier (AMP), global positioning system (GPS) device, compass, accelerometer (not shown), gyroscope (not shown), speaker, camera, and mass storage device (not shown) (e.g., hard disk drive, compact disk (CD), and digital versatile disk (DVD)). Any of the integrated circuit components may be physically and electrically coupled to the board 602. In some implementations, at least one of the integrated circuit components may be part of the processor 604.

[0066] The communication chip enables multiple wireless communications for data transfer to and from computing devices. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through non-solid media. This term does not imply that the devices in question are entirely wireless, although this may not be the case in some embodiments. The communication chip may implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and later. A computing device may include multiple communication chips. For example, the first communication chip may be dedicated to short-range wireless communication such as Wi-Fi® and Bluetooth®, and the second communication chip may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0067] The term “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. At least one of the integrated circuit components may include a core substrate in which one or more individual annular segments are spaced apart and surround one or more inner vias.

[0068] In various implementations, the computing device may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA®), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.

[0069] While certain features described herein have been explained with reference to various implementations, this explanation is not intended to be constrained. Therefore, various modifications and other implementations of the implementations described herein, though obvious to those skilled in the art to whom this disclosure relates, are considered to be within the spirit and scope of this disclosure. It is understood that the subject matter of this specification is not necessarily limited to the specific applications illustrated in Figures 1A to 6. The subject matter of the present invention may be applied to other integrated circuit devices and assembly applications, and may also be applied to any suitable electronic application, as will be understood to those skilled in the art.

[0070] The following examples relate to further embodiments and details, wherein the examples may be used in any one or more embodiments, wherein the first example is an apparatus comprising a core substrate, wherein the core substrate has a layer of glass; a plurality of outer vias, each extending through the layer of glass, wherein the outer vias each have a first lateral width, wherein the outer vias each have individual annular segments separated at a distance from each other; and one or more inner vias, adjacent to the outer vias and extending through the layer of glass, wherein the one or more inner vias have a second lateral width, wherein the first lateral width is greater than the second lateral width, and the outer vias are located in the peripheral portion of the core substrate.

[0071] In the second example, the first example further includes the fact that the one or more inner vias are located in the central portion of the core substrate.

[0072] In the third example, any of Examples 1 to 2 further includes the fact that the core substrate is located above the board, and the one or more inner vias and the more than one outer via extend in the xy plane and are parallel to the board.

[0073] In the fourth example, Example 3 further includes the fact that each annular segment has a length of 200 to 1000 microns and surrounds one or more inner vias.

[0074] In the fifth example, Example 3 further includes the fact that the distance includes 10 microns to 50 microns.

[0075] In the sixth example, any of Examples 1-5 further includes the presence of four or more individual annular segments.

[0076] In the seventh example, any of Examples 1 to 6 further includes the fact that each of the one or more inner vias has a diameter of 80 to 200 microns.

[0077] In the eighth example, any of Examples 1 to 7 further includes the first lateral width including 80 to 200 microns and the second lateral width including 80 to 200 microns.

[0078] In the ninth example, any of Examples 1 to 8 further comprises the one or more inner vias and the multiple outer vias comprising through-glass vias (TGVs) containing copper or a copper alloy, wherein the glass layer comprises one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica.

[0079] In the tenth example, any of Examples 1 to 9 further includes that the core substrate has one or more integrated circuit (IC) dies coupled to it, the one or more inner vias and the one or more outer vias coupled to the one or more IC dies, and a power supply coupled to the one or more IC dies.

[0080] In the eleventh example, any of Examples 1 to 9 further includes the fact that the one or more inner vias include one or more signal vias, and the multiple outer vias include multiple ground vias.

[0081] Example 12 is an apparatus comprising: a first set of conductive vias having a circular shape; a second set of conductive vias surrounding the first set of conductive vias, the second set of conductive vias having a segmented annular ring shape; and a glass layer surrounding the first set of conductive vias and the second set of conductive vias, the glass layer having a first face and a second face opposite the first face, the first set of conductive vias and the second set of conductive vias extending between the first face and the second face of the glass layer.

[0082] In the 13th example, Example 12 further includes the fact that the lateral width of the first set of conductive vias includes 10 to 20 microns, and the lateral width of the second set of conductive vias includes 30 to 80 microns.

[0083] In the 14th example, Examples 12-13 further include the glass layer comprising a glass core, the first set of conductive vias comprising one or more signal vias, and the second set of conductive vias comprising one or more ground vias.

[0084] In the 15th example, examples 12-14 further include the glass core being located above the plate, with a first set of conductive vias and a second set of conductive vias extending in the xy plane and parallel to the plate, and each segment of the second set of conductive vias having a length of 200 to 1000 microns.

[0085] In the 16th example, examples 12-15 further include the fact that the first set of conductive vias and the second set of conductive vias are on a build-up layer and bonded to one or more dies, the one or more dies are on top of the glass layer.

[0086] Example 17 is a method comprising the steps of: receiving a glass core, the glass core having a first face and a second face opposite the first face; forming one or more circular openings within the glass core; forming two or more segmented annular openings within the glass core so as to surround the circular openings, the circular openings and the segmented annular openings extending between the first face and the second face of the glass core; and filling the segmented annular openings and the circular openings with a conductive material.

[0087] In the 18th example, Example 17 further includes a step of filling the segmented annular opening and the circular opening, which includes a step of forming a copper material or copper alloy material within the segmented annular opening and the circular opening.

[0088] In the 19th example, examples 17-18 further include the glass core being located above the plate, the segmented annular opening extending in the xy plane and parallel to the plate, the segmented annular opening comprising four or more individual adjacent segments, and the four or more individual adjacent segments being spaced apart.

[0089] In the 20th example, Example 19 further includes the fact that the one or more circular openings extend in the xy plane and are parallel to the plate, the diameter of the one or more circular openings includes 80 microns to 200 microns, and the length of each adjacent segment includes 200 microns to 1000 microns.

[0090] The principles of this disclosure are not limited to the embodiments described herein, but it will be understood that they can be implemented with modifications and alterations without departing from the scope of the appended claims. The embodiments described above may include applying only a subset of such features, applying different orders of such features, applying different combinations of such features, and / or applying additional features other than those explicitly enumerated. Accordingly, the scope of these embodiments should be determined by referring to the appended claims together with the entire scope of equivalents to which such claims are entitled. [Other possible items] [Item 1] A core substrate, wherein the core substrate has a layer of glass; A plurality of outer vias extending through the glass layer, each having a first lateral width, and each having individual annular segments separated at a distance from each other; and One or more inner vias extending through the glass layer adjacent to the outer via, wherein the one or more inner vias have a second lateral width, and the first lateral width is greater than the second lateral width. A device equipped with the following features. [Item 2] The apparatus according to item 1, wherein the one or more inner vias are located in the central portion of the core substrate. [Item 3] The apparatus according to item 1, wherein the core substrate is located above the board, and the one or more inner vias and the more than one outer via extend in the xy plane and are parallel to the board. [Item 4] The apparatus according to item 3, wherein each annular segment has a length of 200 to 1000 microns and surrounds one or more inner vias. [Item 5] The aforementioned distance includes 10 microns to 50 microns, as described in item 3 of the apparatus. [Item 6] The apparatus described in item 1, wherein there are four or more individual annular segments. [Item 7] The apparatus according to item 1, wherein each of the one or more inner vias includes a diameter of 80 to 200 microns. [Item 8] The apparatus according to item 1, wherein the first lateral width includes 80 to 200 microns, and the second lateral width includes 80 to 200 microns. [Item 9] The apparatus according to item 1, wherein the one or more inner vias and the multiple outer vias comprise through-glass vias (TGVs) containing copper or a copper alloy, and the glass layer comprises one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica. [Item 10] The apparatus according to item 1, wherein one or more integrated circuit (IC) dies are bonded to the core substrate, the one or more inner vias and the multiple outer vias are bonded to the one or more IC dies, and a power supply is bonded to the one or more IC dies. [Item 11] The apparatus according to item 1, wherein the one or more inner vias include one or more signal vias, and the multiple outer vias include multiple ground vias. [Item 12] A first set of conductive vias having a circular shape; A second set of conductive vias surrounds the first set of conductive vias, the second set of conductive vias having a segmented annular ring shape; and A layer of glass surrounding the first set of conductive vias and the second set of conductive vias, The glass layer comprises, Having a first surface and a second surface opposite the first surface, the first set of conductive vias and the second set of conductive vias extend between the first surface and the second surface of the glass layer. Device. [Item 13] The apparatus according to item 12, wherein the lateral width of the first set of conductive vias includes 80 microns to 200 microns, and the lateral width of the second set of conductive vias includes 80 microns to 200 microns. [Item 14] The apparatus according to item 12, wherein the glass layer includes a glass core, the first set of conductive vias includes one or more signal vias, and the second set of conductive vias includes one or more ground vias. [Item 15] The apparatus according to item 14, wherein the glass core is located above the plate, the first set of conductive vias and the second set of conductive vias extend in the xy plane and are parallel to the plate, and each segment of the second set of conductive vias includes a length of 200 microns to 1000 microns. [Item 16] The apparatus according to item 12, wherein the first set of conductive vias and the second set of conductive vias are located on a build-up layer and bonded to one or more dies, the one or more dies being located above the glass layer. [Item 17] In the step of receiving the glass core, the glass core has a first surface and a second surface opposite to the first surface; A step of forming one or more circular openings within the glass core; The step of forming two or more segmented annular openings within the glass core so as to surround the circular opening, wherein the circular opening and the segmented annular openings extend between the first and second surfaces of the glass core; and Steps to fill the segmented annular opening and the circular opening with a conductive material. A method that includes [a certain feature]. [Item 18] The method according to item 17, wherein the step of filling the segmented annular opening and the circular opening comprises the step of forming a copper material or a copper alloy material within the segmented annular opening and the circular opening. [Item 19] The method according to item 17, wherein the glass core is located above the plate, the segmented annular opening extends in the xy plane and is parallel to the plate, the segmented annular opening includes four or more individual adjacent segments, and the four or more individual adjacent segments are spaced apart. [Item 20] The method according to item 19, wherein the one or more circular openings extend in the xy plane and are parallel to the plate, the diameter of the one or more circular openings includes 80 microns to 200 microns, and the length of the individual adjacent segments includes 200 microns to 1000 microns.

Claims

1. A core substrate, wherein the core substrate has a layer of glass; A plurality of outer vias extending through the glass layer, each having a first transverse width, and each having individual annular segments separated at a distance from each other; and One or more inner vias extending through the glass layer adjacent to the outer via, wherein the one or more inner vias have a second lateral width, and the first lateral width is greater than the second lateral width. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the one or more inner vias are located in the central portion of the core substrate.

3. The apparatus according to claim 1, wherein the core substrate is located above the plate, and the one or more inner vias and the more than one outer via extend in the x-y plane and are parallel to the plate.

4. The apparatus according to claim 1, wherein each annular segment has a length of 200 microns to 1000 microns and surrounds one or more inner vias.

5. The apparatus according to claim 1, wherein the distance is 10 microns to 50 microns.

6. The apparatus according to claim 1, wherein there are four or more individual annular segments.

7. The apparatus according to claim 1, wherein each of the one or more inner vias includes a diameter of 80 microns to 200 microns.

8. The apparatus according to claim 1, wherein the first lateral width includes 80 to 200 microns, and the second lateral width includes 80 to 200 microns.

9. The apparatus according to claim 1, wherein the one or more inner vias and the plurality of outer vias comprise through-glass vias (TGVs) containing copper or a copper alloy, and the glass layer comprises one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica.

10. The apparatus according to claim 1, wherein one or more integrated circuit (IC) dies are bonded to the core substrate, the one or more inner vias and the multiple outer vias are bonded to the one or more IC dies, and a power supply is bonded to the one or more IC dies.

11. The apparatus according to any one of claims 1 to 10, wherein the one or more inner vias include one or more signal vias, and the plurality of outer vias include a plurality of ground vias.

12. A first set of conductive vias having a circular shape; A second set of conductive vias surrounds the first set of conductive vias, the second set of conductive vias having a segmented annular ring shape; and A layer of glass surrounding the first set of conductive vias and the second set of conductive vias, The glass layer comprises, A first surface and a second surface opposite the first surface, wherein the first set of conductive vias and the second set of conductive vias extend between the first and second surfaces of the glass layer. Having, Device.

13. The apparatus according to claim 12, wherein the lateral width of the first set of conductive vias includes 80 microns to 200 microns, and the lateral width of the second set of conductive vias includes 80 microns to 200 microns.

14. The apparatus according to claim 12, wherein the glass layer includes a glass core, the first set of conductive vias includes one or more signal vias, and the second set of conductive vias includes one or more ground vias.

15. The apparatus according to claim 14, wherein the glass core is located above the plate, the first set of conductive vias and the second set of conductive vias extend in the x-y plane and are parallel to the plate, and each segment of the second set of conductive vias includes a length of 200 microns to 1000 microns.

16. The apparatus according to any one of claims 12 to 15, wherein the first set of conductive vias and the second set of conductive vias are located on a build-up layer and are bonded to one or more dies, the one or more dies being located above the glass layer.

17. In the step of receiving the glass core, the glass core has a first surface and a second surface opposite to the first surface; A step of forming one or more circular openings within the glass core; The step of forming two or more segmented annular openings within the glass core so as to surround the circular opening, wherein the circular opening and the segmented annular openings extend between the first and second surfaces of the glass core; and Steps to fill the segmented annular opening and the circular opening with a conductive material. A method that includes [a certain feature].

18. The method according to claim 17, wherein the step of filling the segmented annular opening and the circular opening comprises the step of forming a copper material or a copper alloy material within the segmented annular opening and the circular opening.

19. The method according to claim 17 or 18, wherein the glass core is located above the plate, the segmented annular opening extends in the x-y plane and is parallel to the plate, the segmented annular opening includes four or more individual adjacent segments, and the four or more individual adjacent segments are spaced apart.

20. The method according to claim 19, wherein the one or more circular openings extend in the x-y plane and are parallel to the plate, the diameter of the one or more circular openings includes 80 microns to 200 microns, and the length of each adjacent segment includes 200 microns to 1000 microns.

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