Semiconductor device and method for manufacturing the same

Abstract

To reduce the temperature rise in semiconductor devices. [Solution] The semiconductor element comprises a first electrode plate, a second electrode plate, a semiconductor laminated structure disposed between them, and a conductive member. In a direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor laminated structure, the lengths of the first electrode plate and the second electrode plate are greater than the length of the semiconductor laminated structure. The first semiconductor layer is electrically connected to the first electrode plate, and the second semiconductor layer is electrically connected to the second electrode plate. At least a portion of the conductive member is provided outside the semiconductor laminated structure in the aforementioned direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor laminated structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In order to further increase the light output of a semiconductor device that emits light or amplifies light, it is necessary to solve the problem of heat generated during operation. Patent Document 1 discloses a structure in which a semiconductor laser diode is sandwiched between a submount and a support substrate having an anisotropic thermal expansion coefficient in the in-plane direction. The semiconductor laser diode is joined to each of the submount and the support substrate by solder.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is required to dissipate heat generated inside the semiconductor device to the outside and reduce the temperature rise of the semiconductor device.

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same that can solve the above problems.

Means for Solving the Problems

[0006] In exemplary embodiments, the semiconductor device of this disclosure comprises a first electrode plate, a second electrode plate, a semiconductor stacked structure disposed between the first electrode plate and the second electrode plate, the semiconductor stacked structure comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer provided between the first semiconductor layer and the second semiconductor layer, and having a light-emitting end face, and a conductive member disposed between the first electrode plate and the second electrode plate. In a direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure, the lengths of the first electrode plate and the second electrode plate are greater than the length of the semiconductor stacked structure. The first semiconductor layer is electrically connected to the first electrode plate. The second semiconductor layer is electrically connected to the second electrode plate. At least a portion of the conductive member is provided outside the semiconductor stacked structure in the direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure.

[0007] A method for manufacturing a semiconductor device according to the present disclosure, in an exemplary embodiment, includes the steps of: preparing a plurality of semiconductor stacked structures, each comprising, in this order, a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type, disposed on a first substrate; bonding the plurality of semiconductor stacked structures onto a first conductive material substrate and removing the first substrate from the plurality of semiconductor stacked structures; arranging a conductive member on the first conductive material substrate, at least in a direction perpendicular to the stacking direction of the semiconductor stacked structures and outward from the semiconductor stacked structures; bonding a second conductive material substrate to the upper surface of the conductive member to produce a laminate including the plurality of semiconductor stacked structures and the conductive member between the first conductive material substrate and the second conductive material substrate; dividing the laminate to obtain a plurality of bars from the laminate, each of which includes a part of the plurality of semiconductor stacked structures; and framing the plurality of bars to obtain a plurality of semiconductor devices, each having a part of the plurality of semiconductor stacked structures. [Effects of the Invention]

[0008] According to embodiments of this disclosure, it becomes possible to dissipate the heat generated in the semiconductor device to the outside and reduce the temperature rise in the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic perspective view showing an example of the configuration of a semiconductor device in an embodiment of this disclosure. [Figure 2] Figure 2 is an exploded perspective view that clearly shows a portion of the semiconductor device configuration example shown in Figure 1. [Figure 3] Figure 3 is a schematic perspective view showing the cutting process of graphite. [Figure 4] Figure 4 is a perspective view showing an example of the arrangement relationship between the first electrode plate formed from a graphite layer and the semiconductor multilayer structure. [Figure 5] Figure 5 is a perspective view showing another example of the arrangement relationship between the first electrode plate and the semiconductor stacked structure. [Figure 6] Figure 6 is a plan view showing an example of the arrangement relationship between the first electrode plate and the semiconductor stacked structure. [Figure 7] Figure 7 is a side view of the arrangement shown in Figure 6, viewed from the Y-axis direction. [Figure 8] Figure 8 is a side view of the arrangement shown in Figure 6, viewed from the Z-axis direction. [Figure 9] Figure 9 is a perspective view showing an example of a semiconductor stacked structure configuration. [Figure 10A] Figure 10A is a schematic plan view illustrating an example in which a semiconductor multilayer structure functions as a laser resonator. [Figure 10B] Figure 10B is a schematic plan view illustrating an example in which a semiconductor stacked structure functions as a laser light amplifier. [Figure 11] Figure 11 is a plan view showing an example of the shape of the active layer in a configuration in which the semiconductor multilayer structure has both a laser resonator and a laser light amplifier. [Figure 12] Figure 12 is a perspective view showing an example configuration of a semiconductor device in which a semiconductor stacked structure has both a laser resonator and a laser light amplifier. [Figure 13A] FIG. 13A is a cross-sectional view parallel to the XY plane at Z = Z1 of the semiconductor device of FIG. 12. [Figure 13B] FIG. 13B is a cross-sectional view parallel to the XY plane at Z = Z2 of the semiconductor device of FIG. 12. [Figure 13C] FIG. 13C is a cross-sectional view parallel to the XY plane at Z = Z3 of the semiconductor device of FIG. 12. [Figure 14A] FIG. 14A is a cross-sectional view parallel to the YZ plane at X = X3 of the semiconductor device of FIG. 12. [Figure 14B] FIG. 14B is a cross-sectional view parallel to the YZ plane at X = X2 of the semiconductor device of FIG. 12. [Figure 14C] FIG. 14C is a cross-sectional view parallel to the YZ plane at X = X1 of the semiconductor device of FIG. 12. [Figure 14D] FIG. 14D is a cross-sectional view of the semiconductor device of FIG. 12 in a plane including the upper surface of the conductive member. [Figure 15] FIG. 15 is a cross-sectional view in a plane parallel to the XZ plane of the semiconductor device of FIG. 12. [Figure 16] FIG. 16 is a cross-sectional view in a plane parallel to the XZ plane in a modified example of the semiconductor device of FIG. 12. [Figure 17] FIG. 17 is a cross-sectional view in a plane parallel to the XZ plane in another modified example of the semiconductor device of FIG. 12. [Figure 18] FIG. 18 is a cross-sectional view in a plane parallel to the XZ plane in yet another modified example of the semiconductor device of FIG. 12. [Figure 19A] FIG. 19A is a cross-sectional view schematically showing the process in the present embodiment. [Figure 19B] FIG. 19B is a cross-sectional view schematically showing the process in the present embodiment. [Figure 19C] FIG. 19C is a cross-sectional view schematically showing the process in the present embodiment. [Figure 19D] FIG. 19D is a cross-sectional view schematically showing the process in the present embodiment. [Figure 19E] FIG. 19E is a cross-sectional view schematically showing the process in the present embodiment. [Figure 19F] Figure 19F is a schematic cross-sectional view showing the process in this embodiment. [Figure 19G] Figure 19G is a schematic cross-sectional view showing the process in this embodiment. [Figure 19H] Figure 19H is a schematic cross-sectional view showing the process in this embodiment. [Figure 19I] Figure 19I is a schematic cross-sectional view showing the process in this embodiment. [Figure 19J] Figure 19J is a schematic cross-sectional view showing the process in this embodiment. [Figure 19K] Figure 19K is a schematic plan view illustrating the process in this embodiment. [Figure 19L] Figure 19L is a schematic perspective view showing the process in this embodiment. [Figure 19M] Figure 19M is a schematic perspective view showing the process in this embodiment. [Figure 19N] Figure 19N is a schematic perspective view showing the process in this embodiment. [Modes for carrying out the invention]

[0010] The following describes a basic configuration example of a semiconductor device in an embodiment of this disclosure with reference to the attached drawings. For reference, the drawings schematically show mutually orthogonal X, Y, and Z axes.

[0011] (Structure of semiconductor devices) First, the configuration of the semiconductor element in this embodiment will be schematically described with reference to Figures 1 and 2. Figure 1 is a schematic perspective view showing an example of the configuration of the semiconductor element 100 in this embodiment. Figure 2 is an exploded perspective view that clearly shows a part of the configuration of the semiconductor element 100.

[0012] The semiconductor element 100 comprises a first electrode plate 11, a second electrode plate 12, and a semiconductor stacked structure 20 disposed between the first electrode plate 11 and the second electrode plate 12. As shown in Figure 2, the semiconductor stacked structure 20 includes a first semiconductor layer 21 of a first conductivity type, a second semiconductor layer 22 of a second conductivity type, and an active layer 23 provided between the first semiconductor layer 21 and the second semiconductor layer 22. The first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22 are stacked in the X-axis direction. That is, the stacking direction of the semiconductor stacked structure 20 is the X-axis direction. The stacking direction of the semiconductor stacked structure 20 can be a direction perpendicular to the main surface of any one of the layers among the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22. The semiconductor stacked structure 20 also has a light-emitting end face 24. As shown in Figure 1, the semiconductor element 100 further includes a conductive member 40 disposed between the first electrode plate 11 and the second electrode plate 12.

[0013] The lengths of the first electrode plate 11 and the second electrode plate 12 in the lateral direction (Y-axis direction) parallel to the light-emitting end face 24 are greater than the length of the semiconductor stack structure 20 in the lateral direction (Y-axis direction). The Y-axis direction is parallel to the light-emitting end face 24 and perpendicular to the stacking direction of the semiconductor stack structure 20. The first semiconductor layer 21 is electrically connected to the first electrode plate 11, and the second semiconductor layer 22 is electrically connected to the second electrode plate 12. At least a portion of the conductive member 40 is provided outside the semiconductor stack structure 20 in the lateral direction (Y-axis direction) parallel to the light-emitting end face 24.

[0014] The semiconductor element 100 includes a first electrode plate 11 and a second electrode plate 12 that function as heat dissipation blocks above and below the semiconductor stacked structure 20, and also includes a conductive member 40 that connects the first electrode plate 11 and the second electrode plate 12. Therefore, it is easy to dissipate the heat generated by the semiconductor stacked structure 20 to an external heat sink or the like. With a semiconductor element 100 having such a configuration, it is possible to reduce the temperature rise and further increase the output of light emission.

[0015] The following describes in detail each component of the semiconductor device 100.

[0016] <First and second electrode plates> As shown in Figure 2, the first electrode plate 11 has an upper surface 11A and a lower surface 11B. The second electrode plate 12 has an upper surface 12A and a lower surface 12B. In this example, the first electrode plate 11 and the second electrode plate 12 are arranged approximately parallel to each other at a predetermined distance apart. In other words, there is a distance between the upper surface 11A of the first electrode plate 11 and the lower surface 12B of the second electrode plate 12 that is greater than or equal to the height of the semiconductor laminated structure 20 (for example, 1.5 μm to 3 μm). In Figures 1 and 2, the distance from the upper surface 11A of the first electrode plate 11 to the lower surface 12B of the second electrode plate 12 is depicted as being approximately the same in size as the respective thicknesses of the first electrode plate 11 and the second electrode plate 12. The first electrode plate 11 and the second electrode plate 12 are each rigid members that can stand on their own. The first electrode plate 11 and the second electrode plate 12 may have a thickness greater than the distance from the upper surface 11A of the first electrode plate 11 to the lower surface 12B of the second electrode plate 12.

[0017] In the illustrated example, both the first electrode plate 11 and the second electrode plate 12 have a uniform size (thickness) along the Y-axis and Z-axis directions, respectively. Furthermore, the thickness (size in the X-axis direction) of the first electrode plate 11 and the second electrode plate 12 is smaller than their respective sizes in the Y-axis direction and Z-axis direction. The shapes of the first electrode plate 11 and the second electrode plate 12 are not limited to those of the illustrated example. In a plan view from the X-axis direction, the shapes of the first electrode plate 11 and the second electrode plate 12 are not limited to rectangles or squares, but may be polygons such as rhombuses, parallelograms, or hexagons. In addition, in a plan view, each of the first electrode plate 11 and the second electrode plate 12 may have rounded corners, notches, recesses, protrusions, or openings.

[0018] The upper surface 11A and lower surface 11B of the first electrode plate 11, and the upper surface 12A and lower surface 12B of the second electrode plate 12, do not need to be flat and may have a textured structure such as fine irregularities or grooves. If the upper surface 11A and lower surface 11B of the first electrode plate 11, and the upper surface 12A and lower surface 12B of the second electrode plate 12 are flat, there is the advantage that the semiconductor device 100 is easier to manufacture.

[0019] According to the embodiments of the manufacturing method described later in this disclosure, in a plan view, the shape and size of the first electrode plate 11 are the same as the shape and size of the second electrode plate 12. However, according to other manufacturing methods, the shape or size of the first electrode plate 11 may differ from the shape or size of the second electrode plate 12.

[0020] In this disclosure, the term "plate" does not require that its thickness (size in the X-axis direction) be smaller than its size in the other directions (Y-axis and Z-axis directions). The thickness (size in the X-axis direction) of the first electrode plate 11 and the second electrode plate 12 may be equal to or greater than their size in the other directions (Y-axis and Z-axis directions). Therefore, the first electrode plate 11 and the second electrode plate 12 may have a shape that can be referred to as a "block".

[0021] In this disclosure, "plate" is defined as a structure having surfaces that extend laterally on both sides than the semiconductor stacked structure 20 in a plan view along the X-axis. In the example shown in Figures 1 and 2, the upper surface 11A of the first electrode plate 11 has a region that extends outward in the positive Y-axis direction and a region that extends outward in the negative Y-axis direction, relative to the semiconductor stacked structure 20. Similarly, the lower surface 12B of the second electrode plate 12 has a region that extends outward in the positive Y-axis direction and a region that extends outward in the negative Y-axis direction, relative to the semiconductor stacked structure 20. In other words, the length of the first electrode plate 11 and the second electrode plate 12 in the lateral direction (Y-axis direction) parallel to the light-emitting end face 24 is greater than the length of the semiconductor stacked structure 20 in the lateral direction (Y-axis direction). In this way, by arranging structures having surfaces that extend outward (on both sides) from the semiconductor stacked structure 20 above and below the semiconductor stacked structure 20, it becomes possible to provide the conductive member 40 outside the semiconductor stacked structure 20 in the lateral direction (in this example, the Y-axis direction) parallel to the light-emitting end face 24 of the semiconductor stacked structure 20. The role of such conductive member 40 will be described later.

[0022] The first electrode plate 11 is electrically connected to the first semiconductor layer 21 and functions as the first electrode of the semiconductor multilayer structure 20. Similarly, the second electrode plate 12 is electrically connected to the second semiconductor layer 22 and functions as the second electrode of the semiconductor multilayer structure 20. Other conductive layers or other members may be present between the first electrode plate 11 and the first semiconductor layer 21. Similarly, other conductive layers or other members may be present between the second electrode plate 12 and the second semiconductor layer 22.

[0023] The first electrode plate 11 and the second electrode plate 12 are both conductive so as to function as "electrodes" that can be connected to an external circuit. Each of the first electrode plate 11 and the second electrode plate 12 may include an insulating portion in part (e.g., on the surface). In this case, the insulating portion is arranged so that the first electrode plate 11 and the second electrode plate 12 function as electrode plates. Each of the first electrode plate 11 and the second electrode plate 12 may be formed entirely from a conductive material. Each of the first electrode plate 11 and the second electrode plate 12 may have a laminated structure or be formed from a composite material. The material and structure of the first electrode plate 11 may differ from the material and structure of the second electrode plate 12.

[0024] Next, specific examples of the first electrode plate 11 and the second electrode plate 12 will be described with reference to Figures 3, 4, and 5. In this example, each of the first electrode plate 11 and the second electrode plate 12 is formed from graphite. The first electrode plate 11 will be described below.

[0025] First, refer to Figure 3. Figure 3 is a schematic perspective view showing a portion of graphite 10A that can be formed, for example, by CVD (chemical vapor deposition). Graphite 10A has a structure in which multiple graphene G are stacked in a predetermined direction. Each graphene G is a sheet-like material having a two-dimensional crystalline structure in which carbon atoms are located at the vertices of a hexagon. The thickness (interlayer distance) of graphene G is approximately 0.3 nm, but the thickness of graphene G is exaggerated in the drawing. Van der Waals forces act between adjacent graphene G. Graphite 10A has a significantly different thermal conductivity between the in-plane direction in which the graphene G spreads and the direction across the stacked graphene G. The thermal conductivity in the in-plane direction in which the graphene G spreads can exceed, for example, 1000 W / m·K and reach, for example, 1700 W / m·K. In contrast, the thermal conductivity in the direction across the stacked graphene G is, for example, less than 10 W / m·K.

[0026] In this embodiment, multiple graphite layers 10B can be produced from a single graphite 10A by slicing the graphite 10A. The dotted line in Figure 3 schematically shows the position of one cross-section in the graphite 10A.

[0027] Figure 4 is a perspective view showing an example of the arrangement relationship between the first electrode plate 11 formed from the graphite layer 10B and the semiconductor multilayer structure 20. The semiconductor multilayer structure 20 is positioned on the upper surface of the graphite layer 10B such that the light-emitting end face 24 aligns with the end face of the graphite layer 10B. In this arrangement, the thermal conductivity of the graphite layer 10B is X Y The thermal conductivity is high in the in-plane direction and low in the Z-axis direction. Therefore, the heat generated in the semiconductor laminated structure 20 is rapidly conducted in the X-axis and Y-axis directions through the graphite layer 10B that constitutes the first electrode plate 11. When the lower surface 11B of the first electrode plate 11 is in thermal contact with the heat sink, the heat generated in the semiconductor laminated structure 20 flows through the first electrode plate 11 along the XY plane to the lower surface 11B and dissipates from the heat sink to the outside.

[0028] Figure 5 is a perspective view showing another example of the first electrode plate 11. In this example, the first electrode plate 11 includes a graphite layer 10B and a top layer 10C that covers the upper surface of the graphite layer 10B. The top layer 10C may function to enhance the "wettability" between the upper surface 11A of the first electrode plate 11 and the conductive member 40 when the conductive member 40 is formed on the first electrode plate 11. If the wettability between the graphite layer 10B and the metallic material is low, the wettability between the graphite layer 10B and the metallic material can be enhanced by depositing a top layer 10C, formed from a metal such as titanium (Ti) or a semiconductor such as silicon (Si), on the graphite layer 10B. The top layer 10C may be formed from a highly thermally conductive material that does not obstruct the flow of heat. Other layers may be provided on the lower surface 11B side of the first electrode plate 11. Since the lower surface 11B of the first electrode plate 11 is in contact with, for example, a water-cooled heat sink, the layer provided on the lower surface 11B of the first electrode plate 11 may also be formed from a highly thermally conductive material that does not obstruct the flow of heat.

[0029] In the examples shown in Figures 4 and 5, laser light L is emitted in the Z-axis direction from the light-emitting end face 24 of the semiconductor stacked structure 20. The light-emitting end face 24 is parallel to the plane on which the graphene G of the first electrode plate 11 extends. In other words, when the first electrode plate 11 has thermal conductivity anisotropy, the light-emitting end face 24 is parallel to the direction in which the thermal conductivity is relatively high. However, in embodiments of this disclosure, the orientation of the light-emitting end face 24 is not limited to this example.

[0030] The second electrode plate 12 may have a structure similar to that of the first electrode plate 11. For example, the second electrode plate 12 may be formed from the graphite layer 10B shown in Figure 3. In that case, the stacking direction of the graphite layer 10B of the second electrode plate 12 does not need to be parallel to the stacking direction of the graphite layer 10B of the first electrode plate 11, and may be orthogonal. The second electrode plate 12 does not need to be formed from the same material as the first electrode plate 11. Since the graphite layer 10B is excellent as a material for dissipating heat generated in the semiconductor laminated structure 20 to the outside, applying it not only to the first electrode plate 11 but also to the second electrode plate 12 can effectively reduce excessive temperature rise during operation of the semiconductor element 100. Thus, one or both of the first electrode plate 11 and the second electrode plate 12 may include graphite in which multiple graphenes are stacked in the direction normal to the light-emitting end face 24.

[0031] Figure 6 is a plan view showing an example of the arrangement relationship between the first electrode plate 11 and the semiconductor stacked structure 20. Figure 7 is a side view of the arrangement in Figure 6 as seen from the Y-axis direction, and Figure 8 is a side view of the arrangement in Figure 6 as seen from the Z-axis direction.

[0032] As shown in Figure 6, the first electrode plate 11 in this embodiment has extended regions 11e, 11f, and 11g that extend outward from the semiconductor stacked structure 20 in a plan view. As shown in Figure 8, the first extended region 11e is located on one side relative to the region directly below the semiconductor stacked structure 20, and the second extended region 11f is located on the other side relative to the region directly below the semiconductor stacked structure 20. In this embodiment, as shown in Figure 8, the size y1 of the first electrode plate 11 in the Y-axis direction is larger than the size y0 of the semiconductor stacked structure 20 in the Y-axis direction. In this example, the size y2 of the first extended region 11e in the Y-axis direction is larger than the size y0 of the semiconductor stacked structure 20 in the Y-axis direction. Also, the size y3 of the second extended region 11f in the Y-axis direction is larger than the size y0 of the semiconductor stacked structure 20 in the Y-axis direction. However, sizes y2 and y3 may each be smaller than size y0.

[0033] Because the first electrode plate 11 has a first extended region 11e and a second extended region 11f, heat generated in the semiconductor stacked structure 20 flows quickly through the first electrode plate 11 and is easily dissipated to the outside. Furthermore, the contact area between the lower surface 11B of the first electrode plate 11 and the heat sink can be increased. This increased contact area promotes heat dissipation by the heat sink.

[0034] In the examples shown in Figures 6 and 7, the size z1 of the first electrode plate 11 in the Z-axis direction is greater than the size z0 of the semiconductor stacked structure 20 in the Z-axis direction. In other words, the size z2 of the third extension region 11g in the Z-axis direction is greater than 0. However, if the first electrode plate 11 is formed from the graphite layer 10B described above, due to the anisotropy of thermal conductivity, heat generated in the semiconductor stacked structure 20 does not easily flow to the third extension region 11g. Therefore, if the first electrode plate 11 is formed from a graphite layer 10B having such anisotropy of thermal conductivity, the third extension region 11g may be omitted. If the third extension region 11g is absent, the end face opposite the light-emitting end face 24 of the semiconductor stacked structure 20 aligns with the side surface of the first electrode plate 11.

[0035] As can be seen from Figure 8, in order to enhance the heat dissipation function of the first extended region 11e and the second extended region 11f, it is preferable to increase the thermal conductivity between the heat-generating portion (active layer) of the semiconductor laminated structure 20 and the first extended region 11e or the second extended region 11f. In the embodiments of this disclosure, the conductive member 40 contributes to increasing the thermal conductivity between the heat-generating portion (active layer) of the semiconductor laminated structure 20 and the first extended region 11e or the second extended region 11f. As shown in Figure 1, the conductive member 40 also contributes to improving the thermal conductivity between the second electrode plate 12 and the semiconductor laminated structure 20. Therefore, by thermally contacting the upper surface 12A (see Figure 2) of the second electrode plate 12 with the heat sink, it becomes possible to achieve an even higher heat dissipation effect than by thermally contacting only the lower surface 11B of the first electrode plate 11 with the heat sink. Thus, in the embodiments of this disclosure, not only are the first electrode plate 11 and the second electrode plate 12 formed from a material with high thermal conductivity, but the heat dissipation is further enhanced by the conductive member 40 provided on the side of the semiconductor laminated structure 20.

[0036] Furthermore, if the top layer 10C in the example of Figure 5 is formed from a material having a thermal conductivity sufficiently higher than, for example, the thermal conductivity of the graphite layer 10B in the Z-axis direction (e.g., approximately 7 W / m·K), the top layer 10C can function as a heat spreader and contribute to heat conduction in the Z-axis direction. When such a top layer 10C is used, the heat generated in the semiconductor laminated structure 20 is also conducted to the third extended region 11g of the first electrode plate 11, improving heat dissipation. The top layer 10C may be made of, for example, copper, aluminum, or silver.

[0037] <Laminated semiconductor structure 20> The semiconductor multilayer structure 20 functions as a semiconductor light-emitting part, such as a laser resonator, or as a waveguide part of a semiconductor optical amplifier. In the illustrated example, the direction in which light is guided within the semiconductor multilayer structure 20 is the Z-axis direction. A single semiconductor multilayer structure 20 may also include both a semiconductor light-emitting part and a waveguide part. In other words, the semiconductor multilayer structure 20 constitutes at least one of a laser resonator and a laser optical amplifier. In this disclosure, the term “semiconductor multilayer structure” means a single-chip structure produced by fractionating a wafer-like multilayer structure having multiple layers of semiconductor crystals grown on a wafer-like substrate. Such a structure may be called a “die”. The semiconductor multilayer structure may include layers of insulators and layers of conductors in addition to semiconductor layers. The semiconductor multilayer structure 20 may be, for example, a nitride semiconductor, or an arsenide semiconductor, or a phosphide semiconductor.

[0038] The "first conductivity type" is one of the p-type and n-type that define the conductivity type of a semiconductor, and the "second conductivity type" is the other of the p-type and n-type. The semiconductor stacked structure 20 includes a first semiconductor layer 21 of the first conductivity type, a second semiconductor layer 22 of the second conductivity type, and an active layer 23 provided between the first semiconductor layer 21 and the second semiconductor layer 22. The active layer 23 may have a quantum well structure.

[0039] The first semiconductor layer 21 of the first conductivity type and the second semiconductor layer 22 of the second conductivity type do not need to have a uniform semiconductor composition or dopant concentration in the depth direction, and may have a depth-direction distribution.

[0040] The semiconductor multilayer structure 20 has a light-emitting end face 24. Light is emitted from the light-emitting end face 24. When at least a part of the semiconductor multilayer structure 20 functions as a laser resonator, during operation, laser oscillation occurs within the laser resonator including the active layer 23, and laser light is emitted from the light-emitting end face 24. When the semiconductor multilayer structure 20 does not function as a laser resonator but functions as a laser light amplifier, the other end face of the semiconductor multilayer structure 20 receives laser light from the outside, amplifies it within the active layer 23, and emits laser light from the light-emitting end face 24.

[0041] In the example shown in Figure 1, the semiconductor element 100 further includes an insulating layer 30 disposed between the conductive member 40 and the semiconductor multilayer structure 20. The insulating layer 30 has an opening in at least a portion of the upper part of the second semiconductor layer 22 of the semiconductor multilayer structure 20. The insulating layer 30 provides electrical insulation between the conductive member 40 and the first semiconductor layer 21.

[0042] The example configuration of the semiconductor stacked structure 20 shown in the figure is merely one example, and it may have more complex and diverse configurations. In the semiconductor device of this disclosure, the layer structure, shape, and size of the semiconductor stacked structure 20 are not limited to the example shown.

[0043] Figure 9 is a perspective view showing an example configuration of a semiconductor stacked structure 20. In this example, the semiconductor stacked structure 20 has a ridge along the Z-axis direction, and an active layer 23 and a second semiconductor layer 22 are provided within the ridge. The first semiconductor layer 21 may have a semiconductor substrate and a plurality of semiconductor layers provided on the semiconductor substrate. The second semiconductor layer 22 may also include a plurality of semiconductor layers. A contact layer is located at the top of the second semiconductor layer 22. In the example of Figure 9, the ridge includes the active layer 23. In the example of Figure 9, the semiconductor stacked structure 20 has a perfect refractive index type laser element structure. The ridge may be formed on the upper part of the second semiconductor layer 22. An insulating layer (second insulating layer) 25 covering the sides of the ridge is provided on the first semiconductor layer 21. The ridge may be formed only on a part of the second semiconductor layer 22.

[0044] The width of the ridge in the Y-axis direction may be such that it forms a multimode waveguide. This allows for multiple modes, making it possible to extract laser light with a higher output compared to a single-mode waveguide. Furthermore, while multimode waveguides require more heat dissipation due to their higher output, the configuration of this embodiment allows heat to be dissipated from either the first electrode plate 11 or the second electrode plate 12, enabling efficient heat dissipation.

[0045] A metal layer (electrode) 26 is provided on the second semiconductor layer 22. The metal layer 26 and the first semiconductor layer 21 are electrically insulated by an insulating layer 25. The electrode does not have to be a metal layer 26. The electrode may be a conductive oxide layer.

[0046] The configuration shown in Figure 9 is merely one example of the semiconductor stacked structure 20, and the configuration of the semiconductor stacked structure 20 is arbitrary.

[0047] The insulating layer (first insulating layer) 30 shown in Figure 1 is provided to cover a portion of the top surface and side surface of the semiconductor stacked structure 20 shown in Figure 9. The first insulating layer 30 is provided with stripe-shaped openings 27 that expose a portion of the top surface of the ridge. The openings 27 of the first insulating layer 30 enable electrical connection between the second electrode plate 12 and the second semiconductor layer 22 of the semiconductor stacked structure 20.

[0048] The configuration of the semiconductor stacked structure 20 is not limited to this example. Multiple ridges may be provided on a single first semiconductor layer 21. Each of the multiple ridges may include a second semiconductor layer 22. The first semiconductor layer 21 may include a crystal growth substrate in part.

[0049] Figure 9 is a schematic perspective view showing an example configuration of a semiconductor multilayer structure 20 that can function as a laser resonator. When the semiconductor multilayer structure 20 functions as a laser light amplifier, the size (width) of the ridge including the second semiconductor layer 22 and the active layer 23 in the Y-axis direction may vary depending on its position in the Z-axis direction.

[0050] Figure 10A is a schematic plan view showing an example in which the semiconductor multilayer structure 20 functions as a laser resonator 28. Figure 10B is a schematic plan view showing an example in which it functions as a laser light amplifier 29. Both semiconductor multilayer structures 20 have a first end face 20A and a second end face 20B. The first end face 20A is the light emission end face 24. When the semiconductor multilayer structure 20 functions as a laser resonator 28, the first end face 20A and the second end face 20B form the reflective surfaces of the laser resonator 28. For this reason, a reflective film that reflects light of the laser oscillation wavelength may be provided on each of the first end face 20A and the second end face 20B. In contrast, when the semiconductor multilayer structure 20 functions as a laser light amplifier 29, light is incident into the active layer 23 from the second end face 20B, the light is amplified and emitted from the first end face 20A. In this case, a film that transmits light of the laser oscillation wavelength (anti-reflective film) may be provided on each of the first end face 20A and the second end face 20B.

[0051] Furthermore, the laser resonator 28 is not limited to a Fabry-Perot type resonator, but may also be a distributed feedback type resonator. In the case of a distributed feedback type resonator, the semiconductor multilayer structure 20 includes a distributed Bragg reflector inside.

[0052] In the configuration example shown in Figure 10B, the active layer 23 functions as a waveguide for the laser light amplifier 29. In this example, the width (size in the Y-axis direction) of the active layer 23 increases in an inverse tapered manner as it approaches the light emission end face 24. By having such an inverse tapered waveguide portion in the semiconductor stacked structure 20, the saturation of the optical output is reduced, making it possible to emit a higher output light beam. The width of the active layer 23 may be uniform.

[0053] In the configuration example shown in Figure 10A, the second end face 20B of the semiconductor stacked structure 20 is covered by the conductive member 40. Even when the semiconductor stacked structure 20 functions as a laser resonator 28, the second end face 20B may extend to the end of the first electrode plate 11.

[0054] Figure 11 is a schematic plan view illustrating an example of the shape of the active layer 23 in a configuration in which the semiconductor multilayer structure 20 has both a laser resonator 28 and a laser light amplifier 29. This combination of laser resonator 28 and laser light amplifier 29 is also called MOPA (Master Oscillator Power Amplifier). In this example, the active layer 23 includes a first region 23A that functions as the laser resonator 28 and a second region 23B that functions as the laser light amplifier 29. The laser resonator 28 may be configured to oscillate at a wavelength selected by a Bragg reflector formed in the first semiconductor layer 21. In the illustrated example, the active layer 23 is continuous between the first region 23A and the second region 23B, but the first region 23A and the second region 23B may be separated by air, other dielectric material, etc. In that case, optical coupling is achieved so that the laser light generated in the laser resonator 28 can be incident on the laser light amplifier 29 through the dielectric material. The laser light propagated from the laser resonator 28 to the laser light amplifier 29 by optical coupling is amplified as it travels through the laser light amplifier in the Z-axis direction and is emitted to the outside from the light emission end face 24.

[0055] Figure 12 is a perspective view showing an example configuration of a semiconductor element 100 in which the semiconductor stacked structure 20 has both a laser resonator 28 and a laser light amplifier 29. Figure 13A is a cross-sectional view of the semiconductor element 100 in Figure 12 at Z=Z1. Figure 13B is a cross-sectional view at Z=Z2. Figure 13C is a cross-sectional view at Z=Z3. Note that in Figure 12, Z=Z1 is at the position of the first end face 20A (light-emitting end face 24) of the semiconductor stacked structure 20, and Z=0 is at the position of the second end face 20B.

[0056] As shown in Figure 13A, there are materials with excellent thermal conductivity above, below, and to the left and right of the semiconductor stacked structure 20, allowing heat generated in the semiconductor stacked structure 20 to dissipate easily. As shown in Figures 13A and 13C, the cross-sectional shape and size of the semiconductor stacked structure 20 may vary depending on its position in the Z-axis direction.

[0057] As shown in Figure 13B, the insulating isolation layer 16 extends to the insulating layer 30 on the first electrode plate 11. The insulating isolation layer 16 may also penetrate the insulating layer 30 and be in contact with the first electrode plate 11. Furthermore, the bottom of the groove filled by the insulating isolation layer 16 may be located inside the first electrode plate 11.

[0058] In the semiconductor device 100 shown in Figure 12, the semiconductor stacked structure 20 is continuous in at least part and constitutes a laser resonator and a laser light amplifier. The light-emitting end face 24 is the end face of the waveguide portion of the laser light amplifier. The laser resonator and the laser light amplifier are optically coupled inside the semiconductor device 100.

[0059] The second electrode plate 12 comprises a first region 14 on the laser resonator that is electrically connected to the laser resonator, and a second region 15 on the laser light amplifier that is electrically connected to the laser light amplifier. The first region 14 and the second region 15 of the second electrode plate 12 are conductive, but the first region 14 and the second region 15 are electrically insulated from each other. In this embodiment, a groove is formed between the first region 14 and the second region 15, and this groove is filled with an insulating separation layer 16.

[0060] In the example shown in Figure 12, a first electrode 14E is provided on the first region 14 of the second electrode plate 12, and a second electrode 15E is provided on the second region 15. Furthermore, a third electrode 17E is provided on the lower surface of the first electrode plate 11. These electrodes 14E, 15E, and 17E are formed from, for example, layers of metal. The first electrode 14E and the second electrode 15E can be connected to a drive circuit by gold or silver wires, respectively. The drive circuit can independently control the voltage applied between the first electrode 14E and the third electrode 17E, and the voltage applied between the second electrode 15E and the third electrode 17E. Therefore, the laser oscillation in the laser resonator 28 and the optical amplification by the laser light amplifier 29 can be controlled independently.

[0061] The semiconductor device 100 shown in Figure 12 has a junction layer 60 between the conductive member 40 and the second electrode plate 12. The structure and role of the junction layer 60 will be described below.

[0062] Figures 14A, 14B, and 14C are cross-sectional views of the semiconductor element 100 of Figure 12 parallel to the YZ plane at X=X3, X=X2, and X=X1, respectively. Figure 14D is a cross-sectional view of the semiconductor element 100 in a plane including the upper surface of the conductive member 40. In the cross-section of Figure 14D, the bonding layer 60 is in contact with the upper surface of the conductive member 40. If an electrode is provided on the upper surface of the semiconductor stacked structure 20, a portion of the bonding layer 60 may be in contact with the upper surface of this electrode.

[0063] In the semiconductor device 100 shown in Figure 12, the second electrode plate 12 is located at a height of X=X3. The junction layer 60 is located at a height of X=X2, and the active layer 23 is located at a height of X=X1.

[0064] In the second electrode plate 12, as shown in Figure 14A, an insulating separation layer 16 is located between the first region 14 and the second region 15, and the first region 14 and the second region 15 are insulated and separated.

[0065] Referring to Figure 14B, the bonding layer 60 has a first bonding region 60A, a second bonding region 60B, a third bonding region 60C, a fourth bonding region 60D, and an insulating region 60X. The bonding layer 60 contains at least a metal. The insulating region 60X is located above the insulating layer 30 in Figure 14D. The insulating layer 30 shown in Figure 14D corresponds to the uppermost surface of the insulating layer 30 in Figure 9 and is provided along the edge of the active layer 23. In this example, the height of the uppermost surface of the insulating layer 30 shown in Figure 9 is equal to the height of the upper surface of the conductive member 40, which is not shown in Figure 9. In other words, the upper surface of the conductive member 40 and the upper surface of the insulating layer 30, which is located in part of the second semiconductor layer 22, are flush. The bonding layer 60 is in contact with the upper surface of the conductive member 40 and the upper surface of the insulating layer 30, which are flush with each other. The parts of the bonding layer 60 other than the insulating region 60X are conductive. Therefore, the second electrode plate 12 is electrically and thermally connected to the upper surface of the conductive member 40 and the upper surface of the insulating layer 30 via the bonding layer 60. The thickness of the bonding layer 60 can be 10 nm or less.

[0066] In this embodiment, the upper surface of the conductive member 40 and the upper surface of the insulating layer 30 are flush. The bonding of the second electrode plate 12 and the conductive member 40 may be performed, for example, by interatomic bonding between the atoms constituting the second electrode plate 12 and the atoms constituting the conductive member 40. With such bonding, the second electrode plate 12 and the conductive member 40 can be bonded without providing a bonding layer between them, thus suppressing the decrease in heat dissipation performance caused by providing a bonding layer. Such bonding of the second electrode plate 12 and the conductive member 40 can be achieved, for example, by atomic diffusion bonding (ADB).

[0067] In this example, the bonding layer 60 (see Figure 14B) can be formed by metal film deposition technology. However, as a result of oxidation reactions occurring during the deposition process or subsequent manufacturing processes, a portion of the metal film selectively transforms into a metal oxide in areas where the substrate is an oxide layer. In this embodiment, the insulating layer 30 is an oxide such as SiO2. Therefore, at least a portion of the bonding layer 60 that contacts the insulating layer 30 comprises an insulating region 60X formed from the oxide of the metal constituting the bonding layer 60. Such a structure of bonding layer 60 allows for the provision of the insulating region 60X in a simple process. On the other hand, the first bonding region 60A, second bonding region 60B, third bonding region 60C, and fourth bonding region 60D of the bonding layer 60 (see Figure 14B) in areas where the substrate is a semiconductor or metal remain in their metal-formed state and possess conductivity.

[0068] The insulating region 60X can electrically separate the first bonding region 60A and the third bonding region 60C in the bonding layer 60. Furthermore, the insulating region 60X can electrically separate the second bonding region 60B and the fourth bonding region 60D in the bonding layer 60.

[0069] Furthermore, since the insulating isolation layer 16 extends from the second electrode plate 12 to the first electrode plate 11, the semiconductor element 100 is electrically isolated between the laser resonator 28 and the laser light amplifier 29. As a result, the first junction region 60A and the second junction region 60B are also electrically isolated by the insulating isolation layer 16, allowing the laser oscillation in the laser resonator 28 and the optical amplification by the laser light amplifier 29 to be controlled independently. In addition, leakage current flow between the first electrode 14E and the second electrode 15E can be suppressed.

[0070] In this embodiment, the active layer 23 is not separated by the insulating isolation layer 16, as shown in Figure 14C. Therefore, laser light can propagate between the laser resonator 28 and the laser light amplifier 29 of the semiconductor element 100 through a waveguide that includes the active layer 23 in a portion of the core.

[0071] <Conductive member 40> The conductive member 40 is positioned between the first electrode plate 11 and the second electrode plate 12. In the embodiments of this disclosure, the lengths of the first electrode plate 11 and the second electrode plate 12 in the direction parallel to the light-emitting end face 24 (Y-axis direction) are greater than the length of the semiconductor stack structure 20 in the Y-axis direction. Therefore, the conductive member 40 can be provided at least outside the semiconductor stack structure 20 in the direction parallel to the light-emitting end face 24.

[0072] In the example shown in Figure 1, the conductive member 40 fills the space defined between the upper surface 11A of the first electrode plate 11 and the lower surface 12B of the second electrode plate 12 on the side of the semiconductor laminate structure 20. Also in the example shown in Figure 1, a portion of the conductive member 40 is present on the upper part of the semiconductor laminate structure 20 and covers the semiconductor laminate structure 20. In this example, the second semiconductor layer 22 is electrically connected to the second electrode plate 12 via the conductive member 40. In this way, the conductive member 40 can be used as a current path. Preferably, the conductive member 40 covers at least the sides of the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22. This allows heat generated in the semiconductor laminate structure 20 to be more efficiently dissipated to the outside of the semiconductor element 100 via the conductive member 40. The conductive member 40 can cover the sides of the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22 via other members such as an insulating layer 25. The conductive member 40 is thermally connected to the first semiconductor layer 21, the active layer 23, and the second semiconductor layer 22.

[0073] The size of the conductive member 40 in the Y-axis direction is equal to the size of the first electrode plate 11 and the second electrode plate 12 in the Y-axis direction. Similarly, the size of the conductive member 40 in the Z-axis direction is equal to the size of the first electrode plate 11 and the second electrode plate 12 in the Z-axis direction. In plan view, the contour of the conductive member 40 aligns with the contours of the first electrode plate 11 and the second electrode plate 12. Furthermore, as shown in Figure 1, the side surface of the conductive member 40 lies substantially on the same plane as the side surface of the first electrode plate 11 and the side surface of the second electrode plate. Therefore, the semiconductor element 100 in this embodiment has a roughly rectangular block shape. The larger the volume of the conductive member 40, the greater the expected improvement in heat dissipation due to the presence of the conductive member 40.

[0074] In the examples shown in Figures 1 and 2, the lower surface of the conductive member 40 extends along the upper surface 11A of the first electrode plate 11. The upper surface of the conductive member 40 also extends along the lower surface 12B of the second electrode plate 12. In the example in Figure 1, an insulating layer 30 is located between the lower surface of the conductive member 40 and the upper surface 11A of the first electrode plate 11, achieving electrical insulation between the conductive member 40 and the first electrode plate 11. In contrast, no insulating layer is located between the upper surface of the conductive member 40 and the lower surface 12B of the second electrode plate 12, and the conductive member 40 and the second electrode plate 12 are electrically connected. Note that a conductive layer or a partially insulating layer may exist between the upper surface of the conductive member 40 and the lower surface 12B of the second electrode plate 12.

[0075] If the upper surface 11A of the first electrode plate 11 has a pattern such as irregularities, the lower surface of the conductive member 40 may have a pattern corresponding to such a pattern. In contrast, the upper surface of the conductive member 40 may be flat regardless of the shape of its lower surface. As shown in Figure 1, the distance between the upper and lower surfaces of the conductive member 40, i.e., the thickness of the conductive member 40, is uniform in the region outside the semiconductor stacked structure, but is relatively small in the region where the semiconductor stacked structure 20 is provided. In the region outside the semiconductor stacked structure 20, the conductive member 40 functions as a structure that supports the second electrode plate 12 with its surface and connects the second electrode plate 12 to the first electrode plate 11. By providing the conductive member 40 at least outside the semiconductor stacked structure 20 in a direction parallel to the light-emitting end face 24, it becomes possible to support the second electrode plate 12, whose length in the direction parallel to the light-emitting end face 24 (Y-axis direction) is greater than the length of the semiconductor stacked structure 20 in the Y-axis direction, in a balanced manner with the conductive member 40. The thickness of the conductive member 40 in the region outside the semiconductor multilayer structure 20 can be greater than the thickness of the semiconductor multilayer structure 20. The greater the thickness of the conductive member 40, the greater the expected improvement in heat dissipation due to the presence of the conductive member 40.

[0076] The conductive member 40 can be formed from a metallic material such as copper, aluminum, or silver. From the viewpoint of dissipating heat generated in the semiconductor laminated structure 20 to the outside, it is desirable that the conductive member 40 be formed from a conductive material with a high thermal conductivity, such as a metal. Since the conductive member 40 thermally bonds the first electrode plate 11 and the second electrode plate 12, which extend on both sides of the semiconductor laminated structure 20 in the Y-axis direction, it becomes possible to dissipate the heat generated in the semiconductor laminated structure 20 to both the first electrode plate 11 and the second electrode plate 12. In this embodiment, since the direction in which the laser light is emitted and the direction in which the first electrode plate and the second electrode plate are arranged are different, heat can be efficiently dissipated without hindering the extraction of the laser light.

[0077] The conductive member 40 may have a configuration in which multiple conductive layers are laminated. In this embodiment, the aforementioned bonding layer 60 is interposed between the lower surface 12B of the second electrode plate 12 and the upper surface of the conductive member 40. Therefore, depending on the type of bonding layer 60, a layer of material with excellent bonding properties and ohmic contact properties to the bonding layer 60 may be provided on the upper surface of the conductive member 40.

[0078] Figure 15 is a cross-sectional view of the semiconductor element 100 in a plane parallel to the XZ plane. As shown in Figure 15, the first electrode plate 11, the conductive member 40, and the second electrode plate 12 each have a first end face 20A parallel to the light-emitting end face 24 of the semiconductor multilayer structure 20. In the illustrated example, the semiconductor element 100 further comprises a dielectric film 70 covering the first end face 20A and the light-emitting end face 24. An example of the dielectric film 70 is a dielectric multilayer film that functions as an anti-reflection film for laser light. The dielectric film 70 extends in the portion perpendicular to the first end face 20A (in the Z-axis direction) on at least one surface of the first electrode plate 11 and the second electrode plate 12. The dielectric film 70 can cover and protect not only the light-emitting end face 24 of the semiconductor multilayer structure 20, but also the entire end face on the light-emitting side of the semiconductor element 100. Since the dielectric film 70 extends in the portion perpendicular to the first end face 20A (in the Z-axis direction) on at least one surface of the first electrode plate 11 and the second electrode plate 12, the contact area with the semiconductor element 100 is increased, making it less likely to peel off.

[0079] In the example shown in Figure 15, the insulating isolation layer 16 penetrates the conductive member 40 on the semiconductor multilayer structure 20 to separate the laser resonator from the laser light amplifier and reaches the second semiconductor layer 22. In this example, the insulating isolation layer 16 is a dielectric layer that contains the interior of a groove that extends to the second semiconductor layer 22 to separate the laser resonator from the laser light amplifier. The active layer 23 is not separated by the insulating isolation layer 16 and is continuous within the semiconductor device 100. In such a configuration, laser oscillation can be realized, for example, by a distributed feedback Bragg reflector provided on the semiconductor multilayer structure 20. A reflective film 72 is provided on the end face of the semiconductor multilayer structure 20 opposite to the light-emitting end face 24 in Figure 15. This reflective film 72, like the dielectric film 70, may cover the first electrode plate 11, the conductive member 40, and the second end face 20B of the second electrode plate 12. Furthermore, the reflective film 72 may also extend in a portion perpendicular to the second end face 20B (in the Z-axis direction) on at least one surface of the first electrode plate 11 and the second electrode plate 12, similar to the dielectric film 70.

[0080] Figure 16 is a cross-sectional view in a plane parallel to the XZ plane in a modified example of the semiconductor device 100 of Figure 12. In this example, the insulating isolation layer 16 is a layer of air inside a groove that extends to the first semiconductor layer 21 to separate the laser resonator and the laser light amplifier. Between the laser resonator side and the laser light amplifier side, the insulating isolation layer 16 separates not only the second semiconductor layer 22 but also the active layer 23. A reflective film (first reflective film) 72 is provided on the back end face of the active layer 23 on the laser resonator side, and another reflective film (second reflective film) 73 is provided on the front end face. A "resonator" is formed between the first reflective film 72 and the second reflective film 73. Furthermore, a distributed feedback type Bragg reflector may be provided in the semiconductor stacked structure 20 to improve wavelength selectivity. A portion of the laser light formed by the laser oscillation in the resonator on the laser resonator side is emitted from the second reflective film 73, passes through the insulating isolation layer 16, and is incident on the active layer 23 on the laser light amplifier side. In this way, optical coupling is achieved between the spatially separated active layers 23. Since the optical axis of the laser resonator and the optical axis of the laser light amplifier are aligned, the coupling efficiency can be increased compared to when their optical axes are misaligned.

[0081] As shown in Figure 16, all or part of the first semiconductor layer 21 is not separated by grooves. Grooves for the insulating isolation layer 16 can be formed by anisotropic etching technique. In this example, since the laser resonator side and the laser light amplifier side are separated by forming grooves in a part of a single semiconductor multilayer structure 20, there is no need to perform alignment between the individual laser resonator and laser light amplifier.

[0082] Figure 17 is a cross-sectional view in a plane parallel to the XZ plane of another modified example of the semiconductor device 100. In this example, the insulating isolation layer 16 is formed from a translucent dielectric. The interior of a groove extending to the first semiconductor layer 21 to isolate the laser resonator and the laser light amplifier is filled with the dielectric. The insulating isolation layer 16 can function to cover and protect the surface (including the end face of the active layer 23) formed on the semiconductor multilayer structure 20 by etching.

[0083] Figure 18 is a cross-sectional view in a plane parallel to the XZ plane of yet another modification example of the semiconductor element 100. In the example of Figure 18, a translucent plate 80 is provided via a dielectric film 70 on the first end face 20A of the first electrode plate 11, the conductive member 40, and the second electrode plate 12, and on the light-emitting end face 24 of the semiconductor stacked structure 20. This improves the heat dissipation of each end face. Also, since the laser beam can be spread out before being extracted from the translucent plate 80, the light density can be reduced, and deterioration of the end face due to light dust collection can be reduced. The translucent plate 80 is a plate or sheet-like member formed from a material that transmits laser light, such as glass or sapphire. The translucent plate 80 protects the entire end face on the light-emitting side of the semiconductor element 100. As shown in Figure 18, another translucent plate 82 may be provided via a reflective film 72 on the second end face 20B of the first electrode plate 11, the conductive member 40, and the second electrode plate 12. In the example shown in Figure 18, the reflective film 72, like the dielectric film 70, covers the first electrode plate 11, the conductive member 40, and the second end face 20B of the second electrode plate 12, and extends in a direction perpendicular to the second end face 20B (in the Z-axis direction) on at least one surface of the first electrode plate 11 and the second electrode plate 12.

[0084] (Manufacturing method for semiconductor devices) An embodiment of the semiconductor device manufacturing method according to this disclosure will be described with reference to Figures 19A to 19N. Figures 19A to 19J are schematic cross-sectional views showing some of the steps in this embodiment. Figure 19K is a schematic plan view showing the steps in this embodiment. Figures 19L to 19N are schematic perspective views showing some of the other steps in this embodiment.

[0085] First, as shown in Figure 19A, a process is carried out to prepare a plurality of semiconductor stacked structures 20 arranged on a first substrate 90. Each of the plurality of semiconductor stacked structures 20 includes, in this order, a first semiconductor layer 21 of a first conductivity type, an active layer 23, and a second semiconductor layer 22 of a second conductivity type. Specifically, semiconductor stacked structures 20 are obtained by performing a wafer process of semiconductor manufacturing technology, which separates them from each wafer. The semiconductor stacked structure 20 may be a semiconductor chip (die) having a p-side electrode and an n-side electrode, or a semiconductor component extending in a stripe shape that can be divided into a plurality of semiconductor chips.

[0086] The first substrate 90 is a carrier substrate used in the manufacturing process. In the example shown in Figure 19A, a resin layer 92 is provided on the upper surface of the first substrate 90. The resin layer 92 is a layer formed from a material that can be cured by heat or light, for example. Preferably, the resin layer 92 is a layer formed from a material that can be removed by wet treatment (wet etching). This allows the resin layer 92 to be easily removed in a later process. Examples of such materials include polyimide resins. Multiple semiconductor stacked structures 20 are temporarily fixed to the first substrate 90 by the resin layer 92. Although three semiconductor stacked structures 20 are shown in Figure 19A, more than three semiconductor stacked structures 20 may be mounted on a single first substrate 90.

[0087] Next, as shown in Figure 19B, the surface of the first semiconductor layer 21 in the multiple semiconductor stacked structures 20 is polished or etched to reduce the thickness of the first semiconductor layer 21. The first semiconductor layer 21 may include a semiconductor substrate necessary for semiconductor crystal growth, but part or all of such a semiconductor substrate may be removed.

[0088] Next, as shown in Figure 19C, a metal layer 62 is deposited on the resin layer 92 so as to cover the semiconductor multilayer structure 20. The metal layer 62 includes a contact electrode between it and the first semiconductor layer 21, and a metal layer (bonding layer) for bonding to the first electrode plate 11.

[0089] Next, as shown in Figure 19D, multiple semiconductor laminated structures 20 are bonded onto the first conductive material substrate 110. Here, the first conductive material substrate 110 is a substrate for forming the first electrode plate 11 and has a configuration similar to that of the first electrode plate 11. Multiple first electrode plates 11 can be obtained by dividing the first conductive material substrate 110 in a later step. In this step, the first conductive material substrate 110 is bonded onto the metal layer 62 deposited in the step shown in Figure 19C. The bonding layer contained in the metal layer 62 realizes the bonding between the first conductive material substrate 110 and each semiconductor laminated structure 20.

[0090] Next, as shown in Figure 19E, the resin layer 92 and the first substrate 90 are removed. The resin layer 92 can be removed by wet etching. This allows for the removal of both the resin layer 92 and the first substrate 90. Alternatively, the first substrate 90 may be removed first, and then the resin layer 92 may be removed by wet etching or the like.

[0091] Figure 19F shows the state in which the first conductive material substrate 110 to which the semiconductor multilayer structure 20 is bonded is inverted compared to the state in Figure 19E. In this state, an insulating layer 30 covering the semiconductor multilayer structure 20 is deposited on the first conductive material substrate 110. The insulating layer 30 is deposited, for example, by chemical vapor deposition (CVD) or sputtering.

[0092] Next, as shown in Figure 19G, openings 27 are formed in the insulating layer 30 for electrical connection to each semiconductor stack structure 20 (see Figure 9). The openings 27 can be formed by lithography and etching processes. The upper part of the metal layer (electrode) 26 of the semiconductor stack structure 20 is partially exposed through the openings 27 (see Figure 9).

[0093] Next, a step is performed to place the conductive member 40 on the first conductive material substrate 110. The conductive member 40 is positioned so as to be located outside the semiconductor stacked structure 20 in a direction perpendicular to the stacking direction of the semiconductor stacked structure 20. Specifically, in the step of placing the conductive member 40, as shown in Figure 19H, a metal film 40M for forming the conductive member 40 is deposited on the first conductive material substrate 110. The deposition of the metal film 40M can be performed, for example, by plating or PVD. A combination of plating and PVD may also be used. The metal film 40M is formed so as to cover the entirety of the multiple semiconductor stacked structures 20. The upper surface of this metal film 40M does not need to be flat and may have irregularities that reflect the presence of the semiconductor stacked structures 20.

[0094] Next, as shown in Figure 19I, the metal film 40M is planarized to form the conductive member 40 from the metal film 40M. At this time, the upper part of the metal film 40M may be removed until the insulating layer 30 located on the upper surface of the semiconductor laminated structure 20 is exposed. The portion of the metal film 40M located inside the opening 27 of the semiconductor laminated structure 20 may remain on the metal layer (electrode) 26. Note that when manufacturing a semiconductor element 100 having the configuration example shown in Figure 1, it is not necessary to remove the metal film 40M until a part of the insulating layer 30 is exposed. In such a case, the conductive member 40 is continuous between the semiconductor laminated structure 20 and the second electrode plate 12.

[0095] Next, a process is carried out to bond a second conductive material substrate 120 to the upper surface of the conductive member 40, thereby fabricating a laminate 200 containing multiple semiconductor laminate structures 20 and conductive members 40 between the first conductive material substrate 110 and the second conductive material substrate 120. Specifically, first, as shown in Figure 19J, a bonding layer 60 is deposited on the upper surface of the conductive member 40. Next, the second conductive material substrate 120 is brought into close contact with the bonding layer 60 and bonded. Here, the second conductive material substrate 120 is a plate for forming the second electrode plate 12 and has a configuration similar to that of the second electrode plate 12. By dividing the second conductive material substrate 120 in a later process, multiple second electrode plates 12 can be obtained.

[0096] In this embodiment, an insulating separation layer 16 is formed as shown in Figure 12. Subsequently, the laminate 200 is divided in a direction intersecting the multiple semiconductor laminate structures 20, and a process is carried out to obtain multiple bars 220 from the laminate 200, each containing a part of the multiple semiconductor laminate structures 20.

[0097] Figure 19K is a schematic plan view showing bars 220 separated from a laminate 200. The multiple semiconductor laminate structures 20 shown extend parallel to the Z-axis direction. Figure 19K shows multiple dashed lines parallel to the direction (Y-axis direction) that intersect the multiple semiconductor laminate structures 20. For example, by cutting the laminate 200 along the dashed lines using a dicing blade, multiple bars 220 are separated from one laminate 200. In Figure 19K, one bar 220 separated from the laminate 200 is schematically shown. A single semiconductor element 100 can be obtained, for example, from a rectangular region enclosed by the dashed lines of the bar 220.

[0098] Figure 19L is a schematic perspective view showing a portion of a single bar 220. The illustrated portion of the bar 220 contains three semiconductor multilayer structures 20, but the number of semiconductor multilayer structures 20 contained in a single bar 220 may be four or more. It is desirable that the first end face 20A and the second end face 20B of the bar 220 after division be planarized by chemical mechanical polishing (CMP) or the like. After planarization, a dielectric film 70 is formed on the first end face 20A by sputtering or the like.

[0099] Next, as shown in Figure 19M, translucent plates 80 and 82 are attached to the first end face 20A and the second end face 20B of each bar 220, which are parallel to the XY plane (see Figure 18). The translucent plates 80 and 82 contribute to reducing the light dust collection effect on the light-emitting end face 24 of the semiconductor stacked structure 20. The translucent plates 80 and 82 are plate-like members formed from sapphire or glass. The translucent plates 80 and 82 can be bonded to the bar 220 using techniques such as surface-activated bonding (SAB), atomic diffusion bonding (ADB), or hydroxyl group bonding. Since these bonding methods can be performed at room temperature, manufacturing costs can be reduced and device degradation can be reduced.

[0100] Next, a first electrode 14E and a second electrode 15E are provided on the second electrode plate 12 of each bar 220. A third electrode 17E is also provided on the first electrode plate 11. These electrodes function as electrical connection points (pad electrodes) to an external drive circuit. Subsequently, as shown in Figure 19N, each of the multiple bars 220 is separated into individual pieces to obtain multiple semiconductor elements 100, each having a part of a multiple semiconductor stacked structure 20.

[0101] The semiconductor element 100 thus obtained is equipped with a first electrode plate 11 and a second electrode plate 12 that function as heat dissipation blocks on the top and bottom, making it easy to dissipate the heat generated by the semiconductor stacked structure 20 to the outside.

[0102] As is clear from the above explanation, this disclosure provides example configurations for each of the following items.

[0103] [Item 1] First electrode plate and The second electrode plate, A semiconductor stacked structure disposed between the first electrode plate and the second electrode plate, comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer provided between the first semiconductor layer and the second semiconductor layer, and having a light-emitting end face, A conductive member disposed between the first electrode plate and the second electrode plate, Equipped with, In a direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure, the lengths of the first electrode plate and the second electrode plate are greater than the length of the semiconductor stacked structure. The first semiconductor layer is electrically connected to the first electrode plate. The second semiconductor layer is electrically connected to the second electrode plate, A semiconductor element wherein at least a portion of the conductive member is provided outside the semiconductor stacked structure in the direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure. [Item 2] The conductive member covers at least the sides of the first semiconductor layer, the active layer, and the second semiconductor layer, as described in item 1. [Item 3] The semiconductor element according to item 1 or 2, wherein the second semiconductor layer is electrically connected to the second electrode plate via the conductive member. [Item 4] The present invention further includes an insulating layer disposed between the conductive member and the semiconductor laminated structure, The semiconductor element according to any one of items 1 to 3, wherein the insulating layer has an opening in at least a portion of the upper part of the second semiconductor layer of the semiconductor stacked structure. [Item 5] The upper surface of the conductive member and the upper surface of the insulating layer located in a part of the second semiconductor layer are flush with each other. The second electrode plate is connected to the upper surface of the conductive member and the upper surface of the insulating layer via a bonding layer having a thickness of 10 nm or less. The aforementioned bonding layer is a semiconductor device according to item 4, comprising at least a metal. [Item 6] The insulating layer is an oxide, The semiconductor element according to item 5, wherein at least a portion of the bonding layer in contact with the insulating layer comprises an insulating region formed from an oxide of the metal constituting the bonding layer. [Item 7] The upper surface of the conductive member and the upper surface of the insulating layer are flush. A semiconductor element according to any one of items 4 to 6, wherein the atoms constituting the second electrode plate and the atoms constituting the conductive member are connected by interatomic bonding. [Item 8] The semiconductor device according to any one of items 1 to 7, wherein the semiconductor stacked structure constitutes at least one of a laser resonator and a laser light amplifier. [Item 9] The semiconductor stacked structure is continuous in at least a portion and constitutes the laser resonator and the laser light amplifier, and the light-emitting end face is the end face of the waveguide portion of the laser light amplifier. The laser resonator and the laser light amplifier are optically coupled. The second electrode plate is A first region electrically connected to the laser resonator is provided on the laser resonator, The laser light amplifier comprises a second region electrically connected to the laser light amplifier, The semiconductor device described in item 8, wherein the first region and the second region are electrically insulated from each other. [Item 10] The first electrode plate, the conductive member, and the second electrode plate each have a first end face parallel to the light-emitting end face of the semiconductor stacked structure. A semiconductor device according to any one of items 1 to 9, further comprising a dielectric film covering the first end face and the light-emitting end face. [Item 11] The semiconductor device according to item 10, wherein the dielectric film extends over a portion perpendicular to the first end face on at least one surface of the first electrode plate and the second electrode plate. [Item 12] The semiconductor device according to item 10 or 11, further comprising a light-transmitting plate disposed via the dielectric film on the first end face of the first electrode plate, the conductive member, and the second electrode plate and the light-emitting end face of the semiconductor stacked structure. [Item 13] A semiconductor device according to any one of items 1 to 12, wherein at least one of the first electrode plate and the second electrode plate includes graphite in which a plurality of graphenes are stacked in the direction normal to the light-emitting end face. [Item 14] A step of preparing multiple semiconductor stacked structures, each containing, in this order, a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type, arranged on a first substrate; A step of bonding the plurality of semiconductor stacked structures onto a first conductive material substrate, and removing the first substrate from the plurality of semiconductor stacked structures, A step of arranging a conductive member on the first conductive material substrate, at least in a direction perpendicular to the stacking direction of the semiconductor stack structure, outside the semiconductor stack structure; A step of bonding a second conductive material substrate to the upper surface of the conductive member, and fabricating a laminate including the plurality of semiconductor laminated structures and the conductive member between the first conductive material substrate and the second conductive material substrate, A step of dividing the laminate to obtain from the laminate a plurality of bars, each of which includes a part of the plurality of semiconductor laminated structures, A step of separating the plurality of bars into individual pieces to obtain a plurality of semiconductor elements, each having part of the plurality of semiconductor stacked structures, A method for manufacturing semiconductor devices including [specific components]. [Industrial applicability]

[0104] The semiconductor devices of this disclosure can be used as various light sources. [Explanation of Symbols]

[0105] 11...First electrode plate, 12...Second electrode plate, 20...Semiconductor multilayer structure, 30...Insulating layer, 40...Conductive member, 100...Semiconductor element

Claims

1. First electrode plate and The second electrode plate and A semiconductor stacked structure disposed between the first electrode plate and the second electrode plate, comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer provided between the first semiconductor layer and the second semiconductor layer, and having a light-emitting end face, A conductive member disposed between the first electrode plate and the second electrode plate, Equipped with, In a direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure, the lengths of the first electrode plate and the second electrode plate are greater than the length of the semiconductor stacked structure. The first semiconductor layer is electrically connected to the first electrode plate. The second semiconductor layer is electrically connected to the second electrode plate, A semiconductor element wherein at least a portion of the conductive member is provided outside the semiconductor stacked structure in the direction parallel to the light-emitting end face and perpendicular to the stacking direction of the semiconductor stacked structure.

2. The semiconductor element according to claim 1, wherein the conductive member covers at least the sides of the first semiconductor layer, the active layer, and the second semiconductor layer.

3. The semiconductor element according to claim 1, wherein the second semiconductor layer is electrically connected to the second electrode plate via the conductive member.

4. The present invention further includes an insulating layer disposed between the conductive member and the semiconductor laminated structure, The semiconductor element according to claim 1, wherein the insulating layer has an opening in at least a portion of the upper part of the second semiconductor layer of the semiconductor stacked structure.

5. The upper surface of the conductive member and the upper surface of the insulating layer located in a part of the second semiconductor layer are flush with each other. The second electrode plate is connected to the upper surface of the conductive member and the upper surface of the insulating layer via a bonding layer having a thickness of 10 nm or less. The semiconductor element according to claim 4, wherein the bonding layer comprises at least a metal.

6. The insulating layer is an oxide, The semiconductor element according to claim 5, wherein at least a portion of the bonding layer in contact with the insulating layer comprises an insulating region formed from an oxide of the metal constituting the bonding layer.

7. The upper surface of the conductive member and the upper surface of the insulating layer are flush. The semiconductor element according to claim 4, wherein the atoms constituting the second electrode plate and the atoms constituting the conductive member are connected by interatomic bonding.

8. The semiconductor device according to claim 1, wherein the semiconductor stacked structure constitutes at least one of a laser resonator and a laser light amplifier.

9. The semiconductor stacked structure is continuous in at least a portion and constitutes the laser resonator and the laser light amplifier, and the light-emitting end face is the end face of the waveguide portion of the laser light amplifier. The laser resonator and the laser light amplifier are optically coupled. The second electrode plate is A first region electrically connected to the laser resonator is provided on the laser resonator, The laser light amplifier comprises a second region electrically connected to the laser light amplifier, The semiconductor element according to claim 8, wherein the first region and the second region are electrically insulated from each other.

10. The first electrode plate, the conductive member, and the second electrode plate each have a first end face parallel to the light-emitting end face of the semiconductor stacked structure. The semiconductor device according to claim 1, further comprising a dielectric film covering the first end face and the light-emitting end face.

11. The semiconductor element according to claim 10, wherein the dielectric film extends over a portion of at least one surface of the first electrode plate and the second electrode plate that is perpendicular to the first end face.

12. The semiconductor element according to claim 10, further comprising a translucent plate disposed via the dielectric film on the first end face of the first electrode plate, the conductive member, and the second electrode plate, and on the light-emitting end face of the semiconductor stacked structure.

13. The semiconductor device according to any one of claims 1 to 12, wherein at least one of the first electrode plate and the second electrode plate includes graphite in which a plurality of graphenes are stacked in the direction normal to the light-emitting end face.

14. A step of preparing multiple semiconductor stacked structures, each containing, in this order, a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type, arranged on a first substrate; A step of bonding the plurality of semiconductor stacked structures onto a first conductive material substrate, and removing the first substrate from the plurality of semiconductor stacked structures, A step of arranging a conductive member on the first conductive material substrate, at least in a direction perpendicular to the stacking direction of the semiconductor stack structure, outside the semiconductor stack structure; A step of bonding a second conductive material substrate to the upper surface of the conductive member, and fabricating a laminate including the plurality of semiconductor laminated structures and the conductive member between the first conductive material substrate and the second conductive material substrate, A step of dividing the laminate to obtain from the laminate a plurality of bars, each of which includes a part of the plurality of semiconductor laminated structures, A step of separating the plurality of bars into individual pieces to obtain a plurality of semiconductor elements, each having part of the plurality of semiconductor stacked structures, A method for manufacturing semiconductor devices including [specific components].

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