Wiring board

Abstract

Providing a wiring board equipped with fine wiring. [Solution] The wiring board 1 of the embodiment includes an insulating layer 32 and an upper conductor layer 22 laminated on the upper surface of the insulating layer 32 and including an upper wiring pattern. The upper surface of the insulating layer 32 directly below the upper wiring pattern has a curved concave shape, the lower surface of the upper wiring pattern on the upper conductor layer 22 has a curved first convex shape that fits into the concave shape, and the upper surface of the insulating layer 32 exposed from the upper wiring pattern has a curved second convex shape.

Description

Technical Field

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[0001] The present invention relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses an exposure method by direct imaging as a method for curing a photosensitive resin without using a photomask.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When forming an insulating layer of a laminated substrate by curing a photosensitive resin by the exposure method disclosed in Patent Document 1, if the exposure time is long, the photosensitive resin becomes too hard, and the adhesion of the metal film formed on the photosensitive resin becomes low, and it may not be possible to form a fine wiring pattern.

Means for Solving the Problems

[0005] The wiring board of the present invention includes an insulating layer and a conductor layer laminated on the upper surface of the insulating layer and including a wiring pattern. And, the upper surface of the insulating layer directly under the wiring pattern has a curved concave shape, the lower surface of the wiring pattern of the conductor layer has a curved first convex shape that fits into the concave shape, and the upper surface of the insulating layer exposed from the wiring pattern has a curved second convex shape.

[0006] According to an embodiment of the present invention, it is possible to form a wiring board having a fine wiring pattern with good adhesion to an interlayer material.

Brief Description of the Drawings

[0007] <00000A cross-sectional view partially showing an example of a wiring board according to the embodiment. [Figure 2] Cross-sectional perspective view of the wiring pattern in Figure 1. [Figure 3] A cross-sectional view partially showing a modified example of the conductor layer of the wiring board of the embodiment. [Figure 4] Cross-sectional perspective view of the wiring pattern in Figure 3. [Figure 5] A cross-sectional view showing an example of a wiring board according to the first embodiment. [Figure 6] A cross-sectional view showing an example of a wiring board according to the second embodiment. [Figure 7A] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7B] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7C] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7D] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7E] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7F] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7G] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7H] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7I] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7J] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7K] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Figure 7L] A cross-sectional view showing an example of a manufacturing method for a wiring board according to an embodiment. [Modes for carrying out the invention]

[0008] Wiring boards of embodiments of the present invention will be described with reference to the drawings. The wiring boards illustrated in each drawing referenced in the following description are merely examples of wiring boards of embodiments. The laminated structure of the wiring boards of embodiments is not limited to the laminated structure of the wiring boards shown in each drawing, and the number of conductive layers and insulating layers included in the wiring boards of embodiments is not limited to the number of conductive layers and insulating layers included in the wiring boards shown in each drawing. In addition to the insulating layers and conductive layers of the wiring boards shown in each drawing, the wiring boards of embodiments may include any number of insulating layers and conductive layers, and may not include all of the insulating layers and conductive layers of the wiring boards shown in each drawing. Note that in each drawing referenced in the following description, certain parts may be enlarged to facilitate understanding of the disclosed embodiments. Therefore, each component may not be depicted in the exact proportions between them in terms of size and length.

[0009] <Configuration of the wiring board in the embodiment> Figure 1 shows a cross-sectional view of a portion of a wiring board 1, which is an example of a wiring board according to an embodiment, and Figure 2 shows a cross-sectional perspective view of the wiring pattern of the wiring board 1 of Figure 1. As shown in Figure 1, the wiring board 1 is formed by laminating a plurality of substrate elements, substrate element 101 and substrate element 102. Substrate element 101 and substrate element 102 have similar configurations. Substrate element 101 comprises an insulating layer 31 and a conductor layer 21 laminated on the surface 31a of the insulating layer 31. Substrate element 102 comprises an insulating layer 32 and a conductor layer 22 laminated on the surface 32a of the insulating layer 32. The insulating layer 31 consists of two regions, a first region 311 and a second region 312, and the conductor layer 21 is laminated on the surface 311a of the first region 311 of the insulating layer 31. The insulating layer 32 of substrate element 102 is formed to cover substrate element 101. Specifically, the insulating layer 32 is laminated so as to cover the surface 312a of the surface 31a of the insulating layer 31 that is exposed from the conductor layer 21, and the conductor layer 21. The insulating layer 32 consists of two regions, a first region 321 and a second region 322, and the conductor layer 22 is laminated on the surface 321a of the first region 321 of the insulating layer 32. The conductor layer 21 contains a wiring pattern 201, and the conductor layer 22 contains a wiring pattern 202. In Figure 2, the insulating layer 32 is omitted from the illustration so as to make the shapes of the wiring patterns 201 and 202 easier to understand. In Figures 1 and 2, the wiring board 1 is shown as a configuration in which two board elements 101 and 102 are laminated, but it is not limited to this. The number of laminated board elements may be one or more than two. In the following description, the conductor layer 21 is also referred to as the lower conductor layer, and the conductor layer 22 is also referred to as the upper conductor layer. Furthermore, wiring pattern 201 is also referred to as the lower wiring pattern, and wiring pattern 202 is also referred to as the upper wiring pattern.

[0010] In the following description of the wiring board of the embodiment, the surface 31a side of the insulating layer 31 on which the conductor layer 21 is laminated is also referred to as the "upper side" or simply "upper", and the direction from the insulating layer 31 toward the conductor layer 21 is also referred to as the "upward direction". The side on which the insulating layer 31 is formed as viewed from the conductor layer 21 is also referred to as the "lower side" or simply "lower", and the direction from the conductor layer 21 toward the insulating layer 31 is also referred to as the "downward direction". Also, in each insulating layer and each conductor layer, the surface facing the upward direction is also referred to as the "upper surface", and the surface facing the downward direction is also referred to as the "lower surface". Further, the stacking direction of the insulating layer and the conductor layer, that is, the thickness direction of the wiring board 1 is also referred to as the "Z direction". "Plan view" means looking at an object with a line of sight along the Z direction from above.

[0011] The conductor layer 21 and the conductor layer 22 are formed of any metal having appropriate conductivity. For example, copper or nickel etc. are exemplified as the constituent materials of the conductor layer 21 and the conductor layer 22. However, the materials of the conductor layer 2i and the conductor layer 22 are not limited to these metals. Also, the conductor layer 21 and the conductor layer 22 are formed by any metal film forming method. In FIGS. 1 to 2, the conductor layer 21 and the conductor layer 22 are illustrated as one layer, but preferably, they have a two-layer structure including a metal film and a plating film. More preferably, the metal film is a sputtering film. The plating film is, for example, a metal film formed by electrolytic plating using the metal film as a power supply layer. The plating film is formed, for example, by pattern plating using a plating resist having an appropriate opening pattern.

[0012] In the wiring board 1, the conductor layer 21 and the conductor layer 22 each include a wiring pattern 201 and a wiring pattern 202. The wiring pattern is a conductor pattern designed and used to apply a voltage, pass an electric current, supply electric power, or transmit an electrical signal from an arbitrary position in the conductor layer of the wiring board 1 in a plan view to another arbitrary position different from the arbitrary position. In FIGS. 1 to 2, in the wiring patterns 201 and 202, the conductor patterns are arranged in parallel in a direction (X direction) substantially orthogonal to the direction (Y direction) in which each conductor pattern extends. The wiring patterns 201 and 202 are each formed in an arbitrary pattern and may be different from each other. In a high-density wiring board, as shown in FIGS. 1 to 2, the wiring patterns may be formed so as to overlap vertically at substantially the same position in a plan view.

[0013] The width of each wiring of the wiring patterns 201 and 202 of the wiring board 1 is preferably 1.0 μm or more and 20.0 μm or less. Also, the arrangement interval of each wiring in the wiring patterns 201 and 202 is preferably 1.0 μm or more and 20.0 μm or less. Further, the thickness of the conductor layers 21 and 22 in the wiring patterns 201 and 202 may be 3.5 μm or more and 20.0 μm or less.

[0014] The insulating layer 31 and insulating layer 32 are formed from any photosensitive resin, preferably a negative-type photosensitive resin. Here, a negative-type photosensitive resin refers to a resin that undergoes crosslinking and hardens upon irradiation with ultraviolet light or the like. Examples of photosensitive resins used to form the insulating layer 31 and insulating layer 32 include, but are not limited to, photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. In addition to the resins exemplified above, the insulating layer 31 and insulating layer 32 may also be resins containing a photosensitive agent. Furthermore, although the insulating layer 31 and insulating layer 32 are described as not containing fillers, those containing inorganic fillers such as silica may be used to change the properties of the insulating layer 31 and insulating layer 32. Note that the resins listed above are merely examples of materials that can form the insulating layer 31 or insulating layer 32. The insulating layer 31 and the insulating layer 32 may be formed from any material that provides photosensitivity and insulation to the conductor layer 21 and the conductor layer 22, and that can support or cover the conductor layer 21 and the conductor layer 22.

[0015] As shown in Figures 1 and 2, the insulating layer 31 consists of a first region 311 directly beneath the wiring pattern 201 of the conductor layer 21 and a second region 312 exposed from the wiring pattern 201 in a plan view. The insulating layer 32 consists of a first region 321 directly beneath the wiring pattern 202 of the conductor layer 22 and a second region 322 exposed from the wiring pattern 202 in a plan view. The upper surfaces 311a of the first region 311 and 321a of the first region 321 both have a curved concave shape. The upper surfaces 312a of the second region 312 and 322a of the second region 322 both have a curved convex shape (second convex shape). That is, the upper surface 311a of the first region 311 is about 0.5 μm lower than the upper surface 312a of the second region 312. Similarly, the upper surface 321a of the first region 321 is about 0.5 μm lower than the upper surface 322a of the second region 322. Also, the Young's modulus of the first region 311 is between 5% and 95% of the Young's modulus of the second region 312. Similarly, the Young's modulus of the first region 321 is between 5% and 95% of the Young's modulus of the second region 322. Specifically, the Young's modulus of the first regions 311 and 321 is, for example, between 0.5 GPa and 1.9 GPa. Also, the Young's modulus of the second regions 312 and 322 is, for example, between 2.0 GPa and 4.0 GPa. Thus, the first region 311 of the insulating layer 31 directly below where the wiring pattern 201 is formed, and the first region 321 of the insulating layer 32 directly below where the wiring pattern 202 is formed, have a lower Young's modulus and are softer than the second region 312 of the insulating layer 31 and the second region 322 of the insulating layer 32.

[0016] A wiring pattern 201 of the conductor layer 21 is formed on the upper surface 311a of the first region 311, and a wiring pattern 202 of the conductor layer 22 is formed on the upper surface 321a of the first region 321. As described above, since the Young's modulus of the first region 311 and the first region 321 is low, if sputtering is used, for example, to form the wiring patterns 201 and 202, metal particles can penetrate deep into the first region 311 and the first region 321, forming a highly adhesive metal film. On the other hand, since the Young's modulus of the second region 312 and the second region 322 is high, metal particles from sputtering do not penetrate deep into them, and the sputtered film can be easily peeled off. As a result, the adhesion between the wiring pattern 201 and the insulating layer 31, and the adhesion between the wiring pattern 202 and the insulating layer 32 are improved, making peeling less likely and resulting in the formation of a fine wiring pattern.

[0017] The upper surface 201a of the wiring pattern 201 has a flat shape. The lower surface 201b of the wiring pattern 201 has a convex shape (first convex shape) that interlocks with the concave shape of the upper surface 311a of the first region 311 of the insulating layer 31. Similarly, the lower surface 202b of the wiring pattern 202 has a convex shape (first convex shape) that interlocks with the concave shape of the upper surface 321a of the first region 321 of the insulating layer 32. In this way, the lower surface 201b of the wiring pattern 201 and the lower surface 202b of the wiring pattern 202 have shapes that physically interlock with the upper surface 311a of the first region 311 of the insulating layer 31 and the upper surface 321a of the first region 321 of the insulating layer 32, respectively. As a result, the adhesion between the wiring pattern 201 and the wiring pattern 202 is further improved, making peeling less likely and allowing for the formation of a finer wiring pattern.

[0018] When the density of a wiring board increases, the wiring patterns of the conductor layer may overlap in the vertical direction. For example, in Figures 1 and 2, the wiring pattern 201S within the wiring pattern 201 (lower wiring pattern) and the wiring pattern 202S within the wiring pattern 202 (upper wiring pattern) are formed to overlap in a plan view with the insulating layer 32 in between. That is, the upper surface 201a of the wiring pattern 201S of the conductor layer 21 (lower conductor layer) which is laminated on the lower surface of the insulating layer 32 and the lower surface 202b of the wiring pattern 202S of the conductor layer 22 (upper conductor layer) which is laminated on the upper surface of the insulating layer 32 face each other. In such cases, parasitic capacitance occurs between the wiring patterns 201S and 202S, which may degrade the quality of the electrical signals flowing through the wiring patterns 201S and 202S. If the parasitic capacitance is large, it may become difficult to transmit high-speed signals. The parasitic capacitance that occurs between the upper and lower wiring patterns, which are arranged in parallel in this manner, is determined by the distance between the wiring patterns and the surface area of ​​the wiring patterns facing each other. In the wiring board 1, the lower surface 202b of the wiring pattern 202S in the upper wiring pattern has a curved convex shape (first convex shape) that separates from the wiring pattern 201S in the lower wiring pattern at both ends. As a result, the effective distance d between the wiring pattern 201S and the wiring pattern 202S is increased, or the effective area of ​​the lower surface 202b of the wiring pattern 202S facing the upper surface 201a of the wiring pattern 201S is decreased. This reduces the parasitic capacitance between the lower and upper wiring patterns, improving the high-speed signal transmission performance in the wiring patterns of the wiring board 1.

[0019] <Modified example of the wiring board of the embodiment> Figure 3 shows a cross-sectional view of a part of a wiring board 1α, which is a modified example of the wiring board 1 of the embodiment, and Figure 4 shows a cross-sectional perspective view of the wiring pattern of the wiring board 1α of Figure 3. As shown in Figures 3 and 4, the wiring board 1α is formed by stacking multiple substrate elements, namely substrate element 101α and substrate element 102. Substrate element 102 has the same configuration as in Figures 1 and 2, and comprises an insulating layer 32 and a conductor layer 22 (upper conductor layer) stacked on the upper surface 32a of the insulating layer 32. Substrate element 101α comprises an insulating layer 31α and a conductor layer 21α (lower conductor layer) stacked on the upper surface 31αa of the insulating layer 31α. The wiring board 1α differs from the wiring board 1 shown in Figures 1 and 2 in that the insulating layer 31α is homogeneous, and the conductor layer 21α is a so-called solid layer formed over the entire surface on the upper surface 31αa of the insulating layer 31α. Furthermore, the conductor layer 21α is not limited to a solid layer, but may also be a wide wiring pattern that overlaps multiple wiring patterns 202S. The insulating layer 32 of the substrate element 102 is laminated so as to cover the upper surface 21αa of the conductor layer 21α. Similar to Figures 1 and 2, the insulating layer 32 consists of two regions, a first region 321 and a second region 322, and the conductor layer 22 is laminated on the upper surface 321a of the first region 321 of the insulating layer 32. The conductor layer 22 includes the wiring pattern 202 (upper wiring pattern). In Figure 4, the illustration of the insulating layer 32 is omitted so that the shape of the wiring pattern 202 is easier to understand. Thus, the wiring board 1α differs from the wiring board 1 only in the configuration of the substrate element 101α; other configurations are the same. For this reason, the following explanation will focus on the differences from the wiring board 1, and redundant explanations may be omitted.

[0020] The conductive layer 21α and conductive layer 22 are formed from any metal with suitable conductivity, such as copper or nickel, similar to the wiring board 1. Furthermore, the conductive layer 21α and conductive layer 22 preferably have a two-layer structure including a metal film and a plating film. More preferably, the metal film is a sputtered film.

[0021] In the wiring board 1α, the conductor layer 22 is provided with a wiring pattern 202. The conductor layer 21α is a solid layer without a wiring pattern. Therefore, as shown in Figures 3-4, the wiring pattern 202 is always formed on top of the conductor layer 21α. The width of each wire in the wiring pattern 202 is preferably 1.0 μm or more and 20.0 μm or less. The spacing between each wire in the wiring pattern 202 is preferably 1.0 μm or more and 20.0 μm or less. The thickness of the conductor layer 22 in the wiring pattern 202 may be 3.5 μm or more and 20.0 μm or less.

[0022] The insulating layer 32, like the wiring board 1, is formed of any photosensitive resin, preferably a negative-type photosensitive resin such as a photosensitive acrylic resin, a photosensitive polyimide resin, a photosensitive polybenzoxazole resin, a photosensitive phenolic resin, a photosensitive epoxy resin, a photosensitive cycloolefin resin, or a photosensitive benzocyclobutene resin. The insulating layer 31α, like the insulating layer 32, may be formed of a photosensitive resin, or of any insulating resin having insulating properties. Examples of insulating resins used to form the insulating layer 31α include thermosetting resins such as epoxy resins, bismaleimide triazine resins (BT resins), or phenolic resins, as well as thermoplastic resins such as fluororesins, liquid crystal polymers (LCPs), fluoroethylene fluorine (PTFE) resins, polyester (PE) resins, and modified polyimide (MPI) resins. The insulating layer 31 may further contain fillers such as silicon dioxide, alumina, or mullite.

[0023] As shown in Figures 3 and 4, the insulating layer 32 consists of a first region 321 directly beneath the wiring pattern 202 of the conductor layer 22 and a second region 322 exposed from the wiring pattern 202 in a plan view. The upper surface 321a of the first region 321 has a curved concave shape. The upper surface 322a of the second region 322 has a curved convex shape (second convex shape). The Young's modulus of the first region 321 is 5% or more and 95% or less of the Young's modulus of the second region 322. Thus, the first region 321 of the insulating layer directly beneath where the wiring pattern 202 is formed has a lower Young's modulus and is softer than the second region 322. Therefore, during the formation of the wiring pattern 202, metal particles can penetrate deep into the first region 321, and a highly adhesive metal film can be formed. This improves the adhesion between the wiring pattern 202 and the insulating layer 32, making peeling less likely and enabling the formation of a fine wiring pattern.

[0024] The lower surface 202b of the wiring pattern 202 has a convex shape (first convex shape) that interlocks with the concave shape of the upper surface 321a of the first region 321 of the insulating layer 32. In other words, the lower surface 202b of the wiring pattern 202 is formed in a shape that physically interlocks with the upper surface 321a of the first region 321 of the insulating layer 32. This further improves the adhesion of the wiring pattern 202, making peeling and other issues less likely to occur, and thus enabling the formation of finer wiring patterns.

[0025] As described above, in the wiring board 1α shown in Figures 3 and 4, the wiring pattern 202S within the wiring pattern 202 (upper wiring pattern) of the conductor layer 22 (upper conductor layer) is formed overlapping the conductor layer 21α (lower conductor layer), which is a solid layer, with the insulating layer 32 in between. That is, the upper surface 21αa of the conductor layer 21α, which is laminated on the lower surface of the insulating layer 32, and the lower surface 202b of the wiring pattern 202S of the conductor layer 22, which is laminated on the upper surface of the insulating layer 32, face each other. In such a case, parasitic capacitance occurs between the conductor layer 21α and the wiring pattern 202S, which can degrade the quality of the electrical signal flowing through the wiring pattern 202S. The parasitic capacitance that occurs between the upper wiring pattern and the lower conductor layer, which are arranged in parallel in this way, is determined by the distance between the wiring pattern and the conductor layer and the surface area between the wiring pattern and the conductor layer. In the wiring board 1α, the lower surface 202b of the wiring pattern 202S in the upper wiring pattern has a curved convex shape (first convex shape) that separates from the lower conductor layer 21α at both ends. As a result, the effective distance d between the conductor layer 21α and the wiring pattern 202S is increased, or the effective area of ​​the lower surface 202b of the wiring pattern 202S facing the upper surface 21αa of the conductor layer 21α is reduced. This reduces the parasitic capacitance between the lower conductor layer and the upper wiring pattern, improving the high-speed signal transmission performance in the wiring pattern of the wiring board 1α.

[0026] <First Embodiment> Figure 5 shows a cross-sectional view of a wiring board 100, which is an example of a wiring board according to the first embodiment. Similar to the wiring board 1 in Figure 1, the wiring board 100 includes four substrate elements consisting of an insulating layer and a conductor layer laminated on the upper surface of the insulating layer. That is, the wiring board 100 has four sets of insulating layers and conductor layers that are alternately laminated. Specifically, a conductor layer 21 is laminated on the upper surface 31a of an insulating layer 31, and an insulating layer 32 is laminated so as to cover the upper surface 31a of the insulating layer 31 that is exposed from the conductor layer 21 in a plan view and the conductor layer 21. Furthermore, a conductor layer 22 is laminated on the upper surface 32a of the insulating layer 32, and an insulating layer 33 is laminated so as to cover the upper surface 32a of the insulating layer 32 that is exposed from the conductor layer 22 in a plan view and the conductor layer 22. Furthermore, a conductor layer 23 is laminated on the upper surface 33a of the insulating layer 33, and an insulating layer 34 is laminated so as to cover the upper surface 33a of the insulating layer 33 that is exposed from the conductor layer 23 in a plan view and the conductor layer 23. Furthermore, a conductor layer 24 is laminated on the upper surface 34a of the insulating layer 34. Conductor layers 21, 22, 23, and 24 each contain wiring patterns 201, 202, 203, and 204, respectively. Note that in Figure 5, the top-bottom relationship of the insulating layer and conductor layer in Figures 1 and 2 is depicted as if rotated 180°. That is, the surface facing downwards in Figure 5 is depicted as the "top surface".

[0027] The wiring board 100 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) perpendicular to its thickness direction. In addition to four sets of insulating layers and conductor layers, the wiring board 100 includes a conductor layer 20 exposed on the first surface 1F, a conductor layer 25 exposed on the second surface 1B, and an insulating layer 35 exposed on the second surface 1B. In the description of the wiring board 100, the second surface 1B side is also referred to as the "upper side" or simply "up," and the direction from the first surface 1F towards the second surface 1B is also referred to as the "upper direction." The second surface 1F side is also referred to as the "lower side" or simply "down," and the direction from the second surface 1B towards the first surface 1F is also referred to as the "downward direction." Furthermore, in each insulating layer and each conductor layer, the surface facing upward is also referred to as the "upper surface," and the surface facing downward is also referred to as the "lower surface."

[0028] In the wiring board 100, a conductor layer 20 is provided on the first surface 1F, and on the conductor layer 20, four insulating layers 31-34 and four conductor layers 21-24 are alternately laminated toward the second surface 1B. Then, an insulating layer 35 is formed to cover the insulating layer 34 and conductor layer 24 closest to the second surface 1B, and a conductor layer 25 is formed on the upper surface of the insulating layer 35. Thus, the wiring board 100 includes a laminate 10 consisting of multiple conductor layers and multiple insulating layers.

[0029] Conductor layers facing each other across the insulating layer of the wiring board 100 are connected by via conductors 11c. Conductor layer 20 and conductor layer 25 each contain an arbitrary conductor pattern. Conductor layer 20 includes a conductor pad 20P, and conductor layer 25 includes a conductor pad 25P. External components (not shown) may be mounted and connected to the conductor pad 20P when the wiring board 100 is in use. That is, the conductor pad 20P can be a component mounting pad, and the wiring board 100 shown in Figure 5 may have a component mounting surface consisting of a first surface 1F.

[0030] The second surface 1B of the wiring board 100 is a surface that can be connected to the motherboard of the electronic device in which the wiring board 100 is used, or to the redistribution board of the semiconductor package in which the wiring board 100 is used, when the wiring board 100 is in use. The wiring board 100 may further be provided on the first surface 1F and / or the second surface 1B with a solder resist (not shown) having an opening to expose the conductor pad 20P or the conductor pad 25P.

[0031] The conductor layers 20-25 and the via conductor 11c are formed from any metal with suitable conductivity, such as copper or nickel, similar to the conductor layers 21 and 22 of the wiring board 1 in Figures 1 and 2. In Figure 5, the conductor layers 20-25 and the via conductor 11c are each shown as a single layer, but they may have a multilayer structure including two or more metal films. Preferably, the conductor layers 21-24 have a two-layer structure including a metal film and a plating film, and more preferably, the metal film is a sputtered film.

[0032] In the wiring board 100, the conductor layers 21 to 24 each contain wiring patterns 201 to 204. The width of each wiring in wiring patterns 201 to 204 is preferably 1.0 μm or more and 20.0 μm or less. The spacing between each wiring in wiring patterns 201 to 204 is preferably 1.0 μm or more and 20.0 μm or less.

[0033] The insulating layers 31 to 34 of the wiring board 100 are formed from a photosensitive resin, such as a photosensitive acrylic resin, a photosensitive polyimide resin, a photosensitive polybenzoxazole resin, a photosensitive phenolic resin, a photosensitive epoxy resin, a photosensitive cycloolefin resin, or a photosensitive benzocyclobutene resin, similar to the insulating layers 31 and 32 of the wiring board 1 in Figure 1. The insulating layer 35 may be formed from any insulating resin, such as epoxy resin, in addition to the photosensitive resin. Furthermore, the insulating layer 35 may contain a filler, such as silicon dioxide.

[0034] As shown in Figure 5, the insulating layers 31 to 34 consist of a region directly beneath the wiring pattern and a region exposed from the wiring pattern in a plan view. Specifically, insulating layer 31 consists of a first region 311 directly beneath the wiring pattern 201 of the conductor layer 21 and a second region 312 exposed from the wiring pattern 201 in a plan view. Insulating layer 32 consists of a first region 321 directly beneath the wiring pattern 202 of the conductor layer 22 and a second region 322 exposed from the wiring pattern 202 in a plan view. Insulating layer 33 consists of a first region 331 directly beneath the wiring pattern 203 of the conductor layer 23 and a second region 332 exposed from the wiring pattern 203 in a plan view. Insulating layer 34 consists of a first region 341 directly beneath the wiring pattern 204 of the conductor layer 24 and a second region 342 exposed from the wiring pattern 204 in a plan view. The Young's modulus of the first regions 311, 321, 331, and 341 of the insulating layer directly beneath wiring patterns 201 to 204 is 5% or more and 95% or less of the Young's modulus of the second regions 312, 322, 332, and 342 of the insulating layer exposed in a plan view from wiring patterns 201 to 204, respectively. Thus, the insulating layer directly beneath where wiring patterns 201 to 204 are formed has a low Young's modulus and is soft. Therefore, during the formation of each wiring pattern, metal particles can penetrate deep into the insulating layer, potentially forming a highly adhesive metal film. This improves the adhesion of the wiring pattern including the metal film, making peeling less likely and enabling the formation of fine wiring patterns.

[0035] Similar to the wiring board 1 shown in Figures 1 and 2, the upper surfaces of the first regions 311, 321, 331, and 341 of the insulating layer directly beneath the wiring patterns 201 to 204 of the conductor layers 21 to 24 all have a curved concave shape. Furthermore, the lower surfaces of the wiring patterns 201 to 204 have a convex shape (first convex shape) that interlocks with the concave shape of the upper surfaces of the first regions 311, 321, 331, and 341. In this way, the lower surface of the wiring pattern is formed in a shape that physically interlocks with the upper surface of the insulating layer directly beneath it. This further improves the adhesion of the wiring pattern and makes peeling less likely, thus enabling the formation of finer wiring patterns.

[0036] In high-density wiring boards, the wiring patterns of the conductor layer may overlap vertically. For example, in Figure 5, wiring patterns 201 to 204 are formed to overlap in a plan view. That is, the upper surface of the wiring pattern (lower wiring pattern) of the conductor layer (lower conductor layer) laminated on the lower surface of the insulating layer and the lower surface of the wiring pattern (upper wiring pattern) of the conductor layer (upper conductor layer) laminated on the upper surface of the insulating layer face each other across the insulating layer. In such cases, parasitic capacitance between the lower and upper wiring patterns facing each other across the insulating layer may degrade the quality of the electrical signals flowing through the wiring patterns. In the wiring board 100 shown in Figure 5, the lower surface of the upper wiring pattern has a curved convex shape (first convex shape) that separates from the lower wiring pattern at both ends, thereby increasing the effective distance between the wiring patterns facing each other across the insulating layer, or decreasing the effective area of ​​the lower surface of the upper wiring pattern. As a result, the parasitic capacitance of the wiring patterns is reduced, and the high-speed signal transmission performance in the wiring patterns of the wiring board 100 is improved.

[0037] In the wiring board 100 shown in Figure 5, it was explained that only the lower surfaces of the wiring patterns 201 to 204 among the conductor layers 21 to 24 have a convex shape, but the lower surfaces of the other conductor layers 21 to 24 may also have a convex shape. Similarly, in the wiring board 100 of Figure 5, it was explained that only the upper surfaces of the first regions 311, 321, 331, and 341 directly beneath the wiring patterns 201 to 204 among the insulating layers 31 to 34 have a concave shape, but the upper surfaces of the insulating layers 31 to 34 that are covered by the conductor layers may also have a concave shape. Similarly, in the wiring board 100 of Figure 5, it was explained that only the upper surfaces of the second regions 312, 322, 332, and 342 exposed from the wiring patterns 201 to 204 among the insulating layers 31 to 34 have a convex shape, but the upper surfaces of the insulating layers 31 to 34 that are exposed from the conductor layers may also have a convex shape.

[0038] <Second Embodiment> Figure 6 shows a cross-sectional view of a wiring board 101, which is an example of a wiring board according to the second embodiment. As shown in Figure 6, the wiring board 101 includes a laminate 11 (first build-up layer) of a plurality of conductor layers and a plurality of insulating layers, and a build-up layer 12 (second build-up layer) composed of a laminate of an insulating layer 12a and a conductor layer 12b. The wiring board 101 in Figure 6 further includes a build-up layer 13 (third build-up layer) composed of a laminate of an insulating layer 13a and a conductor layer 13b.

[0039] The wiring board 101 in Figure 6 has a first surface 11F that corresponds to the first surface 1F of the wiring board 100 in Figure 5, and a second surface 13S that is the opposite surface of the first surface 11F. In the description of the wiring board 101, the side of the second surface 13S of the wiring board 101 is referred to as the "upper side" or simply "top". The build-up layer 12 is laminated on top of the laminate 11. The build-up layer 13 is laminated on top of the build-up layer 12.

[0040] The laminate 11, like the laminate 10 that constitutes the wiring board 100 in Figure 5, includes one or more conductor layers and one or more insulating layers. In the example in Figure 6, the laminate 11 includes four conductor layers 21-24 and four insulating layers 31-34. Similar to Figure 5, each conductor layer is formed on the upper surface of each insulating layer. That is, the conductor layers 21-24 are formed on the upper surfaces 31a-34a of each of the insulating layers 31-34. The conductor layers 21-24 each include wiring patterns 201-204, similar to the wiring board 100 in Figure 5.

[0041] The insulating layers 31-34 of the wiring board 101, similar to the wiring board 100 in Figure 5, consist of a first region 311, 321, 331, and 341 which is directly beneath the wiring patterns 201-204, and a second region 312, 322, 332, and 342 which is exposed from the wiring patterns 201-204 in a plan view. The Young's modulus of the first region 311, 321, 331, and 341 is low and soft, being 5% or more and 95% or less of the Young's modulus of the second region 312, 322, 332, and 342. Therefore, a highly adhesive metal film can be formed during the formation of each wiring pattern. This improves the adhesion of the wiring patterns, making peeling less likely and enabling the formation of fine wiring patterns.

[0042] Similar to the wiring board 100 in Figure 5, in the wiring board 101, the upper surfaces of the first regions 311, 321, 331, and 341 of the insulating layer directly beneath the wiring patterns 201 to 204 of the conductor layers 21 to 24 all have a curved concave shape. Furthermore, the lower surfaces of the wiring patterns 201 to 204 have a convex shape (first convex shape) that interlocks with this concave shape. This further improves the adhesion of the wiring patterns, making peeling less likely and enabling the formation of finer wiring patterns.

[0043] In Figure 6, wiring patterns 201 to 204 are formed to overlap in a plan view. That is, the upper surface of the wiring pattern formed on the lower surface of the insulating layer (lower wiring pattern) and the lower surface of the wiring pattern formed on the upper surface of the insulating layer (upper wiring pattern) face each other across the insulating layer. In the wiring board 101 shown in Figure 6, the lower surface of the upper wiring pattern formed on the upper surface of the insulating layer has a curved convex shape (first convex shape) that separates from the lower wiring pattern formed on the lower surface of the insulating layer at both ends. As a result, the effective distance between wiring patterns facing each other across the insulating layer is increased, or the effective area of ​​the lower surface of the upper wiring pattern is decreased. This reduces parasitic capacitance between wiring patterns and improves the high-speed signal transmission performance on the wiring board 101.

[0044] In the build-up layer 12, insulating layers 12a and conductor layers 12b are alternately stacked. Via conductors 12c are formed in the insulating layer 12a, penetrating each insulating layer 12a and connecting opposing conductor layers 12b through each insulating layer 12a. Each conductor layer 12b contains a desired conductor pattern.

[0045] The build-up layer 13 includes an insulating layer 13a formed on the insulating layer 12a and conductor layer 12b of the build-up layer 12, and a conductor layer 13b formed on the surface of the insulating layer 13a facing the second surface 13S of the wiring board 101. The insulating layer 13a has via conductors 13c formed thereon that penetrate the insulating layer 13a and connect the conductor layer 13b and the conductor layer 12b of the build-up layer 12. The conductor layer 13b may include a desired conductor pattern. In the example in Figure 6, the conductor layer 13b includes a conductor pad 13P.

[0046] The wiring board 101 in the example shown in Figure 6 further includes a solder resist layer 14 formed on the second surface 13S. The solder resist layer 14 is formed using, for example, a photosensitive polyimide resin or epoxy resin. An opening 14a is formed in the solder resist layer 14. The conductive pads 13P of the conductive layer 13b are exposed through the opening 14a.

[0047] The second surface 13S of the wiring board 101 is the surface that connects to external components (not shown) such as the motherboard of the electronic device in which the wiring board 101 is used when the wiring board 101 is in use. The conductor pads 13P may be connected to any circuit board, electrical component, or mechanical component.

[0048] The insulating layer 12a constituting the build-up layer 12 and the insulating layer 13a of the build-up layer 13 can be formed using any insulating resin. Although not shown, the insulating layers 12a and 13a may contain a core material (reinforcement) made of glass fibers or aramid fibers. In the example of Figure 6, the insulating layer 13a of the build-up layer 13 contains a core material 13aa made of glass fibers. The insulating layers 12a and 13a may further contain an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. In the wiring board 101, the thickness of the insulating layer 12a may be greater than the thickness of the insulating layer constituting the laminate 11, and the thickness of the insulating layer 13a may be greater than the thickness of the insulating layer 12a.

[0049] The conductor layer 12b of build-up layer 12 and the conductor layer 13b of build-up layer 13, as well as the via conductors 12c and 13c, can be formed using any metal such as copper or nickel, similar to the conductor layers 20-25 and via conductor 11c. The conductor layer 12b, conductor layer 13b, and via conductors 12c and 13c may have only one layer, for example, consisting of a plating film, or they may have a multilayer structure including two or more metal films formed by any method such as sputtering or various plating processes. In the wiring board 101, the thickness of the conductor layer 12b may be greater than the thickness of the conductor layer constituting the laminate 11, and the thickness of the conductor layer 13b may be greater than the thickness of the conductor layer 12b.

[0050] <Method for manufacturing a wiring board according to an embodiment> Referring to Figures 7A to 7K, an example of a manufacturing method for the wiring board of the embodiment will be described using the wiring board 101 shown in Figure 6 as an example. Note that, unless otherwise specified, each component formed in the manufacturing method described below may be formed using the materials exemplified as the materials for the corresponding components in the description of the wiring board 1 in Figures 1 to 2.

[0051] First, as shown in Figure 7A, a support substrate SP is prepared, which includes a core layer GS and metal film layers ML1 and ML2 laminated on both sides of the core layer GS, respectively. The core layer GS is composed of, for example, glass material or glass epoxy material. The metal film layers ML1 and ML2 are metal layers formed by electroless plating or sputtering, etc., using materials such as copper or titanium, respectively. The metal film layer ML1 and the metal film layer ML2 are joined by an adhesive layer AL, which is composed of, for example, an adhesive whose adhesive properties change upon light irradiation.

[0052] In the following explanation, the side of the support substrate SP closer to the core layer GS will be referred to as the "lower side" or simply "bottom," and the side further from the core layer GS will be referred to as the "upper side" or simply "top." Therefore, the side of each component of the manufactured wiring board facing the support substrate SP will also be referred to as the "bottom surface," and the side facing away from the support substrate SP will also be referred to as the "top surface."

[0053] Next, as shown in Figure 7B, a conductive layer 20 including a plurality of conductive pads 20P is formed on the support substrate SP. In the formation of the conductive layer 20, for example, a resist film (not shown) is formed on the metal film layer ML2. By forming openings in the resist film corresponding to the formation areas of the conductive pads 20P using photolithography, a plating resist is formed. A plating film is formed within the openings in the plating resist by electroplating using the metal film layer ML2 as a power supply layer. Subsequently, the plating resist is removed to form the conductive layer 20 as shown in Figure 7B.

[0054] Note that in Figure 7B, and in Figures 7C to 7K referred to below, only one surface of the support substrate SP is shown after each process, and the state of the other surface is omitted. However, the insulating layer and the conductive layer may be formed on the surface of the support substrate SP on the side that is omitted from the illustration, just as on the illustrated side, or such conductive layer and insulating layer may not be formed.

[0055] Next, an insulating layer 31 is formed to cover the conductive layer 20. The insulating layer 31 is preferably formed of a photosensitive resin. Examples of photosensitive resins include photosensitive acrylic resins, photosensitive polyimide resins, photosensitive polybenzoxazole resins, photosensitive phenolic resins, photosensitive epoxy resins, photosensitive cycloolefin resins, or photosensitive benzocyclobutene resins. The insulating layer 31 is formed, for example, by laminating a photosensitive resin molded into a film. Alternatively, the photosensitive resin may be formed through a liquid coating and heat curing process.

[0056] Next, the Young's modulus of the insulating layer 31 is adjusted by performing an exposure treatment on the insulating layer 31. The exposure treatment consists of a first exposure step in which the entire surface of the insulating layer 31 is exposed, and a second exposure step in which only the area of ​​the insulating layer 31 not covered by the wiring pattern 201 (see Figure 7H) is exposed. In the first exposure step, any exposure method, including direct imaging, is used. In the second exposure step, exposure treatment by direct imaging is preferably performed as shown in Figure 7C. In direct imaging, laser light LZ is directly irradiated onto the insulating layer 31 along the pattern without using an exposure mask. With direct imaging, compared to when an exposure mask is used, a wide area can be exposed with a fine pattern in a single step.

[0057] In the second exposure step, additional exposure is performed by irradiating only the area of ​​the insulating layer 31 that is not covered by the wiring pattern 201 with laser light LZ. As shown in Figure 7D, the first region 311 of the insulating layer 31 directly beneath the wiring pattern 201 of the conductor layer 21 formed in the steps of Figures 7E to 7H described later, and the second region 312 of the insulating layer 31 that is exposed from the wiring pattern 201 in a plan view are formed. The Young's modulus of the first region 311 is 5 to 95% lower than that of the second region 312. This improves the adhesion of the sputtered film to the first region 311 while improving the peelability of the sputtered film in the second region 312 during the formation process of the conductor layer 21 (Figures 7E to 7H). Note that the order of the first exposure step and the second exposure step may be reversed, and the first exposure step may be performed after the second exposure step.

[0058] In the first and second exposure processes, an unexposed region 313 is formed in the area where the via conductor 11c (see Figure 7I) of the insulating layer 31 is to be formed. Specifically, when direct imaging is used in the first and / or second exposure processes, the laser light LZ is not irradiated onto the region 313 of the insulating layer 31. When the entire insulating layer 31 is exposed in the first exposure process, an exposure mask is formed in advance on the upper surface of the region 313 of the insulating layer 31.

[0059] Next, as shown in Figure 7D, through-holes 11d are formed in the insulating layer 31 by the photolithography process. That is, the photosensitive resin in the unexposed region 313 is removed by the development process after the exposure process, and through-holes 11d are formed in the insulating layer 31. The through-holes 11d may also be formed by laser irradiation, such as carbon dioxide laser light or excimer laser light. In this case, preferably, after the formation of the through-holes 11d, resin residue (smear) that tends to form in the through-holes 11d is removed by dry desmearing with plasma gas or wet desmearing with a permanganate solution.

[0060] Next, the shape of the upper surface of the insulating layer 31 is fixed by a baking process. That is, as shown in Figure 7D, the upper surface of the first region 311 of the insulating layer 31, which is exposed only once, becomes concave, and the upper surface of the second region 312, which is exposed again, becomes convex (second convex shape).

[0061] Next, a conductor layer 21 including a wiring pattern 201 (see Figure 7I) is formed on the upper surface 31a of the insulating layer 31 through the process shown in Figures 7E to 7I. First, as shown in Figure 7E, a metal film 2a is formed on the inner wall surface of the through hole 11d and the upper surface 31a of the insulating layer 31 by sputtering. By using sputtering, a thin and uniform metal film 2a can be easily formed. Copper, copper alloy, nickel, nickel alloy, titanium, or titanium alloy can be used as the sputtering target, and the metal film 2a can be formed as a sputtered film containing copper, copper alloy, nickel, nickel alloy, titanium, or titanium alloy. The metal particles formed by sputtering do not adhere well to the second region 312, where the Young's modulus is increased by additional exposure in the process shown in Figure 7C, and are easily peeled off. On the other hand, in the first region 311, where there is no additional exposure and the Young's modulus is low, the metal particles penetrate deep into the material, so a metal film 2a with high adhesion and resistance to peeling can be formed.

[0062] The process shown in Figures 7E to 7I improves the adhesion between the wiring pattern 201 formed in the first region 311 with the metal film 2a as a seed layer and the insulating layer 31, making peeling less likely and enabling the formation of fine wiring patterns. Furthermore, since the metal film 2a on the upper surface of the second region 312, where no wiring pattern is formed, can be easily removed, short circuits between adjacent wirings and between wirings and via conductors are suppressed.

[0063] Next, as shown in Figure 7F, a resist layer 40 is formed on the upper surface 31a of the insulating layer 31 via the metal film 2a. The resist layer 40 is formed by bonding a dry film resist, for example, one containing a photosensitive epoxy resin, polyhydroxy ether resin, phenol resin, or polyimide resin.

[0064] Next, as shown in Figure 7G, exposure and development are performed on the resist layer 40 using a mask having an appropriate aperture pattern, thereby forming a resist wall 4 on the resist layer 40. As a result, the resist wall 4 has an aperture 4a corresponding to the wiring pattern 201 of the conductor layer 21 (Figure 7I), an aperture 4c corresponding to other conductor patterns of the conductor layer 21, and a through hole 11d. The exposure treatment used to form the resist wall 4 can be performed by any exposure method, and may be performed by direct imaging as shown in Figure 7C.

[0065] Next, as shown in Figure 7H, a plating film 2b is formed within the opening 4a of the resist layer 40. The plating film 2b is formed by pattern plating using the resist layer 40 as a mask. Preferably, the plating film 2b is formed by electroplating with the metal film 2a as the power supply layer. The plating film 2b is also filled into the opening 4c of the resist layer 40, forming various conductor patterns such as via conductors 11c (see Figure 7I).

[0066] Next, the resist layer 40 is removed, for example, using an alkaline stripping solution. Furthermore, the portion of the metal film 2a that is exposed by the removal of the resist layer 40 is removed, for example, by quick etching. This forms a conductor layer 21 including the wiring pattern 201, as shown in Figure 7I. A via conductor 11c that penetrates the insulating layer 31 is also formed. The wiring pattern 201 is composed of the metal film 2a and the plating film 2b. Similar to Figure 5, the wiring pattern 201 is formed on the upper surface of the first region 311 of the insulating layer 31 directly beneath the wiring pattern 201, and the lower surface of the wiring pattern 201 has a curved convex shape (first convex shape) that fits into the curved concave shape of the upper surface of the first region 311. This further enhances the adhesion between the wiring pattern 201 and the insulating layer 31.

[0067] Next, as shown in Figure 7J, a desired number of insulating layers and conductive layers, as well as via conductors penetrating each insulating layer, are formed using the same procedure and method as previously described for forming the insulating layer 31, conductive layer 21, and via conductor 11c (Figures 7B to 7I). In Figure 7J, three additional insulating layers 32 to 34 and conductive layers 22 to 24 are formed. Although the conductive layer 21 is simplified and shown as a single layer in Figures 7J to 7L, it has a two-layer structure consisting of a metal film 2a and a plating film 2b, similar to Figure 7I. Conductor layers 22 to 24 also have a two-layer structure consisting of a metal film 2a and a plating film 2b. Then, an insulating layer 35 is formed on top of the uppermost insulating layer 34 and conductive layer 24. For the insulating layer 35, for example, a photosensitive resin similar to that used for the insulating layer 31 may be used, or any other arbitrary insulating resin material may be used. Furthermore, a conductive layer 25 is formed on the surface of the insulating layer 35, for example, by a general semi-additive method. Furthermore, via conductors 11c that penetrate the insulating layer 35 are formed together with the conductor layer 25.

[0068] Furthermore, as shown in Figure 7K, a build-up layer 12 is formed. That is, an insulating layer 12a and an insulating layer 12b are alternately laminated in a desired number on top of the conductor layer 25 and the insulating layer 35. In Figure 7K, three sets of insulating layers 12a and conductor layers 12b are laminated. Each insulating layer 12a has via conductors 12c formed to connect the upper and lower conductor layers. The insulating layer 12a is formed, for example, by thermocompression bonding of an insulating resin molded into a film. In forming the insulating layer 12a, instead of a film-like resin, a core-filled resin molded into a sheet, such as a prepreg, may be used. The conductor layers 12b and via conductors 12c are formed using any method, for example, by a semi-additive method.

[0069] Next, a build-up layer 13 is formed on the uppermost insulating layer 12a and conductor layer 12b of the build-up layer 12. First, the insulating layer 13a is formed in the same manner as the insulating layer 12a. In the example of Figure 7K, the insulating layer 13a is formed using a prepreg containing a core material 13aa made of, for example, glass fiber. A prepreg with copper foil may also be used. Through holes are formed in the insulating layer 13a at the locations where via conductors 13c are to be formed by laser irradiation or drilling. Then, the conductor layer 13b is formed on the surface of the insulating layer 13a, and via conductors 13c are formed in the through holes of the insulating layer 13a. The conductor layer 13b and via conductors 13c are formed by any method, for example, using an appropriate method such as a semi-additive method or a subtractive method.

[0070] Next, a solder resist layer 14 is formed on the surfaces of the insulating layer 13a and the conductive layer 13b using a photosensitive epoxy resin or polyimide resin. Then, an opening 14a defining the conductive pad 13P is formed using photolithography technology.

[0071] Next, as shown in Figure 7L, the core layer GS of the support substrate SP is removed. This exposes the underside of the metal film layer ML2 beneath the conductor pad 20P. During the removal of the support substrate SP, for example, the adhesive layer AL is softened by laser irradiation, after which the metal film layer ML2 is peeled off from the adhesive layer AL. Then, the metal film layer ML2 is removed by etching, exposing the underside of the conductor pad 20P and the underside of the insulating layer 31. The wiring board 101 shown in Figure 6 is completed.

[0072] In the manufacturing method of the wiring board of the embodiment illustrated in Figures 7A to 7L, it was explained that only the lower surfaces of the wiring patterns 201 to 204 among the conductor layers 21 to 24 have a convex shape, but the lower surfaces of the other conductor layers 21 to 24 may also have a convex shape. Similarly, in Figures 7A to 7L, it was explained that only the upper surfaces of the first regions 311, 321, 331 and 341 directly beneath the wiring patterns 201 to 204 among the insulating layers 31 to 34 have a concave shape, but the upper surfaces of the insulating layers 31 to 34 that are covered by the conductor layers may also have a concave shape. Similarly, in Figures 7A to 7L, it was explained that only the upper surfaces of the second regions 312, 322, 332 and 342 exposed from the wiring patterns 201 to 204 among the insulating layers 31 to 34 have a convex shape, but the upper surfaces of the insulating layers 31 to 34 that are exposed from the conductor layers may also have a convex shape.

[0073] The wiring boards of the embodiments are not limited to those having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. As stated above, the wiring boards of the embodiments may have any laminated structure. The wiring boards of the embodiments may have any number of conductor layers and insulating layers. Each conductor layer may include any conductor pattern other than the wiring pattern. The wiring pattern does not have to be provided on all conductor layers, and the surface of the wiring board of the embodiments does not have to be a component mounting surface. The insulating layers 12a and 13a may be thinner than the insulating layers 31-34, and the conductor layers 12b and 13b may be thinner than the conductor layers 21-24. [Explanation of symbols]

[0074] 1, 1α, 100, 101 Wiring board 20, 23, 24, 25 Conductor layers 21, 21α Conductor layer (lower conductor layer) 22 Conductor layer (upper conductor layer) 201, 201S Wiring Pattern (Lower Wiring Pattern) 202, 202S wiring pattern (upper wiring pattern) Wiring patterns 203 and 204 Top view of the 201a wiring pattern Underside of wiring patterns 201b and 202b 31, 31α, 32, 33, 34, 35 Insulating layer 311, 321, 331, 341 First region of the insulating layer 312, 322, 332, 342 Second region of the insulating layer 31a, 32a, 33a, 34a Upper surface of the insulating layer 2a Metal film 2b Plating film 4 Resistance Wall 40 resistance layers d Distance between conductive layers stacked with an insulating layer in between.

Claims

1. Insulating layer and, An upper conductor layer is laminated on the upper surface of the insulating layer and includes an upper wiring pattern, A wiring board including, The upper surface of the insulating layer directly beneath the upper wiring pattern has a curved concave shape. The lower surface of the upper wiring pattern of the upper conductor layer has a curved first convex shape that fits into the concave shape. The upper surface of the insulating layer exposed from the upper wiring pattern has a curved second convex shape.

2. A wiring board according to claim 1, The insulating layer is a negative-type photosensitive resin material.

3. A wiring board according to claim 1, The upper surface of the upper wiring pattern has a flat shape.

4. A wiring board according to claim 1, The Young's modulus of the insulating layer directly beneath the upper wiring pattern is 5% or more and 95% or less of the Young's modulus of the insulating layer exposed from the upper wiring pattern.

5. A wiring board according to claim 1, The upper conductor layer has a metal film in contact with the upper surface of the insulating layer and a plating film in contact with the metal film.

6. A wiring board according to claim 5, The aforementioned metal film is a sputtered film.

7. A wiring board according to claim 1, The aforementioned wiring board is The insulating layer further includes a lower conductor layer formed on the lower surface and containing a lower wiring pattern, The flat upper surface of the lower wiring pattern and the lower surface of the upper wiring pattern having the first convex shape face each other.

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