Indication device

Abstract

To provide semiconductor devices that can keep power consumption low. [Solution] The electrical connection between the first and second transistors having the same polarity as the first wiring to which a first potential is supplied, the second wiring to which a second potential higher than the first potential is supplied, the third wiring to which a third potential higher than the second potential is supplied, and the fourth wiring to which a first clock signal is supplied in which the same potential as or higher than the third potential and the second potential are sequentially repeated is the first wiring to which a first potential is supplied, the second wiring to which a second potential higher than the first potential is supplied, and the gate of the first transistor or the gate of the second transistor and the first wiring or the third wiring is the first wiring to which A semiconductor device having a circuit that controls a second clock signal and an input signal, wherein a third potential and a third potential are repeated in sequence, one of the source and drain of the first transistor is connected to a second wire, one of the source and drain of the second transistor is connected to a fourth wire, and the other of the source and drain of the first transistor and the other of the source and drain of the second transistor are connected to each other.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. In particular, one aspect of the present invention relates to a unipolar transistor This relates to semiconductor devices such as sequential circuits using the above-mentioned sequential circuits and semiconductor display devices using the above-mentioned sequential circuits. . [Background technology]

[0002] A semiconductor display device whose drive circuit is composed of unipolar transistors requires cost to manufacture. It is desirable because it can lower the temperature. Patent documents 1 and 2 below describe semiconductor display devices. Various circuits used in drive circuits, such as inverters and shift registers, are unipolar transistors. The technology that makes up ZISTA is disclosed. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2001-325798 [Patent Document 2] Japanese Patent Publication No. 2010-277652 [Overview of the project] [Problems that the invention aims to solve]

[0004] Unipolar transistors are prone to a negative threshold voltage shift due to various factors, and normal It has a tendency to become ion. Semiconductor display devices composed of unipolar transistors In the drive circuit, in a sequential circuit that outputs a pulsed signal, the threshold voltage of the transistor When the voltage shifts to the negative, the amplitude of the potential of the output signal decreases, and the drive circuit becomes positive. It will stop working at all times. Or, even if normal operation can be ensured, the power consumption of the drive circuit will be It will increase.

[0005] For example, in the circuit described in FIG. 10 of Patent Document 2, the transistor Q2 has its source fixed to the low potential VSS. If the transistor Q2 is normally off, when a low potential VSS is applied to its gate, the transistor Q2 enters a non-conducting state (off). However, if the transistor Q2 is normally on, even when a low potential VSS is applied to its gate, the gate voltage, which is the voltage between the gate and the source with respect to the potential of the source, remains higher than the threshold voltage of the transistor Q2. Therefore, the transistor Q2 does not turn off and enters a conducting state (on).

[0006] If the transistor Q2 turns on when it should be off, an unnecessary current will flow in the circuit, increasing the power consumption. Furthermore, due to the above unnecessary current, a current will flow in the wiring for supplying a potential (for example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS, or the high-level potential VDD and the low-level potential VSS of the clock signal CLKA) to the circuit. And due to the resistance of the above wiring, the potential of the wiring for supplying the potential VDD will decrease, and the potential of the wiring for supplying the potential VSS will increase. As a result, the amplitude of the potential output from the circuit becomes smaller than the potential difference between the potential VDD and the potential VSS, which is the ideal potential difference. It will become smaller.

[0007] [[ID=3 / 8]]Also, if the transistor (for example, the transistor Q1 in the case of FIG. 10 of Patent Document 2) that controls the electrical connection between the wiring to which the clock signal is supplied and the output terminal is normally on, the output terminal is charged and discharged through the transistor Q1, increasing the power consumption of the circuit. As a result, the power consumption of the circuit increases.

[0008] In particular, in the pixel section of a semiconductor display device, a bus line is connected to multiple pixels. When supplying potential output from a circuit to wiring, such as scan lines or signal lines, A transistor that controls the potential output (for example, in the case of Figure 10 of Patent Document 2, the transistor Transistor Q1 (and transistor Q2) require a large current supply capacity. Therefore, the transistor The channel width W of the transistor is greater than the channel width W of the other transistors in the circuit. It is often designed to a specific value. However, the drain current of a transistor is often relative to the channel width W. For example, if the channel width W of a normally on transistor is increased, it turns off When this should be the case, the current flowing through that transistor becomes larger than that of other transistors. Therefore, the unnecessary current flowing through the circuit increases, leading to increased power consumption, or the output power... The phenomena described above, such as a decrease in amplitude, are more likely to occur.

[0009] Based on the technical background described above, the present invention provides a semiconductor device that can keep power consumption low. One of the challenges is to provide the following. Alternatively, in this invention, the amplitude of the output potential becomes smaller. One of the challenges is to provide semiconductor devices that can prevent this from happening. [Means for solving the problem]

[0010] In one aspect of the present invention, a first transistor controls the supply of power potential to the output terminal, and output A second transistor controls the supply of the clock signal potential to the terminal, and the first transistor The electrical relationship between the gate and the gate of the second transistor and the pair of wires to which the power supply potential is supplied. It has a circuit that controls the connection, and the connection is between the source and drain of the first transistor. The power supply potential supplied to the output terminal is different from the wiring to which the pair of power supply potentials are supplied. The power is to be supplied to the sequential circuit via a wire.

[0011] With the above configuration, the gate of the first transistor and the source and drain of the first transistor are... One of them can be electrically isolated. Therefore, the source and drain of the first transistor The power supply potential supplied to one side of the input and the power supply potential supplied to the gate of the first transistor By controlling each of these, the gate voltage of the first transistor is controlled so that it turns off. Therefore, even if the first transistor is normally on, the first The transistor can be turned off when it should be turned off.

[0012] Furthermore, in one aspect of the present invention, the first transistor and the second transistor are of the n-channel type. In this case, of the two potentials of the above clock signal, the source and drain of the first transistor The potential closest to the power supply potential supplied to the output terminal via the input is the same as the power supply potential mentioned above. or higher. Also, the first and second transistors are p-channel. In the case of a type 1, of the binary potentials of the above clock signal, the saturation of the first transistor The potential closer to the power supply potential supplied to the output terminals via the gap between the drain and the power supply is the power supply potential mentioned above. It should be the same as or lower than the rank.

[0013] With the above configuration, even if the second transistor is normally on, the second transistor is turned off. It can be turned off when it should be. Therefore, the output terminal is connected via the second transistor. This prevents the battery from being charged and discharged, keeping the circuit's power consumption low.

[0014] Specifically, a semiconductor device according to one aspect of the present invention is supplied with a first potential (VSS) A wiring, a second wiring to which a second potential (VEE) higher than the first potential is supplied, and a wiring to which a second potential higher than the second potential is supplied The third wiring is supplied with a high third potential (VDD), and the third wiring is supplied with a third potential that is the same as or higher than the third potential. The first clock signal (CLKB), which alternates between the fourth potential (VCC) and the second potential, The supplied fourth wiring, the first and second transistors having the same polarity, and The gate of one transistor or the gate of the second transistor and the first wiring or the third wiring The electrical connection is connected to a second clock signal in which the first potential and the third potential are repeated in sequence, and the input The circuit has a signal (Vin) and controls according to the source and drain of the first transistor. One end of the input is electrically connected to the second wiring, and the source and drain of the second transistor. One end of the input is electrically connected to the fourth wire, and the source and drain of the first transistor. The other end of the input and the other end of the source and drain of the second transistor are electrically connected to each other. It is being done. [Effects of the Invention]

[0015] In one aspect of the present invention, a semiconductor using a unipolar transistor, which can keep power consumption low, is used. A device can be provided. Alternatively, in one aspect of the present invention, the amplitude of the output potential is We can provide a semiconductor device that can prevent miniaturization. [Brief explanation of the drawing]

[0016] [Figure 1] A diagram showing the configuration of a sequential circuit and a diagram showing the waveform of the clock signal potential. [Figure 2] A diagram showing the configuration of a sequential circuit. [Figure 3] A timing chart illustrating the operation of a sequential circuit. [Figure 4] A diagram showing the configuration of a shift register. [Figure 5] A timing chart showing the operation of a shift register. [Figure 6] A schematic diagram showing the jth sequential circuit 10_j. [Figure 7] A diagram showing the configuration of a sequential circuit. [Figure 8] A diagram showing the configuration of a sequential circuit. [Figure 9] A diagram showing the configuration of a sequential circuit. [Figure 10] A diagram showing the configuration of a semiconductor display device. [Figure 11] Top view of a pixel. [Figure 12] Cross-sectional view of a pixel. [Figure 13] A diagram showing the cross-sectional structure of a transistor. [Figure 14] Top view of a liquid crystal display device. [Figure 15] Cross-sectional view of a liquid crystal display device. [Figure 16] A diagram of an electronic device. [Modes for carrying out the invention]

[0017] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0018] Furthermore, the present invention relates to integrated circuits, RF tags, semiconductor display devices, and other devices that utilize transistors. This category includes all kinds of semiconductor devices. Note that integrated circuits include microprocessors, image processors, etc. Circuitry, DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit) including Trolla t), FPGA (Field Programmable Gate Array) and C Programmable logic circuits such as PLDs (Complex PLDs) (PLD: Progr Amplifiable Logic Devices (AMMABLE Logic Devices) fall into this category. Also, semiconductor tables... The display device includes a liquid crystal display device and a light-emitting device with light-emitting elements, such as organic light-emitting elements, in each pixel. Electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi It has circuit elements using semiconductor films in its driving circuit, such as a ssion display. Semiconductor display devices fall into that category.

[0019] In this specification, a semiconductor display device refers to a device in which display elements such as liquid crystal elements and light-emitting elements each screen. A panel formed in its raw state, and a model in which an IC including a controller is mounted on the panel. This category includes Joules.

[0020] Furthermore, in this specification, "connection" means an electrical connection, and current, voltage, or potential is This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes states where devices are electrically connected.

[0021] Furthermore, the source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to a region, or a source electrode electrically connected to the semiconductor film mentioned above. Similarly, transient The drain of a stylus is a drain region that is part of the semiconductor film that functions as the active layer, or This refers to the drain electrode electrically connected to the semiconductor film mentioned above. The gate, on the other hand, refers to the gate electrode. It means...

[0022] The source and drain of a transistor are supplied to the channel and each terminal of the transistor. The name changes depending on the level of the potential being generated. Generally, n-channel type transients In a stator, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the dot. It is called rain. Also, in p-channel transistors, the terminal to which a low potential is applied is The terminal to which a high potential is applied is called the source, and is called the drain. In this specification, for convenience, Above, assuming the source and drain are fixed, we will explain the connection relationship of the transistor. Although it may be clarified in some cases, in practice the names of source and drain are assigned according to the potential relationship described above. It will change.

[0023] <Examples of sequential circuit configurations> Figure 1(A) shows an example of the circuit configuration of a sequential circuit according to one aspect of the present invention. The sequential circuit 10 shown includes a circuit 11 having multiple transistors, a transistor 12, and It has a transistor 13. In the sequential circuit 10 shown in Figure 1(A), at least a transistor Transistor 12 and transistor 13 have the same polarity. In Figure 1(A), transistor This example illustrates the case where both transistor 12 and transistor 13 are of the n-channel type.

[0024] Circuit 11 receives a high-level power supply potential VDD via wiring 14 and a low-level power supply potential VDD via wiring 15. The power supply potential VSS of each level is supplied. In addition, circuit 11 is supplied via wiring 17. The potential of the input signal Vin is supplied, and multiple clock signals CLK are transmitted via multiple wirings 18. Potential A is supplied to each.

[0025] Circuit 11 distributes the potentials according to the potential of the input signal Vin and the potentials of the multiple clock signals CLKA. The wire 14 or wiring 15 and the gate of transistor 12 or the gate of transistor 13 It has the function of controlling the electrical connection.

[0026] Furthermore, transistor 12 is connected to wiring 16 to which a low-level power supply potential VEE is supplied, and output It has the function of controlling the electrical connection with terminal 20. In addition, transistor 13 is a cross A function that controls the electrical connection between the wiring 19 to which the signal CLKB is supplied and the output terminal 20. It holds.

[0027] Specifically, transistor 12 has either its source or drain electrically connected to wiring 16. The source and drain are electrically connected to the output terminal 20. The zista 13 has either its source or drain electrically connected to the wiring 19, and the source The other end of the drain is electrically connected to the output terminal 20.

[0028] Furthermore, a capacitive element that has the function of holding the gate voltage of transistor 13 is used as the transistor It may also be connected to the gate of 13. However, the parasitic capacitance of the gate of transistor 13 is In cases where the gate voltage can be maintained without providing a capacitive element, such as when the capacitance is large, it is not necessarily required to provide a capacitive element. There is no need to provide a quantitative element.

[0029] Multiple pixels are connected to a wiring called a bus line, from the output terminal 20 of the sequential circuit 10. When supplying the output potential Vout, the transistor controls the output of the above potential Vout. Transistors 12 and 13 require a large current supply capacity. Therefore, the transistors The channel width W of transistors 12 and 13 is greater than that of the transistors in circuit 11. It is desirable to set it to a large value.

[0030] Furthermore, the power supply potential VEE is lower than the power supply potential VDD and higher than the power supply potential VSS. It is desirable to do so.

[0031] Furthermore, in one aspect of the present invention, the clock signal CLKB has a repeating binary potential, and The low-level potential on the side closer to the source potential VSS is the same as or higher than the power supply potential VEE. Let's assume that... Figure 1(B) shows a crossover where the power supply potential VSS and the power supply potential VDD are repeated in sequence. The waveform of the potential of the signal CLKA, and the power supply potential VEE and the power supply potential V which is higher than the power supply potential VDD. The waveform of the potential of the clock signal CLKB, in which CC and are repeated in sequence, is illustrated as an example. In 1(B), the high-level potential of the clock signal CLKB is higher than the power supply potential VDD. The example shows the power supply potential VCC, but the clock signal CLKB is at a high level potential. It is sufficient for the voltage to be equal to or higher than the power supply potential VDD.

[0032] If transistor 13 is an n-channel type, then from circuit 11 to the gate of transistor 13 When a potential higher than the power supply potential VDD is supplied, the source and drain of transistor 13 The high-level potential VCC of the clock signal CLKB supplied to one side is the ON transistor It is supplied to the output terminal 20 via transistor 13. Then, the gate of transistor 13 is supplied from circuit 11. Power supply potential VSS is supplied to the terminal, and a crossover is made to either the source or drain of transistor 13. When a low-level potential VEE of the clock signal CLKB is supplied, the gate of transistor 13 The voltage is equal to the potential VSS - VEE. The potential V is set such that the potential VSS - VEE ≤ Vth. By setting the height of EE, even if transistor 13 is normally on, the transistor Transistor 13 can be turned off, and the wiring 18 is charged and discharged via transistor 13. This prevents excessive power consumption.

[0033] Furthermore, if transistor 12 is an n-channel type, transistor 12 is connected to circuit 11. The gate is connected to the power supply potential VDD or the threshold voltage of the transistor used in circuit 11. It turns on when a potential lower than the power supply potential VDD is supplied by a certain amount. Also, transistor 1 2. When the power supply potential VSS is supplied to its gate from circuit 11, the gate voltage Vgs is V The result is SS-VEE. The height of the potential VEE is set such that the potential VSS-VEE ≤ Vth. By setting this, even if transistor 12 is normally on, transistor 12 can be turned off. This allows for increased power consumption.

[0034] Furthermore, when the transistor in circuit 11 is also normally on, just like transistor 12, Current flows through the transistor in circuit 11 to the wiring 15, causing the potential of the wiring 15 to rise. The potential of line 15 is supplied to the gate of transistor 12 via circuit 11, therefore wiring 1 Due to the rise in potential at 5, the potential supplied to the gate of transistor 12 also increases to the power supply potential VSS. The potential rises to VSS+Vα.

[0035] Even if the potential supplied to the gate of transistor 12 increases, the gate voltage Vgs = VSS+ If Vα - VEE ≤ Vth, transistor 12 remains off. Therefore, the gate To ensure that voltage Vgs ≤ Vth, the power supply potential VS is calculated, taking into account the potential rise across wiring 15. If S and the height of the power supply potential VEE are determined, then even if transistor 12 is normally on, When the transistor 12 should be turned off, it can be brought to a state close to being off.

[0036] Furthermore, the output terminal 2 of the sequential circuit 10 is connected to a wiring called a bus line that is connected to multiple pixels. When supplying a potential Vout that is output from 0, transistors 12 and 13 A large current supply capacity is required, but the transistor in circuit 11 is transistor 12 Furthermore, a current supply capacity as large as that of transistor 13 is not required. Therefore, the transistor in circuit 11 The channel width W of the transistor is greater than the channel width W of transistors 12 and 13. It can also be made smaller. Therefore, the transistor in circuit 11 is normally on, Even if the gate voltage is slightly higher than the threshold voltage, the transistor in circuit 11 will The current flowing through wiring 15 is when the gate voltage of transistor 12 is slightly greater than the threshold voltage. The current flowing through wiring 16 can be made smaller. Therefore, wiring 15 It is relatively easy to keep the voltage Vα, which corresponds to the change in potential, small.

[0037] Thus, in the sequential circuit 10 according to one aspect of the present invention, the transistor 12 located on the output side A wire 16 electrically connected to either the source or drain of the transistor of circuit 11, and the transistor of circuit 11. By configuring the system to electrically isolate the electrically connected wiring 15 from the transistor, The power supply potential VEE supplied to either the source or drain of transistor 12, and the power supply potential VEE supplied to transistor 12 The power supply potential VSS supplied to the gate can be controlled separately. Even if transistor 12 is normally on, it is still possible to turn off transistor 12. The gate voltage of transistor 12 can be controlled so that it turns off when the transistor is activated. Therefore, the power consumption of the sequential circuit 10 can be kept low, and also, from the sequential circuit 10 This prevents the amplitude of the output potential Vout from decreasing.

[0038] Note that in Figure 1(A), both transistor 12 and transistor 13 are n-channel type. The example given is that transistor 12 and transistor 13 are both p-channels. A Nell type is also acceptable. However, in this case, the wiring 15 connected to circuit 11 and the transistor Wiring 16 connected to either the source or drain of station 12 has a higher frequency than wiring 14. The configuration is such that an electric potential is supplied. Furthermore, the electric potential of wiring 16 is lower than the electric potential of wiring 15. Let's assume that.

[0039] <Example 1 of a specific sequential circuit configuration> Next, a specific example of the configuration of the sequential circuit 10 will be described. Figure 2 shows one aspect of the present invention. An example of a sequential circuit is shown.

[0040] The sequential circuit 10 shown in Figure 2 consists of circuit 11, transistor 101 and transistor 102 It has. Transistor 101 corresponds to transistor 12 in Figure 1(A), and the transistor Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, the sequential circuit 10 has wiring. Various power potentials are supplied via wiring 110 to 112, and via wiring 113 to 115 The clock signals CLKA1 to CLKA3 are then supplied respectively. Additionally, a clock signal CLKB is supplied via wiring 116 and input via wiring 117. The signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, sequential rotation In path 10, the output signal SROUT is output via wiring 119, and the output signal GOUT is distributed It is output via line 120.

[0041] Furthermore, in the sequential circuit 10 shown in Figure 2, circuit 11 is a transistor 130 to transistor It has 139.

[0042] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0043] Transistors 101 and 102, and transistors 130 to 1 If 39 is an n-channel type, specifically, the power supply potential VDD is supplied to the wiring 110. Power supply potential VSS is supplied to wiring 111, and power supply potential VEE is supplied to wiring 112. Furthermore, the input signal LIN is supplied to wiring 117, and the input signal RIN is supplied to wiring 118. The input signals LIN and RIN are supplied to the sequential circuit 10 shown in Figure 1(A). This corresponds to the input signal Vin.

[0044] Transistor 130 has a gate that is the same as the gate of transistors 136 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other drain is connected to one of the sources and drains of transistor 137, and transistor 13 It is connected to either the source or the drain of transistor 9. Transistor 136 is connected to its source One of the drains is connected to wiring 111, and the other of its source and drain is connected to wiring 11 It is connected to 9. Transistor 101 has one of its sources and drains connected to wiring 11 It is connected to 2, and its source and drain are connected to wiring 120.

[0045] Furthermore, transistor 131 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 13 It is connected to the other side of the source and drain of 0. Transistor 134 has its gate It is connected to wiring 114, and one of its source and drain is connected to wiring 110, and its source The other end of the source and drain is connected to one of the source and drain of transistor 133. Transistor 135 has its gate connected to wiring 118, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 13 It is connected to the gates of transistor 0, transistor 136, and transistor 101.

[0046] Transistor 133 has its gate connected to wiring 115, and its source and drain The other side is in contact with the gates of transistors 130, 136, and 101. It is continued. Transistor 132 has its gate connected to wiring 117, and its source One of the drains is connected to wiring 111, and the other of its source and drain is a transient It is connected to the gates of transistor 130, transistor 136, and transistor 101. Transistor 137 has its gate connected to wiring 110, and its source and drain One side is the source and drain of transistor 131, the other side is the source of transistor 130. and connected to the other side of the drain, the source and the other side of the drain are of transistor 138 It is connected to the gate. Transistor 138 has one of its sources and drains wired. It is connected to 113, and the source and drain of that one end are connected to wiring 119.

[0047] Transistor 139 has its gate connected to wiring 110, and its source and drain One side is the source and drain of transistor 131, the other side is the source of transistor 130. It is connected to the other side of the drain, and its source and the other side of the drain are connected to transistor 102 It is connected to the gate. Transistor 102 has one of its sources and drains wired. It is connected to 116, and the other end of its source and drain is connected to wiring 120.

[0048] The operation of the sequential circuit 10 shown in Figure 2 will be explained using the timing chart shown in Figure 3. I will reveal it.

[0049] As shown in Figure 3, during period t1, the clock signal CLKA1 is supplied to wiring 113. The clock signal CLKA2 supplied to wiring 114 is at potential VSS, and the clock signal CLKA2 is at potential VDD, wiring 11 The clock signal CLKA3 supplied to 5 is at potential VDD, and the clock supplied to wiring 116 is also at potential VDD. The signal CLKB is at potential VEE, and the input signal LIN supplied to wiring 117 is at potential VSS, wiring The input signal RIN supplied to 118 is at the potential VSS.

[0050] Therefore, in period t1, in the sequential circuit 10, transistor 101, transistor 13 0, Transistor 133, Transistor 134, Transistor 136, Transistor 13 7. Transistor 139 turns on. Also, transistors 131 and 132 Transistors 135, 138, and 102 turn off. So, the power supply potential VEE of wiring 112 is output from wiring 120 as the potential of the output signal GOUT. It is powered. Also, the power supply potential VSS of wiring 111 is wired as the potential of the output signal SROUT. Output from 119.

[0051] Next, as shown in Figure 3, during period t2, the clock signal C is supplied to wiring 113. LKA1 is at potential VSS, the clock signal CLKA2 supplied to wiring 114 is at potential VSS. The clock signal CLKA3 supplied to wiring 115 is at potential VDD, and is supplied to wiring 116. The clock signal CLKB is at potential VEE, and the input signal LIN supplied to wiring 117 is at potential VD. D, the input signal RIN supplied to wiring 118 is at potential VSS.

[0052] Therefore, in period t2, in the sequential circuit 10, transistor 131 to transistor 1 33. Transistors 137 through 139 and transistor 102 are turned on. Also, transistor 101, transistor 130, transistor 134, and so on. 136 turns off. Therefore, the potential VCC of the clock signal CLKB on wiring 116 is The output signal GOUT is output from wiring 120 as its potential, and the clock signal CL from wiring 113 is output. The potential VSS of KA1 is output from wiring 119 as the potential of the output signal SROUT.

[0053] Next, as shown in Figure 3, during period t3, the clock signal C is supplied to wiring 113. LKA1 is at potential VDD, the clock signal CLKA2 supplied to wiring 114 is at potential VSS. The clock signal CLKA3 supplied to wiring 115 is at potential VSS, and is supplied to wiring 116. The clock signal CLKB is at potential VCC, and the input signal LIN supplied to wiring 117 is at potential VD. D, the input signal RIN supplied to wiring 118 is at potential VSS.

[0054] Therefore, in period t3, in the sequential circuit 10, transistor 131, transistor 13 2. Transistors 138 and 102 turn on. Also, transistor 101 , transistor 130, transistor 133 to transistor 137, transistor 13 9 is turned off. Therefore, the potential VCC of the clock signal CLKB on wiring 116 is the output The signal GOUT is output from wiring 120 as its potential, and the clock signal CLKA from wiring 113 is output. The potential VDD of 1 is output from wiring 119 as the potential of the output signal SROUT.

[0055] Next, as shown in Figure 3, during period t4, the clock signal C is supplied to wiring 113. LKA1 is at potential VDD, the clock signal CLKA2 supplied to wiring 114 is at potential VDD, The clock signal CLKA3 supplied to wiring 115 is at potential VSS, and is supplied to wiring 116. The clock signal CLKB is at potential VCC, and the input signal LIN supplied to wiring 117 is at potential VS. S, the input signal RIN supplied to wiring 118 is at potential VSS.

[0056] Therefore, in period t4, in sequential circuit 10, transistor 134, transistor 13 8. Transistor 102 turns on. Also, transistors 101 and 130 Transistor 133, Transistor 135, Transistor 137, Transistor 1 39 turns off. Therefore, the potential VCC of the clock signal CLKB on wiring 116 is output. The potential of the power signal GOUT is output from wiring 120, and the clock signal CLK is output from wiring 113. The potential VDD of A1 is output from wiring 119 as the potential of the output signal SROUT.

[0057] Next, as shown in Figure 3, during period t5, the clock signal C is supplied to wiring 113. LKA1 is at potential VSS, the clock signal CLKA2 supplied to wiring 114 is at potential VDD. The clock signal CLKA3 supplied to wiring 115 is at potential VDD, and is supplied to wiring 116. The clock signal CLKB is at potential VEE, and the input signal LIN supplied to wiring 117 is at potential VS. S, the input signal RIN supplied to wiring 118 is at potential VDD.

[0058] Therefore, in period t5, in sequential circuit 10, transistor 101, transistor 13 0, transistor 136, transistor 133 to transistor 135, transistor 1 37. Transistor 139 turns on. Also, transistors 131 and 13 2. Transistors 138 and 102 turn off. Therefore, wiring 112 The power supply potential VEE is output from wiring 120 as the potential of the output signal GOUT. The power supply potential VSS of line 111 is output from wiring 119 as the potential of the output signal SROUT. ru.

[0059] In the above operation, transistor 101 turns off during periods t2 to t4. In particular, during periods t3 and t4, the clock signal CLKB is supplied to wiring 116. Because the potential VCC is at a high level, when transistor 101 is ON, the transistor Current flows between wiring 116 and wiring 112 via transistor 101 and transistor 102. However, in one aspect of the present invention, the gate of transistor 101 and the source and drain One side is electrically isolated. Specifically, when transistor 101 is turned off, The gate of transistor 101 is supplied with the power supply potential VSS of the wiring 111, and transistor 10 The power supply potential VEE of the wiring 112 can be applied to either the source or drain of 1. Therefore, even if current flows between wire 116 and wire 112, that current will cause wire 112 The power supply potential VEE rises, and the gate voltage Vgs of transistor 101 reaches the threshold voltage Vth. To get closer, transistor 101 can eventually be turned off.

[0060] Furthermore, in the above operation, transistor 102 is turned off during periods t1 and t5. During these periods, the gate of transistor 102 is at the power supply potential VS of wiring 111. S is supplied. However, one of the source and drain of transistor 102 is powered. Because the potential VEE of the clock signal CLKB, which is higher than the source potential VSS, is supplied, The gate voltage of the zista 102 can be lowered to below the threshold voltage Vth. Specifically, The potential VEE should be higher than the potential VSS minus the threshold voltage Vth. .

[0061] Figure 4 shows an example of a shift register configured by connecting multiple sequential circuits 10 in stages. This is shown as follows.

[0062] The shift register shown in Figure 4 uses sequential circuits 10_1 through 10_y (where y is a natural number) It possesses. Sequential circuits 10_1 to 10_y are, respectively, sequential circuits 10_1 to 10_y shown in Figure 2. It has the same configuration as 0. However, the wiring 113 to 115 shown in Figure 2 has a clock Any three of the signals CLKA1 to CLKA4 are clock signals C These are supplied as LKA1 or clock signal CLKA3, respectively. Also, wiring 116 This means that one of the clock signals CLKB1 to CLKB4 is It is supplied as the lock signal CLKB.

[0063] Specifically, in sequential circuit 10_4m+1, the clock signal CLKA1 is connected to wire 113, and wire 1 Clock signal CLKA2 is supplied to wire 14, and clock signal CLKA3 is supplied to wire 115. In the first circuit 10_4m+2, the clock signal CLKA2 is connected to wire 113, and the clock signal is connected to wire 114. The clock signal CLKA3 and the clock signal CLKA4 are supplied to wiring 115. Sequential circuit 10_ In 4m+3, the clock signal CLKA3 is connected to wire 113, and the clock signal CLK is connected to wire 114. A4, the clock signal CLKA1 is supplied to wiring 115. In sequential circuit 10_4m+4 Clock signal CLKA4 to wire 113, clock signal CLKA1 to wire 114, wire 1 A clock signal CLKA2 is supplied to 15. However, m is the total number of sequential circuits 10, where y is Let be any integer that satisfies a certain condition.

[0064] Furthermore, specifically in sequential circuit 10_4m+1, the clock signal CLKB1 is connected to wiring 116. It is supplied. In sequential circuit 10_4m+2, the clock signal CLKB4 is supplied to wiring 116. In sequential circuit 10_4m+3, the clock signal CLKB3 is supplied to wiring 116. In sequential circuit 10_4m+4, the clock signal CLKB2 is supplied to wiring 116.

[0065] In the shift register shown in Figure 4, the sequential circuit 10_j (where j is a natural number less than or equal to y) The positions of wiring 113 to wiring 120 are schematically shown in Figure 6. As can be seen from Figures 4 and 6... Therefore, the wiring 117 of sequential circuit 10_j is connected to the wiring 119 of the preceding sequential circuit 10_j-1. The output signal SROUTj-1, which is output from there, is supplied as the input signal LIN. However, The wiring 117 of the first stage sequential circuit 10_1 is supplied with the potential of the start pulse signal SP. The configuration will be as follows.

[0066] Also, the wiring 118 of sequential circuit 10_j is connected to the wiring 11 of the sequential circuit 10_j+2, which is two stages later. The output signal SROUTj+2, output from 9, is supplied as the input signal RIN. And the input signal RIN_y-1 is supplied to the wiring 118 of the y-1 stage sequential circuit 10_y-1. The input signal RIN_y is supplied to the wiring 118 of the y-stage sequential circuit 10_y. The configuration is as follows: The input signal RIN_y-1 is assumed to be the sequential circuit 10_y+1. In this case, we consider the output signal SROUTy+1 that will be output from the sequential circuit 10_y+1. It is fixed. Also, the input signal RIN_y is assumed to be the same as the sequential circuit 10_y+2. Sometimes, the output signal SROUTy+2 that will be output from the sequential circuit 10_y+2 is That's what we're anticipating.

[0067] The output signal GOUTj is output from wiring 120 of sequential circuit 10_j.

[0068] Figure 5 shows the potentials of clock signals CLKA1 to CLKA4 and the start pulse. The timing chain between the potential of signal SP and the potentials of output signals GOUT1 to GOUT3. The clock signals CLKA1 to CLKA4 indicate the rising edge of the potential. The waveform has a timing that is shifted backward by one-quarter of a period. The shift shown in Figure 4 The resistor operates according to the above signal, and the pulse width is half of the above clock signal. This is one cycle, and furthermore, pulses equivalent to one-quarter of the clock signal's cycle are added at the end. It outputs output signals GOUT1 to GOUTy, each having a specific waveform.

[0069] For example, using the shift register shown in Figure 4, multiple pixels in a semiconductor display device can be connected. Output signals GOUT1 to GOUTy are supplied to the connected wiring called the bus line. When supplying, the output side transients of sequential circuits 10_1 to 10_y The st 101 and transistor 102 require a large current supply capacity. Therefore, The channel width W of transistor 101 and transistor 102 is The channel width W of transistors other than the transistor 102 is designed to be larger than that of other transistors. There are many. Therefore, if transistors 101 and 102 are normally on... The power consumption of the shift register increases, or the output signal GOUT1 or output A phenomenon such as a decrease in the amplitude of the force signal GOUTY is more likely to occur. However, In one aspect of the present invention, the output side of each sequential circuit 10_1 to sequential circuit 10_y Even if transistors 101 and 102 are normally on, the transistors Transistors 101 and 102 can be turned off when they should be turned off.

[0070] Therefore, the semiconductor device according to one aspect of the present invention using the above shift register has low power consumption. The amplitude of the output signals GOUT1 to GOUTy is reduced as the signal is suppressed. This can prevent this from happening. Furthermore, according to one aspect of the present invention using the above shift register, Conductor display devices have low power consumption and small signal amplitudes supplied to the bus line. This can prevent display malfunctions caused by this issue.

[0071] <Specific example of sequential circuit configuration 2> Another example of the configuration of a sequential circuit according to one aspect of the present invention will be described.

[0072] The sequential circuit 10 shown in Figure 7(A) consists of circuit 11, transistor 101 and transistor 1 It has 02. Transistor 101 corresponds to transistor 12 in Figure 1(A), and Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, in the sequential circuit 10 Various power potentials are supplied via wiring 110 to wiring 112, and wiring 113 and wiring 11 Clock signals CLKA1 and CLKA2 are supplied via 4, respectively. Furthermore, a clock signal CLKB is supplied via wiring 116, and via wiring 117. The input signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via wiring 120.

[0073] Furthermore, in the sequential circuit 10 shown in Figure 7(A), circuit 11 is a transistor 313 to a transistor It has a Zista 319.

[0074] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0075] Transistor 313 has its gate connected to the gates of transistors 314 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other end of the drain is connected to the gate of transistor 319 and the gate of transistor 102. Transistor 314 has one of its sources and drains connected to wiring 111. The source and drain of the transistor 101 are connected to wiring 119. The source and drain of the device are connected to wiring 112, and the source and drain of the device The other end is connected to wiring 120.

[0076] Furthermore, transistor 315 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 31 It is connected to the gate of transistor 9 and the gate of transistor 102. Transistor 316 is The gate is connected to wiring 114, and one of its source and drain is connected to wiring 110. The source and drain of the other are transistors 313, 314, and It is connected to the gate of transistor 101. Transistor 317 is connected to the gate of transistor 101. It is connected to wire 118, and one of its source and drain is connected to wiring 110, and its source The other side of the drain is transistor 313, transistor 314, and transistor 1 It is connected to gate 01.

[0077] Transistor 318 has its gate connected to wiring 117, and its source and drain One side is connected to wiring 111, and the other side of its source and drain is connected to transistor 313. It is connected to the gates of transistor 314 and transistor 101. Transistor 3 19 has its gate connected to the gate of transistor 102, and its source and drain. One end is connected to wiring 113, and the other end of its source and drain is connected to wiring 119. Transistor 102 has its gate connected to the gate of transistor 319. One of the source and drain is connected to wiring 116, and the other of the source and drain It is connected to wiring 120.

[0078] In the sequential circuit 10 shown in Figure 7(A), the case where all transistors are of the n-channel type is an example. This is shown. Specifically, in Figure 7(A), the power supply potential VDD is supplied to the wiring 110, and When power supply potential VSS is supplied to line 111 and power supply potential VEE is supplied to wiring 112 This illustrates the combination.

[0079] The sequential circuit 10 shown in Figure 7(A) consists of the gate and source of the output transistor 101 and It is possible to electrically isolate one of the drains. Therefore, transistor 101 is no Assuming it was a mullion, then one of the source and drain of the transistor 101 Even if the potential of the wiring 112 that supplies potential to the transistor 101 rises, It can be turned off when it should be turned off. Also, the source of transistor 102 and On one side of the drain, there is a potential VEE, which is higher than the power supply potential VSS and corresponds to the clock signal CLKB. Therefore, the gate voltage of transistor 102 is set lower than the threshold voltage Vth. This is possible. Therefore, even if transistor 102 is normally on, You can turn off 102 when you should.

[0080] The sequential circuit 10 shown in Figure 7(B) consists of circuit 11, transistor 101 and transistor 1 It has 02. Transistor 101 corresponds to transistor 12 in Figure 1(A), and Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, in the sequential circuit 10 Various power potentials are supplied via wiring 110 to wiring 112, and wiring 113 to wiring 11 Clock signals CLKA1 to CLKA3 are supplied via 5, respectively. Furthermore, a clock signal CLKB is supplied via wiring 116, and via wiring 117. The input signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via wiring 120.

[0081] Furthermore, in the sequential circuit 10 shown in Figure 7(B), circuit 11 consists of transistors 344 to transistors It has a ZISTA 351.

[0082] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0083] Transistor 344 has its gate connected to the gates of transistors 345 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other end of the drain is connected to the gates of transistors 351 and 102. Transistor 345 has one of its sources and drains connected to wiring 111, and The source and the other drain are connected to wiring 119. Transistor 101 is One of the source and drain is connected to wiring 112, and the other of the source and drain is connected to It is connected to line 120.

[0084] Furthermore, transistor 346 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 35 It is connected to the gate of transistor 102. Transistor 347 is connected to its gate The wire is connected to wiring 114, and one of its source and drain is connected to wiring 110, The source and drain of the other are transistors 344, 345, and It is connected to the gate of transistor 101. Transistor 348 has its gate connected to wiring 115 It is connected to and one of its source and drain is connected to wiring 110, and its source and drain The other side of Rain is the gate of transistors 344, 345, and 101. It is connected to the terminal. Transistor 349 has its gate connected to wiring 117, and One of the source and drain of is connected to wiring 111, and the other of the source and drain is Connected to the gates of transistors 344, 345, and 101 It is.

[0085] Transistor 350 has its gate connected to wiring 118, and its source and drain One side is connected to wiring 110, and the other side of its source and drain is connected to transistor 344, It is connected to the gates of transistor 345 and transistor 101. Transistor 3 51 has its gate connected to the gate of transistor 102, and its source and drain. One end is connected to wiring 113, and the other end of its source and drain is connected to wiring 119. Transistor 102 has its gate connected to the gate of transistor 351. One of the source and drain is connected to wiring 116, and the other of the source and drain It is connected to wiring 120.

[0086] In the sequential circuit 10 shown in Figure 7(B), the case where all transistors are of the n-channel type is an example. This is shown. Specifically, in Figure 7(B), the power supply potential VDD is supplied to the wiring 110, and When power supply potential VSS is supplied to line 111 and power supply potential VEE is supplied to wiring 112 This illustrates the combination.

[0087] The sequential circuit 10 shown in Figure 7(B) consists of the gate and source of the output transistor 101 and It is possible to electrically isolate one of the drains. Therefore, transistor 101 is no Assuming it was a mullion, then one of the source and drain of the transistor 101 Even if the potential of the wiring 112 that supplies potential to the transistor 101 rises, It can be turned off when it should be turned off. Also, the source of transistor 102 and On one side of the drain, there is a potential VEE, which is higher than the power supply potential VSS and corresponds to the clock signal CLKB. Therefore, the gate voltage of transistor 102 is set lower than the threshold voltage Vth. This is possible. Therefore, even if transistor 102 is normally on, You can turn off 102 when you should.

[0088] The sequential circuit 10 shown in Figure 8(A) consists of circuit 11, transistor 101 and transistor 1 It has 02. Transistor 101 corresponds to transistor 12 in Figure 1(A), and Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, in the sequential circuit 10 Various power potentials are supplied via wiring 110 to wiring 112, and wiring 113 and wiring 11 Clock signals CLKA1 and CLKA2 are supplied via 4, respectively. Furthermore, a clock signal CLKB is supplied via wiring 116, and via wiring 117. The input signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via wiring 120.

[0089] Furthermore, in the sequential circuit 10 shown in Figure 8(A), circuit 11 consists of transistors 374 to It has a ZISTA 381.

[0090] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0091] Transistor 374 has its gates connected to the gates of transistors 375 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other drain is connected to one of the source and drains of transistor 377. The transistor 375 has one of its sources and drains connected to wiring 111, and its source The other end of the spool and drain is connected to wiring 119. Transistor 101 has its spool One of the source and drain is connected to wiring 112, and the other of its source and drain is connected to wiring 1 It is connected to 20.

[0092] Furthermore, transistor 376 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 37. It is connected to either the source or the drain of 7. Transistor 377 has its gate It is connected to wiring 110, and its source and the other drain are connected to transistor 381 and transistor 110. It is connected to the gate of transistor 102. Transistor 378 has its gate connected to wiring 11 It is connected to 4, and one of its source and drain is connected to wiring 110, and its source and The other side of the drain is transistor 374, transistor 375, and transistor 101 It is connected to the gate.

[0093] Transistor 379 has its gate connected to wiring 117, and its source and drain One side is connected to wiring 111, and the other side of its source and drain is connected to transistor 374, It is connected to the gates of transistor 375 and transistor 101. Transistor 3 80 has its gate connected to wiring 118, and one of its source and drain is connected to wiring 11 It is connected to 0, and its source and the other drain are transistors 374 and 37 5, and connected to the gate of transistor 101. Transistor 381 is connected to its so One of the source and drain is connected to wiring 113, and the other of its source and drain is connected to wiring It is connected to 119. Transistor 102 has one of its sources and drains wired. It is connected to 116, and the other end of its source and drain is connected to wiring 120.

[0094] In the sequential circuit 10 shown in Figure 8(A), the case where all transistors are of the n-channel type is an example. This is shown. Specifically, in Figure 8(A), the power supply potential VDD is supplied to the wiring 110, and When power supply potential VSS is supplied to line 111 and power supply potential VEE is supplied to wiring 112 This illustrates the combination.

[0095] The sequential circuit 10 shown in Figure 8(A) consists of the gate and source of the output transistor 101 and It is possible to electrically isolate one of the drains. Therefore, transistor 101 is no Assuming it was a mullion, then one of the source and drain of the transistor 101 Even if the potential of the wiring 112 that supplies potential to the transistor 101 rises, It can be turned off when it should be turned off. Also, the source of transistor 102 and On one side of the drain, there is a potential VEE, which is higher than the power supply potential VSS and corresponds to the clock signal CLKB. Therefore, the gate voltage of transistor 102 is set lower than the threshold voltage Vth. This is possible. Therefore, even if transistor 102 is normally on, You can turn off 102 when you should.

[0096] The sequential circuit 10 shown in Figure 8(B) consists of circuit 11, transistor 101 and transistor 1 It has 02. Transistor 101 corresponds to transistor 12 in Figure 1(A), and Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, in the sequential circuit 10 Various power potentials are supplied via wiring 110 to wiring 112, and wiring 113 and wiring 11 Clock signals CLKA1 and CLKA2 are supplied via 4, respectively. Furthermore, a clock signal CLKB is supplied via wiring 116, and via wiring 117. The input signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via wiring 120.

[0097] Furthermore, in the sequential circuit 10 shown in Figure 8(B), the circuit 11 consists of transistors 414 to It has a ZISTA 422.

[0098] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0099] Transistor 414 has its gate connected to the gates of transistors 415 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other drain is connected to one of the source and drains of transistor 417. The transistor 415 has one of its sources and drains connected to wiring 111, and its source The other end of the spool and drain is connected to wiring 119. Transistor 101 has its spool One of the source and drain is connected to wiring 112, and the other of its source and drain is connected to wiring 1 It is connected to 20.

[0100] Furthermore, transistor 416 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 41. It is connected to either the source or drain of 7. Transistor 417 has its gate It is connected to wiring 110, and its source and the other drain are connected to the gate of transistor 421. They are connected. Transistor 418 has its gate connected to wire 114, and its saw One of the source and drain is connected to wiring 110, and the other of its source and drain is connected to the transistor. It is connected to the gates of transistor 414, transistor 415, and transistor 101. Transistor 419 has its gate connected to wiring 117, and its source and drain. One end is connected to wiring 111, and the other end of its source and drain is connected to transistor 414. It is connected to the gates of transistors 415 and 101. 420 has its gate connected to wiring 118, one of its source and drain connected to wiring 1 10, and the other of its source and drain connected to the gates of transistor 414, transistor 4 15, and transistor 101. Transistor 421 has one of its source and drain connected to wiring 113, and the other of its source and drain connected to wiring 119. Transistor 422 has its gate connected to wiring 110 , one of its source and drain connected to the gate of transistor 421 and the other of the source and drain of transistor 41 7, and the other of its source and drain connected to the gate of transistor 102. Transistor 102 has one of its source and drain connected to wiring 116, and the other of its source and drain connected to wiring 120.

[0101] In the sequential circuit 10 shown in FIG. 8(B), a case where all transistors are n-channel type is illustrated. Specifically, in FIG. 8(B), a case where the power supply potential VDD is supplied to wiring 110, the power supply potential VSS is supplied to wiring 111, and the power supply potential VEE is supplied to wiring 112 is exemplified.

[0102] The sequential circuit 10 shown in FIG. 8(B) can electrically isolate the gate of the output-side transistor 101 from one of its source and drain. Thus, even if transistor 101 is a non-marian, and thereby the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 increases, it can be turned off when transistor 101 should be turned off. Also, the source and drain of transistor 102 On one side of the drain, there is a potential VEE, which is higher than the power supply potential VSS and corresponds to the clock signal CLKB. Therefore, the gate voltage of transistor 102 is set lower than the threshold voltage Vth. This is possible. Therefore, even if transistor 102 is normally on, You can turn off 102 when you should.

[0103] The sequential circuit 10 shown in Figure 9 consists of circuit 11, transistor 101 and transistor 102 It has. Transistor 101 corresponds to transistor 12 in Figure 1(A), and the transistor Transistor 102 corresponds to transistor 13 in Figure 1(A). Also, the sequential circuit 10 has wiring. Various power potentials are supplied via wiring 110 to 112, and via wiring 113 and wiring 114 The clock signal CLKA1 and the clock signal CLKA2 are supplied respectively. Additionally, a clock signal CLKB is supplied via wiring 116 and input via wiring 117. The signal LIN is supplied, and the input signal RIN is supplied via wiring 118. Also, sequential rotation In path 10, the output signal SROUT is output via wiring 119, and the output signal GOUT is distributed It is output via line 120.

[0104] Furthermore, in the sequential circuit 10 shown in Figure 9, circuit 11 is transistor 444 to transistor It has 452.

[0105] A shift register can be constructed by connecting multiple sequential circuits 10 in stages.

[0106] Transistor 444 has its gate connected to the gates of transistors 445 and 101. It is connected to the source, and one of its source and drain is connected to wiring 111, and its source and The other drain is connected to one of the source and drains of transistor 452. The transistor 445 has one of its sources and drains connected to wiring 111, and its source The other end of the spool and drain is connected to wiring 119. Transistor 101 has its spool One of the source and drain is connected to wiring 112, and the other of its source and drain is connected to wiring 1 It is connected to 20.

[0107] Furthermore, transistor 446 has its gate connected to wiring 117, and its source and drain One end of the input is connected to wiring 110, and the other end of its source and drain is connected to transistor 45 It is connected to either the source or drain of 2. Transistor 447 has its gate It is connected to wiring 114, and one of its source and drain is connected to wiring 110, and its source The other side of the drain is transistor 444, transistor 445, and transistor It is connected to the gate of 101. Transistor 448 has its gate connected to wiring 118. The source and drain of the wire are connected to the wiring 110, and the source and drain The other side of the gates of transistors 444, 445, and 101 It is connected to. Transistor 449 has its gate connected to wiring 117, and its so One of the source and drain is connected to wiring 111, and the other of its source and drain is connected to the trace The gates of transistors 444, 445, and 101 are connected. Transistor 450 has its gate connected to wiring 110, and its source and slave One end of the wire is connected to the source and drain of transistor 452, and the other end is connected to the transistor It is connected to the gate of transistor 451. Transistor 451 has its source and drain One side of the in is connected to wiring 113, and the other sides of its source and drain are connected to wiring 119 Transistor 452 has its gate connected to wiring 110, and the other sides of its source and drain are connected to the gate of transisttor 102. Transisttor 102 has one side of its source and drain connected to wiring 116, and the other sides of its source and drain are connected to wiring 120.

[0108] In the sequential circuit 10 shown in FIG. 9, the case where all transistors are n-channel type is illustrated Specifically, in FIG. 9, the case where the power supply potential VDD is supplied to wiring 110, the power supply potential VSS is supplied to wiring 111, and the power supply potential VEE is supplied to wiring 112 is illustrated Specifically, in FIG. 9, the case where the power supply potential VDD is supplied to wiring 110, the power supply potential VSS is supplied to wiring 111, and the power supply potential VEE is supplied to wiring 112 is illustrated Specifically, in FIG. 9, the case where the power supply potential VDD is supplied to wiring 110, the power supply potential VSS is supplied to wiring 111, and the power supply potential VEE is supplied to wiring 112 is illustrated

[0109] The sequential circuit 10 shown in FIG. 9 can electrically separate the gate of the output-side transistor 101 from one of the source and drain Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102 Therefore, even if transistor 101 is a normally-on transistor, and thus the potential of wiring 112 for supplying a potential to one of the source and drain of the transistor 101 has risen, it can be turned off when transistor 101 should be turned off. Also, since the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the source and drain of transistor 102

[0110] <Example configuration of semiconductor display device> Next, an example of the configuration of a semiconductor display device according to one aspect of the present invention will be described.

[0111] The semiconductor display device 70 shown in Figure 10(A) has a pixel section 71 with a plurality of pixels 55 and a pixel 5 5 corresponds to a bus line for selecting each row, wiring GL1 to wiring GLy (y is natural Wiring GL, indicated by the number, and wiring SL, for supplying image signals to the selected pixel 55. Wiring SL, denoted by 1 to SLx (where x is a natural number), is provided. The signal input is controlled by the drive circuit 72. The image signal input to wiring SL is, It is controlled by the drive circuit 73. Multiple pixels 55 are connected to at least one of the wiring GLs, Each is connected to at least one of the wirings SL.

[0112] Specifically, the drive circuit 72 generates signals to sequentially select wiring GL1 to GLy. It has a shift register 75. Specifically, the drive circuit 73 has pulses in sequence. A shift register 76 generates a signal, and according to the signal generated by the shift register 76 It includes a switch circuit 77 that controls the supply of image signals to wiring SL1 to wiring SLx. .

[0113] A sequential circuit according to one aspect of the present invention comprises one of the shift register 75 and the shift register 76. It can be used for both purposes.

[0114] The type and number of wirings provided in the pixel section 71 are determined by the configuration, number, and arrangement of the pixels 55. Therefore, it can be determined. Specifically, in the case of the pixel section 71 shown in Figure 10(A), x row × y The pixels 55 in each row are arranged in a matrix, with wiring SL1 to SLx, and wiring GL1 This example illustrates the case where the wiring GLy is located within the pixel section 71.

[0115] In Figure 10(A), the drive circuit 72 and the drive circuit 73 are located together with the pixel unit 71. Although the example shows the case where it is formed on a plate, the drive circuits 72 and 73 are located in the pixel section It may be formed on a substrate different from that of 71.

[0116] Furthermore, Figure 10(B) shows an example of the configuration of the pixels 55. Each pixel 55 is a liquid crystal element 60 The transistor 56 controls the supply of an image signal to the liquid crystal element 60, and the liquid crystal element 60 The liquid crystal element 60 has a capacitive element 57 for maintaining the voltage between the pixel electrode and the common electrode. This includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. It has a liquid crystal layer.

[0117] Transistor 56 controls whether or not to apply the potential of the wiring SL to the pixel electrodes of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0118] The following describes the specific connection configuration of transistor 56 and liquid crystal element 60. Figure 10( In B), the gate of transistor 56 is connected to one of the wires from GL1 to GLy. The connection continues. One of the source and drain of transistor 56 is connected from wiring SL1 to wiring S It is connected to one of Lx, and the source and drain of transistor 56 are liquid crystal. It is connected to the pixel electrode of element 60.

[0119] In the liquid crystal element 60, the liquid crystal layer contains according to the voltage value applied between the pixel electrode and the common electrode. The orientation of the liquid crystal molecules changes, and the transmittance changes. Therefore, the liquid crystal element 60 is a pixel electrode. The transmittance is controlled by the potential of the image signal applied to it, thereby displaying grayscale. This is possible. And in each of the multiple pixels 55 that the pixel unit 71 has, liquid crystal element The gradation of sub-60 is adjusted according to the image signal containing image information, thereby the image in the pixel section 71. This will be displayed.

[0120] Figure 10(B) shows a switch in pixel 55 that controls the input of the image signal to pixel 55. The example given is the case where transistor 56 is used. However, the example given is the case where switch 56 is used. Multiple transistors that function together may be used in pixel 55.

[0121] In one aspect of the present invention, a transistor 56 with a remarkably low off-current is used for the pixels 55 of an image signal. It is preferable to use it as a switch to control the input to. The off current of transistor 56 is If it is small, it can prevent charge leakage through transistor 56. Therefore, To more reliably maintain the potential of the image signal applied to the liquid crystal element 60 and the capacitive element 57. Therefore, the transmittance of the liquid crystal element 60 changes due to charge leakage within a single frame period. This prevents this and thereby improves the quality of the displayed image. If the off-current of transistor 56 is small, it prevents charge leakage through transistor 56. Therefore, during the period when a still image is displayed, the drive circuit 72 and drive circuit 73 The power potential or signal supply to the pixel unit 71 may be stopped. With the above configuration, the image signal This reduces the number of times the number is written to, thereby lowering the power consumption of the semiconductor display device.

[0122] For example, transistors that include oxide semiconductors in their semiconductor films have significantly reduced off-current. Therefore, it is suitable to use this as transistor 56.

[0123] In Figure 10(B), the transistor 56 is a single layer of semiconductor film sandwiched between two overlapping components. It may have a pair of gate electrodes. The pair of gate electrodes are electrically connected. In one aspect of the present invention, the above configuration increases the on-current of the transistor 56, and further This can improve the reliability of transistor 56.

[0124] Next, Figure 10(C) shows another example of pixel 55. Pixel 55 is an image signal to pixel 55. A transistor 95 controls the input of the signal, a light-emitting element 98, and a light-emitting element 9 according to the image signal. A transistor 96 controls the current value supplied to 8, and a capacitor for holding the potential of the image signal. It has a quantitative element 97.

[0125] The light-emitting element 98 is an LED (Light Emitting Diode) or an OLED (O2 Current or voltage, such as in an electromagnetic light-emitting diode. Therefore, elements whose brightness is controlled are included in that category. For example, an OLED has an EL layer and It has at least an anode and a cathode. The EL layer is placed between the anode and the cathode. It consists of one or more layers, and these layers contain a luminescent substance. It includes at least a light-emitting layer.

[0126] Furthermore, the EL layer is activated when the potential difference between the cathode and anode exceeds the threshold voltage of the light-emitting element 98. Electroluminescence is obtained by the current supplied when this occurs. Nessens exhibits luminescence (fluorescence) when returning from the singlet excited state to the ground state, and the triplet excited state. This includes the emission (phosphorescence) that occurs when returning to the ground state.

[0127] Either the anode or cathode of the light-emitting element 98 is connected to the image signal input to the pixel 55. Therefore, its potential is controlled. Of the anode and cathode, its potential is controlled according to the image signal. The controlled electrode is designated as the pixel electrode, and the other electrode is designated as the common electrode. A predetermined potential is applied to the electrodes, and the brightness of the light-emitting element 98 is determined between the pixel electrode and the common electrode. It is determined by the potential difference. Therefore, the brightness of the light-emitting element 98 changes according to the potential of the image signal. By being controlled, it is possible to display gradations. And the multiple pixels 5 that the pixel part has In each of the five, the gradation of the light-emitting element 98 is adjusted according to the image signal containing image information. As a result, an image is displayed in the pixel section 71.

[0128] Next, the pixel 55 has transistor 95, transistor 96, capacitive element 97, and light emission The connection configuration of element 98 will be explained below.

[0129] Transistor 95 has one of its sources and drains connected to wiring SL, and the source and drain The other end of the input is connected to the gate of transistor 96. The gate of transistor 95 is , connected to wiring GL. Transistor 96 has either its source or drain connected to the power line It is connected to VL, and the source and the other drain are connected to the light-emitting element 98. Specifically The source and drain of transistor 96 are connected to the anode and cathode of light-emitting element 98. It is connected to either the anode or cathode of the light-emitting element 98. A predetermined potential is applied.

[0130] In Figure 10(C), transistor 96 is a pair of overlapping gates with a semiconductor film in between. It may have gate electrodes. The pair of gate electrodes are electrically connected. In one embodiment, the above configuration increases the on-current of transistor 96, and furthermore, This can improve the reliability of the 96.

[0131] <Pixel composition> Next, we will take a liquid crystal display device, which is one of the semiconductor display devices 70 shown in Figure 10(A), as an example. Next, we will explain an example of the configuration of pixel 55. Figure 11 shows an example of a top view of pixel 55. Note that in Figure 11, various insulating films have been omitted to clarify the layout of pixel 55. Furthermore, a liquid crystal display device formed using an element substrate having pixels 55 as shown in Figure 11. A cross-sectional view is shown in Figure 12. The liquid crystal display device shown in Figure 12 includes the element substrate 31. This corresponds to the cross-sectional view along the dashed line B1-B2 in Figure 11.

[0132] The pixel 55 shown in Figures 11 and 12 has a transistor 56 and a capacitive element 57. Furthermore, the pixel 55 shown in Figure 12 has a liquid crystal element 60.

[0133] The transistor 56 has a gate electrode function on the substrate 31 which has an insulating surface. A conductive film 40 and an insulating film that functions as a gate insulating film and is located on the conductive film 40. The film 22, the oxide semiconductor film 41 which overlaps with the conductive film 40 on the insulating film 22, and the oxide semiconductor A conductive electrode electrically connected to the body membrane 41, which functions as a source electrode or drain electrode. It has a film 43 and a conductive film 44. The conductive film 40 is a wiring GL as shown in Figure 10(B). It has a function. Furthermore, the conductive film 43 has the function of wiring SL as shown in Figure 10(B). .

[0134] Furthermore, the pixel 55 has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is It is a conductive film that is transparent to light. And on the metal oxide film 42, A conductive film 61 is provided electrically connected to the physical film 42. The conductive film 61 is a metal oxide. It functions as wiring that supplies a predetermined potential to the film 42.

[0135] The insulating film 22 can be aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, Silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, gallium oxide One or more of the following: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film may be used as a single layer or in a laminated configuration. Note that in this specification, acid Nitrides refer to materials whose composition contains more oxygen than nitrogen, while nitride oxides are... This refers to materials whose composition contains more nitrogen than oxygen.

[0136] Furthermore, in Figure 12, the oxide semiconductor film 41, conductive film 43 and conductive film 44 and the metal oxide film Insulating films 26 and 27 are provided to be laminated sequentially on 42 and the conductive film 61. Even though transistor 56 includes insulating film 26 and insulating film 27 as its components, Good. Note that Figure 12 illustrates the sequentially stacked insulating films 26 and 27, Instead of insulating film 26 and insulating film 27, a single-layer insulating film may be used, or a laminated film may be used. A dielectric film consisting of three or more layers may be used.

[0137] Furthermore, the insulating film 26 and insulating film 27 have openings 58 at positions that overlap with the metal oxide film 42. The opening 58 is in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. It is present and located in a region that overlaps with the metal oxide film 42.

[0138] Furthermore, in Figure 12, the metal oxide film 4 on insulating film 26 and insulating film 27 and at the opening 58 is shown. A nitride insulating film 28 and an insulating film 29 are arranged on top of each other in a sequential manner.

[0139] Furthermore, an oxide semiconductor film is formed on the insulating film 22, and a nitride is formed in contact with the oxide semiconductor film. By forming the insulating film 28, the conductivity of the oxide semiconductor film can be increased. The oxide semiconductor film with increased conductivity can then be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed, or when the nitride insulating film 2 When 8 is formed, oxygen vacancies are formed in the oxide semiconductor film and diffuse from the nitride insulating film 28. This is thought to be because the hydrogen binds to the oxygen deficiency, generating the donor. The resistivity of the metal oxide film 42 is typically 1 × 10⁻⁶. -3 Ωcm or more, 1 × 10 4 Ωcm Less than, more preferably, a resistivity of 1 × 10⁻⁶ -3 Ωcm or more, 1 × 10 -1 Less than Ωcm It would be good to do so.

[0140] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the material film 42, secondary ion mass spectrometry (SIMS) was performed. The hydrogen concentration obtained by (assess spectrometry) is 8 × 10 19 Atom s / cm 3 Preferably 1 × 10 20 atoms / cm 3More preferably, 5× 10 20 atoms / cm 3 or more. In the oxide semiconductor film 41, the hydrogen concentration obtained by secondary ion mass analysis is 5×10 19 atoms / cm 3 or less, preferably 5 ×10 18 atoms / cm 3 or less, preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, still more preferably 1×10 16 a toms / cm 3 or less.

[0141] As the nitride insulating film 28, for example, silicon nitride, silicon oxynitride, aluminum nitride , aluminum oxynitride, etc. can be used. The nitride insulating film 28 made of the above materials can prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film 41 compared with oxide insulating films such as silicon oxide and aluminum oxide.

[0142] Also, an opening 62 is provided in the nitride insulating film 28 and the insulating film 29 at a position overlapping with the conductive film 44. And on the nitride insulating film 28 and the insulating film 29, a conductive film 45 having translucency to visible light and functioning as a pixel electrode is provided. The conductive film 45 is electrically connected to the conductive film 44 at the opening 62. Also, the conductive film 45 overlaps with the metal oxide film 42 at the opening 58. The portion where the conductive film 45 and the metal oxide film 42 overlap with the nitride insulating film 28 and the insulating film 29 interposed therebetween functions as a capacitive element 57. 58. ​ .

[0143] The capacitive element 57 consists of a metal oxide film 42 and a conductive film 45 that function as a pair of electrodes, and a dielectric The nitride insulating film 28 and insulating film 29, which function as a film, are transparent to visible light. Therefore, the capacitive element 57 has light transmission to visible light, and the capacitive element Compared to pixels with low light transmittance to visible light, the aperture ratio of pixel 55 can be increased. Therefore, while securing the necessary capacity to obtain high image quality, the loss of light within the panel is minimized. This can reduce power consumption in semiconductor devices.

[0144] As mentioned above, the insulating film 29 is not necessarily required, but the nitride insulating film 28 Furthermore, an insulating film 29 made of an insulator with a lower dielectric constant is used together with a nitride insulating film 28 as a dielectric film. By using this, the dielectric constant of the dielectric film of the capacitive element 57 is increased, and the thickness of the nitride insulating film 28 is increased. It can be adjusted to the desired value without any effort.

[0145] An orientation film 52 is provided on the conductive film 45.

[0146] Furthermore, a substrate 46 is provided opposite the substrate 31. Visible light A shielding film 47 that has the function of blocking light, and a colored layer 48 that transmits visible light in a specific wavelength range, A resin film 50 is provided on the shielding film 47 and the colored layer 48, and the resin A conductive film 59, which functions as a common electrode, is provided on the film 50. An orientation film 51 is provided on 59.

[0147] Then, between substrate 31 and substrate 46, the liquid crystal is sandwiched between alignment film 52 and alignment film 51. A liquid crystal layer 53 containing the material is provided. The liquid crystal element 60 has a conductive film 45, a conductive film 59, and It has a liquid crystal layer 53.

[0148] Note that in Figures 11 and 12, TN (Twisted Nemat) is used as the driving method for the liquid crystal. The example given uses the IC mode, but as a method for driving liquid crystals, FFS (Fring e Field Switching) mode, STN (Super Twisted) Nematic mode, VA (Vertical Alignment) mode, MV A (Multi-domain Vertical Alignment) mode, IP S (In-Plane Switching) mode, OCB (Optically Controlled) Compensated Birefringence mode, Blue phase mode, TBA (Transverse Bend Alignment) mode, VA-IPS mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) Mode, PDLC (Polymer Dispersed Liquid Crystals) tal) mode, PNLC (Polymer Network Liquid Crystals tal) mode, guest host mode, ASV (Advanced Super Vie It is also possible to apply modes such as w).

[0149] Furthermore, in a liquid crystal display device according to one aspect of the present invention, the liquid crystal layer includes, for example, thermotropic Liquid crystal materials classified as chlorotropic liquid crystals or liotropic liquid crystals can be used. The liquid crystal layer may include, for example, nematic liquid crystal, smectic liquid crystal, cholesteric liquid crystal, and For this, liquid crystal materials classified as discotic liquid crystals can be used. Alternatively, the liquid crystal layer can be For example, this involves using liquid crystal materials classified as ferroelectric liquid crystals or antiferroelectric liquid crystals. Yes, it is possible. Alternatively, the liquid crystal layer may contain, for example, a main-chain polymer liquid crystal, a side-chain polymer liquid crystal, or By using liquid crystal materials classified as polymer liquid crystals, such as composite polymer liquid crystals, or low molecular weight liquid crystals... This is possible. Alternatively, the liquid crystal layer may be classified as, for example, polymer-dispersed liquid crystal (PDLC). Liquid crystal materials can be used.

[0150] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used as the liquid crystal layer. The blue phase is the liquid crystal phase. One such example is when a cholesteric liquid crystal is heated, and it transitions from the cholesteric phase to the isotropic phase. This phase appears just before transfer. The blue phase only appears within a narrow temperature range, so Kaira The temperature range is improved by adding a curing agent or UV-curing resin. The liquid crystal exhibits a blue phase and a chiral agent. A liquid crystal composition containing these elements has a short response time of 1 msec or less and is optically isotropic, therefore orientation It is preferable because it requires no processing and has low dependence on the viewing angle.

[0151] Figure 12 also shows a liquid crystal display device that uses a color filter to display a color image. While the above is an example, a liquid crystal display device according to one aspect of the present invention emits light of different hues. The system may have a configuration that displays a color image by sequentially lighting up several light sources.

[0152] Furthermore, the oxide semiconductor film 41 of the transistor 56 is composed of a single oxide semiconductor film. This is not necessarily the case; it may also be composed of multiple stacked oxide semiconductor films. Figure 13(A) Now, consider the case where the oxide semiconductor film 41 is composed of three stacked oxide semiconductor films. The example shows that, specifically, in the transistor 56 shown in Figure 13(A), an oxide semiconductor film As 41, the oxide semiconductor films 41a to 41c are arranged in order from the insulating film 22 side. They are stacked.

[0153] Furthermore, the oxide semiconductor film 41a and the oxide semiconductor film 41c constitute the oxide semiconductor film 41b. It contains at least one of the constituent metal elements, and the energy at the lower end of the conduction band is acid 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less, true It is an oxide film close to an empty state. Furthermore, the oxide semiconductor film 41b contains at least indium Including this is preferable because it increases carrier mobility.

[0154] Furthermore, as shown in Figure 13(B), the oxide semiconductor film 41c is composed of conductive film 43 and conductive film 44. It may also be configured to be superimposed on the insulating film 22 in the upper layer.

[0155] <Top view and cross-sectional view of a semiconductor display device> Next, taking a liquid crystal display device as an example, the appearance of a semiconductor display device according to one aspect of the present invention... Next, we will explain using Figure 14. Figure 14 shows substrate 4001 and substrate 4006 sealed with sealing material 40 This is a top view of the liquid crystal display device bonded by 05. Also, Figure 15 is the dashed line C in Figure 14. This corresponds to the cross-sectional view in 1-C2.

[0156] The pixel section 4002 and the pair of drive circuits 4004 are surrounded on the substrate 4001. A sealing material 4005 is provided. Also, a base is provided on the pixel section 4002 and the drive circuit 4004. A plate 4006 is provided. Therefore, the pixel unit 4002 and the drive circuit 4004 are connected to the substrate. It is sealed by 4001, the sealing material 4005, and the substrate 4006.

[0157] Furthermore, in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, The dynamic circuit 4003 is implemented.

[0158] Furthermore, the pixel section 4002 and the drive circuit 4004 provided on the substrate 4001 are transistors It has multiple such elements. Figure 15 illustrates the transistor 4010 included in the pixel section 4002. It is. On transistor 4010, there is an insulating film composed of various insulating films, including an oxide insulating film. An insulating layer 4022 is provided, which is composed of an edge film 4020 and various insulating films including a nitride insulating film. The transistor 4010 has an opening provided in the insulating film 4020 and the insulating layer 4022. In this configuration, it is connected to the pixel electrode 4021 on the insulating film 4022.

[0159] Furthermore, a resin film 4059 is provided on the substrate 4006, and a common resin film 4059 is provided on the resin film 4059. An electrode 4060 is provided. And between substrate 4001 and substrate 4006, a pixel electrode A liquid crystal layer 4028 is provided so as to be sandwiched between electrode 4021 and common electrode 4060. The liquid crystal element 4023 has a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0160] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Then, the liquid crystal element 4023 is affected by the potential of the image signal applied to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0161] Furthermore, as shown in Figure 15, in one embodiment of the present invention, the insulating film 4020 and the insulating layer 4022 are , removed at the edges of the panel. And the insulating film 4020 and insulating layer 4022 In the area that has been removed, a conductive film 4050 is formed. The conductive film 4050 and The conductive film that functions as the source or drain of the Rangista 4010 is one conductive film. It can be formed by cutting.

[0162] Furthermore, conductive particles 4061 having electrical conductivity are separated between substrate 4001 and substrate 4006. A scattered resin film 4062 is provided. The conductive film 4050 is connected to the common electrode 4060 and They are electrically connected via the electrically charged particle 4061. That is, the common electrode 4060 and the conductive The film 4050 is electrically connected at the edge of the panel via conductive particles 4061. This means that a thermosetting resin or an ultraviolet curing resin can be used for the resin film 4062. This can be done. In addition, the conductive particles 4061 can be made of, for example, spherical organic resins such as Au, Ni, and Co Particles coated with a thin film of metal, such as the above, can be used.

[0163] Although the alignment layer is not shown in Figure 15, the alignment layer is connected to the pixel electrode 4021 and the common electrode 4 When placed on 060, the common electrode 4060, conductive particles 4061, and conductive film 4050 To electrically connect them, a portion of the alignment film is removed in the area overlapping with the common electrode 4060. Therefore, the alignment film can be partially removed in the area where it overlaps with the conductive film 4050.

[0164] Furthermore, in a liquid crystal display device according to one aspect of the present invention, a color filter is used to produce color You can display an image, or you can sequentially light up multiple light sources that emit light of different hues. You may display color images.

[0165] Furthermore, the image signal from the drive circuit 4003 and various control signals and potentials from the FPC 4018 are also transmitted. The drive circuit 4004 or the pixel unit 400 is connected via the routing wires 4030 and 4031. It is given to 2.

[0166] <About semiconductor films> Impurities such as water or hydrogen, which act as electron donors, are reduced, and oxygen is deficient. The oxide semiconductor (purified oxide) is purified by reducing the amount of oxides. Semiconductors have few carrier sources, so they are i-type (intrinsic semiconductors) or It can be made to be as close as possible to type i. Therefore, the highly purified oxide semiconductor film can be made to Transistors with a channel formation region have significantly low off-current and high reliability. Therefore, in a transistor in which a channel formation region is formed in the oxide semiconductor film, the threshold voltage is It is prone to developing electrical characteristics that result in a loss (also known as normally-off characteristics).

[0167] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small current can be proven through various experiments. For example, if the channel width is 1 × 1 0 6 Even with a μm element and a channel length of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current normalized by the transistor channel width is 100 Hz A / μm or less. It can be seen that there is a capacitive element and a transistor are connected so that the current flows into the capacitive element or The off-current is measured using a circuit that controls the charge flowing out of a capacitive element with the transistor. The measurement was performed using a highly purified oxide semiconductor film as the channel of the transistor. Used in the formation region, the transistor's off state is determined from the change in the amount of charge per unit time of the capacitive element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. In some cases, it was found that even smaller off-currents, such as tens of yA / μm, can be obtained. Therefore Therefore, transistors that use a highly purified oxide semiconductor film in the channel formation region are off-voltage. The current is significantly lower compared to transistors using crystalline silicon.

[0168] Furthermore, when using an oxide semiconductor film as the semiconductor film, the oxide semiconductor must be at least It is preferable that the oxide semiconductor contains indium (In) or zinc (Zn). As a stabilizer to reduce variations in the electrical characteristics of transistors using, In addition to these, it is preferable to have gallium (Ga). Also, as a stabilizer, It is preferable to have s(Sn). Also, hafnium(Hf) is used as a stabilizer. It is preferable to have it. Furthermore, it is preferable to have aluminum (Al) as a stabilizer. This is preferable. It is also preferable to include zirconium (Zr) as a stabilizer.

[0169] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon dioxide, gallium nitride, or gallium oxide, sputtering and wet processes This makes it possible to fabricate transistors with excellent electrical characteristics, and offers superior mass-producibility. These are some of the advantages. Also, unlike silicon carbide, gallium nitride, or gallium oxide The above In-Ga-Zn oxide is used to form transistors with excellent electrical properties on a glass substrate. It is possible to manufacture these. Furthermore, it can accommodate larger substrate sizes.

[0170] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0171] For example, as oxide semiconductors, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, S n-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides Materials (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, I n-Hf-Zn oxides, In-La-Zn oxides, In-Pr-Zn oxides, In -Nd-Zn oxides, In-Ce-Zn oxides, In-Sm-Zn oxides, In- Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-D y-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm -Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn- Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides Substances, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn oxides can be used.

[0172] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. This is about taste, and the ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn are not considered. It may contain. In-Ga-Zn oxides have sufficiently high resistance in the absence of an electric field and are off-electric. It is possible to significantly reduce the flow rate, and it also has high mobility.

[0173] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0174] The structure of oxide semiconductor films will be described below.

[0175] Oxide semiconductor films are broadly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. Single-crystal oxide semiconductor films include amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and polycrystalline oxide films. This refers to monocrystalline semiconductor films, CAAC-OS films, etc.

[0176] Amorphous oxide semiconductor films have an irregular arrangement of atoms within the film and do not contain crystalline components. It is a crystalline semiconductor film. Even in minute regions, it does not have crystalline areas; the entire film has a completely amorphous structure. Oxide semiconductor films are a typical example.

[0177] Microcrystalline oxide semiconductor films are, for example, microcrystals (nanocrystals) with a size of 1 nm to less than 10 nm. Also known as. ) contains. Therefore, microcrystalline oxide semiconductor films are more fundamental than amorphous oxide semiconductor films. The arrangement of the microcrystalline oxide semiconductor film is highly regular. Therefore, microcrystalline oxide semiconductor films are superior to amorphous oxide semiconductor films. It also has the characteristic of having a low defect level density.

[0178] CAAC-OS film is one of the oxide semiconductor films having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC-O The crystalline portion contained in the S film is within a cube with sides less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within the given space. CAAC-OS films are less porous than microcrystalline oxide semiconductor films. It is characterized by a low void density. CAAC-OS film is examined using a transmission electron microscope (TEM:T). Observed using a transmission electron microscope. Then, we can confirm the clear boundaries between the crystalline parts, that is, the grain boundaries (also called grain boundaries). It is not possible. Therefore, the CAAC-OS film has an electron mobility due to grain boundaries. It can be said that a decline is unlikely to occur.

[0179] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer has irregularities on the surface (also called the surface to be formed) or the upper surface that forms the CAAC-OS film. The shape reflects this, and the elements are arranged parallel to the surface or top surface of the CAAC-OS film.

[0180] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the angle is perpendicular. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "perpendicular" This refers to a state where two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°.

[0181] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) In the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. stomach.

[0182] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. You can tell they are there.

[0183] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0184] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0185] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in a certain direction. Therefore, it is arranged in layers as confirmed by the aforementioned cross-sectional TEM observation. Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0186] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0187] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, the CAAC-OS film When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to a C-OS film, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0188] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 2θ of 36° indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0189] Transistors using CAAC-OS film exhibit changes in electrical characteristics due to irradiation with visible light or ultraviolet light. The dynamics are small. Therefore, this transistor is highly reliable.

[0190] Oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0191] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0192] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities present in the processing room (hydrogen, water, carbon dioxide, and nitrogen, etc.) It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0193] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate. A reaction occurs, and the flat surface of the sputtered particles adheres to the substrate.

[0194] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0195] As an example of a target, an In-Ga-Zn oxide target is shown below.

[0196] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a predetermined molar ratio and then subjected to pressure treatment. By heat treatment at temperatures between 1000°C and 1500°C, polycrystalline In-Ga - A Zn-based oxide target is used. X, Y, and Z are arbitrary positive numbers. Here, A constant molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is in a 2:2 ratio. The ratios are 1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The type of powder and the molar ratio in which they are mixed should be appropriately changed depending on the target being prepared. Yes.

[0197] Furthermore, alkali metals are not elements that make up oxide semiconductors, and are therefore impurities. Earth metals also become impurities when they are not elements that constitute oxide semiconductors. Among alkali metals, Na is used when the insulating film in contact with the oxide semiconductor film is an oxide. Na diffuses into the insulating film. + This is the result. Furthermore, Na is present in the oxide semiconductor film. It breaks the bond between the metal and oxygen that make up the conductor, or intervenes in that bond. For example, normalization due to a shift in the threshold voltage in the negative direction, low mobility In lower-grade transistors, the electrical characteristics deteriorate, and variations in characteristics also occur. Specifically, the measured Na concentration by secondary ion mass spectrometry was 5 × 10⁻⁶. 16 / cm 3 below Preferably 1 × 10 16 / cm 3 More preferably 1 × 10 15 / cm 3 The following It would be good to do so. Similarly, the measured value of Li concentration is 5 × 10 15 / cm 3 The following is preferably 1×1 0 15 / cm 3 The following is recommended. Similarly, the measured value of the K concentration is 5 × 10 15 / cm 3 Below Below, preferably 1 × 10 15 / cm 3 The following is recommended.

[0198] Furthermore, when metal oxides containing indium are used, the bond energy with oxygen is Larger silicon and carbon atoms than indium break the bond between indium and oxygen, resulting in an oxygen deficiency. This can form. Therefore, if silicon or carbon is mixed into the oxide semiconductor film, Similar to alkali metals and alkaline earth metals, degradation of the transistor's electrical characteristics occurs. It is prone to stiffness. Therefore, it is desirable that the concentrations of silicon and carbon in oxide semiconductor films be low. Specifically, the measured values ​​of C concentration or Si concentration by secondary ion mass spectrometry. is 1 × 10 18 / cm 3 The following is preferable. With the above configuration, the electrical characteristics of the transistor This can prevent degradation of performance and improve the reliability of semiconductor devices.

[0199] Furthermore, depending on the conductive material used for the source electrode and drain electrode, the source electrode and The metal in the drain electrode may extract oxygen from the oxide semiconductor film. In this case, acid In the semiconductor film, the regions in contact with the source electrode and drain electrode are affected by the formation of oxygen vacancies. It will be converted to the n-type.

[0200] Because the n-type region functions as either a source region or a drain region, in oxide semiconductors... This can reduce the contact resistance between the film and the source and drain electrodes. Therefore, the formation of an n-type region increases the transistor's mobility and on-current. This makes it possible to achieve high-speed operation of semiconductor devices using transistors. It is possible.

[0201] Furthermore, the extraction of oxygen by metal in the source electrode and drain electrode is performed by the source electrode and drain electrode. This can occur when forming the rain electrode by sputtering or other methods, and the source electrode and the dash This can also occur due to heat treatment performed after the formation of the rain electrode.

[0202] Furthermore, the n-type region is made of a conductive material that readily bonds with oxygen, and is used as both the source electrode and the drain electrode. Using it makes it easier to form. Examples of the conductive materials mentioned above include Al and C. Examples include r, Cu, Ta, Ti, Mo, and W.

[0203] Furthermore, oxide semiconductor films are not necessarily composed of a single metal oxide film, but rather are stacked It may be composed of multiple metal oxide films. For example, the first to third metal oxide films may be arranged sequentially. In the case of semiconductor films stacked on a substrate, the first metal oxide film and the third metal oxide film are the second The metal oxide film contains at least one of the metal elements that make up the metal oxide film, and the conduction band The edge energy is 0.05 eV or more, 0.07 eV or more, and 0.07 eV or more than the second metal oxide film. 1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, The first oxide film is below 0.4 eV, close to the vacuum level. Furthermore, the second metal oxide film is small Even if indium is not present, it is preferable because it increases carrier mobility.

[0204] When a transistor has a semiconductor film with the above configuration, applying a voltage to the gate electrode allows the transistor to... When an electric field is applied to a semiconductor film, the second gold layer of the semiconductor film, which has low energy at the lower end of the conduction band, is formed. A channel region is formed in the metal oxide film. That is, between the second metal oxide film and the gate insulating film. A third metal oxide film is provided in between, which separates the gate insulating film from the third A channel region can be formed in the metal oxide film of type 2.

[0205] Furthermore, the third metal oxide film is composed of at least one of the metal elements that make up the second metal oxide film. Because it contains as a component, at the interface between the second metal oxide film and the third metal oxide film, Scattering is less likely to occur. Therefore, carrier movement is less likely to be hindered at the interface, The field-effect mobility of the transistor increases.

[0206] Furthermore, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, the interface Because a channel region is formed in the neighboring region, the threshold voltage of the transistor fluctuates. However, the first metal oxide film has fewer metal elements in the second metal oxide film. Since both contain one of the components, at the interface between the second metal oxide film and the first metal oxide film Therefore, interface states are less likely to form. Thus, with the above configuration, the threshold voltage of the transistor, etc. Variations in electrical characteristics can be reduced.

[0207] Furthermore, the presence of impurities between the metal oxide films creates a carrier flow at the interface of each film. Multiple metal oxide films are stacked to prevent the formation of interfering interface states. Desirable. If impurities are present between the layers of metal oxide films, The energy continuity at the lower end of the conduction band is lost, and carriers are trapped near the interface. This is because they are either removed or eliminated through recombination. By reducing the amount of metal oxide film, multiple metal oxide films, each containing at least one main metal component, Rather than simply stacking layers, continuous bonding (in this case, the energy at the lower end of the conduction band is continuous between each film) This makes it easier for a state with a continuously changing U-shaped well structure to form.

[0208] To form continuous bonds, a multi-chamber deposition apparatus equipped with a load-lock chamber is required. (Using a sputtering device) to continuously stack each film without exposing it to the atmosphere. This is necessary. Each chamber in the sputtering apparatus is impure for oxide semiconductors. To remove as much of the water and other materials as possible, an adsorption-type vacuum pump such as a cryopump is used. Using high vacuum evacuation (5×10 -7 Pa~1×10 -4 It is preferable to do so (up to approximately Pa). Alternatively, a turbomolecular pump and a cold trap can be combined to run from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the container.

[0209] To obtain high-purity, intrinsic oxide semiconductors, it is not enough to simply evacuate each chamber to a high vacuum. Furthermore, increasing the purity of the gas used in sputtering is also important. The oxygen gas used as the above gas The dew point of the argon gas is set to -40°C or lower, preferably -80°C or lower, more preferably - By keeping the temperature below 100°C and increasing the purity of the gas used, moisture and other substances are prevented from being absorbed into the oxide semiconductor film. This can prevent it from being incorporated as much as possible. Specifically, the second metal oxide film is In- In the case of M-Zn oxide (where M is Ga, Y, Zr, La, Ce, or Nd), the second metal In a target used to form an oxide film, the atomic ratio of metal elements is In:M: If Zn = x1:y1:z1, then 、 x1 / y1 is between 1 / 3 and 6, and also between 1 and 6. The following conditions must be met, and it is preferable that z1 / y1 is between 1 / 3 and 6, and moreover, between 1 and 6. It seems so. Furthermore, by setting z1 / y1 to between 1 and 6, CA can be used as the second metal oxide film. AC-OS films are more easily formed. Typical examples of atomic ratios of target metal elements include Examples include In:M:Zn=1:1:1 and In:M:Zn=3:1:2.

[0210] Specifically, the first metal oxide film and the third metal oxide film are In-M-Zn oxide (where M is G In the case of a, Y, Zr, La, Ce, or Nd, the first metal oxide film, the third metal oxide In a target used for forming a metal film, the atomic ratio of metal elements is In:M:Zn Let =x2:y2:z2 、 x2 / y2 <x1 / y1であって、z2 / y2は、1 / 3 It is preferable that z2 / y2 is 6 or less, and more preferably 1 or more and 6 or less. By doing the following, the CAAC-OS film is formed as the first metal oxide film and the third metal oxide film. It becomes easier to form. A typical example of the atomic ratio of the target metal elements is In:M:Z n=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M Examples include Zn=1:3:8.

[0211] The thickness of the first metal oxide film and the third metal oxide film is between 3 nm and 100 nm. Preferably, the thickness of the second metal oxide film is 3nm or more and 50nm or less. m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably The range is between 3nm and 50nm.

[0212] In a three-layer semiconductor film, the first to third metal oxide films are amorphous. It can take both crystalline and non-crystalline forms. However, the second metal oxide in which the channel region is formed The crystalline nature of the film allows for stable electrical characteristics to be imparted to the transistor. Therefore, the second metal oxide film is preferably crystalline.

[0213] The channel formation region is the part of the transistor's semiconductor film that overlaps with the gate electrode. This refers to the region sandwiched between the source electrode and the drain electrode. The channel region is also defined as the channel region. This refers to the region within the Nell formation area where electric current primarily flows.

[0214] For example, the first metal oxide film and the third metal oxide film are shaped by the sputtering method. When using the resulting In-Ga-Zn oxide film, the first metal oxide film and the third metal acid For the deposition of oxide films, In-Ga-Zn oxides (In:Ga:Zn=1:3:2 [number of atoms]) are used. A target with a ratio of [ ] can be used. The film deposition conditions are, for example, using as the deposition gas. Using 30 sccm of argon gas and 15 sccm of oxygen gas, at a pressure of 0.4 Pa, the substrate temperature was... The temperature should be set to 200°C and the DC power to 0.5kW.

[0215] Furthermore, when the second metal oxide film is a CAAC-OS film, the deposition of the second metal oxide film is required. It is an In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]), It is preferable to use a target containing a polycrystalline In-Ga-Zn oxide. Film deposition conditions For example, 30 sccm of argon gas and 15 sccm of oxygen gas are used as the film-forming gas. The pressure can be set to 0.4 Pa, the substrate temperature to 300°C, and the DC power to 0.5 kW. Cut.

[0216] Furthermore, the transistor may have a structure in which the edges of the semiconductor film are sloped, The body membrane may have a structure in which the ends are rounded.

[0217] Furthermore, when using a semiconductor film having multiple stacked metal oxide films in a transistor, Even if the source electrode and drain electrode are in contact with each other, the regions in contact with each other may be n-type. This improves the mobility and on-current of transistors, and enables the creation of semiconductor devices using transistors. This enables high-speed operation. Furthermore, a semiconductor having multiple stacked metal oxide films When a conductive film is used in a transistor, the region that becomes n-type is the second gold region which becomes the channel region. Reaching the oxide film increases the transistor's mobility and on-current, thus improving the semiconductor's performance. This is more preferable for achieving even faster operation of the device.

[0218] <Examples of electronic device configurations using semiconductor devices> A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention And mobile phones, game consoles including portable devices, personal digital assistants, e-books, video cameras, digital cameras Cameras such as still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 16. vinegar.

[0219] Figure 16(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It has illustration 5008, etc. Display unit 5003 or display unit 5004, and other integrated circuits. A semiconductor device according to one aspect of the present invention can be used. The portable game console has two display units 5003 and 5004, but the portable The number of display units a game console has is not limited to this.

[0220] Figure 16(B) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 They are connected by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It can be changed by 5605. The video in the first display unit 5603 is connected to the connection unit 5 The switching mechanism is determined according to the angle between the first housing 5601 and the second housing 5602 in 605. It may also be made into a first display unit 5603 or a second display unit 5604 or other integrated circuit. A semiconductor device according to one aspect of the present invention can be used.

[0221] Figure 16(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It has a keyboard 5403, a pointing device 5404, etc. Display unit 5402 and A semiconductor device according to one aspect of the present invention can be used in other integrated circuits.

[0222] Figure 16(D) shows a wristwatch, consisting of a casing 5201, a display unit 5202, operation buttons 5203, and It has a display unit 5202 and other integrated circuits, according to one aspect of the present invention. A semiconductor device can be used.

[0223] Figure 16(E) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 58 03, it has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 580 4 and lens 5805 are provided in the first housing 5801, and the display unit 5803 is in the second housing It is located in 5802. And the first housing 5801 and the second housing 5802 are connected by a connection part. They are connected by 5806, and the angle between the first housing 5801 and the second housing 5802 is, The change can be made by the extension unit 5806. The video switching in the display unit 5803 This is done according to the angle between the first housing 5801 and the second housing 5802 at the connection part 5806. The configuration is also good. The display unit 5803 and other integrated circuits use semiconductors according to one aspect of the present invention. Body devices can be used.

[0224] Figure 16(F) shows a mobile phone, with a housing 5901 containing a display unit 5902, a microphone 5907, and a microphone. The speaker 5904, camera 5903, external connection unit 5906, and operation buttons 5905 are provided. It is installed. The display unit 5902 and other integrated circuits are equipped with a semiconductor device according to one aspect of the present invention. A flexible substrate can be used. Furthermore, a semiconductor device according to one aspect of the present invention can be provided on a flexible substrate. When formed in this manner, the semiconductor is mounted on the display section 5902 having a curved surface as shown in Figure 16(F). It is possible to apply the placement. [Explanation of Symbols]

[0225] 10 sequential circuits 10_j Sequential circuit 10_j-1 Sequential circuit 10_y sequential circuit 10_y-1 sequential circuit 10_1 Sequential circuit 10_4m sequential circuit 11 circuits 12 transistors 13 transistors 14 Wiring 15 Wiring 16 Wiring 17 Wiring 18 Wiring 19 Wiring 20 output terminals 22 Insulating film 26 Insulating film 27 Insulating film 28 Nitride insulating film 29 Insulating film 31 circuit boards 40 Conductive film 41 Oxide semiconductor film 41a Oxide semiconductor film 41b Oxide semiconductor film 41c oxide semiconductor film 42 Metal oxide film 43 Conductive film 44 Conductive film 45 Conductive film 46 circuit boards 47 Shielding membrane 48 Colored layer 50 Resin film 51 Orientation film 52 Orientation film 53 Liquid crystal layer 55 pixels 56 transistors 57 Capacitive elements 58 Opening 59 Conductive film 60 Click the LCD button 61 Conductive film 62 Opening 70 Semiconductor display devices 71 pixel section 72 Drive Circuit 73 Drive Circuit 75 Shift Register 76 Shift Registers 77 Switch Circuits 95 transistors 96 transistors 97 Capacitive elements 98 light-emitting elements 101 Transistors 102 transistors 110 Wiring 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 119 Wiring 120 Wiring 130 transistors 131 transistors 132 transistors 133 transistors 134 transistors 135 transistors 136 transistors 137 transistors 138 transistors 139 Transistors 313 Transistors 314 transistors 315 transistors 316 transistors 317 transistors 318 transistors 319 transistors 344 transistors 345 transistors 346 transistors 347 transistors 348 transistors 349 transistors 350 transistors 351 transistors 374 transistors 375 transistors 376 transistors 377 transistors 378 transistors 379 transistors 380 transistors 381 transistors 414 transistors 415 transistors 416 transistors 417 transistors 418 transistors 419 transistors 420 transistors 421 Transistors 422 transistors 438 Wiring 444 transistors 445 transistors 446 transistors 447 transistors 448 transistors 449 transistors 450 transistors 451 transistors 452 transistors 4001 circuit board 4002 pixel section 4003 Drive Circuit 4004 Drive Circuit 4005 Sealing material 4006 circuit board 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel Electrode 4023 Liquid crystal element 4028 Liquid Crystal Layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Operation Buttons 5204 Band 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 enclosure 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part 5901 enclosure 5902 Display section 5903 Camera 5904 Speaker 5905 button 5906 External connection section 5907 Mike

Claims

1. The pixel has a transistor, a display element, and a capacitive element. The source or drain of the transistor is electrically connected to the pixel electrode of the display element and one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film, An oxide semiconductor film having a region positioned above the first insulating film and having a channel formation region for the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A second conductive film having a region positioned above the oxide semiconductor film and functioning as either the source or the drain of the transistor, A third conductive film having a region positioned above the oxide semiconductor film and functioning as the other of the source or drain of the transistor, A fourth conductive film having a region positioned above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film, The second insulating film has a region in contact with the channel formation region of the transistor and a region in contact with the metal oxide film. The metal oxide film has a first region that overlaps with the third insulating film without the second insulating film in between, and without the fourth conductive film in between. Display device.

2. The pixel has a transistor, a display element, and a capacitive element. The source or drain of the transistor is electrically connected to the pixel electrode of the display element and one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film, An oxide semiconductor film having a region positioned above the first insulating film and having a channel formation region for the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A second conductive film having a region positioned above the oxide semiconductor film and functioning as either the source or the drain of the transistor, A third conductive film having a region positioned above the oxide semiconductor film and functioning as the other of the source or drain of the transistor, A fourth conductive film having a region positioned above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film, The second insulating film has a region in contact with the channel formation region of the transistor and a region in contact with the metal oxide film. The metal oxide film has a first region that overlaps with the third insulating film without the second insulating film in between, and without the fourth conductive film in between. The second conductive film does not overlap with the first region. Display device.

3. The pixel has a transistor, a display element, and a capacitive element. The source or drain of the transistor is electrically connected to the pixel electrode of the display element and one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film, An oxide semiconductor film having a region positioned above the first insulating film and having a channel formation region for the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A second conductive film having a region positioned above the oxide semiconductor film and functioning as either the source or the drain of the transistor, A third conductive film having a region positioned above the oxide semiconductor film and functioning as the other of the source or drain of the transistor, A fourth conductive film having a region positioned above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film, The second insulating film has a region in contact with the channel formation region of the transistor and a region in contact with the metal oxide film. The metal oxide film has a first region that overlaps with the third insulating film without the second insulating film in between, and without the fourth conductive film in between. The lower surface of the metal oxide film is in contact with the first insulating film as a whole. Display device.

4. The pixel has a transistor, a display element, and a capacitive element. The source or drain of the transistor is electrically connected to the pixel electrode of the display element and one electrode of the capacitive element, in a display device, A first conductive film having the function of a photoelectrode of the transistor, A first insulating film having a region positioned above the first conductive film, An oxide semiconductor film having a region positioned above the first insulating film and having a channel formation region for the transistor, A metal oxide film having a region positioned above the first insulating film and functioning as the other electrode of the capacitive element, A second conductive film having a region positioned above the oxide semiconductor film and functioning as either the source or the drain of the transistor, A third conductive film having a region positioned above the oxide semiconductor film and functioning as the other of the source or drain of the transistor, A fourth conductive film having a region positioned above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film, A second insulating film having a region positioned above the oxide semiconductor film and a region positioned above the metal oxide film, A third insulating film having a region positioned above the second insulating film, The second insulating film has a region in contact with the channel formation region of the transistor and a region in contact with the metal oxide film. The metal oxide film has a first region that overlaps with the third insulating film without the second insulating film in between, and without the fourth conductive film in between. The lower surface of the metal oxide film is in contact with the first insulating film as a whole. The second conductive film does not overlap with the first region. Display device.

5. In any one of claims 1 to 4, Each of the oxide semiconductor film and the metal oxide film contains In, Ga, and Zn. Display device.

6. In any one of claims 1 to 5, Each of the oxide semiconductor film and the metal oxide film contains In and Zn. Display device.

Images