Semiconductor equipment

Abstract

To improve data retention characteristics in semiconductor memory devices To provide a semiconductor device that achieves [specific objective] and reduces power consumption. [Solution] The transistor 162 having a wide-bandgap semiconductor is a trench structure transistor having a trench for the gate electrode 148a and a trench for the element isolation region 161. Even if the distance between the source electrode 142a and the drain electrode 142b is narrowed, the occurrence of short-channel effects can be suppressed by appropriately setting the depth of the trench for the gate electrode.

Description

[Technical Field]

[0001] This invention relates to a miniaturization technique for semiconductor integrated circuits. Among the inventions disclosed herein are semiconductor In addition to silicon semiconductors, compound semiconductors are also used as components of conductive integrated circuits. This includes elements, and one example disclosed is one that applies a wide-bandgap semiconductor. [Background technology]

[0002] Dynamic RAM (DRAM) is a well-known semiconductor memory device, and today It is also used in various electronic devices. The memory cells that make up the core of DRAM are It consists of transistors and capacitors for writing and reading.

[0003] Like other semiconductor integrated circuits, DRAMs follow scaling laws to miniaturize their circuit patterns. Although progress has been made, it is considered difficult to make the design rules smaller than 100nm. There was a time when this was the case. One of the reasons for this was that the channel length of the transistor was less than 100 nm. This means that the short-channel effect makes it easier for punch-through current to flow, and the transistor... The problem was that it would cease to function as a weaving element. To prevent current, one could dope the silicon substrate with a high concentration of impurities, but then... This makes it easier for junction leakage current to flow between the base and the substrate, or between the drain and the substrate, ultimately affecting the memory. This can cause a decrease in retention properties, and is therefore not an appropriate solution to this problem. It was.

[0004] To address this problem, the transistors that make up the memory cell are formed in three dimensions, While reducing the area occupied by memory cells, the effective channel length of the transistor is shortened. Methods have been devised to maintain the effect to an extent that does not result in any noticeable change. For example, the channel of a transistor. A U-shaped elongated groove is formed in the region where the part is formed, and a gate insulating film is formed along the wall surface of the groove. This structure involves embedding a gate electrode in the groove (see Non-Patent Document 1).

[0005] A transistor having such a structure in its channel region has a gap between the source region and the drain region. Because the current flows around the groove, the effective channel length is increased. Therefore, the area occupied by transistors in the memory cell is reduced while suppressing the short-channel effect. The advantage was that it allowed them to control the situation. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Kinam Kim, "Technology for sub-50nm DRAM and NAND Flash Manufacturing," International Electron Devices Meeting, 2005. IEDM Technical Digest, December 2005, p. 333 - 336 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, conventional DRAM requires refreshing at intervals of tens of milliseconds to retain data. This required frequent switching on of the transistors, leading to increased power consumption. The transistor degradation was a problem because it switched between the active and off states. It has become remarkable as the memory capacity increases and the miniaturization of transistors progresses.

[0008] Therefore, one object of the present invention is to provide a technology capable of improving data retention characteristics in a semiconductor memory device. Another object is to provide a technology capable of reducing power consumption while improving data retention characteristics in a semiconductor memory device.

Means for Solving the Problems

[0009] In order to solve the above problems, a transistor having a wide-gap semiconductor, particularly, an insulated-gate transistor having a wide-gap semiconductor is used to construct a circuit, specifically, a semiconductor memory device. By using a transistor having a wide-gap semiconductor, refreshing can be performed at intervals longer than those of a conventional DRAM, and power consumption can be reduced. Also, since the number of switching times between the on-state and off-state of the transistor per unit time is reduced, the life of the transistor can be made longer than that of a conventional DRAM.

[0010]

[0011] Also, in a transistor using a wide-gap semiconductor layer, as the miniaturization of the transistor progresses, the short-channel effect may occur. Therefore, a new transistor structure using a wide-gap semiconductor layer is proposed.

[0012] One aspect of the embodiments disclosed in this specification includes a first trench and a second trench in an insulating layer, a wide-gap semiconductor layer contacting the bottom surface and inner wall surface of the first trench, a gate insulating layer on the wide-gap semiconductor layer, a gate electrode on the gate insulating layer, and filling the second trench. ​​​​​​​​​​ The structure has an insulating layer, and the gate insulating layer is located on the bottom surface and inner wall surface of the second trench. The electrode is a semiconductor device characterized by filling the first trench. The first trench is for the gate electrode, and the second trench is for element isolation. The top surface shape of the first trench is striped or bar-shaped, and the second trench The top surface shape of the inch is either grid-like, striped, or bar-like.

[0013] In the above configuration, the source electrode or drain electrode in contact with the wide-bandgap semiconductor layer It is characterized by having poles.

[0014] As a wide-bandgap semiconductor, it has a band gap that is at least larger than silicon's 1.1 eV. Oxide semiconductors that have (for example, In-Ga-Zn-O oxide semiconductors have 3.15 eV, Dium-tin-zinc oxide semiconductors have a voltage of 2.6 eV to 2.8 eV or higher, while indium oxide has a voltage of approximately 3.0 eV. eV, indium tin oxide is approximately 3.0 eV, indium gallium oxide is approximately 3.3 eV. Indium zinc oxide has an energy of approximately 2.7 eV, tin oxide has an energy of approximately 3.3 eV, and zinc oxide has an energy of approximately 3.37 eV. Examples include V (for example) and GaN (approximately 3.4 eV).

[0015] Furthermore, the cross-sectional shape in the channel length direction of the wide-bandgap semiconductor layer is the cross-section of the first trench. The shape is curved along the surface shape, i.e., U-shaped, and the depth of the first trench is deep. The structure is such that the channel length of the transistor increases as the value increases.

[0016] Furthermore, the trench structure transistor disclosed herein has a source electrode and a drain electrode and Even if the distance is narrowed, the short-channel effect can be achieved by appropriately setting the depth of the first trench. It can be suppressed. [Effects of the Invention]

[0017] This enables improvements in data retention characteristics in semiconductor memory devices. This allows for improved data retention characteristics while simultaneously reducing power consumption. [Brief explanation of the drawing]

[0018] [Figure 1] These are a cross-sectional view and a top view illustrating one aspect of the present invention. [Figure 2] These are a cross-sectional view and a circuit diagram illustrating one aspect of the present invention. [Figure 3] This is a cross-sectional view showing one aspect of the present invention. [Figure 4] This is a circuit diagram and a conceptual diagram illustrating one aspect of the present invention. [Figure 5] This is a cross-sectional view showing one aspect of the present invention. [Figure 6] These are the structural cross-section diagrams used in the calculations and the calculation results. [Figure 7] These are the structural cross-section diagrams used in the calculations and the calculation results. [Figure 8] These are the structural cross-section diagrams used in the calculations and the calculation results. [Figure 9] This is a circuit diagram showing one aspect of the present invention. [Figure 10] This is a block diagram of a portable device showing one aspect of the present invention. [Figure 11] This is a block diagram of a semiconductor device showing one aspect of the present invention. [Figure 12] This is a block diagram of an e-book illustrating one aspect of the present invention. [Figure 13] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 14] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 15] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Modes for carrying out the invention]

[0019] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It's not something that can be done.

[0020] (Embodiment 1) In this embodiment, the structure and fabrication method of a transistor, which is one aspect of the present invention, Let's explain using Figure 1. Figure 1(A) is a cross-sectional view of transistor 162 in the channel length direction. An example is shown. Also, Figure 1(B) shows the component parts of transistors 162 and 163. An example of a cross-sectional view of the separation region 165 is shown. Also, Figure 1(C) shows transistor 162 and An example of a top view of transistor 163 is shown. Note that Figure 1(B) shows transistor 162 This is a portion of the cross-sectional view in the channel width direction, specifically the section cut along the dashed line D1-D2 in Figure 1(C). This corresponds to [the above]. Also, Figure 1(A) corresponds to the cross-section cut along the dashed line A1-A2 in Figure 1(C). do.

[0021] First, an insulating layer 130 made of an oxide film is formed on the semiconductor substrate. Then multiple layers are applied to the insulating layer 130. It forms several trenches (also called grooves). Then, a wide gap half covers the trenches. A conductive layer 144 is formed. The method for forming the trench can be done using known techniques, and in this embodiment In this state, a trench with a depth of approximately 0.4 μm is formed. Also, in this embodiment, the gate electrode A trench for this purpose is formed by one or more etching steps.

[0022] As for semiconductor substrates, SOI substrates and drive circuits including transistors with a MOSFET structure are formed. A pre-formed semiconductor substrate, a semiconductor substrate with capacitance formed on it, etc., is used.

[0023] The insulating layer 130 consists of a silicon oxide film, a gallium oxide film, an aluminum oxide film, and silicon nitride. Using a film, silicon oxide / nitride film, aluminum oxide / nitride film, or silicon oxide / nitride film It can be formed.

[0024] The film thickness of the wide-bandgap semiconductor layer 144 shall be between 1 nm and 100 nm, and sputtering G method, MBE (Molecular Beam Epitaxy) method, CVD method, pulsed Laser deposition, ALD (Atomic Layer Deposition), coating method Printing methods and other techniques can be used as appropriate. In addition, the wide bandgap semiconductor layer 144 is spa With multiple substrate surfaces set approximately perpendicular to the surface of the taring target, the film is deposited. The sputtering equipment used, also known as CP sputtering equipment (Columnar Plasma Sputtering Equipment) The film may also be deposited using a film deposition system.

[0025] The material for the wide-bandgap semiconductor layer 144 is one with a band gap at least larger than that of silicon. Using oxide semiconductors with a wide range, such as gallium nitride, gallium oxide nitride, and zinc gallium oxide nitride. Yes, there are oxide semiconductors with a larger band gap than silicon, at least indigo It is preferable that it contains in (In) or zinc (Zn). It is particularly preferable that it contains both In and Zn. Furthermore, in order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, It is preferable to have gallium (Ga) in addition to those as a stabilizer. Furthermore, it is preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as the stabilizer. Also, aluminum is used as the stabilizer. It is preferable that it contains nium (Al).

[0026] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0027] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. These are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn acids oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides Materials, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Using Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible to be there.

[0028] For example, an In-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. This means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not specified. It is also acceptable for metal elements other than a and Zn to be present.

[0029] In addition, as an oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer) Materials represented by may also be used. Note that M is selected from Ga, Fe, Mn, and Co. It represents one or more metallic elements. Also, as an oxide semiconductor, In3SnO5 (ZnO) n Materials expressed as (n>0 and n is an integer) may also be used.

[0030] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn acid with an atomic ratio of a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used. Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use In-Sn-Zn oxides with a specific atomic ratio or oxides with a similar composition.

[0031] Furthermore, In-Sn-Zn oxides can be called ITZO (registered trademark), and the type used The composition ratio of the GET is In:Sn:Zn in atomic ratios of 1:2:2, 2:1:3, and 1:1. Use an oxide target with a ratio of :1 or 20:45:35, etc.

[0032] However, this is not limited to these, and depends on the required semiconductor characteristics (mobility, threshold, variability, etc.) A suitable composition should be used accordingly. Furthermore, in order to obtain the required semiconductor properties, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density It is preferable to make the following appropriate.

[0033] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0034] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of (a-A) = 1) means that a, b, and c are in the vicinity of (a-A) 2 +(b-B) 2 + (c-C) 2 ≤r 2 This means that the following conditions are met, and r can be set to, for example, 0.05. The same applies to monsters.

[0035] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or polycrystalline. But that's fine too. Also, even if the structure contains crystalline parts within the amorphous material, it can be non-amorphous. But that's fine.

[0036] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0037] In this embodiment, the c-axis orientation is used, and the ab-plane, surface, or interface is triangular when viewed from that direction. Alternatively, it has a hexagonal atomic arrangement, and along the c-axis, metal atoms are layered or metal atoms and oxygen atoms The elements are arranged in layers, and in the ab plane, the orientation of the a axis or b axis is different (with the c axis in the middle). (C)C-axis-aligned crystal (also known as CAAC: C Axis Aligned Crystal) This section describes oxides containing ( ).

[0038] CAAC-containing oxides, in a broad sense, are non-single crystals that can be viewed from a direction perpendicular to their ab-plane. And, having an atomic arrangement of triangles, hexagons, equilateral triangles or regular hexagons, and perpendicular to the c-axis direction When viewed from a particular direction, the acid contains a phase in which metal atoms are arranged in layers, or in which metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0039] CAAC is not a single crystal, but it is not formed solely from amorphous material either. AC contains crystalline parts (crystalline portions), but the boundary between one crystalline portion and another is not clearly defined. Sometimes it's impossible to determine for sure.

[0040] If CAAC contains oxygen, some of the oxygen may be replaced with nitrogen. The c-axis of each individual crystal portion that makes up the structure is in a constant direction (for example, the substrate surface supporting CAAC, C They may be aligned in a direction perpendicular to the surface of the AAC, etc. Or, each of the components of the CAAC The normal to the ab plane of the crystal portion is in a certain direction (for example, the substrate surface supporting CAAC, CAAC It may be oriented perpendicular to the surface, etc.

[0041] CAAC can be a conductor, a semiconductor, or an insulator, depending on its composition. Depending on its composition, it may be transparent or opaque to visible light. To do.

[0042] Examples of such CAACs include those formed in a film-like manner, with perpendicularity to the film surface or the supporting substrate surface. When observed from a particular direction, a triangular or hexagonal atomic arrangement is observed, and when the cross-section of the film is observed... Upon examination, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) can be observed. Crystals can also be cited.

[0043] An example of the crystal structure contained in CAAC will be explained in detail using Figures 13 to 15. Unless otherwise specified, Figures 13 through 15 define the upward direction as the c-axis, and the direction perpendicular to the c-axis is used. Let the surface be called surface ab. Note that when simply referring to the upper half and the lower half, the boundary is surface ab. This refers to the upper half and the lower half. Also, in Figure 13, the circled O indicates a 4-coordinate O, and two The O enclosed in a double circle indicates a three-coordinate O.

[0044] Figure 13(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter referred to as 4 The structure shows a coordinated O) and a nearby oxygen atom. Here, for each metal atom, A structure showing only the children is called a small group. The structure in Figure 13(A) takes the form of an octahedron, but For simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 13(A) are respectively There are 4-coordinate oxygen atoms, 3 in each group. The small group shown in Figure 13(A) has a charge of 0.

[0045] Figure 13(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter referred to as 3 The structure shows a coordinated oxygen atom and two adjacent four-coordinate oxygen atoms. The three-coordinate oxygen atoms are all It also exists in the ab plane. In the upper and lower halves of Figure 13(B), there is one 4-coordinate O is present. Also, since In can take on a 5-coordinate structure, it can take on the structure shown in Figure 13(B). Figure 13 The subgroup shown in (B) has a charge of 0.

[0046] Figure 13(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to the Zn. The structure is shown. The upper half of Figure 13(C) has one 4-coordinate oxygen atom, and the lower half has three 4-coordinate oxygen atoms. There is an O. Alternatively, there are three 4-coordinate Os in the upper half of Figure 13(C) and one in the lower half There may be oxygen atoms with 4 coordination. The small group shown in Figure 13(C) has a charge of 0.

[0047] Figure 13(D) shows a structure having one 6-coordinate Sn and six 4-coordinate O adjacent to the Sn. The structure is shown. The upper half of Figure 13(D) has 3 four-coordinate oxygen atoms, and the lower half has 3 four-coordinate oxygen atoms. There is an O. The small group shown in Figure 13(D) has a charge of +1.

[0048] Figure 13(E) shows a small group containing two Zn molecules. The upper half of Figure 13(E) shows one There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. The small group shown in Figure 13(E) The charge becomes -1.

[0049] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is This is called a large group (also known as a unit cell).

[0050] Here, we will explain the rules by which these subgroups combine. These rules are shown in Figure 13(A). The three oxygen atoms in the upper half of the 6-coordinate In each have three adjacent oxygen atoms in the lower half, and the three oxygen atoms in the lower half... Each of the O atoms has three adjacent In atoms in the upward direction. The 5-coordinate Ga shown in Figure 13(B) The upper half of the O has one adjacent Ga in the downward direction, and the lower half of the O has one in the upward direction It has adjacent Ga. In the upper half of the four-coordinate Zn shown in Figure 13(C), one O is located downwards. It has adjacent Zn atoms, and the three O atoms in the lower half each have three adjacent Zn atoms in the upward direction. Similarly, the number of oxygen atoms in four-coordinate positions above a metal atom and the number of neighboring metal atoms below that oxygen atom are considered. Equally, the number of 4-coordinate oxygen atoms in the metal atom and the number of neighboring metal atoms above that oxygen. The number of atoms is equal. Since O is 4-coordinate, the number of nearby metal atoms below and the number of nearby atoms above are equal. The sum of the number of metal atoms in contact with the metal is 4. Therefore, the number of 4-coordinate oxygen atoms above the metal atom, and the number of other metal atoms in contact with the metal is 4. When the sum of the number of 4-coordinate oxygen atoms below the metal atom is 4, two types of metal atoms Small groups can combine with each other. The reason for this is explained below. For example, 6-coordinate metals. When an atom (In or Sn) is bonded via four-coordinate oxygen atoms in the lower half, there are three four-coordinate oxygen atoms. Therefore, a 5-coordinate metal atom (Ga or In) or a 4-coordinate metal atom (Zn) It will be combined with one of them.

[0051] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine such that the total charge of the layered structure becomes 0. It forms a middle group.

[0052] Figure 14(A) shows a model diagram of the intermediate groups that constitute the layered structure of the In-Sn-Zn-O system. Figure 14(B) shows the large group, which is composed of three subgroups. C) shows the atomic arrangement when the layer structure of Figure 14(B) is observed from the c-axis direction.

[0053] In Figure 14(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate oxygen atoms (indicated by the circle). It is shown as 3. Similarly, in Figure 14(A), the upper half and lower half of In are Each of these has one 4-coordinate oxygen atoms, which are shown as 1 in the circle. Similarly, Figure 14 In (A), the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. Zn has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. This indicates that.

[0054] In Figure 14(A), the middle group constituting the layered structure of the In-Sn-Zn-O system is from the top In order, Sn has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with In in the half and lower half, and that In has three 4-coordinate O in the upper half. It bonds with n, and through one 4-coordinate oxygen atom in the lower half of the Zn, three 4-coordinate oxygen atoms are bonded to the upper half. And bonded to In in the lower half, that In has one 4-coordinate O in the upper half of Zn2 It combines with a small group consisting of , and through one 4-coordinate O in the lower half of this small group, 4 The coordination is structured so that three oxygen atoms are bonded to the Sn atoms in the upper half and three in the lower half. Multiple loops combine to form a larger group.

[0055] Here, for 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0.6, respectively. 67, -0.5 can be considered. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of (5-coordinate) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore Therefore, the small group containing Sn has a charge of +1. As a result, it forms a layered structure containing Sn. For this to work, a charge of -1 is needed to cancel out the charge of +1. Figure 1 shows a structure that takes on a charge of -1. As shown in 3(E), a small group containing two Zn elements is an example. If there is one small group and one small group containing two Zn atoms, the charges cancel each other out. Therefore, the total charge of the layered structure can be set to 0.

[0056] Specifically, the large groups shown in Figure 14(B) are repeated, resulting in In-Sn-Zn -O-based crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be represented by the following empirical formula:

[0057] In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, and ternary metal oxides. In-Ga-Zn oxides (also written as IGZO), which are oxides of the original metal, Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-C e-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm -Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb- Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides In-Zn oxides, Sn-Zn oxides, and Al oxides are examples of oxides of binary metals. -Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and I The same applies when using n-Ga-based oxides, etc.

[0058] For example, Figure 15(A) shows the intermediate group that constitutes the layered structure of the In-Ga-Zn-O system. A diagram is shown.

[0059] In Figure 15(A), the middle group constituting the layered structure of the In-Ga-Zn-O system is from the top In order, the ion molecule has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with Zn, and through the three 4-coordinate oxygen atoms in the lower half of that Zn, one 4-coordinate oxygen atom is bonded. Each bondes with Ga in the upper and lower halves, and via one 4-coordinate O in the lower half of that Ga Thus, the structure consists of three 4-coordinate oxygen atoms bonded to the in atoms in the upper and lower halves, respectively. Multiple of these smaller groups combine to form larger groups.

[0060] Figure 15(B) shows the large group, which is composed of three subgroups. Figure 15(C) is Figure 15(B) shows the atomic arrangement when the layered structure is observed from the c-axis direction.

[0061] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, small groups containing any of In, Zn, and Ga Therefore, the charge becomes 0. The charge of the sum is always 0.

[0062] Furthermore, the intermediate groups that constitute the layered structure of the In-Ga-Zn-O system are shown in Figure 15(A). Not limited to medium groups, but combining medium groups with different arrangements of In, Ga, and Zn. The group could also be included.

[0063] Next, it is in contact with the wide-bandgap semiconductor layer 144 and serves as a source electrode or drain electrode. Functional electrodes 142a and 142b are formed. Electrodes 142a and 142b are made of molybdenum. Titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, Scandinavian It can be formed using metallic materials such as um, or alloy materials mainly composed of these materials.

[0064] Furthermore, when GaN is used as the wide-bandgap semiconductor layer 144, the source electrode or drain The materials used for electrodes 142a and 142b, which function as in electrodes, are titanium, etc. A two-dimensional electron gas is formed between 2a, 142b and the wide-bandgap semiconductor layer 144. Aluminum gallium nitride (AlGaN) is used as the buffer layer.

[0065] Furthermore, insulating layers 143a and 143b are formed to protect electrodes 142a and 142b. Next, a planarization treatment is performed using CMP (chemical mechanical polishing), etc. In addition, the insulating layers 143a and 143b act as buffer layers to prevent the electrodes 142a and 142b from being scraped. It functions as such.

[0066] Next, trenches for element isolation in the channel length direction and trenches for element isolation in the channel width direction These trenches for separating elements can also form a connected top surface pattern. Alternatively, an independent top surface pattern shape may be used. In this embodiment, the trench is formed Therefore, in order to separate the wide-bandgap semiconductor layer, in Figure 1(C), these trends The pattern of the channel has a connected top surface pattern shape (grid-like). During the formation of the trench for separation, the electrodes 142a and 142b can also be separated. The timing of forming the trench for element isolation is not particularly limited. The depth of the isolation trench is such that sufficient element isolation can be achieved, and the trench for the gate electrode is also such that It is not limited to a depth that is at the same horizontal position on the bottom surface. It offers better element isolation than gate electrode trenches. By increasing the horizontal depth of the trench's bottom surface, element isolation can be reliably achieved.

[0067] Next, a portion of the wide-bandgap semiconductor layer 144 serves as either a source electrode or a drain electrode. A gate insulating layer 14 covers the electrodes 142a, 142b and the insulating layers 143a, 143b. 6 is formed. Also, the inner wall and bottom surface of the trench for element isolation in the channel length direction and the channel A gate insulating layer 146 is also formed on the inner wall and bottom surface of the trench in the width direction.

[0068] The thickness of the gate insulating layer 146 shall be between 1 nm and 100 nm, and shall be manufactured by sputtering or MB. Methods such as E, CVD, pulsed laser deposition, ALD, coating, and printing may be used as appropriate. Yes, it is possible. Also, the gate insulating layer 146 is approximately perpendicular to the sputtering target surface. A sputtering apparatus that performs film deposition with multiple substrate surfaces set on it, also known as a CP sputtering apparatus. The film may be formed using [a specific method / tool].

[0069] The material for the gate insulating layer 146 is a silicon oxide film, a gallium oxide film, and aluminum oxide. Aluminum film, silicon nitride film, silicon oxide nitride film, aluminum oxide nitride film, or silicon nitride oxide film It can be formed using a silicon film. Furthermore, the gate insulating layer 146 is fabricated It is preferable to form it in consideration of the size of the transistor and the step coverage of the gate insulating layer 146. In this embodiment, as the gate insulating layer 146, SiO 2+α (where α > 0) is used. By using this silicon oxide film as the gate insulating layer 146, oxygen can be supplied to the In-Ga-Zn-O-based oxide semiconductor, and the characteristics can be improved.

[0070] Also, as the material of the gate insulating layer 146, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSi x O y N z (x > 0, y > 0, z > 0)), hafnium aluminate (Hf Al x O y (x > 0, y > 0)), etc. By using high-k materials such as these, the gate leakage current can be reduced. Further, the gate insulating layer 146 may have a single-layer structure or a stacked structure.

[0071] Then, the gate electrode 148a is formed on the gate insulating layer 146 so as to be filled in the trench for the gate electrode. The material of the gate electrode 148a can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material having these as the main components. The gate electrode 148a may have a single-layer structure or a stacked structure.

[0072] As a layer of the gate electrode 148a in contact with the gate insulating layer 146, a metal oxide containing nitrogen, Specifically, nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, and nitrogen In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, These films use nitrogen-containing In-O films or metal nitride films (InN, SnN, etc.). It has a work function of 5 electron volts, preferably 5.5 electron volts or more, and is used as a gate electrode. If this is the case, the threshold voltage of the transistor can be made positive, resulting in what is known as normally off. This enables the realization of a switching element.

[0073] At the stage when the gate electrode 148a is formed in the trench for the gate electrode, the trench structure A converter 162 is formed.

[0074] Next, an insulating layer 149 is formed to cover the gate electrodes 148a and 148b. It is preferable to use an insulating film with good step coverage. As for the material of the insulating layer 149, Recon film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxide nitride film It can be formed using an aluminum oxide nitride film or a silicon oxide nitride film. In this embodiment, an aluminum oxide film is used as the material for the insulating layer 149. Figure 1(A) And in Figure 1(B), the gate insulating layer is in contact with the side surface of the wide-bandgap semiconductor layer 144. 146 is formed, and then an insulating layer 149 is formed. Therefore, in this embodiment, Si O 2+α (However, the side of the wide-bandgap semiconductor layer 144 in the silicon oxide film where α > 0) The aluminum oxide film covers the surface, and the aluminum oxide film covers the silicon oxide film, thereby creating a barrier within the silicon oxide film. Oxygen diffuses, and the insulating layer 149 is blocked from passing through.

[0075] After forming the insulating layer 149, an insulating layer 150 is formed to fill the trench for element isolation. Formed by method D, etc. By filling the trench for element isolation with an insulating layer 150. Element isolation regions 161 and 165 are formed. Note that before the formation of the insulating layer 150, element isolation In the trench, the gate insulating layer 146 and insulating layer 149 are laminated, so insulating layer 15 This reduces the area to be filled with zero, allowing for smoother filling of the insulating layer 150. Next, planarization is performed using CMP or similar methods to obtain the structures shown in Figures 1(A) and 1(B). It is possible.

[0076] Also, as shown in Figure 1(B), the gate electrode 148a of transistor 162 and the adjacent An insulating layer 150 is also filled between the gate electrode 148b of transistor 163, and the gate electric Short circuits between the poles are prevented. Also, as shown in Figure 1(A), transistor 162 An electrode that functions as the source or drain electrode, and adjacent to the channel in the channel length direction. An insulating layer 150 is also provided between the electrode that functions as the source electrode or drain electrode of the inverter. It is filled, and measures are taken to prevent short circuits between the source or drain electrodes.

[0077] In this embodiment, a wide-bandgap semiconductor layer 144 is placed in contact with the inner wall of a 0.4 μm trench. To form it, the channel length will be approximately 0.8 μm or more. Wide bandgap semiconductor layer 144 and Furthermore, when using an In-Ga-Zn-O oxide semiconductor, the channel length is 0.8 μm or longer. This allows for a normally-off transistor, thus reducing the short-channel effect. This can also be prevented from occurring. Furthermore, by adopting a trench structure, the transient Because the planar area of ​​the device can be reduced, high integration is possible.

[0078] (Embodiment 2) Using the transistor 162 shown in Figure 1, the stored contents can be retained even when power is not supplied. Figure 2 shows an example of a semiconductor device that is capable of this and has no limitations on the number of write cycles.

[0079] Transistor 162 has a low off-current, so by using it, it can be used for long-term recording. It is possible to retain the stored data. In other words, the frequency of refresh operations can be made extremely low. This makes it possible to significantly reduce power consumption.

[0080] Figure 2(A) shows an example of a cross-section of a semiconductor device.

[0081] The semiconductor device shown in Figure 2(A) has a transistor 160 made of a first semiconductor material at the bottom. It has a transistor 162 made of a second semiconductor material on its upper part. Since the Zista 162 is the same as in Embodiment 1, in Figures 2(A) and (B), it is shown as Figure 1(A Sections identical to those marked with ) will be explained using the same symbols.

[0082] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0083] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the invention is the use of wide-bandgap semiconductors in transistors to hold information. Since it is used in 162, the materials used in semiconductor devices and the structure of semiconductor devices are semi The specific configuration of the conductive device does not need to be limited to what is shown here.

[0084] The transistor 160 in Figure 2(A) includes a semiconductor material (e.g., silicon). A channel formation region 116 provided on the substrate 100, and a portion sandwiching the channel formation region 116 An impurity region 120 is provided therein, and a metal compound region 124 is in contact with the impurity region 120, A gate insulating layer 108 provided on the channel forming region 116, and on the gate insulating layer 108 It has a gate electrode 110 provided.

[0085] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160. Here, electrode 126 functions as the source electrode and drain electrode of transistor 160. Furthermore, an element isolation insulating layer is provided on the substrate 100 so as to surround the transistor 160. Furthermore, an insulating layer 130 is provided so as to cover the transistor 160. To achieve this, as shown in Figure 2(A), transistor 160 has sidewall insulation A layerless configuration is desirable. On the other hand, the characteristics of transistor 160 are important. In some cases, a sidewall insulating layer is provided on the side of the gate electrode 110, and the impurity concentration is different. An impurity region 120 including the region may also be provided.

[0086] As shown in Figure 2(A), the transistor 162 has a wide-bandgap semiconductor layer 144. It is a trench-structured transistor.

[0087] In this case, it is desirable that the wide-bandgap semiconductor layer 144 be of high purity. By using highly purified wide-bandgap semiconductors, extremely excellent electrical characteristics of transients are achieved. You can obtain 162 stamina.

[0088] Furthermore, in transistor 162 in Figure 2(A), leakage occurs between elements due to miniaturization. To suppress this, an element isolation region 161 is provided. Furthermore, it is surrounded by the element isolation region 161. Although a wide-bandgap semiconductor layer 144 that is smaller than the region and processed into an island shape is used, As shown in the first form of the method, the area is not processed into an island shape until trenches for element isolation are formed. A configuration may be adopted. If the wide-bandgap semiconductor layer is not processed into an island shape, the processing This prevents contamination of the wide-gap semiconductor layer 144 by etching. If the gap semiconductor layer is not processed in an island-like manner, the number of process steps can also be reduced. , wide-gap semiconductor processed into an island shape smaller than the region surrounded by the element isolation region 161 When using a body layer, the wide-bandgap semiconductor layer is separated by forming trenches for element isolation. Since there is no need to do so, the horizontal position of the bottom surface of the element isolation trench is the same as the trench for the gate electrode. It can be made shallower, or the total area for forming trenches for element isolation can be reduced. ru.

[0089] An insulating layer 151 is provided on the transistor 162, and the gate is located on the insulating layer 151. An electrode 153 is provided that is electrically connected to electrode 148a. An insulating layer 152 is provided. Then, a gate insulating layer 146, an insulating layer 150, and an insulating layer An electrode 154 is provided in the opening formed in the insulating layer 151, the insulating layer 152, etc. A wire 156 is formed above, which connects to electrode 154. Note that in Figure 2(A), electrode 126 And using electrode 154, the metal compound region 124, electrode 142b, and wiring 156 Although connected, the disclosed invention is not limited to this. For example, electrode 142b is directly connected to gold It may be brought into contact with the compound region 124. Alternatively, the wiring 156 may be brought into direct contact with the electrode 142b. You can touch it.

[0090] Next, an example of a circuit configuration corresponding to Figure 2(A) is shown in Figure 2(B).

[0091] In Figure 2(B), the first wiring (1st Line) and the source power of transistor 160 The poles are electrically connected to the second line and the transistor 160. The rain electrode is electrically connected. Also, the third wire (3rd Line) and One of the source or drain electrodes of the transistor 162 is electrically connected to the fourth The wiring (4th Line) and the gate electrode of transistor 162 are electrically connected. And the gate electrode of transistor 160 and the source electrode of transistor 162 The other electrode, or drain electrode, is electrically connected to one of the electrodes of capacitor 164, The wiring of line 5 (5th Line) and the other electrode of capacitor 164 are electrically connected. Yes, they are.

[0092] Capacitor 164 is manufactured using the same process as transistors 160 and 162. It can be formed by a pair of electrodes and an insulating layer that acts as a dielectric sandwiched between them. It will be formed using the same process as the manufacturing process for transistors 160 and 162. The capacitor layer 164 may be provided separately above the transistor 162, although this is not limited to the original configuration. For example, trench-type capacitors or stack-type capacitors can be used separately for the 16 transistors. By forming it above 2 or below transistor 160 and stacking them three-dimensionally, high Integration may be considered.

[0093] In the semiconductor device shown in Figure 2(B), the potential of the gate electrode of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows.

[0094] This section will explain how to write and retain information. First, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 162 is ON, thereby turning on transistor 162. The potential of the third wiring is supplied to the gate electrode of transistor 160 and capacitor 164. It can be obtained. That is, a predetermined charge is given to the gate electrode of transistor 160. (Writing). Here, we have a charge that gives two different potential levels (hereinafter referred to as the low-level charge). One of the following is given (referred to as a high-level charge). Then, the fourth wiring The potential is set to the potential at which transistor 162 is in the off state, and transistor 162 is turned off. By doing so, the charge applied to the gate electrode of transistor 160 is retained. retention).

[0095] Furthermore, a back gate electrode may be provided, and by applying a voltage to the back gate electrode... It is preferable to ensure that transistor 162 is normally turned off.

[0096] This embodiment can be freely combined with Embodiment 1.

[0097] (Embodiment 3) In this embodiment, the transistor 162 shown in Figure 1 is used, and power is not supplied. Regarding semiconductor devices that can retain stored data even under certain conditions and have no limitations on the number of write cycles: Next, we will explain a configuration different from the one shown in Embodiment 2 using Figure 3.

[0098] The semiconductor device shown in Figure 3 has a transistor 350 made of a first semiconductor material at the bottom. It has a transistor 162 made of a second semiconductor material at the top. And multiple transistors are formed in the semiconductor material below, but typically the transistor We will now explain transistor 350 and transistor 162. Note that the wire is cut along line B1-B2. Figure 3, shown below, corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor.

[0099] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0100] Furthermore, the transistor 162, which uses a second semiconductor material on its upper part, is similar to the first embodiment described above, and Since it is the same as the transistor 162 described in Embodiment 2, in Figure 3 it is shown in Figure 1 (A The same symbols are used in the same places as in ( ), and detailed explanations are omitted.

[0101] Here, we will explain transistor 350 using the first semiconductor material shown below. cormorant.

[0102] The transistor 350 consists of a semiconductor substrate 310, a gate insulating layer 314, a semiconductor layer 316, and a conductive layer. Layer 318, protective insulating layer 320, sidewall insulating layer 322, impurity region 324, and insulation It is composed of a border layer 326. The semiconductor layer 316 and the conductive layer 318 are gate electric The impurity region 324 functions as a pole and either as a source or drain region.

[0103] Also, transistor 350 is adjacent to STI (Shallow Trench Is It has an olation region 312.

[0104] First, as the STI region 312, a protective insulating film is formed on the semiconductor substrate 310 in a desired region. Then, by etching, trenches (also called grooves) are formed. Afterward, the STI region 312 can be formed by embedding an insulating dielectric film in the trench. As the insulating dielectric film, silicon oxide films, silicon nitride films, etc., can be used. .

[0105] Next, we will give a detailed explanation of transistor 350. Gate insulating layer 31 of transistor 350 As for step 4, after forming an insulating film on the semiconductor substrate 310 on which the STI region 312 is formed, Patterning and etching are performed at the desired location, and the STI region 312 and This forms trenches of different depths. Subsequently, by heat treatment in an oxygen atmosphere, The semiconductor substrate 310 in the trench is oxidized, and a gate insulating layer 314 can be formed. .

[0106] After the gate insulating layer 314 is formed, a silicon film is formed using methods such as LPCVD. , the silicon film has n + , p + Doping treatment or heat treatment is performed on the so-called polysilicone A highly conductive semiconductor layer is formed as a base. Then, sputtering is performed on the semiconductor layer. Metal films are deposited according to the law, etc. Examples of metal films include tungsten, titanium, and cobalt. Nickel, or alloy films containing tungsten, titanium, cobalt, or nickel; metal nitride A film, silicide film, etc., can be used as appropriate. A patterning can be applied to a desired region on the metal film. The conductive layer 318 is formed by performing a process and etching. By etching the semiconductor layer as a scrap, the semiconductor layer 316 can be formed. Furthermore, the conductive layer 318 and the semiconductor layer 316 function as the gate electrode of the transistor 350. .

[0107] Next, a protective insulating layer 320 is formed on the conductive layer 318. The protective insulating layer 320 is as follows: Using methods such as plasma CVD, silicon oxide films, silicon nitride films, etc., are deposited to form the desired region. It can be formed by patterning and etching processes on the area.

[0108] Next, the semiconductor substrate 310 and the protective insulating layer 320 are covered by a plasma CVD method or the like. Furthermore, by forming a silicon nitride film and performing etch-back, the sidewall insulating layer 32 It is possible to form 2.

[0109] Next, the protective insulating layer 320 and the sidewall insulating layer 322 are used as a mask for doping. The process forms an impurity region 324. The dopant used is boron, etc. Phosphorus can be used, and the dopant used as the impurity region 324 will determine n + area, p + Regions can be formed as appropriate. Note that the impurity region 324 is transistor 350 It functions as either a source or drain area.

[0110] Next, the impurity region 324, the protective insulating layer 320, and the sidewall insulating layer 322 are covered. A insulating layer 326 is formed. The insulating layer 326 is formed by oxidation by methods such as plasma CVD. It can be formed using a silicon film or the like.

[0111] Next, an opening is made in a desired region of the insulating layer 326, and it is electrically connected to the impurity region 324. Connecting electrodes 325 and 331 are formed. After the formation of 331, the surfaces of the insulating layer 326, the connecting electrode 325, and the connecting electrode 331 are flattened. You may also perform CMP processing or similar procedures.

[0112] Next, sputtering is applied to the insulating layer 326, the connecting electrode 325, and the connecting electrode 331. By using a conductive film to form a film, patterning is performed on the desired area, and then etching, Form electrodes 328 and 332. Materials that can be used for electrodes 328 and 332. Materials such as tungsten, copper, and titanium can be used as appropriate.

[0113] Next, an insulating layer 329 is formed on the insulating layer 326, electrode 328, and electrode 332. Layer 329 can be formed using the same materials and methods as the insulating layer 326.

[0114] Through the above process, a semiconductor substrate formed on which a transistor 350 using the first semiconductor material is formed A plate 310 can be formed.

[0115] Here, a transistor 350 using the first semiconductor material at the bottom and a second semiconductor material at the top The connection relationship of transistor 162 using the material will be explained below.

[0116] Transistor 350 has an impurity region 324, a connecting electrode 325, an electrode 328, and a connecting electrode It is electrically connected to transistor 162 by pole 330. On the other hand, Pure material region 324, connecting electrode 331, electrode 332, connecting electrode 334, electrode 336 The connecting electrode 338 is electrically connected to the wiring 156.

[0117] Furthermore, the gate electrode of transistor 350 (i.e., semiconductor layer 316 and conductive layer 318 ) is electrically connected to the source electrode of transistor 162. However, in Figure 3 The connection between the gate electrode of transistor 350 and the source electrode of transistor 162 is shown. It is not connected in a three-dimensional direction.

[0118] As described above, the multiple memory cells formed on the top are a type of wide-bandgap semiconductor. It is formed by a transistor using an oxide semiconductor. Because the inverter has a low off-current, it can be used to preserve stored data over a long period of time. It is possible to maintain this. In other words, it is possible to make the frequency of refresh operations extremely low. Therefore, power consumption can be significantly reduced. On the other hand, in the surrounding circuits, oxidation Semiconductor materials other than monocrystalline semiconductors are used. Examples of semiconductor materials other than oxide semiconductors include: For example, silicon, germanium, silicon germanium, silicon carbide, or galium Muhidin and the like can be used, and it is preferable to use a single-crystal semiconductor. Transistors using these materials can operate at sufficiently high speeds. Therefore, oxide semiconductors Transistors made from materials other than those mentioned above are used in various circuits (logic circuits, drive circuits) that require high-speed operation. It is possible to suitably realize dynamic circuits, etc.

[0119] Thus, transistors using materials other than oxide semiconductors (in other words, sufficiently high-speed operation) A peripheral circuit using transistors capable of operation, and a transistor using oxide semiconductors ( In a broader sense, it integrates a memory circuit using a transistor with a sufficiently low off-current. This makes it possible to realize a semiconductor device with unprecedented features. By using a stacked structure for the paths and memory circuits, it is possible to integrate semiconductor devices.

[0120] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0121] (Embodiment 4) In this embodiment, the transistor 162 shown in Figure 1 is used, and power is not supplied. Regarding semiconductor devices that can retain stored data even under certain conditions and have no limitations on the number of write cycles: Regarding configurations different from those shown in Embodiments 2 and 3, see Figures 4 and 4. We will use number 5 to explain.

[0122] Figure 4(A) shows an example of a semiconductor device circuit configuration, and Figure 4(B) shows an example of a semiconductor device. This is a conceptual diagram. First, we will explain the semiconductor device shown in Figure 4(A), and then we will continue with Figure 4( The semiconductor device shown in B) will be described below.

[0123] In the semiconductor device shown in FIG. 4(A), the bit line BL is electrically connected to the source electrode or the drain electrode of the transistor 162, the word line WL is electrically connected to the gate electrode of the transistor 162, and the source electrode or the drain electrode of the transistor 162 is electrically connected to the first terminal of the capacitor 254.

[0124] The transistor 162 using an oxide semiconductor as the wide-gap semiconductor layer has a characteristic that the off-current is extremely small. Therefore, by turning off the transistor 162, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitor 254) can be held for an extremely long time. Further, the transistor 162 using an oxide semiconductor as the wide-gap semiconductor layer also has an advantage that the short-channel effect is unlikely to appear.

[0125] Next, a case where information is written and held in the semiconductor device (memory cell 250) shown in FIG. 4 will be described.

[0126] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, <00009!4>and the transistor 162 is turned on. As a result, the potential of the bit line BL is applied to the first terminal of the capacitor 254 (writing). Then, the potential of the word line WL is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, whereby the potential of the first terminal of the capacitor 254 is held (holding).

[0127] Since the off-current of the transistor 162 is extremely small, the potential of the first terminal The charge (or the charge stored in the capacitor) can be maintained for a long period of time.

[0128] Next, we will explain how to read the information. When transistor 162 is turned on, floating In this state, the bit line BL and capacitor 254 are conductive, and the bit line BL and capacitor 25 Charge is redistributed between 4. As a result, the potential of bit line BL changes. bit line BL The change in potential is the potential of the first terminal of capacitor 254 (or the potential of capacitor 254). It takes on different values ​​depending on the accumulated charge.

[0129] For example, let V be the potential at the first terminal of capacitor 254, C be the capacitance of capacitor 254, and The capacitive component of the bit line BL (hereinafter also called bit line capacitance) is called CB, and the charge is redistributed. If the potential of the previous bit line BL is VB0, then the potential of bit line BL after charge redistribution is... This becomes (CB*VB0+C*V) / (CB+C). Therefore, the state of memory cell 250 is... Assuming the potential of the first terminal of capacitor 254 is in two states, V1 and V0 (V1 > V0), If so, the potential of the bit line BL when the potential V1 is maintained is (=CB*VB0+C* V1) / (CB+C)) is the potential of bit line BL (=CB) when potential V0 is maintained. It can be seen that this is higher than (*VB0+C*V0) / (CB+C)).

[0130] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. ru.

[0131] Thus, the semiconductor device shown in Figure 4(A) has an extremely low off-current for transistor 162. Due to this characteristic, the charge stored in capacitor 254 can be retained for a long time. This becomes possible. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to retain the stored content over a long period of time. Next, the semiconductor device shown in FIG. 4(B) will be described. The semiconductor device shown in FIG. 4(B) has a memory cell array 251 having a plurality of memory cells 250 shown in FIG. 4(A) as memory elements at the upper part, and a memory cell array 252 having a plurality of memory cells 250 shown in FIG. 4(A). At the lower part, it has a peripheral circuit 253 necessary for operating the memory cell array 251 and the memory cell array 252. In the present embodiment, although the memory cell array 252 is located inside the memory cell array 251 and the peripheral circuit 253, since it is located above the peripheral circuit 253, the memory cell array 251 and the memory cell array 252 are considered to be located at the upper part. By adopting the configuration shown in FIG. 4(B), the peripheral circuit 253 can be provided directly below the memory cell array 251 and the memory cell array 252. Also, by making the memory cell array 251 and the memory cell array 252 have a stacked structure, the semiconductor device can be miniaturized. ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​a) and memory cell 452b) are located at the bottom, and peripheral circuitry 400 is located at the bottom. Peripheral circuitry at the bottom 400 has a transistor 450 made of a first semiconductor material, and is formed in multiple layers on top. The multiple memory cells (memory cell 452a and memory cell 452b) are part of the second semiconductor It has a transistor 162 made of material. Note that it is cut along the line C1-C2. Figure 5 corresponds to a cross-sectional view of the transistor perpendicular to the channel length direction.

[0137] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0138] Furthermore, the transistor 162, which uses a second semiconductor material on its upper part, is based on the first to second embodiments described above. Since it is the same as transistor 162 described in embodiment 3, in Figure 5 it is the same as in Figure 1(A) The same symbols are used in the same places, and detailed explanations are omitted. Here, the first half at the bottom The following is a description of transistor 450, which uses conductive materials.

[0139] In Figure 5, transistor 450 is located on a substrate 4 containing a semiconductor material (e.g., silicon). A channel formation region 404 is provided in 02, and is provided so as to sandwich the channel formation region 404. The impurity region 406 and the high-concentration impurity region 408 (these together are simply called the impurity region) (Also called the region), a metal compound region 410 adjacent to the high-concentration impurity region 408, and a channel-shaped A gate insulating layer 411 is provided on the formed region 404, and is provided in contact with the gate insulating layer 411. The gate electrode layer 412 is electrically connected to the impurity region, and the source electrode or drain is electrically connected to it. It has an electrode 418a and a source electrode or drain electrode 418b.

[0140] Here, a sidewall insulating layer 414 is provided on the side surface of the gate electrode layer 412. Furthermore, an element isolation insulating layer 403 is provided on the substrate 402 so as to surround the transistor 450. The interlayer insulating layer 420 and interlayer insulating layer 422 are provided to cover the transistor 450. A source electrode or drain electrode 418a is provided. The rain electrode 418b passes through the openings formed in the interlayer insulating layer 420 and the interlayer insulating layer 422. And it is electrically connected to the metal compound region 410. That is, the source electrode or Dre The in electrode 418a and the source electrode or drain electrode 418b are located in the metal compound region 4 10 is electrically connected to the high-concentration impurity region 408 and the impurity region 406. Furthermore, a sidewall insulating layer 414 is formed for the purpose of integrating transistors 450, etc. In some cases, this may not be possible. Also, the source electrode of the transistor 450 is on top of the interlayer insulating layer 422. The drain electrode 418a and the source electrode or drain electrode 418b are electrically connected. It has connecting electrodes 424a, 424b, and 424c, and an interlayer insulating layer 422, The electrode 424a, electrode 424b, and electrode 424c are flattened by an insulating layer 425. Yes, they are.

[0141] Electrode 424c is electrically connected to electrode 428 by connecting electrode 426. The electrode 428 is formed in the same layer as the source electrode layer and drain electrode layer of the transistor 162. It has been done.

[0142] Furthermore, the wiring 432 is electrically connected to electrode 428 by connecting electrode 430. The connecting electrode 434 is the same as the source electrode layer and drain electrode layer of transistor 162. It is electrically connected to the electrode 436 which is formed of layers. 38 is electrically connected to wiring 440.

[0143] The electrodes 424c, wiring 432, and wiring 440 provide electrical connections between memory cells and peripheral connections. Electrical connections between the edge circuit 400 and the memory cell can be made.

[0144] Note that the semiconductor device shown in Figure 5 has two memory cells (memory cell 452a and memory Although an example configuration in which cells 452b) are stacked was given, the number of stacked memory cells is not limited to this. It is not possible. A configuration with three or more stacked memory cells is also acceptable.

[0145] Furthermore, in the semiconductor device shown in Figure 5, memory cell 452a, memory cell 452b, and For connection to the edge circuit 400, electrode 424c, electrode 428, wiring 432, electrode 436, and Wiring 440 illustrates the connection configuration, but it is not limited to this. Between 452a, memory cell 452b, and peripheral circuit 400, there are two or more wiring layers, and The configuration may also include electrodes.

[0146] As described above, the multiple memory cells formed in multiple layers on top are wide-bandgap semiconductor layers and It is formed by a transistor using an oxide semiconductor. Wide bandgap semiconductor layer Transistors using oxide semiconductors have a low off-current, so they can be used This makes it possible to retain the contents of memory for a long period of time. In other words, the refresh operation Because the frequency can be reduced to an extremely low level, power consumption can be significantly reduced. On the other hand, peripheral circuits use semiconductor materials other than oxide semiconductors. Examples of semiconductor materials other than conductors include silicon, germanium, and silicon-germanium. It is possible to use silicon carbide, gallium arsenide, etc., and single-crystal semiconductors can be used. This is preferable. Alternatively, organic semiconductor materials may be used. Transistors can operate at sufficiently high speeds. Therefore, materials other than oxide semiconductors Transistors using this technology enable various circuits requiring high-speed operation (logic circuits, drive circuits, etc.). This makes it possible to suitably achieve the above.

[0147] Thus, transistors using materials other than oxide semiconductors (in other words, sufficiently high-speed operation) A peripheral circuit using transistors capable of operation, and a transistor using oxide semiconductors ( In a broader sense, it integrates a memory circuit using a transistor with a sufficiently low off-current. This makes it possible to realize a semiconductor device with unprecedented features. By using a stacked structure for the paths and memory circuits, it is possible to integrate semiconductor devices.

[0148] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0149] (Embodiment 5) In this embodiment, the semiconductor device described in the previous embodiment is used in a mobile phone, smartphone, Examples of applications to portable devices such as e-books will be explained using Figures 9 to 12.

[0150] In mobile devices such as cell phones, smartphones, and e-readers, temporary storage of image data SRAM or DRAM is used in such applications. The reason is that flash memory has a slow response time and is unsuitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics apply. .

[0151] In a typical SRAM, as shown in Figure 9(A), one memory cell is connected to transistors 801-8 It consists of six 06 transistors, which are used for the X decoder 807 and the Y decoder. It is driven by transistors 808, 803, 805, and 80 4 and transistor 806 form an inverter, enabling high-speed drive. However, one Because the memory cell is composed of 6 transistors, it has the disadvantage of having a large cell area. When the minimum dimension of the design rule is F, the memory cell area of ​​SRAM is typically 100 ~150F 2 Therefore, SRAM has the highest cost per bit among all types of memory. stomach.

[0152] In contrast, DRAM has memory cells, as shown in Figure 9(B), transistor 811, It is composed of a capacity 812, which is driven by the X decoder 813 and Y decoder 814. It is working. Each cell has a configuration of 1 transistor and 1 capacitance, resulting in a small area. D The memory cell area of ​​RAM is typically 10F 2 The following applies. However, DRAM is always refreshed This requires power consumption, even if no rewriting is performed.

[0153] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Front and back Furthermore, frequent refreshing is unnecessary. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0154] Next, Figure 10 is a block diagram of the portable device. The portable device shown in Figure 10 has an RF circuit 901. Analog baseband circuit 902, digital baseband circuit 903, battery 904 , power supply circuit 905, application processor 906, flash memory 910, D Play controller 911, memory circuit 912, display 913, touch sensor 9 It consists of components such as 19, an audio circuit 917, a keyboard 918, and a display 913. It consists of a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 is CPU907, DSP908, interface It has 909 (IF909). Generally, the memory circuit 912 is SRAM or DRAM. It is composed of the semiconductor device described in the previous embodiment, Therefore, it offers high-speed information writing and reading, long-term memory retention, and low power consumption. The force can be sufficiently reduced.

[0155] Next, Figure 11 shows the memory circuit 950 of the display connected to the semiconductor device described in the previous embodiment. This is an example of its use. The memory circuit 950 shown in Figure 11 includes memory 952, memory 953, It consists of switch 954, switch 955, and memory controller 951. Furthermore, the memory circuit 950 receives image data (input image data) from the signal line, The data (storage image data) stored in the memory 952 and memory 953 is read, and A display controller 956 that performs control, and from the display controller 956 A display 957, which displays information based on the signal, is connected.

[0156] First, some image data is formed by an application processor (not shown). (Input image data A). Input image data A is sent to memory 952 via switch 954. It is stored. And the image data stored in memory 952 (stored image data A) is... The signal is sent to the display 957 via the switch 955 and the display controller 956. , it will be displayed.

[0157] If there are no changes to the input image data A, the stored image data A is typically stored at a frequency of about 30-60 Hz. During this period, the memory 952 is transmitted via the switch 955 to the display controller 956. It will be read out.

[0158] Next, for example, when a user performs an operation to rewrite the screen (i.e., input image data A If there are any changes, the application processor will use the new image data (input image data). Form B). Input image data B is stored in memory 953 via switch 954. During this time, the stored image data A was periodically read from memory 952 via switch 955. It is being done. When the new image data (storage image data B) has finished being stored in memory 953, From the next frame on display 957, stored image data B is read out, and switch 95 5. The stored image data is sent to the display 957 via the display controller 956. Data B is sent and displayed. This read then memos new image data. This continues until it is stored in RI952.

[0159] In this way, memory 952 and memory 953 alternately write image data and image data By reading the data, the display on display 957 is displayed. 952 and memory 953 are not limited to separate memory locations, but rather to a single memory location divided into parts. It may be used as follows. The semiconductor device described in the previous embodiment is used as memory 952 and memory 9 By adopting 53, information can be written and read quickly, and long-term storage can be maintained. It is possible to maintain this while significantly reducing power consumption.

[0160] Next, Figure 12 is a block diagram of the e-book. Figure 12 shows battery 1001, power supply circuit 1 002, microprocessor 1003, flash memory 1004, audio circuit 1005, Keyboard 1006, memory circuit 1007, touch panel 1008, display 100 9. It is comprised of a display controller 1010.

[0161] Here, the memory circuit 1007 in Figure 12 uses the semiconductor device described in the previous embodiment. It is possible. The role of the memory circuit 1007 is to temporarily hold the contents of the book. Examples of features include when a user uses the highlighting function. Sometimes, when reading an ebook, you might want to mark a specific section. The highlighting function is also called the "coloring function," and it allows you to change the display color, underline, and bold text. This involves making something different from its surroundings by changing the font or typeface. This function stores and retains information from a specified location. If this information is to be stored for a long period of time... It is also acceptable to copy it to flash memory 1004. In this case as well, the previously performed By employing the semiconductor device described in the form, information writing and reading are highly efficient. It allows for rapid, long-term memory retention while significantly reducing power consumption.

[0162] As described above, the portable device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is listed. Therefore, it has high read speed, can retain data for long periods, and consumes low power. Portable devices with reduced noise levels will be realized.

[0163] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together. [Examples]

[0164] In this embodiment, the short-channel effect is exhibited in the trench structure transistor shown in Embodiment 1. I performed a calculation to confirm whether it would work.

[0165] For the calculations, we used Synopsys' device simulation software, Sentaurus. I used a device.

[0166] Figure 6(A) shows the structure and individual sizes used in the calculation. The gate insulating layer thickness is 5 nm. The thickness of the wide-bandgap semiconductor layer is set to 5 nm, and the depth of the trench for the gate electrode is set to 0.4 Set to μm. Figure 6(A) shows that the length of the trench bottom (length in the channel direction) is 90 The distance between the source electrode and the drain electrode (length in the channel direction) is 110 nm. This is a wrench-structured transistor. The material of the wide-bandgap semiconductor layer is In-Ga-Zn. -O-based oxide semiconductor (bandgap 3.15 eV, electron affinity 4.6 eV, electron mobility) 10cm 2 Using / Vs), the electrodes in contact with the wide-bandgap semiconductor layer (source electrode and dray Let the work function of the gate electrode be 4.6 eV, and the work function of the gate electrode be 5.5 eV. The results of calculating the Vg-Id characteristics of a inch-structured transistor (Vds=1V, temperature 27℃) This is shown in Figure 6(B).

[0167] Furthermore, Figure 7(A) shows that the length of the trench bottom (length in the channel length direction) is 60 nm, A trench structure in which the distance between the drain electrode and the channel electrode (length in the channel direction) is 80 nm. It is a transistor. Except for the length of the trench bottom and the distance between the source and drain electrodes, it is as shown in the diagram. Figure 7(B) shows the result calculated under the same conditions as in 6(B).

[0168] Furthermore, Figure 8(A) shows that the length of the trench bottom (length in the channel direction) is 30 nm, and the saw A trench structure in which the distance between the drain electrode and the channel electrode (length in the channel direction) is 50 nm. It is a transistor. Except for the length of the trench bottom and the distance between the source and drain electrodes, it is as shown in the diagram. Figure 8(B) shows the result calculated under the same conditions as in 6(B).

[0169] The calculation results show that the transistor characteristics of all structures in Figures 6(A), 7(A), and 8(A) are They were almost identical. The threshold voltage (Vth) of each transistor was 0.8V, and the S value was 0.8V. It showed a good value of 60mV / dec.

[0170] From these calculation results, the distance between the source electrode and the drain electrode (length in the channel direction) is 5 Even when narrowed to 0nm, short-channel effects such as a negative threshold shift and an increase in the S value do not occur. It does not exhibit any apparent characteristics and shows good transistor performance.

[0171] For comparison, a similar calculation was performed using a planar transistor structure instead of a trench structure. The calculations showed that narrowing the distance between the source electrode and the drain electrode (length in the channel direction) This also narrows the channel length, leading to short channel behaviors such as a negative threshold shift and an increase in the S value. The effect manifests, and furthermore, the leakage current (off-current) when a negative bias is applied to the gate. An increase in [the number of cases] was also confirmed.

[0172] Compare the calculation results for this comparison with the calculation results in Figures 6(B), 7(B), and 8(B). This is good, and by using the transistor structure shown in Embodiment 1, the source electrode and the drain Even when the spacing between electrodes (length in the channel direction) is narrowed, the effective change in channel length is small. Therefore, the short-channel effect does not occur, and the off-current can be kept low. As a result, the holding characteristic This makes it possible to create memory cells with good performance. [Explanation of Symbols]

[0173] 100 circuit boards 108 Gate Insulation Layer 110 Guard Station 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 130 Insulating layer 142a, 142b electrode 143a, 143b Insulating layer 144 Wide-bandgap semiconductor layer 146 Gate Insulation Layer 148a, 148b gate gate 149 Insulating layer 150 Insulating layer 151 Insulating layer 152 Insulating layer 153 Electrode 154 Electrode 156 Wiring 160 transistors 161 Element Isolation Region 162 transistors 163 transistors 164 Capacitors 165 element isolation region 250 memory cells 251 memory cell array 253 Peripheral Circuits 254 Capacitors 310 Semiconductor substrates 312 STI area 314 Gate Insulation Layer 316 Semiconductor layer 318 Conductive layer 320 Protective insulating layer 322 Sidewall insulation layer 324 Impurity region 325 Connecting electrodes 326 Insulating layer 328 Electrode 329 Insulating layer 330 connecting electrodes 331 Connecting electrodes 332 Electrode 334 Connecting electrodes 336 Electrode 338 Connecting electrodes 350 transistors 400 Peripheral Circuits 402 circuit board 403 Element isolation insulating layer 404 Channel formation region 406 Impurity region 408 High concentration impurity region 410 Metal compounds area 411 Gate Insulation Layer 412 Terminal 414 Sidewall insulation layer 418a Source electrode or drain electrode 418b Source electrode or drain electrode 420 Interlayer insulating layer 422 Interlayer insulating layer 424a electrode 424b electrode 424c electrode 425 Insulating layer 426 Connecting electrodes 428 Electrode 430 Connecting electrodes 432 Wiring 434 Connecting electrodes 436 Electrode 438 Connecting electrodes 440 Wiring 450 transistors 452a memory cell 452b memory cell 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistors 807 X Decoder 808 Y Decoder 811 Transistors 812 holding capacity 813 X Decoder 814 Y Decoder 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 909 Interface 910 Flash Memory 911 Display Controller 912 memory circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Audio Circuit 918 Keyboard 919 Touch Sensor 950 memory circuit 951 Memory Controller 952 memory 953 memory 954 Switch 955 Switch 956 Display Controller 957 displays 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

1. A first insulating layer having trenches, An oxide semiconductor layer having a region covering the inner wall of the trench, A second insulating layer having a region located within the trench, a region in contact with the oxide semiconductor layer, and a region capable of functioning as a gate insulating layer, A first conductive layer having a region located within the trench, a region in contact with the second insulating layer, a region overlapping with the oxide semiconductor layer, and a region capable of functioning as a gate electrode, A second conductive layer having a region in contact with the oxide semiconductor layer and a region that can function as either a source electrode or a drain electrode, A third conductive layer having a region in contact with the oxide semiconductor layer and a region that can function as the other of a source electrode and a drain electrode, Semiconductor equipment.

2. In claim 1, The oxide semiconductor layer contains indium and oxygen. Semiconductor equipment.

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