Manufacturing method for semiconductor devices

Abstract

This technology provides a method for easily manufacturing semiconductor element stacks while suppressing distortion. [Solution] A method for manufacturing a semiconductor device is provided, comprising the steps of: irradiating a laminate in which a first semiconductor element formed on a first substrate via a first separation layer containing a polycrystalline material and a second semiconductor element formed on a second substrate are joined together with laser light; having the first separation layer absorb the irradiated laser light; and separating the first substrate from the laminate, wherein the laminate has a second separation layer between the first separation layer and the first substrate.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] For example, in Patent Document 1, a first substrate having a first elastic modulus is bonded onto a second substrate having a second elastic modulus higher than the first elastic modulus, a semiconductor element is formed on the thinned first substrate, and then the first substrate is peeled off from the second substrate, and a method for manufacturing a semiconductor device is proposed. In Patent Document 1, for example, Si (single crystal silicon) is used for the first substrate and SiC is used for the second substrate, the Si substrate is bonded onto the SiC substrate, the Si substrate is thinned, and a semiconductor element is formed on the thinned Si substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a technique capable of easily manufacturing a stacked body of semiconductor elements while suppressing distortion.

Means for Solving the Problems

[0005] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device including a step of irradiating a stacked body in which a first semiconductor element formed via a first separation layer containing a polycrystalline material on a first substrate and a second semiconductor element formed on a second substrate are bonded with laser light, a step of absorbing the irradiated laser light by the first separation layer, and a step of separating the first substrate from the stacked body, wherein the stacked body has a second separation layer between the first separation layer and the first substrate.

Effects of the Invention

[0006] From one perspective, it is possible to easily manufacture a stack of semiconductor elements while suppressing distortion. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view showing the manufacturing method of a semiconductor device, following Figure 1. [Figure 3] A cross-sectional view showing the manufacturing method of a semiconductor device, following Figure 2. [Figure 4] Figure 2 is a cross-sectional view showing a method for reusing the first substrate that was peeled off (method of manufacturing a semiconductor device). [Figure 5] A cross-sectional view showing an example of a memory cell array and peripheral circuit of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0008] The following describes embodiments for implementing this disclosure with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0009] [Manufacturing method for semiconductor devices] The semiconductor device of this embodiment includes a memory cell array in which multiple memory cells are arranged in three dimensions, and peripheral circuits including a CMOS (Complementary Metal-Oxide-Semiconductor) circuit that controls the memory cell array. One example of the semiconductor device of this embodiment is a 3D NAND flash memory.

[0010] One example of a method for manufacturing a semiconductor device having a memory cell array and peripheral circuits is to arrange the memory cell array and peripheral circuits side by side on the same Si (silicon) substrate. In contrast, a manufacturing method for 3D NAND Cell on Peri is known, in which peripheral circuits are fabricated on a Si substrate and memory cells are stacked on top of them. Furthermore, a manufacturing method for 3D NAND Cell bond Peri is known, in which peripheral circuits and memory cell arrays are fabricated on two Si substrates, respectively, and the metal pads connected to the Cu wiring layers of the peripheral circuits and the metal pads connected to the Cu wiring layers of the memory cells are bonded together to connect them. According to this method, the semiconductor device can be miniaturized and the circuit integration density can be increased by stacking the memory cell array and peripheral circuits.

[0011] Memory cell arrays have a multilayer film in which silicon oxide and silicon nitride films are alternately stacked. In recent years, the number of layers in this multilayer film has increased, for example, to three digits. As a result, film stress on the multilayer film causes it to become concave, convex, or potato chip-shaped, resulting in a distorted shape for the memory cell array. When the memory cell array is distorted, the focus margin shifts during the lithography process when the photoresist is exposed and patterned, leading to a decrease in patterning accuracy.

[0012] In contrast, there is a semiconductor device manufacturing method in which a Si substrate is bonded to a SiC substrate, the Si substrate is thinned, semiconductor elements are formed on the thinned Si substrate, and then the Si substrate is peeled off from the SiC substrate. In this method, since the peripheral circuits and semiconductor elements of the memory cell array are stacked on the Si substrate, the Si substrate warps, causing film stress on the multilayer film of the memory cell array. Therefore, it is difficult to suppress distortion of the multilayer film. In addition, the process of thinning the Si substrate increases the number of steps in the semiconductor device manufacturing method, which leads to decreased productivity and increased manufacturing costs.

[0013] Therefore, in the semiconductor device manufacturing method according to this embodiment, a SiC substrate or the like, which has a higher elastic modulus than a Si substrate, is used, and a memory cell array is fabricated on the substrate. By using a substrate that is harder than a Si substrate, warping of the substrate can be suppressed, and film stress on the multilayer film of the memory cell array can be suppressed. As a result, distortion of the multilayer film can be suppressed, and the problem of reduced patterning accuracy in the lithography process can be resolved. In addition, the process of thinning one of the substrates after joining the two types of substrates is eliminated, making it easier to manufacture semiconductor devices, improving productivity, and reducing manufacturing costs.

[0014] The method for manufacturing a semiconductor device according to this embodiment will be described in detail below with reference to Figures 1 to 4. Figures 1 to 4 are cross-sectional views showing the method for manufacturing a semiconductor device according to this embodiment. The manufacturing method according to this embodiment produces a semiconductor device having a stacked structure in which a first semiconductor element 6 and a second semiconductor element 7 are stacked. The first semiconductor element 6 includes a memory cell array, and the second semiconductor element 7 includes peripheral circuits.

[0015] First, as shown in Figure 1(a), an isolation layer D is formed on the surface of the first substrate 1. Next, an insulating layer 3 is formed on the surface of the isolation layer D, and the first semiconductor element 6 is formed on top of it. The isolation layer D is optional. If the isolation layer D is not present, an insulating layer 3 is formed on the surface of the first substrate 1, and the first semiconductor element 6 is formed on top of it. In the following description, for convenience, the insulating layer 3 may be included in the first semiconductor element 6. The first semiconductor element 6 has a first junction surface 6a on the opposite side of the surface adjacent to the first isolation layer 4. In this embodiment, there is an isolation layer D between the first substrate 1 and the insulating layer 3, and the isolation layer D has a first isolation layer 4 and a second isolation layer 5. The configuration and function of the isolation layer D will be described later.

[0016] As shown in FIG. 1(b), a second semiconductor element 7 is formed on the surface of the second substrate 2. The second semiconductor element 7 has a second bonding surface 7a on the side opposite to the surface adjacent to the second substrate 2. The second substrate 2 has a second elastic modulus and is, for example, single crystal silicon. The first substrate 1 has a first elastic modulus higher than the second elastic modulus and is, for example, any one of SiC, sapphire, and diamond.

[0017] The elastic moduli indicated by the first elastic modulus and the second elastic modulus can be indicated by at least any one of the indexes of bending strength, tensile strength, Young's modulus, and thermal expansion coefficient. For example, the first substrate 1 having a first elastic modulus higher than the second elastic modulus is formed from a material having at least any one of the physical property values of higher bending strength, higher tensile strength, higher Young's modulus, or lower thermal expansion coefficient than the second substrate 2 having the second elastic modulus.

[0018] Next, using the structures shown in FIGS. 1(a) and (b), as shown in FIG. 1(c), a laminate is formed by bonding the first bonding surface 6a and the second bonding surface 7a to stack the first semiconductor element 6 and the second semiconductor element 7. FIG. 1(c) shows a view in which the structure including the first substrate 1 and the first semiconductor element 6 shown in FIG. 1(a) is turned upside down and the first bonding surface 6a and the second bonding surface 7a are bonded together. However, the structure of the second substrate 2 and the second semiconductor element 7 shown in FIG. 1(b) may be turned upside down and the first bonding surface 6a and the second bonding surface 7a may be bonded together.

[0019] Finally, the first substrate 1 is removed from the laminate. Any method may be used to remove the first substrate 1 from the laminate as long as the first substrate 1 can be removed from the laminate. For example, the first substrate 1 may be cut and removed. The first substrate 1 may be polished using a back side grinding method or a CMP (Chemical Mechanical Polishing) method, and further, the first substrate 1 may be removed using wet etching.

[0020] Through the above processes, a semiconductor device (3D NAND memory) according to the manufacturing method of this embodiment is completed. Note that the configuration of the above embodiment is merely an example, and this embodiment is applicable to other stacked semiconductor devices.

[0021] According to the semiconductor device by the manufacturing method of this embodiment, the first semiconductor element 6 is formed on a first substrate having a higher elastic modulus than the second substrate of single-crystalline silicon. Thereby, warping of the first substrate can be suppressed, and film stress can be prevented from being applied to the multilayer film of the memory cell array included in the first semiconductor element 6 and being distorted. Thereby, the accuracy of patterning in the lithography process can be maintained.

[0022] As described above, in the manufacturing method of a semiconductor device, the following steps (a) to (e) are performed, and a semiconductor device can be easily manufactured while suppressing distortion of the first semiconductor element 6.

[0023] (a) Form an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus.

[0024] (b) Form the first semiconductor element having a first bonding surface on the insulating layer.

[0025] (c) Form the second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus.

[0026] (d) Bond the first bonding surface and the second bonding surface to form a laminate in which the first semiconductor element and the second semiconductor element are stacked.

[0027] (e) Remove the first substrate from the laminate.

[0028] [Removal of the First Substrate Using a Separation Layer] Next, the removal of the first substrate 1 in step (e) using the separation layer D and the subsequent steps will be explained with reference to Figures 2 and 3. Figure 2 is a cross-sectional view showing the method for manufacturing a semiconductor device, following Figure 1. Figure 3 is a cross-sectional view showing the method for manufacturing a semiconductor device, following Figure 2.

[0029] In the semiconductor device manufacturing method according to this embodiment, the first substrate 1 is removed using a separation layer D. The separation layer D according to this embodiment has a first separation layer 4 and a second separation layer 5. The first separation layer 4 and the second separation layer 5 are formed between the first substrate 1 and the first semiconductor element 6.

[0030] The first separation layer 4 is formed adjacent to the first semiconductor element 6. As shown in Figure 2(a), the light source 9 outputs laser light of a wavelength that meets the conditions described later, and the first separation layer 4 absorbs the laser light, thereby generating heat and thermally expanding. For example, the first separation layer 4 is made of polysilicon (Poly Si) or polysilicon germanium (Poly SiGe).

[0031] The second separation layer 5 is formed between the first separation layer 4 and the first substrate 1. For example, the second separation layer 5 is a silicon oxide film (SiO2) or a silicon nitride film (SiN). The second separation layer 5 functions as a buffer layer to prevent damage to the first substrate 1 from the strong stress that is applied to the first separation layer 4 when the first substrate 1 is peeled off.

[0032] The second separation layer 5 is not required, but it is preferable to provide it between the first substrate 1 and the first separation layer 4. The second separation layer 5 allows the first substrate 1 to be removed from the laminate without damage, making it easier to reuse the first substrate 1.

[0033] As shown in Figure 2(a), the laser light is irradiated from the first substrate 1 side. Therefore, the first substrate 1 and the second separation layer 5 are made of a material that transmits laser light. The first substrate 1 is made of, for example, SiC, sapphire, or diamond. Furthermore, the second separation layer 5 is preferably a silicon oxide film in order to sufficiently transmit laser light. As a result, the laser light output from the light source 9 can pass through the first substrate 1 and the second separation layer 5 and reach the first separation layer 4.

[0034] The laser light penetrates the first substrate 1 and the second separation layer 5, and is absorbed by the first separation layer 4. As a result, the difference in thermal expansion coefficients (stress difference) between the first separation layer 4 and the second separation layer 5 and the first substrate 1, as well as the increase in pressure within the first separation layer 4 due to heating, creates a force that separates the first semiconductor element 6 from the first substrate 1. The laser light is scanned and irradiated over the entire surface of the first separation layer 4. The first substrate 1 peels off sequentially from the areas of the first separation layer 4 that have been irradiated with the laser light.

[0035] In the example shown in Figure 2(b), the difference in thermal expansion coefficients between the first isolation layer 4, the second isolation layer 5, and the first substrate 1, as well as the increase in pressure within the first isolation layer 4 due to heating, causes the first isolation layer 4 to peel off, resulting in the state where it is separated into the first isolation layer 4a and 4b. As a result, the first substrate 1 is removed from the first semiconductor device 6. However, this is not the only possible outcome; the first isolation layer 4 may remain on the first semiconductor device 6 side, and the second isolation layer 5 may be removed together with the first substrate 1. Alternatively, a portion of the first isolation layer 4 and the second isolation layer 5 may remain on the first semiconductor device 6 side, and the remainder of the second isolation layer 5 may be removed together with the first substrate 1.

[0036] The laser light output from the light source 9 should have a wavelength that can penetrate the first substrate 1. For example, if the first substrate 1 is sapphire or diamond, light with a wavelength of 200 nm to 1500 nm can penetrate the first substrate 1. Therefore, if the first substrate 1 is sapphire or diamond, the wavelength of the laser light output from the light source 9 may be between 200 nm and 1500 nm. However, if the first substrate 1 is sapphire or diamond, it is more preferable that the wavelength of the irradiated laser light be between 300 nm and 400 nm.

[0037] The first separation layer 4 and the second separation layer 5 are made of materials that exhibit their respective functions depending on the material of the first substrate 1. When the first substrate 1 is sapphire or diamond and the wavelength of the laser light output from the light source 9 is 400 nm or less, the first separation layer 4 is preferably polysilicon. In this case, the first separation layer 4 can sufficiently absorb laser light with a wavelength of 400 nm or less. The second separation layer 5 is preferably a silicon oxide film, as described above.

[0038] When the first substrate 1 is SiC, light with a wavelength of 400 nm to 1500 nm can pass through the first substrate 1. Therefore, when the first substrate 1 is SiC, the wavelength of the laser light output from the light source 9 can be between 400 nm and 1500 nm. However, when the first substrate 1 is SiC, it is more preferable that the wavelength of the irradiated laser light be between 450 nm and 600 nm. Also, when the first substrate 1 is SiC, it is preferable that the first separation layer 4 is polysilicon germanium. In this case, the first separation layer 4 can sufficiently absorb laser light with a wavelength of 1500 nm or less. As mentioned above, it is preferable that the second separation layer 5 is a silicon oxide film.

[0039] Regardless of whether the first substrate 1 is sapphire, diamond, or SiC, it is important that the laser light is completely absorbed by the first isolation layer 4 and that the device structure, such as the memory cell array within the first semiconductor element 6, is not damaged. For this reason, the first isolation layer 4 is preferably 50 nm or thicker to completely absorb the laser light.

[0040] As shown in Figure 2(b) as an example, the first isolation layer 4 remains on at least one of the first substrate 1 side and the first semiconductor device 6 side. In the example in Figure 2(b), the first isolation layer 4 is divided into the first isolation layer 4a on the first substrate 1 side and the first isolation layer 4b on the first semiconductor device 6 side, remaining on both sides. The second isolation layer 5 may remain only on the first substrate 1 side, or it may remain on both the first substrate 1 side and the first semiconductor device 6 side.

[0041] Figure 3 is a cross-sectional view showing a method for manufacturing a semiconductor device, following Figure 2. The first isolation layer 4b remaining on the first semiconductor device 6 side as shown in Figure 3(a) may be removed by wet etching or CMP. If the second isolation layer 5 remains on the first semiconductor device 6 side, the second isolation layer 5 may be removed by wet etching using hydrofluoric acid. Note that the first isolation layer 4b on the first semiconductor device 6 side may be left as is, and the removal of the first isolation layer 4b can be omitted. Similarly, the second isolation layer 5 on the first semiconductor device 6 side may be left as is, and the removal of the second isolation layer 5 can be omitted.

[0042] After peeling off the first substrate 1, the first isolation layer 4b is removed from the laminate of the first semiconductor element 6 and the second semiconductor element 7 on the second substrate 2, as shown in Figure 3(b). In this state, a probing pad 8 is formed on the surface of the first semiconductor element 6, as shown in Figure 3(c). This completes the manufacturing of the semiconductor device, which is a laminate of the first semiconductor element 6 and the second semiconductor element 7 with the probing pad 8. The probing pad 8 enables electrical connection with external elements.

[0043] [Reuse of the first circuit board] Next, the reuse of the first substrate 1 will be explained with reference to Figure 4. Figure 4 is a cross-sectional view showing a method for reusing the first substrate 1 that has been peeled off from the first semiconductor element 6, as shown in Figure 2(b). The method for reusing the first substrate 1 shown in Figure 4 is one step in the manufacturing method of the semiconductor device according to this embodiment.

[0044] In Figure 2(b), the first substrate 1, which has been peeled off from the first semiconductor element 6, is cleaned. The second separation layer 5 can be removed by wet etching with hydrofluoric acid, without damaging the first substrate 1.

[0045] As shown in Figure 4(a), if the first separation layer 4a remains in addition to the second separation layer 5, the first separation layer 4a is removed by wet etching or CMP. This makes it possible to reuse the first substrate 1. If the first substrate 1 is damaged when removing the second separation layer 5 or the first separation layer 4a, the damaged surface of the first substrate 1 is planarized by grinding with CMP, making it possible to reuse the first substrate 1.

[0046] After cleaning the first substrate 1, a new insulating layer 3 is formed on the first substrate 1. Furthermore, steps (b) to (e) above are performed to manufacture a new semiconductor device. This allows the first substrate to be reused in the manufacture of a semiconductor device.

[0047] [Example of a memory cell array and peripheral circuit] An example of the internal structure of a stack of first semiconductor element 6 and second semiconductor element 7 manufactured by the semiconductor device manufacturing method according to this embodiment will be described with reference to Figure 5. Figure 5 shows the stack shown in Figure 1(c) inverted, with the first semiconductor element 6 on the bottom and the second semiconductor element 7 on the top.

[0048] Figure 5 is an enlarged cross-sectional view of the periphery of the columnar portion BL of the memory cell array 11 of the first semiconductor element 6, and a part of the CMOS circuit and its surrounding structure of the peripheral circuit 50 of the second semiconductor element 7. Note that the memory cell array 11 in Figure 5 mainly shows the stepped structure portion 21.

[0049] As shown in Figure 5, a second isolation layer 5, a first isolation layer 4, and an insulating layer 3 are stacked on the first substrate 1 in that order, and a memory cell array 11 containing multiple memory cells is formed on the insulating layer 3. A conductive common-source line CSL is formed between the insulating layers 3, and the columnar portion BL of the memory cell array 11 is connected to the common-source line CSL.

[0050] The memory cell array 11 includes a plurality of conductive layers (word lines WL) and a plurality of insulating layers stacked in the Z direction (perpendicular to the first junction surface 6a). The plurality of conductive layers are provided as a plurality of word lines WL. The plurality of insulating layers are provided between a plurality of adjacent word lines WL in the Z direction, electrically insulating the plurality of word lines WL from each other. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. The word lines WL include, for example, a conductive material such as tungsten. The plurality of insulating layers include, for example, an insulating film such as a silicon oxide film.

[0051] A selection gate SG is provided on the laminate of the word wire WL and the insulating layer. The selection gate SG is electrically connected to the selection gate wiring layer 27 via a contact plug 26. The selection gate SG also contains a conductive material, such as tungsten. An interlayer insulating film 15 is provided on the selection gate SG. Furthermore, a wiring layer 24, a contact plug 25, and a metal pad 28 are formed within or on the interlayer insulating film 15. An interlayer insulating film 16 is provided between the uppermost metal pads 28.

[0052] The columnar section BL penetrates the word line WL and the selection gate SG and is electrically connected to the bit line AL. The columnar section BL comprises a memory insulating film, a channel semiconductor layer, and a core insulating film extending in the Z direction. The memory insulating film includes a block insulating film, a charge storage layer, and a tunnel insulating film.

[0053] By making the selection gate SG conductive, the columnar portion BL is selectively connected to the bit line AL and receives a voltage from the bit line AL. In this selected columnar portion BL, charge is injected / released between the channel semiconductor layer and the charge storage layer via a tunnel insulating film. This writes or erases data. The block insulating film is provided to block the leakage of charge from the charge storage layer to the word line WL. The configuration at the intersection of the word line WL and the memory insulating film forms a memory cell. A memory cell array 11 having such a configuration and function is formed on the first substrate 1.

[0054] A memory cell array 11 is formed on a first substrate 1, such as SiC, which is used as a support substrate. In other words, the memory cell array 11 is supported on the first substrate 1, which has a higher elastic modulus than the second substrate 2. As a result, the first substrate 1 is harder and less prone to warping than the second substrate 2, such as Si, and the memory cell array 11 can be supported on the surface of the first substrate 1 and maintain a substantially flat state.

[0055] In this state, the first semiconductor element 6 is oriented toward the first surface F41 of the second substrate 2 and the second semiconductor element 7 is oriented toward the second surface F12 of the first substrate 1 so as to connect the memory cell array 11 to the peripheral circuit 50. In Figure 5, the first junction surface 6a of the first semiconductor element 6 and the second junction surface 7a of the second semiconductor element 7 are shown in a non-contact state, but from this state, the first junction surface 6a of the first semiconductor element 6 and the second junction surface 7a of the second semiconductor element 7 are bonded together. As a result, the metal pad 28 on the first semiconductor element 6 side and the metal pad 37 on the second semiconductor element 7 side come into contact. The metal pads 28 and 37 include, for example, conductive materials such as copper and tungsten. An interlayer insulating film 35 is provided between the metal pads 37.

[0056] The peripheral circuitry 50 includes, for example, a CMOS circuit (logic circuit) that constitutes a controller for the memory cell array 11. The second semiconductor element 7 in Figure 5 is a cross-sectional view showing a part of the peripheral circuitry 50, including the CMOS circuitry, and the structure of its surroundings. A plurality of transistors 31 are provided on the first surface F41 of the second substrate 2. Each transistor 31 comprises a gate electrode 32 provided on the first surface F41 of the second substrate 2 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the second substrate 2. The plurality of transistors 31 constitute a CMOS circuitry and function to control the memory cell array 11.

[0057] Furthermore, an interlayer insulating film 34 is provided on the CMOS circuit, a plurality of plugs 33 are provided on the source diffusion layer or drain diffusion layer of the transistor 31, and a multilayer wiring structure 36 is provided on the plugs 33. In addition, a contact plug 38 is provided on the multilayer wiring structure 36, and a metal pad 37 is connected to the contact plug 38. A peripheral circuit 50 having such a configuration is formed on the first surface F41 of the second substrate 2.

[0058] In this way, the first semiconductor element 6 having the memory cell array 11 and the second semiconductor element 7 having the peripheral circuit 50 are bonded together so that the first junction surface 6a and the second junction surface 7a are joined. As shown in Figures 1(c) and 5, the memory cell array 11 and the peripheral circuit 50 are stacked in the Z direction between the first substrate 1 and the second substrate 2.

[0059] As a result, the metal pad 28 exposed on the first bonding surface 6a and the metal pad 37 exposed on the second bonding surface 7a come into contact with each other and are electrically connected. This makes it possible to control the memory cell array 11. In this way, when the peripheral circuit 50 and the memory cell array 11 are facing each other, the metal pads 28 and 37 are arranged to correspond to each other.

[0060] Furthermore, contact line DL, connected to the common source line CSL, passes through the word line WL and the selection gate SG, and is connected to contact line CL. The junction between the first junction surface 6a and the second junction surface 7a connects contact line CL to contact line EL, which is connected to the CMOS circuit. As a result, the multilayer wiring structure 36 of the second semiconductor element 7 is electrically connected to the common source line CSL.

[0061] As described above, according to the semiconductor device manufacturing method of this embodiment, a first semiconductor element 6 having a memory cell array 11 is fabricated on a first substrate 1 having a first elastic modulus, such as a SiC substrate. A second semiconductor element 7 having peripheral circuits 50 is fabricated on a second substrate 2 having a second elastic modulus, such as a Si substrate.

[0062] Then, the first semiconductor element 6 and the second semiconductor element 7 are bonded together, and the memory cell array 11 and the peripheral circuit 50 are electrically connected with the first semiconductor element 6 and the second semiconductor element 7 stacked together.

[0063] The first substrate 1, which has a first elastic modulus, is formed from a material with a higher elastic modulus than the second substrate 2, which has a second elastic modulus. For example, the first substrate 1 is formed from SiC, and the second substrate 2 is formed from Si. Therefore, the multilayer film included in the memory cell array 11 on the first substrate 1 is less prone to distortion compared to when the memory cell array 11 is formed on the second substrate 2. As a result, the memory cell array 11 can be supported on the surface of the first substrate 1 and maintain a substantially flat state. Consequently, a semiconductor device stack can be easily manufactured while suppressing distortion of the memory cell array 11.

[0064] Furthermore, fabricating the peripheral circuit 50 on a SiC substrate is difficult because it leads to a decrease in yield. Therefore, in the semiconductor device manufacturing method according to this embodiment, a first semiconductor element 6 having a memory cell array 11 is fabricated on a first substrate 1, and the first semiconductor element 6 and the second semiconductor element 7 are stacked using bonding technology. Accordingly, according to the semiconductor device manufacturing method of this embodiment, the memory cell array 11 can be formed on the first substrate 1 which is made of a material with a higher elastic modulus than the second substrate 2, and the peripheral circuit 50 can be formed on the second substrate 2. This makes it possible to avoid a decrease in yield caused by forming the peripheral circuit 50 on the first substrate 1 which has a higher elastic modulus than the second substrate 2.

[0065] Furthermore, after stacking the first semiconductor element 6 and the second semiconductor element 7, the first substrate 1 is peeled off from the first semiconductor element 6. After cleaning the peeled first substrate 1, a new insulating layer is formed on the first substrate 1 and it can be used to manufacture a new semiconductor device. This allows the first substrate 1 to be reused, thereby reducing manufacturing costs.

[0066] The methods for manufacturing semiconductor devices according to the embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The embodiments can be modified and improved in various ways without departing from the scope and spirit of the appended claims. The matters described in the above embodiments can be otherwise configured and combined in a non-consistent manner.

[0067] This application claims priority to Basic Application No. 2021-167235, filed with the Japan Patent Office on 12 October 2021, the entire contents of which are incorporated herein by reference. [Explanation of Symbols]

[0068] 1. First circuit board 2. Second board 3. Insulating layer 4 1st separation layer 5 Second separation layer 6. First Semiconductor Element 6a 1st bonding surface 7. Second semiconductor element 7a Second bonding surface 11 memory cell array 50 Peripheral Circuits D separation layer

Claims

1. A process of irradiating a laminate, which is formed by bonding a first semiconductor element formed on a first substrate via a first separation layer containing a polycrystalline material and a second semiconductor element formed on a second substrate, with laser light, A step in which the first separation layer absorbs the irradiated laser light, The step includes separating the first substrate from the laminate, The laminate has a second separation layer between the first separation layer and the first substrate. A method for manufacturing a semiconductor device.

2. The first substrate is separated from the laminate by the first separation layer absorbing the irradiated laser light and undergoing thermal expansion. A method for manufacturing a semiconductor device according to claim 1.

3. The first separation layer is a polycrystalline material containing silicon. A method for manufacturing a semiconductor device according to claim 1.

4. The second separation layer functions as a buffer layer against the stress applied to the first separation layer. A method for manufacturing a semiconductor device according to claim 1.

5. The second separation layer is a silicon oxide film (SiO ２ ) or silicon nitride film (SiN) A method for manufacturing a semiconductor device according to claim 1.

6. The process includes removing the first separation layer or the second separation layer from the first substrate separated from the laminate, A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

7. The process includes removing the first separation layer or the second separation layer from the first substrate, and then forming a new first separation layer or second separation layer on the first substrate to reuse the first substrate. The method for manufacturing a semiconductor device according to claim 6.

8. The process includes removing the first separation layer or the second separation layer from the first substrate, and then planarizing the first substrate. The method for manufacturing a semiconductor device according to claim 6.

9. The laminate has an insulating layer between the first separation layer and the first semiconductor element. A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

10. The first substrate has a first modulus of elasticity, and the second substrate has a second modulus of elasticity. The first modulus of elasticity is higher than the second modulus of elasticity. A method for manufacturing a semiconductor device according to claim 1.

11. The first semiconductor device includes a memory cell array, The second semiconductor element includes peripheral circuits. A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

12. A method for manufacturing a semiconductor device including a first semiconductor device and a second semiconductor device, A step of forming a first separation layer containing a polycrystalline material on a first substrate, A step of forming the first semiconductor element having a first junction surface on the first separation layer, A step of forming the second semiconductor element having a second bonding surface on a second substrate, A step of bonding the first bonding surface and the second bonding surface to form a laminate in which the first semiconductor element and the second semiconductor element are stacked, The process includes removing the first substrate from the laminate by irradiating the laminate with laser light, The laminate has a second separation layer between the first separation layer and the first substrate. A method for manufacturing a semiconductor device.

13. A process of irradiating a laminate, which is formed by bonding a first substrate, a first separation layer, a second separation layer, a semiconductor element, and a second substrate together, with laser light, A step in which the first separation layer absorbs the irradiated laser light, The step includes separating the first substrate from the laminate, The second separation layer is disposed between the first separation layer and the first substrate. A method for manufacturing a semiconductor device.

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