Recording device

Abstract

This provides an auxiliary circuit for serial transmission and reception that stably receives signals from the received data line. [Solution] In the master device 101, the user circuit 301 operates with the system clock CLK and communicates with an external slave device via the synchronous serial bus transmit / receive circuit 302. The received data delay circuit 303 further delays the received data synchronized by the synchronization circuit 304 in units of the system clock using a shift register, and outputs one of the signals of the shift register via the selector 308 based on RXSEL specified by the user circuit. The synchronization circuit 304 synchronizes the received data RX input from outside the master device with the system clock. The synchronous serial bus transmit / receive circuit 302 serializes TXpara using the serialization circuit 305, synchronizes it with the transfer clock, and outputs the signal RXd received with the transfer clock by deserializing it using the deserialization circuit 306.

Description

Technical Field

[0001] The present invention relates to a transmission / reception circuit for a synchronous serial bus. In particular, it relates to a data reception circuit in which a slave device transmits data synchronized with a clock output from a master device.

Background Art

[0002] Synchronous serial buses are widely used as communication interfaces between a control circuit as a master device and peripheral ICs as slave devices. Generally, in a full-duplex synchronous serial bus, it is connected using three lines: a transfer clock line, a transmission data line, and a reception data line. Transmission data is transmitted synchronized with the transfer clock output from the master slave, and the slave device outputs reception data synchronized with the transmission clock. The master device receives the reception data output by the slave device synchronized with the transfer clock.

[0003] Particularly in the case of use in large devices such as in large printers devices, the communication interface may have an increasing number of slave devices to be connected and the connecting cables may be long. In such a case, the slave device drives the signal on the reception data line synchronized with the transmission clock, but there is a large delay when the master device receives it. As a result, in the master device, there arises a problem that the value of the reception data signal is acquired at a timing when the data is not stable near the change point (edge) of the transmission clock, and the correct value cannot be obtained. To avoid the problem, countermeasures such as shortening the transmission path and lowering the transfer clock frequency can be considered.

[0004] As a method for dealing with such data reception timing issues, Patent Document 1 describes adjusting the timing by operating counters on both the transfer clock and an internal clock with a higher frequency than the transfer clock, and receiving data when the two counters reach predetermined values. This method in Patent Document 1 allows for stable data reception in synchronous serial bus transfers without compromising the transfer bit rate associated with the transfer clock frequency. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2005-354353 [Overview of the project] [Problems that the invention aims to solve]

[0006] In the method described in Patent Document 1 above, the timing at which the received data is determined by the adjusted counter value is out of sync with the transfer clock, so the timing at which the data can be used in the master device's internal circuitry also needs to be adjusted. Furthermore, it becomes impossible to directly use IP provided by vendors that do not have the functionality of such a method.

[0007] The object of the present invention is to provide an auxiliary serial transmission circuit that can stably receive signals on the received data line without modifying the basic synchronous serial transmission circuit. [Means for solving the problem]

[0008] To achieve the above objective, the present invention provides a clock-synchronous serial signal transmission and reception circuit, characterized by comprising: an internal operating clock of an integrated circuit; a clock generation circuit that generates a transfer clock by dividing the internal operating clock; a receiving signal shift register circuit that performs shift register operation of a serial received signal with the internal operating clock; a receiving signal selector circuit that selects an arbitrary signal from the receiving signal shift register circuit; and a circuit that uses the signal output by the receiving signal selector circuit to acquire received data with the transfer clock. [Effects of the Invention]

[0009] According to the present invention, by delaying the received data with a clock faster than the transfer clock and selecting the delay amount according to the wiring length, the received data can be stably acquired in a synchronous serial transceiver circuit. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows the configuration of a synchronous serial bus according to an embodiment. [Figure 2] This diagram illustrates the internal configuration of the master device according to the embodiment. [Figure 3] This diagram illustrates the constraints on the received data line according to the embodiment. [Figure 4] This is a timing chart of the receiving data circuit according to the embodiment. [Figure 5] This diagram shows a configuration that includes a circuit for measuring the temporal positional relationship between the transfer clock and the received data, and generates a signal selected from that positional relationship. [Modes for carrying out the invention]

[0011] [Mode 1 for carrying out the invention] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the following embodiments are not intended to limit the scope of the present invention as defined in the claims, and not all combinations of features described in these embodiments are necessarily essential to the solution of the present invention.

[0012] Figure 1 shows the configuration of a communication system using a synchronous serial bus in Embodiment 1 of the present invention. The master device 101 has a port that outputs a transfer clock SCLK and transmit data TX, and a port that inputs received data RX output by the slave device 102. The slave device 102 has an SCLK port and a DI port that input the transfer clock SCLK and transmit data TX output by the master device 101, and a DO port that outputs data to the master device 101. The respective ports are connected to form a communication interface. When connecting multiple slave devices to a single master device, it is also possible to configure the system using a chip select signal (not shown).

[0013] Here, the constraints on the timing of receiving data RX will be explained using Figure 2. This type of synchronous serial communication has the advantage of being able to communicate at a faster speed than asynchronous serial communication, which does not use a transfer clock, because the data transmission and reception timing can be defined by a single transfer clock. In synchronous serial communication, generally, the slave device 102 outputs received data in synchronization with the transfer clock, and the master device 101 takes in the received data RX into its internal circuit at the timing of the rising edge of the transfer clock. At this time, the received data RX needs to be stable. A setup time Ts and a hold time Th are defined for each device relative to the rising edge of the transfer clock, and if the received data changes during this period, the data cannot be acquired correctly. However, depending on the installation location of the master device 101 and the slave device 102, and depending on the length of the connecting wires, the point at which the received data RX of the master device 101 changes may fall just around the rising edge of the transfer clock SCLK.

[0014] This means that the propagation speed V of an electrical signal through a signal trace can generally be expressed as V = C ÷ √ε, where C is the speed of light and ε is the relative permittivity of the substrate. Depending on the material near the trace path, a delay of approximately 6 nsec occurs per meter. For example, if synchronous serial communication is operated with a transfer clock SCLK frequency of 10 MHz (100 nsec / cycle) and the trace length between the master device 101 and the slave device 102 is 8 m, then the delay time for the transfer clock SCLK to reach the slave device 102 and the time for the received data RX, which is output synchronously with the transfer clock SCLK, to reach the master device 101 will be added together, resulting in a total trace length of 16 m round trip, and a delay of approximately 100 nsec. As a result, the change point of the received data RX may occur near the rising edge of the transfer clock SCLK.

[0015] Figure 3 is a diagram illustrating the internal configuration of the master device 101 according to this embodiment 1.

[0016] User circuit 301 operates with the system clock CLK and controls communication with an external slave device 102 via a synchronous serial bus transceiver circuit 302. TXpara is the data transmitted from user circuit 301 to slave device 102, and RXpara is the data received from slave device 102.

[0017] The synchronization circuit 304 synchronizes the received data RX, which is input from outside the master device 101, with the system clock CLK.

[0018] The received data delay circuit 303 delays the received data synchronized with the system clock CLK by the synchronization circuit 304 further by one system clock CLK unit using the shift register RXsff. The received data delay circuit 303 outputs one of the signals of the shift register RXsff as the RXdly signal via the selector 308 based on the value of RXSEL specified from the user circuit 301. The value of the RXSEL signal is determined in advance by calculating from the wiring length and measuring the delay amount of the received data RX by waveform confirmation, and the CPU or the like sets the value of RXSEL.

[0019] The synchronous serial bus transceiver circuit 302 serializes TXpara using the serializer circuit 305, synchronizes it with the transfer clock SCLK, and outputs it. Also, the synchronous serial bus transceiver circuit 302 deserializes the signal RXd received with the transfer clock SCLK using the deserialization circuit 306 and outputs it to the user circuit 301. The synchronous serial bus transceiver circuit 302 includes a clock divider 307, and the clock divider 307 divides the serial clock CLK by 8 to generate the transfer clock SCLK. Here, in the master device 101 of the first embodiment, the system clock CLK is 80 MHz and the transfer clock SCLK is 10 MHz. In a synchronous serial bus, generally, the internal operation clock of a device operates faster than the transfer clock of the synchronous serial bus.

[0020] FIG. 4 is a diagram showing the timing chart of the synchronous serial bus of the master device 101 according to the first embodiment. The horizontal axis represents time.

[0021] The transmitted data TX shows the state of being output in synchronization with the transfer clock SCLK. In the synchronous serial bus of the first embodiment, regarding data transfer, the serialization circuit 305 outputs a value that is always 0 so that the first bit of a predetermined transfer unit (for example, 8 bits) can be easily distinguished as the start bit. After the start bit, it shows that 0 or 1 is output depending on TXpara received from the user circuit 301. RX in FIG. 4 shows the state when the data output in synchronization with the transfer SCLK received by the slave device 102 reaches the reception port RX of the master device 101. Due to the delay depending on the wiring lengths of the master device 101 and the slave device 102, it shows that RX changes near the transfer clock SCLK. If the synchronous serial bus transceiver circuit 302 directly receives this RX, there is a high possibility that RXd cannot be correctly received.

[0022] In the master device 101 of the first embodiment, after being synchronized with the system clock by the synchronization circuit 304, it shows the state of being delayed by the received data delay circuit 303 in synchronization with the system clock. Further, in the received data delay circuit 303, an RXdly signal is output based on RXSEL specified by the user circuit 301, and the value of the signal RXdly is stable at the rising timing of the transfer clock SCLK. The synchronous serial bus transceiver circuit 302 of the first embodiment shows the state of receiving this stable signal RXdly at the timing of the transfer clock SCLK.

[0023] As described above, according to the first embodiment, by delaying the received data with a clock faster than the transfer clock and selecting according to the delay amount depending on the wiring length, the received data can be stably acquired in the synchronous serial transceiver circuit.

[0024] [Mode for Carrying Out the Invention 2] In Embodiment 1, the selection of which signal to use from the delayed received data RXsff was specified by the RXSEL signal from the user circuit 301. However, a configuration is also conceivable in which there is a circuit that measures the temporal positional relationship between the transfer clock SCLK and the received data RX, and generates a signal to be selected based on that positional relationship.

[0025] Figure 5 shows such a configuration. Note that the explanation here is almost the same as that in Figure 3 of Embodiment 1 described above, so only the differences will be explained below. In the master device 101 in Embodiment 2, a selection signal generation circuit 501 is configured to generate a received data delay signal selection signal RXSEL. The selection signal generation circuit 501 operates as a shift register with respect to the transfer clock CLK using a shift register CKsff. While the shift register RXsff represented the delay circuit for received data RX, the shift register CKsff represents a past state in time of the transfer clock SCLK.

[0026] The received signal change point detection circuit 503 uses the shift register RXsff signal to detect the falling or rising edge of the RX signal. Furthermore, the selection signal generation circuit 501 stores the value of the shift register CKsff in the CKcap register at the timing detected by the received signal change point detection circuit 503. This means that at the change point of the received data RX, it is possible to check what the transfer clock SCLK was in the past 8 cycles in units of the system clock CLK.

[0027] Furthermore, the shifted registered CKsff of the transfer clock SCLK acquired within the master device 101 operates consistently because it is internal to the master device 101. Therefore, the value of the CKcap register, which is the value of the transfer clock SCLK for the past 8 cycles, is equivalent to indicating the value of the transfer clock SCLK for the subsequent period. In other words, it is possible to measure the state of the transfer clock SCLK before and after the change point of the received data RX in terms of time.

[0028] The selection signal generation circuit 502 determines, based on the value of the CKcap register, how many cycles the received data RX should be delayed to move it away from the change point of the transfer clock SCLK, and then determines and outputs the selection signal RXsel.

[0029] Here, the temporal positional relationship between the transfer clock SCLK and the received data RX was calculated from the value CKsff obtained by shifting the transfer clock SCLK in the register and the change point of the received data RX. However, the temporal positional relationship between the transfer clock SCLK and the received data RX may also be calculated from the change point of the transfer clock and the value RXsff obtained by shifting the received data RX in the register. Furthermore, in this embodiment 2, a circuit was used to generate the selection signal RXsel from the CKcap register value. However, the CPU may read the value of the CKcap register via the user circuit 301 and set the value of the selection signal RXsel based on the read value of CKcap, as in embodiment 1.

[0030] As described above, according to this embodiment 2, in addition to the effects of the embodiment 1 described above, it is not necessary to calculate the delay amount of the received data RX for each wiring length or to determine the delay amount by waveform confirmation. [Explanation of symbols]

[0031] 101 Master Device 102 Slave Devices 302 Synchronous Serial Bus Transceiver Circuit 303 Received signal delay circuit 304 Received signal synchronization circuit 305 Serialization Circuit 306 Deserialization Circuit 307 Clock frequency divider 308 Selector Circuit

Claims

1. A clock-synchronous serial signal transmission and reception circuit, A clock-synchronous serial signal transceiver circuit characterized by comprising: an internal operating clock of an integrated circuit; a clock generation circuit that generates a transfer clock by dividing the internal operating clock; a receive signal shift register circuit that operates a shift register with the internal operating clock for serial received signals; a receive signal selector circuit that selects an arbitrary signal from the receive signal shift register circuit; and a circuit that uses the signal output by the receive signal selector circuit to acquire received data with the transfer clock.

2. The receiving signal selector circuit further includes a transfer clock shift register circuit that operates the transfer clock using an internal operating clock. The clock-synchronous serial signal transceiver circuit according to claim 1, characterized in that it selects the received signal based on the signal output of the received signal shift register circuit and the signal output of the transfer clock shift register circuit, such that the change point of the received signal moves away from the edge of the transfer clock.

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