Alignment method

Abstract

This invention provides a method for accurately aligning a good chip located at an arbitrarily specified position among multiple chips formed and arranged on a wafer. [Solution] A positioning method for aligning a target chip CT, arbitrarily selected from a plurality of chips C formed and arranged on a substrate W, with a recognition means 22 for the chip C, comprising: a movement process (S1, S4) in which the recognition means 22 and the substrate W are moved relative to each other so that the pattern formed on the substrate W is within the field of view of the recognition means 22; and a correction process (S2, S3, S5, S6) in which the recognition means 22 recognizes the pattern and corrects the misalignment between the recognition means 22 and the pattern, wherein the movement process (S1, S4) and the correction process (S2, S3, S5, S6) are repeated in this order with respect to the target chip CT until the movement process (S1, S4) and the correction process (S2, S3, S5, S6) of the recognition means 22 are completed.

Description

Technical Field

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[0001] The present invention relates to a pickup method for picking up chips in order from a target chip arbitrarily specified from a plurality of chips formed and arranged on a wafer.

Background Art

[0002] Semiconductor devices are manufactured through two processes generally classified as a front process and a back process. The front process is a process of forming circuit patterns arranged in a matrix on a wafer. The back process is a process of dicing the circuit patterns formed on the wafer into individual pieces called chips, bonding the chips onto a package substrate, and performing wiring and packaging.

[0003] In bonding, it is necessary to mount only good chips on the package substrate. Generally, only good chips are picked up and mounted on the package substrate based on map data in which the position information of each chip is linked and recorded together with the result of the pass / fail determination of the electrical characteristic inspection.

[0004] Patent Document 1 discloses a method of correcting the position of a wafer set on a wafer table by referring to the alignment mark of the wafer and starting pickup based on the map data if the positional deviation amount between the wafer ID and the map data is less than a predetermined value.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] When using the method described in Patent Document 1, there is a risk of mistakenly picking up a chip other than the one that should be mounted, due to the miniaturization of chip sizes in recent years, positioning errors in mounting equipment, and machining errors in the chips. In this case, the mistakenly picked-up chip may be defective, which would have a significant impact on the quality and reliability of the product.

[0007] Therefore, in view of the aforementioned problems, the present invention aims to provide a method for accurately aligning a good chip located at an arbitrarily specified position among a plurality of chips formed and arranged on a wafer. [Means for solving the problem]

[0008] To solve the aforementioned problems, the present invention provides a positioning method for aligning a target chip, arbitrarily selected from a plurality of chips formed and arranged on a substrate, with a recognition means for the chip, comprising: a movement process in which the recognition means and the substrate are moved relative to each other so that the pattern formed on the substrate is within the field of view of the recognition means for recognizing the pattern; and a correction process in which the recognition means recognizes the pattern and corrects any misalignment between the recognition means and the pattern, wherein the movement process and the correction process are repeated in this order until the movement process and the correction process of the recognition means are completed for the target chip.

[0009] According to the alignment method of the present invention, the recognition means can be moved to the target chip by repeatedly checking its position each time through the movement process and correction process, while following chips in relatively close positions. This prevents the accidental pickup of a chip other than the one that should be mounted.

[0010] Furthermore, in the alignment method of the present invention, it is preferable that the distance traveled when the recognition means and the package substrate are moved relative to each other during the movement process is equal to the distance between the patterns calculated from the pattern design information.

[0011] Furthermore, the alignment method of the present invention is characterized in that the first movement process involves moving the recognition means and the substrate relative to each other so that a reference mark provided on the substrate comes within the field of view of the recognition means, and the first correction process involves recognizing the reference mark with the recognition means and correcting the misalignment between the recognition means and the reference mark.

[0012] According to the alignment method of the present invention, by using a reference mark on the substrate for the initial movement process and correction process, the initial alignment of the recognition means can be performed more accurately.

[0013] Furthermore, the alignment method of the present invention is characterized in that the pattern is a common pattern provided for each chip.

[0014] According to the alignment method of the present invention, since the movement process and correction process are repeated using a common pattern provided for each chip, accurate alignment is possible without making special marks on the substrate.

[0015] Furthermore, the alignment method of the present invention is characterized in that, if the recognition means and the substrate move relative to each other during the movement process and the destination is a missing area where the chip does not exist, the recognition means and the substrate are moved relative to each other so that the pattern of an adjacent chip adjacent to the missing area comes within the field of view of the recognition means, the recognition means recognizes the pattern of the adjacent chip, and an adjacent chip search process is performed to correct the positional misalignment between the recognition means and the pattern of the adjacent chip.

[0016] According to the alignment method of the present invention, even if there is no chip at the destination of the recognition means, movement and correction can be resumed from an adjacent chip, thus preventing the device from stopping due to an abnormality. [Effects of the Invention]

[0017] It is possible to accurately align a good chip located at an arbitrarily specified position among multiple chips formed and arranged on a wafer.

Brief Description of Drawings

[0018] [Figure 1] It is a perspective view showing a schematic configuration of an implementation device according to this embodiment. [Figure 2] It is a flowchart showing a series of operations of this embodiment. [Figure 3] It is a plan view showing a schematic of a wafer. [Figure 4] It is a diagram for explaining Step 1 of the alignment method of this embodiment. [Figure 5] It is a diagram for explaining Step 2 of the alignment method of this embodiment. [Figure 6] It is a diagram for explaining Step 3 of the alignment method of this embodiment. [Figure 7] It is a diagram for explaining Step 4 of the alignment method of this embodiment. [Figure 8] It is a diagram for explaining Step 6 of the alignment method of this embodiment. [Figure 9] It is a diagram for explaining the state of moving to the target chip by the alignment method of this embodiment. [Figure 10] It is a diagram for explaining Step 9 of the alignment method of this embodiment. [Figure 11] It is a diagram for explaining a modification example of this embodiment. [Figure 12] It is a diagram for explaining a modification example of this embodiment.

Modes for Carrying Out the Invention

[0019] Hereinafter, the alignment method of the present invention will be described based on the drawings.

[0020] FIG. 1 is a perspective view showing a schematic configuration of an implementation device in which the alignment method according to the embodiment of the present invention is used.

[0021] As shown in Figure 1, the mounting apparatus 1 consists of a pickup stage 10, a pickup mechanism 20, a chip slider 30, a bonding head 40, a holding stage 50, and a control unit (not shown). The mounting apparatus 1 sequentially picks up chips C from the wafer W (substrate in this invention) placed on the pickup stage 10 using the pickup mechanism 20, passes them to the bonding head 40 via the chip slider 30, and finally heat-presses them onto the package substrate S, repeating this process to mount the chips C onto the package substrate S.

[0022] The pickup stage 10 holds the wafer W, which has been transported by a wafer transport mechanism (not shown), by suction. The wafer W is in the form of chips C, which have been divided into individual pieces by dicing and expanding processes and arranged in a matrix, and are held in place by adhesion on a dicing tape.

[0023] The pickup mechanism 20 picks up the chip C placed on the pickup stage 10 and consists of a pickup nozzle 21, a chip recognition camera 22, and a drive mechanism. The pickup nozzle 21 is capable of adsorbing and holding the chip, and has an adsorption surface facing downwards (in the -Z direction in the figure). The chip recognition camera 22 (recognition means in this invention) is capable of acquiring imaging data of the chip C necessary for aligning the pickup nozzle 21 and is mounted facing downwards (in the -Z direction in the figure). The drive mechanism is movable in the in-plane direction (XY direction in the figure) and vertical direction (Z direction in the figure) of the wafer W, and the pickup nozzle 21 and chip recognition camera 22 are mounted on it. This allows the pickup nozzle 21 and chip recognition camera 22 to move to any position above the wafer W. Furthermore, the relative positions of the pickup nozzle 21 and the chip recognition camera 22 remain constant. After the chip recognition camera 22 recognizes any chip C, the pickup nozzle 21 and the chip recognition camera 22 move by the amount of their relative positions, so that the pickup nozzle 21 is positioned on the aforementioned chip C and can pick up that chip C.

[0024] The chip slider 30 receives the chip C held by the pickup mechanism 20 and passes it to the bonding head 40, which will be described later. It consists of a suction plate and a drive mechanism. The suction plate is capable of holding the chip C by suction, and its suction surface is provided facing upward (in the +Z direction in the figure). The drive mechanism is movable in the X direction in the figure and has the suction plate attached to it.

[0025] The bonding head 40 heats and presses the chip C onto the package substrate S, which is held by adsorption on the holding stage 50.

[0026] Next, the method for positioning a chip C to any chip C during pickup by the aforementioned pickup mechanism 20 will be explained following the flowchart in Figure 2.

[0027] In this embodiment, a positioning method is described for the purpose of picking up the target chip CT shown in Figure 3. The wafer W is provided with a notch N (reference mark in this embodiment), which is a cutout that facilitates the determination and alignment of the crystal orientation of the wafer W. The position information of the chip C is input to the control unit in advance, and the pickup mechanism 20 is moved based on that position information.

[0028] First, the chip recognition camera 22 is moved to notch N as shown in Figure 4 during the starting position movement (S1). Initially, the chip recognition camera 22 is located at the standby position P0. From the standby position P0, the chip recognition camera 22 is moved in the XY direction by the difference between P1 and P0 (X1-X0, Y1-Y0) toward the position P1 of notch N. However, due to various errors, the chip recognition camera 22 cannot move to the position P1 of notch N and instead moves to P1' (X1', Y1').

[0029] Therefore, the next step is pattern recognition (S2), and the chip recognition camera 22 is used to align the notch N based on its shape. If the alignment is accurate, the chip recognition camera 22 will obtain image data with the notch N in the center of the field of view, as shown in Figure 5(a). However, in reality, positional misalignment occurs due to various errors, so image data with the notch N outside the center of the field of view, as shown in Figure 5(b), is obtained. To correct the aforementioned positional misalignment, the control unit performs calculation processing to calculate a correction value to correct the positional misalignment from the image data in Figure 5(b) obtained by the chip recognition camera 22 and the design information stored in the control unit.

[0030] Next, the position of the chip recognition camera 22 (S3) is corrected based on the correction values ​​obtained in pattern recognition (S2). As shown in Figure 6, the chip recognition camera 22 is moved in the XY direction by the difference between P1 and P1' (X1-X1', Y1-Y1') from the position of P1' where the notch N is located, towards P1 where the notch N is located. This completes the alignment to the starting position, notch N.

[0031] After the chip recognition camera 22 has aligned with notch N, the chip recognition camera 22 is moved to position on chip C (S4), followed by pattern recognition (S5) and position correction (S6). Here, the next target chip C must be selected to be close to notch N in order to minimize errors that occur during movement. If a chip C far from notch N is selected as the target, the errors that occur during movement may become large, potentially causing the camera to move to a different chip C than intended. In this embodiment, the operation will be explained using the example of aligning to chip C at position P2 shown in Figure 7.

[0032] First, the chip recognition camera 22 is moved to chip C, which is located at position P2 as shown in Figure 7, during chip position movement (S4). As shown in Figure 7, the chip recognition camera 22 moves toward P2 by the difference between P1 and P2 (X2-X1, Y2-Y1) based on the design information, but as with the starting position movement (S1), due to various errors, it actually moves to position P2', which is slightly off from P2.

[0033] Next, pattern recognition (S5) is performed, but the operation changes depending on whether or not there is a chip C at position P2. First, let's explain the case where there is a chip C at position P2. If there is a chip C at position P2, pattern recognition is performed in the same way as the pattern recognition (S2) performed on the notch N. In this embodiment, a part of the circuit pattern on the chip C, which is a pattern formed in common on all chip Cs, is registered as a mark for the control unit to recognize the chip C. This circuit pattern is captured by the chip recognition camera 22, and the control unit performs a calculation process to correct the positional deviation from the obtained image data and design information.

[0034] Subsequently, the position of the chip recognition camera 22 is corrected (S6) based on the correction values ​​obtained in pattern recognition (S5). As shown in Figure 8, the chip recognition camera 22 is moved toward P2 by the difference between P2 and P2' (X2-X2', Y2-Y2') in the XY direction, and alignment with the chip C located at P2 is completed.

[0035] From this point onward, the aforementioned chip position movement (S4) to position correction (S6) is repeated until the target chip CT is reached. Subsequent chip position movement (S4) is performed based on the pitch of chip C input to the control unit. As shown in Figure 9, by selecting a nearby chip C as the next destination to minimize errors that occur during movement, it is possible to avoid moving to the wrong chip C due to errors during movement. Furthermore, by performing position correction using the circuit pattern of the destination chip C, positional deviations due to errors during movement can be eliminated. Therefore, even if the target chip CT is relatively far from the notch N, it is possible to accurately move the chip recognition camera 22 to the target chip CT.

[0036] After the chip recognition camera 22 reaches the target chip CT, based on the relative position of the chip recognition camera 22 and the pickup nozzle 21, the pickup mechanism movement (S7) is performed to move the pickup nozzle 21 directly above the target chip CT, and the pickup (S8) is performed to pick up the chips C one by one from the target chip CT using the pickup nozzle 21.

[0037] As described above, the chip recognition camera 22 is moved to the target chip CT by repeating the movement process (S1, S4 in this embodiment) and the correction process (S2, S3, S5, S6 in this embodiment). Then, the target chip CT is picked up by the pickup nozzle 21. This prevents the pickup mechanism 20 from picking up the wrong chip C, thus preventing the accidental pickup of defective products and compromising quality and reliability.

[0038] Next, using the flowchart in Figure 2, we will explain the adjacent chip search process performed when chip C is not found.

[0039] As shown in Figure 10, the camera moves to P1 where the notch N is located, then to P2 where a nearby chip C is located, and after completing pattern recognition and position correction, it moves to P3 where a chip C is located near P2. We will now explain assuming that there is a missing section where chip C is not present. In this case, since P3 is a missing section, the chip recognition camera 22 searches for a location where chip C exists among the chips C adjacent to P3 (adjacent chips in this invention). Specifically, as shown in the flowchart in Figure 2, first, it performs an adjacent chip position movement (S9) and moves to a chip C adjacent to P3 based on the design information. Then, the chip recognition camera 22 performs pattern recognition of chip C again (S5). If, as a result, chip C is not found, the chip recognition camera 22 moves to an adjacent chip C again using the adjacent chip position movement (S9), and the chip recognition camera 22 repeats the process of checking for the presence or absence of a chip using pattern recognition (S5). As shown in Figure 10, if chip C is located at position P3A, pattern recognition (S5) and position correction (S6) are performed on the spot to align with chip C located at P3A. Then, the system moves to P4 and performs position correction, and this movement and position correction to chip C is repeated until the target chip CT is reached.

[0040] As mentioned above, even if there is no chip C at the location where the chip recognition camera 22 moves to, by performing adjacent chip position movement (S9), it is possible to reach the target chip CT without moving to the wrong chip C, and it is also possible to prevent the device from stopping due to an abnormality.

[0041] Up to this point, we have described embodiments of the alignment method proposed by the present invention, but the present invention is not limited to these embodiments.

[0042] For example, Figure 9 shows the chip recognition camera 22 always moving to the adjacent chip C, but as shown in Figure 11, it may also move by skipping one chip. However, as mentioned above, it is important to note that the next target chip C must be one that the pickup mechanism 20 does not move to due to errors that occur during movement.

[0043] Furthermore, although Figure 9 shows the chip recognition camera 22 moving only in a single axis direction, either the X or Y direction, it may also move in the XY direction (i.e., diagonally), as shown in Figure 11.

[0044] Furthermore, in the embodiment described above, movement and alignment were performed to the notch N as the starting position, but as shown in Figure 12, movement and alignment may also be performed to the characteristic mark M on the wafer W.

[0045] Furthermore, in the embodiment described above, alignment with the target chip CT was achieved by repeatedly moving to and aligning with chip C located in the middle of the target chip CT. However, as shown in Figure 12, alignment with the target chip CT may also be achieved by repeatedly moving to and aligning with a characteristic mark M on the wafer W.

[0046] Furthermore, although this embodiment describes the alignment method of the present invention using the pickup of chip C as an example, the alignment method of the present invention may also be used for applications other than the pickup of chip C. [Explanation of Symbols]

[0047] 1. Mounting device 10 Pickup Stages 20 Pickup mechanism 21 Pickup Nozzle 22 Chip Recognition Camera 30 Chip Slider 40 Bonding Heads 50 holding stages C Chip CT target chip M mark N Notch S Package Substrate W wafer

Claims

1. A positioning method for aligning a target chip, arbitrarily selected from among a plurality of chips formed and arranged on a substrate, with a chip recognition means, A movement process in which the recognition means and the substrate are moved relative to each other so that the pattern formed on the substrate comes within the field of view of the recognition means for recognizing the pattern formed on the substrate, The system includes a recognition means for recognizing the pattern and a correction process for correcting the positional misalignment between the recognition means and the pattern. The movement process and the correction process of the recognition means are repeated in this order until the movement process and the correction process of the recognition means are completed with respect to the target chip. A positioning method characterized by the following.

2. A method for alignment according to claim 1, In the aforementioned movement process, the distance traveled when the recognition means and the substrate are moved relative to each other is equal to the distance between the patterns calculated from the pattern design information. A positioning method characterized by the following.

3. A method for alignment according to claim 1, The first movement process involves moving the recognition means and the substrate relative to each other so that a reference mark provided on the substrate comes within the field of view of the recognition means. The first correction process involves recognizing the reference mark with the recognition means and correcting the misalignment between the recognition means and the reference mark. A positioning method characterized by the following.

4. A method for alignment according to claim 1, The pattern is a common pattern provided for each chip. A positioning method characterized by the following.

5. The alignment method according to claim 4, If, during the aforementioned movement process, the location where the recognition means and the substrate move relative to each other is a missing area where the chip does not exist, The recognition means and the substrate are moved relative to each other so that the pattern of the adjacent chip adjacent to the missing portion comes within the field of view of the recognition means. The recognition means recognizes the pattern of the adjacent chip, and an adjacent chip search process is performed to correct the positional misalignment between the recognition means and the pattern of the adjacent chip. A positioning method characterized by the following.

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