Display Data Buffering in Chiplet Architectures

Abstract

An apparatus and method are provided for efficiently managing power consumption among multiple replicated functional blocks of an integrated circuit. The integrated circuit includes multiple replicated functional blocks that use separate power domains. Data of a predetermined type is stored in an interleaved manner among at least two of the multiple functional blocks. In one embodiment, a prior static allocation determines that only a subset of the functional blocks store data of the predetermined type. In another embodiment, each of the functional blocks stores data of the predetermined type, and when an idle state occurs, data of the predetermined type is moved among the multiple functional blocks until one or more functional blocks no longer store data of the predetermined type. When a transition to the idle state occurs, functional blocks that do not store data of the predetermined type transition to a sleep state.

Description

[Background technology]

[0001] Description of Related Art Both planar and non-planar transistors (devices) are fabricated for use in integrated circuits within semiconductor chips. To integrate multiple types of integrated circuits, various options exist for arranging processing circuits in system packaging. Some examples are system-on-chip (SOC), multi-chip module (MCM), and system-in-package (SiP). Mobile devices, desktop systems, and servers use these packages. Regardless of the system packaging options, in some applications, power consumption in modern integrated circuits is becoming a design challenge that increases with each generation of semiconductor chips.

[0002] As power consumption increases, more expensive cooling systems, such as larger fans and heat sinks, are utilized to remove excess heat and prevent integrated circuit failure. However, cooling systems increase system costs. Power dissipation constraints in integrated circuits are not only an issue for portable computers and mobile communication devices, but also for high-performance desktop and server computers. A power management circuit assigns (specifies) operating parameters to various partitions of an integrated circuit. The operating parameters include at least an operating power supply voltage and an operating clock frequency.

[0003] Although a partition may not have computational tasks to perform during certain periods while an application is running, the power management circuitry cannot assign a partition to a sleep state due to infrequent maintenance tasks targeted at that partition. Modern integrated circuits include multiple replicated functional blocks within a partition to increase throughput. Each functional block includes one or more sub-blocks for data processing, one or more levels of cache, and an interface for communicating with local memory. In one example, when a video graphics application is executed by an integrated circuit, a partition including multiple functional blocks responsible for rendering video frame data has no further computational tasks to perform if there are no updates to the image presented on the display device. The image remains unchanged during application pauses, waits for user input information, or other states that do not require an image update even though the application is still running. However, the power management circuitry cannot assign a sleep state to the multiple functional blocks due to periodic refresh operations that require retrieving data from the multiple functional blocks and sending it to the display device.

[0004] In view of the above, a method and mechanism for efficiently managing power consumption of multiple replicated functional blocks in an integrated circuit is desired. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 2] 1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 3] 1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 4]1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 5] FIG. 1 is a generalized block diagram of a power manager that manages power consumption among replicated functional blocks of an integrated circuit. [Figure 6] FIG. 1 is a generalized block diagram of a computing system that manages power consumption among replicated functional blocks of an integrated circuit. [Figure 7] FIG. 1 is a generalized block diagram of a system-in-package that manages power consumption among replicated functional blocks of an integrated circuit. [Figure 8] 1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 9] 1 is a generalized block diagram of an apparatus for managing power consumption among replicated functional blocks of an integrated circuit. [Figure 10] 1 is a generalized diagram of a method for efficiently managing power consumption among replicated functional blocks of an integrated circuit. [Figure 11] 1 is a generalized diagram of a method for efficiently managing power consumption among replicated functional blocks of an integrated circuit. [Figure 12] FIG. 1 is a generalized block diagram of a computing system that manages power consumption among replicated functional blocks of an integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0006] While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0007] In the following specification, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Furthermore, it should be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements are exaggerated relative to other elements.

[0008] Apparatuses and methods are contemplated for efficiently managing power consumption among multiple replicated functional blocks of an integrated circuit. When using a multi-chip module (MCM), one or more of the multiple replicated chiplets may be connected to separate power rails and therefore may use separate power domains. The multiple replicated chiplets may be provided from a silicon wafer separate from the silicon wafers of the other functional blocks used in the MCM. When using a system-on-chip (SoC), one or more of the functional blocks may be connected to separate power rails and therefore may use separate power domains. The multiple replicated functional blocks may be provided from the same silicon wafer that provides the other functional blocks used in the SoC. Thus, the techniques and processes described below directed to power management of multiple replicated chiplets arranged in an MCM are also applicable to power management of multiple replicated functional blocks arranged in an SoC.

[0009] In various embodiments, an integrated circuit includes multiple replicated functional blocks using separate power domains. The multiple functional blocks store data of a predetermined type in an interleaved manner between at least two of the multiple functional blocks. In one embodiment, the predetermined type of data is video frame data from a frame buffer rendered by the multiple functional blocks. The idle state can represent a static screen on a display device connected to a display controller. When a transition to the idle state occurs, one or more of the functional blocks that do not store data of the predetermined type are transitioned to a sleep state. In some embodiments, prior static allocation determines that only a subset of the functional blocks store data of the predetermined type. Functional blocks not designated for that subset can immediately transition to a sleep state when an idle state occurs. In another embodiment, each of the functional blocks is permitted to store data of the predetermined type, and when an idle state occurs, a power manager or other circuit moves data of the predetermined type among the multiple functional blocks until one or more functional blocks no longer store data of the predetermined type. These functional blocks then transition to a sleep state. In some embodiments, the functional blocks are powered off rather than transitioned to a sleep state.

[0010] 1, a generalized block diagram of an apparatus 100 for managing power consumption among replicated chiplets of an integrated circuit is shown. In the illustrated embodiment, the apparatus 100 includes multiple replicated chiplets 110, 120, 130, and 140. Each of the chiplets 110, 120, 130, and 140 is connected to a corresponding one of memories 114, 124, 134, and 144. In addition, each of the chiplets 110, 120, 130, and 140 may store a copy of data stored in the memory 114, 124, 134, and 144 for a corresponding one of caches 112, 122, 132, and 142.

[0011] As used herein, a "chiplet" is also referred to as a "functional block" or an "intellectual property block" (or IP block). However, a "chiplet" is a semiconductor die (or dies) that is fabricated separately from other dies and then interconnected with other dies in a single integrated circuit within a system packaging known as a multi-chip module (MCM). A chiplet is a type of functional block. However, functional blocks can also include blocks fabricated with other functional blocks on a larger semiconductor die, such as a system-on-chip (SoC). Thus, a chiplet is a subset of multiple types of functional blocks. A chiplet is not fabricated with other functional blocks on a larger semiconductor die, such as an SoC, but is fabricated by itself as multiple copies on a silicon wafer. For example, a first silicon wafer (or first wafer) is fabricated with multiple copies of a first chiplet, and the first wafer is diced using laser cutting techniques to separate the multiple copies of the first chiplet.

[0012] A second silicon wafer (or second wafer) is fabricated with multiple copies of a second chiplet, and the second wafer is diced using laser cutting techniques to separate the multiple copies of the second chiplet. The first chiplet provides a function different from that of the second chiplet. One or more copies of the first chiplet are arranged in an integrated circuit, and one or more copies of the second chiplet are arranged in the integrated circuit. The first chiplet and the second chiplet are interconnected to each other within a corresponding MCM. Such a process replaces the process of fabricating a third silicon wafer (or third wafer) with multiple copies of a single monolithic semiconductor die, where the single monolithic semiconductor die includes the functionality of the first chiplet and the second chiplet as integrated functional blocks within the single monolithic semiconductor die.

[0013] The process yield of a single monolithic die on a silicon wafer is lower than the process yield of smaller chiplets on separate silicon wafers. Additionally, semiconductor processes can be tailored to the specific type of chiplet being manufactured. With a single monolithic die, each die on the wafer is formed using the same manufacturing process. However, the process parameters of the semiconductor manufacturer's expensive process that provide the fastest devices and smallest geometric dimensions beneficial to the high-throughput processing units on the die may not be required for the interface functional blocks. Using separate chiplets allows designers to easily create products in different performance categories by adding or removing chiplets for a particular integrated circuit. In contrast, when using a single monolithic die, entirely new silicon wafers must be manufactured for different products.

[0014] The following description describes power management of multiple replicated chiplets located on an MCM and provided from a silicon wafer separate from the silicon wafers of other functional blocks used in the MCM. However, the following description is also applicable to power management of multiple replicated functional blocks located on an SoC, where the multiple replicated functional blocks are provided from the same silicon wafer that provides other functional blocks used in the SoC. When using an MCM, one or more of the chiplets may be connected to separate power rails and therefore may use separate power domains. Similarly, when using an SoC, one or more of the functional blocks may be connected to separate power rails and therefore may use separate power domains.

[0015] Although not shown for ease of explanation, each of the chiplets 110, 120, 130, and 140 also includes one or more sub-blocks that provide various functions. These sub-blocks utilize transistors. As used herein, “transistor” is also referred to as “semiconductor device” or “device.” The chiplets 110, 120, 130, and 140 use p-type metal-oxide-semiconductor (PMOS) field-effect transistor (FET)s (or pFETs) in addition to n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET)s (or nFETs). In some embodiments, the devices (or transistors) in the memory array portion 100 are planar devices. In other embodiments, the devices (or transistors) in the memory array portion 100 are non-planar devices. Examples of non-planar transistors are tri-gate transistors, fin field-effect transistors (FETs), and gate-all-around (GAA) transistors. In some embodiments, the chiplets 110, 120, 130, and 140 comprise one or more three-dimensional integrated circuits (3D ICs). A 3D IC includes two or more layers of active electronic elements integrated both vertically and / or horizontally into a single circuit. In one embodiment, interposer-based integration is used, whereby the 3D IC is placed next to a central processing unit (CPU) containing one or more general-purpose processor cores. Alternatively, the 3D IC is stacked directly on top of another IC.

[0016] As shown, each of chiplets 110, 120, 130, and 140 and each of memories 114, 124, 134, and 144 stores a copy of one or more portions of a predetermined type of data. Each of memories 114, 124, 134, and 144 is any of various types of dynamic random access memory (DRAM). Portions of a predetermined type of data are shown as shaded boxes along with the corresponding alphabetic letter used to identify them. For example, memory 114 stores a copy of portion "A" and a copy of portion "E," memory 124 stores a copy of portion "B," memory 134 stores a copy of portion "C," and memory 144 stores a copy of portion "D." Caches 112, 122, 132, and 142 store copies of data stored in the corresponding ones of memories 114, 124, 134, and 144. For example, cache 112 stores a copy of portion "A" and a copy of portion "E." Cache 114 stores a copy of portion "B," and so on.

[0017] In one embodiment, chiplets 110, 120, 130, and 140 process tasks of a video graphics workload, such as rendering video frame data for a display device (not shown). The predetermined type of data is image data rendered by chiplets 110, 120, 130, and 140 (e.g., video frame data in a frame buffer). This predetermined type of data is transmitted from chiplets 110, 120, 130, and 140 to the display device. In some embodiments, chiplets 110, 120, 130, and 140 store the predetermined type of data in an interleaved manner among themselves. For example, a first portion (portion “A”) of the predetermined type of data is stored in a first chiplet (chiplet 110), and a second portion (portion “B”) of the predetermined type of data that is different from the first portion (portion “A”) is stored in a second chiplet (chiplet 120). A third portion (portion "C") of the predetermined type of data, different from the first and second portions, is stored in the third chiplet (chiplet 110), and so on. When the last chiplet of the plurality of chiplets (chiplet 140) has a portion (portion "D") of the predetermined type of data stored therein, the next portion (portion "E") of the predetermined type of data is stored in the first chiplet (chiplet 110). Data storage of the predetermined type of data continues in this manner.

[0018] In some embodiments, each portion of data is a contiguous portion relative to the preceding portion of a larger data set (e.g., a video frame buffer), and each portion has the same size. In other embodiments, one or more portions have different sizes, and one or more portions are not contiguous relative to the preceding portion. In one embodiment, power management circuitry (not shown) determines an idle state or receives an indication of an idle state for a computing system using chiplets 110, 120, 130, and 140. For example, a video graphics application may stop updating frame data viewed on a display device. The video graphics application may be paused or waiting for further user input, and during the wait time, the scene or image is not updated on the display device. Thus, a video processing subsystem of a computing system utilizing chiplets 110, 120, 130, and 140 enters an idle state even though the video graphics application has not stopped executing.

[0019] The power management circuit (or other circuitry) identifies a subset of chiplets 110, 120, 130, and 140 that do not utilize their corresponding caches above a threshold for storing data of a predetermined type. The threshold may be a value stored in a programmable configuration and status register (CSR). In one embodiment, the threshold is stored in the CSR as a value indicating an amount of data equal to at least two parts less one byte. Thus, any chiplet among 110, 120, 130, and 140 that stores an amount of data of a predetermined type in its corresponding cache that is at least two parts is utilizing its cache above the threshold. Alternatively, any chiplet among 110, 120, 130, and 140 that stores an amount of data of a predetermined type in its corresponding cache that is at least one byte less than two parts is not utilizing its cache above the threshold. Thus, the power management circuit (or other circuitry) identifies this chiplet as being among the subset of chiplets that do not utilize their corresponding caches above the threshold. One or more bytes of data of the predetermined type can later be transferred from another cache to this chiplet's cache.

[0020] In another embodiment, the threshold is stored in the CSR as a value indicating an amount of data equal to a certain number of portions, where the certain number is a positive, non-zero integer. In such an embodiment, the chiplets 110, 120, 130, and 140 transfer data at the granularity of portions rather than at the granularity of bytes. Thus, a chiplet 110, 120, 130, or 140 that stores an amount of data of a predetermined type in its corresponding cache that is at least equal to the certain number of portions is utilizing its cache above the threshold. Alternatively, a chiplet 110, 120, 130, or 140 that stores an amount of data of a predetermined type in its corresponding cache that is at least one or more portions less than the certain number of portions is not utilizing its cache above the threshold. Thus, the power management circuit (or other circuit) identifies the chiplet as being among a subset of chiplets that do not utilize their corresponding cache above the threshold. One or more portions of data of a predetermined type can later be transferred from another cache to the cache of this chiplet. In other embodiments, other thresholds and other granularities for transferring data between chiplets may be selected and are contemplated based on design requirements.

[0021] As shown, cache 112 of chiplet 110 stores an amount of data of a predetermined type that exceeds a threshold. In contrast, caches 122, 132, and 142 do not each store an amount of data of the predetermined type that exceeds a threshold. Power management circuitry (or other circuitry) sends commands to chiplets 120, 130, and 140 to transfer data of the predetermined type between them until at least one chiplet in the subset no longer stores data of the predetermined type. For example, chiplet 130 sends a copy of portion "C" to be stored in cache 122 of chiplet 120. The copy of portion "C" stored in memory 134 remains in memory 134. Chiplet 120 does not store a copy of portion "C" in memory 124. Cache 122 currently stores an amount of data of the predetermined type that exceeds a threshold. Similarly, chiplet 140 sends a copy of portion "D" to be stored in cache 132 of chiplet 130. The copy of portion "D" stored in memory 144 remains in memory 144. Chiplet 130 does not store a copy of portion "D" in memory 134. Cache 132 does not yet store an amount of data of the predetermined type that exceeds the threshold. Cache 142 no longer currently stores data of the predetermined type.

[0022] The power management circuit (or other circuitry) then transitions chiplets 140 that no longer store the predetermined type of data into a sleep state. The sleep state is a state of minimal power consumption, but the corresponding functional blocks still receive power supply voltages. In other embodiments, the power management circuit (or other circuitry) powers down chiplets 140 rather than transitioning them into a sleep state. When the power management circuit powers down chiplets 140, the power rails of chiplets 140 no longer receive power supply voltages. The sleep state and one or more active states may be associated with one or more power performance states (P-states) that indicate respective power domains managed by the power management circuitry. Each power domain includes at least operating parameters such as an operating power supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to clock generation circuits and power references. In various embodiments, each of chiplets 110, 120, 130, and 140 utilizes separate power rails and may be set to a separate power domain. The power management circuitry assigns (designates) active state operating parameters to chiplets 110, 120, 130 and designates a sleep state to chiplet 140. The designated active state may be associated with a low-power performance state (P-state), but still allows chiplets 110, 120, 130 to process tasks with minimal latency when required.

[0023] During the video subsystem idle state, chiplets 110, 120, and 130 storing data of a predetermined type (portions "A" through "E") process any generated requests for the predetermined type of data. For example, a display device of a computing system may still perform a refresh operation despite not requesting the rendering of new frame data. In this case, the predetermined type of data (portions "A" through "E") is the rendered data of the last frame processed before transitioning to an idle state showing a still screen on the display device. To perform the refresh operation, the display device requests data of the predetermined type (portions "A" through "E") from chiplets 110, 120, and 130 of device 100. While still supporting the refresh operation, device 100 reduces power consumption by transitioning chiplet 140 to a sleep state rather than maintaining chiplet 140 in an active state.

[0024] Referring to FIG. 2 , a generalized block diagram of an apparatus 200 for managing power consumption among replicated chiplets of an integrated circuit is shown. Signals and circuits previously described are similarly numbered. Here, each of chiplets 110, 120, 130, and 140 and each of memories 114, 124, 134, and 144 stores a corresponding copy of portions “A” through “E,” as described above. When power management circuitry (not shown) determines an idle state or receives an idle state indication indicating a static screen on a display device, chiplet 130 sends a copy of portion “C” to cache 122 of chiplet 120 for storage, as described above. In some embodiments, cache 132 supports a write-back policy, such that cache 132 updates the copy of portion “C” in memory 134 before invalidating the copy of portion “C” in cache 132. In another embodiment, cache 132 supports a write-through policy, such that memory 134 already stores an up-to-date copy of portion “C.” Thus, no update of memory 134 occurs. In yet another embodiment, cache 132 flushes its contents of the predetermined type of data, and any modified (“dirty”) data is written to memory 134. The copy of portion “C” stored in memory 134 remains in memory 134. Chiplet 120 no longer stores a copy of portion “C” in memory 124. However, cache 132 no longer stores the predetermined type of data. Thus, in contrast to the implementation described above, chiplet 140 does not transmit the copy of portion “D” stored in cache 132 of chiplet 130. Rather, chiplet 140 continues to store a copy of portion “D” in its cache 142.

[0025] The power management circuit then transitions chiplets 130 that no longer store data of the predetermined type into a sleep state. The power management circuit assigns active state operating parameters to chiplets 110, 120, and 140 and designates the sleep state for chiplets 130. The designated active state may be associated with a lower-power performance state (P-state), but in the designated active state, chiplets 110, 120, and 140 are still able to process tasks with minimal latency if requested. In one embodiment, the predetermined type of data (portions “A” through “E”) is rendered data of the last frame processed before transitioning to an idle state that shows a still screen for the display device. To perform a refresh operation, the display device requests the predetermined type of data (portions “A” through “E”) from chiplets 110, 120, and 140 of device 100. While still supporting refresh operations, device 100 reduces power consumption by transitioning chiplets 130 into a sleep state rather than maintaining chiplets 130 in an active state.

[0026] Note that when the idle state ends, in some embodiments, each of caches 112-142 invalidates its contents before later fetching the corresponding portions from memory 114-144. For example, cache 122 of chiplet 120 currently stores portions "B" and "C" during the idle state. When the idle state ends and chiplets 110-140 are expected to render video frame data again, cache 122 invalidates its contents. Cache 122 then fetches portion "B" from memory 124 and stores portion "B." Cache 122 no longer stores portion "C." Instead, cache 132 fetches portion "C" from memory 134 and stores portion "C." In another embodiment, when the idle state ends, chiplets 110-140 transfer portions between each other to return to the state they were in before the idle state. For example, chiplet 120 sends portion “C” to chiplet 130 for storage in cache 132 .

[0027] Referring now to FIG. 3, a generalized block diagram of an apparatus 300 for managing power consumption among replicated chiplets of an integrated circuit is shown. Signals and circuits previously described are similarly numbered. Here, each of chiplets 110, 120, 130, and 140 and each of memories 114, 124, 134, and 144 stores a corresponding copy of portions "A" through "D," as described above. The amount of data of a given type is less than in the previously described embodiment. For example, the frame buffer of rendered video frame data represented by portions "A" through "D" is smaller than the frame buffer of rendered video frame data represented by portions "A" through "E," even if the portions have the same size.

[0028] Chiplets 110, 120, 130, and 140 store portions "A" through "D" in an interleaved manner to hide the overhead latency of the memory devices used to implement memories 114, 124, 134, and 144. For example, opening a page in DRAM, storing the page in a row buffer, accessing the row buffer, and closing the page each involve significant latency. When a power management circuit (not shown) determines an idle state or receives an idle state indicator indicating a static screen on a display device, chiplet 130 sends a copy of portion "C" to cache 112 of chiplet 110 for storage. The copy of portion "C" stored in memory 134 remains in memory 134. Chiplet 110 no longer stores a copy of portion "C" in memory 114. Cache 132 no longer stores data of the given type. Similarly, chiplet 140 sends a copy of portion "D" to cache 122 of chiplet 120 for storage. The copy of portion "D" stored in memory 144 remains in memory 144. Chiplet 120 does not store a copy of portion "D" in memory 124. Cache 142 no longer stores data of the given type.

[0029] The power management circuit then transitions each of the chiplets 130 and 140 that no longer store data of the predetermined type into a sleep state. The power management circuit assigns active state operating parameters to the chiplets 110 and 120 and designates the sleep state for the chiplets 130 and 140. The designated active state may be associated with a lower-power performance state (P-state), but in the designated active state, the chiplets 110 and 120 are still able to process tasks with minimal latency if required. To perform refresh operations, the display device requests data of the predetermined type (portions "A" through "D") from the chiplets 110 and 120 of the device 100. While still supporting refresh operations, the device 300 reduces power consumption by transitioning the chiplets 130 and 140 into a sleep state rather than maintaining the chiplets 130 and 140 in an active state.

[0030] It should again be noted that the above describes power management of multiple replicated chiplets arranged in an MCM, where the multiple replicated chiplets are provided from a silicon wafer separate from the silicon wafers of other functional blocks used in the MCM. However, the above is also applicable to power management of multiple replicated functional blocks located on an SoC, where the multiple replicated functional blocks are provided from the same silicon wafer that provides the other functional blocks used in the SoC. When an MCM is used, one or more of the chiplets may be connected to separate power rails and therefore may use separate power domains. Similarly, when an SoC is used, one or more of the functional blocks may be connected to separate power rails and therefore may use separate power domains. Thus, the power management of devices 100-300 (of FIGS. 1-3) may also be used for multiple replicated functional blocks in an SoC. Similarly, the power management techniques and processes provided below in the description of FIGS. 4-12 for multiple replicated chiplets arranged in an MCM are also applicable to multiple replicated functional blocks arranged in an SoC.

[0031] Referring to FIG. 4, a generalized block diagram of an apparatus 400 for managing power consumption among replicated chiplets of an integrated circuit is shown. In the illustrated embodiment, apparatus 400 includes a power manager 440, a display controller 450, a direct memory access (DMA) circuit 460, a network interface 470, and at least two chiplets, such as chiplets 410A-410B. In various embodiments, the circuitry of chiplet 410B is an embodiment of the circuitry of chiplet 410A. While only two chiplets 410A-410B are shown, other numbers of chiplets can and are contemplated for use by apparatus 400, based on design requirements. Other components of apparatus 400 are not shown for ease of illustration. For example, an off-chip memory controller, one or more input / output (I / O) interface units, an interrupt controller, one or more phase-locked loops (PLLs) or other clock generation circuits, and various other functional blocks may be used by apparatus 400 but are not shown.

[0032] In some embodiments, the functionality of device 400 is included as multiple components on a single die, such as a single integrated circuit. In one embodiment, the functionality of device 400 is included as any one of multiple dies on a multi-chip module (MCM). In various embodiments, device 400 is used in a desktop computer, a portable computer, a mobile device, a server, a peripheral device, or the like. Device 400 may also communicate with various other external circuits, such as one or more of a digital signal processor (DSP), various application-specific integrated circuits (ASICs), a multimedia engine, or the like.

[0033] Hardware such as the circuits in each of blocks 414A and 416A provides various functions. In some embodiments, one or more of blocks 414A and 416A includes a relatively broad single instruction, multiple data (SIMD) microarchitecture. For example, one or more of blocks 414A and 416A is used as a dedicated GPU (or dGPU), a dedicated video graphics chip or chipset, or the like. In some embodiments, one or more of blocks 414A and 416A renders video frame data that is then sent to display controller 450. In one embodiment, cache 420A is the last-level cache in a cache memory subsystem hierarchy. Cache 420A can support a write-back policy, or cache 420A can support a write-through policy. Chiplet 410A uses local memory controllers 422A and 426A to transfer data to and from local memory 430A via communication channels 424A and 428A.

[0034] Local memory 430A includes memory devices 432A and 434A. In some embodiments, memory devices 432A and 434A are any of various types of synchronous dynamic random access memory (SDRAM) specifically designed for applications requiring both high memory data bandwidth and high memory data rates. In other embodiments, memory devices 432A and 434A are any of other types of DRAM. In various embodiments, communication channels 424A and 428A are each point-to-point (P2P) communication channels. A point-to-point communication channel is a dedicated communication channel between a single source and a single destination. Thus, a point-to-point communication channel transfers data only between a single source and a single destination. Address information, command information, response data, payload data, header information, and other types of information are transferred over metal traces or wires accessible only by a single source and a single destination. In one embodiment, local memory controllers 422A and 426A support any of various types of graphics double data rate (GDDR) communication protocols.

[0035] It should be noted that although communication channels 424A and 428A use the term "communication channel," each of communication channels 424A and 428A can transfer data across multiple memory channels supported by the corresponding memory device. For example, a single memory channel of a particular memory device can include 60 or more individual signals, with 32 of the signals dedicated to response or payload data. A memory controller or interface of a memory device can support multiple memory channels, each of which is included within one of communication channels 424A and 428A.

[0036] The interface 412A includes circuitry that allows the chiplet 410A to communicate with external integrated circuits, such as at least the illustrated components 440-470. One or more of a communication bus, point-to-point channel, communication fabric, or the like, is used to transfer data and commands between the chiplets 410A-410B and at least the components 440-470. The network interface 470 supports communication protocols for communication with any of various types of networks. The DMA circuit 460 supports memory mapping and communication protocols for communication with any of various types of system memory. The display controller 450 receives rendered video frame data from the chiplets 410A-410B and prepares this data for presentation of images on a corresponding display device. Each of the chiplets 410A-410B is assigned a respective power domain by the power manager 440. A power domain includes at least operating parameters such as an operating power supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to clock generation circuits and power references.

[0037] In some embodiments, hardware, such as circuitry in power manager 440, determines when a task in a workload enters an idle state. In other embodiments, power manager 440 receives an indication of the idle state. The idle state may indicate a static screen on a display device connected to display controller 450. For example, a video graphics application stops updating frame data viewed on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or image is not updated on the display device. Thus, a video processing subsystem of a computing system, such as chiplets 410A-410B, enters the idle state even though the video graphics application has not stopped executing. Power manager 440 sends operating parameters and data storage commands 442 to chiplets 410A-410B. For example, power manager 440 performs the steps described with respect to the discussion of power management by devices 100-300 (FIGS. 1-3) and devices 800-900 (FIGS. 8-9). In another embodiment, other circuitry than power manager 440 sends data storage commands to chiplets 410A-410B. In some embodiments, chiplets 410A-410B each have the functionality of chiplets 110-140 (FIGS. 1-3 and 8-9).

[0038] Referring now to FIG. 5, a generalized block diagram of a power manager 500 for managing power consumption among replicated chiplets of an integrated circuit is shown. As shown, power manager 500 includes a table 510 and a control circuit 530. Control circuit 530 includes multiple components 532-538 used to generate operating parameters and data storage commands 540 for updating the power domains of the multiple chiplets. Table 510 includes multiple table entries (or entries), each of which stores information in multiple fields, such as at least fields 512-522. Table 510 may be implemented using flip-flop circuits, random access memory (RAM), content addressable memory (CAM), or the like. While particular information is shown as being stored in a particular contiguous order in fields 512-522, other embodiments may use a different order and store different numbers and types of information. As shown, field 512 stores status information, such as at least a valid bit. Field 514 stores an identifier that designates one of the multiple chiplets.

[0039] Field 516 stores an indicator of whether dynamic identification or static allocation is used to store a given type of data across multiple chiplets. Field 518 stores an indicator specifying a specified static allocation, such as half of the chiplets, one-quarter of the chiplets, or the like. Field 520 stores a value indicating cache utilization for storing a given type of data in a particular cache of the chiplet. For example, a last level cache is monitored for its cache utilization. Field 522 stores a current value indicating the most recent P-state or power domain of the chiplet.

[0040] Control circuitry 530 receives usage measurements and indicators 524 representing chiplet activity levels and power consumption measurements or parameters used to determine the chiplet's recent power consumption values. A power performance state (P-state) selector 532 selects the next operating parameters to use for the chiplet. A dynamic / static storage allocator 534 (or allocator 534) includes circuitry that determines whether dynamic specification or static allocation is used to store a predetermined type of data across multiple chiplets. In some embodiments, the predetermined type of data is video frame data, and allocator 534 receives an indication of the expected size of the frame data for a video graphics application. Based on the expected size, the size of the chiplet's last-level cache, the expected performance degradation if the number of chiplets available for video rendering were reduced, any quality of service (QoS) values ​​associated with the video graphics application, values ​​stored in table 510, etc., allocator 534 determines whether dynamic specification or static allocation is used to store the predetermined type of data across multiple chiplets. Examples of dynamic identification are provided in the above-mentioned description of devices 100-300 (FIGS. 1-3) and in the following description of method 1000 (FIG. 10). Examples of static allocation are provided in the below-mentioned description of devices 800-900 (FIGS. 8-9) and in the below-mentioned description of method 1100 (FIG. 11).

[0041] One or more components of power manager 500 use values ​​stored in configuration and status register (CSR) 536. CSR 536 stores values ​​such as cache utilization thresholds, performance thresholds, etc. These thresholds are the same values ​​as those described with respect to devices 100-300 (FIGS. 1-3), method 1000 (FIG. 10), devices 800-900 (FIGS. 8-9), and method 1100 (FIG. 11). In some embodiments, one or more of the components and corresponding functionality of power manager 500 are provided in separate external circuitry rather than within power manager 500 itself.

[0042] Referring now to FIG. 6, a generalized block diagram of one embodiment of a computing system 600 for managing power consumption among replicated chiplets of an integrated circuit is shown. Integrated circuit 610 includes chiplets 620a-620h, interface 640, unit 650, functional blocks 660-666, and engine 670. Chiplets 620a-620h use receiver front-end blocks 622a-622h to communicate with unit 650. Integrated circuit 610 includes multiple types of designs that provide different functions. In some embodiments, integrated computing system 600 is a multi-chip module (MCM) that includes various processing units and functional blocks that provide different functions. In one embodiment, interface 640, unit 650, functional blocks 660-666, and engine 670 provide distinct functions. In contrast, each of chiplets 620a-620h provides the same function. For example, in some designs, each of chiplets 620a-620h is an implementation of the same processor core. In other designs, each of chiplets 620a-620h includes the same number and types of dies. In various embodiments, each of chiplets 620a-620h has the functionality of chiplets 110-140 (FIGS. 1-3 and 8-9) and chiplets 410A-410B (FIG. 4). Power manager 668 has the same functionality as power manager 440 (FIG. 4) and power manager 500 (FIG. 5).

[0043] In some embodiments, integrated circuit 610 includes a central processing unit (CPU) having circuitry used to process instructions of a selected instruction set architecture (ISA), a graphics processing unit (GPU) having circuitry implementing a highly parallel data microarchitecture, a hub used to communicate with the multimedia engine, and a multimedia engine such as engine 670 having circuitry to process audio and visual data for multimedia applications. In another embodiment, unit 650 and functional blocks 660-666 include one or more application specific integrated circuits (ASICs) or microcontrollers, one or more digital signal processors (DSPs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs).

[0044] In one embodiment, a communications fabric supports communication between components of integrated circuit 610. The communications fabric supports the transfer of messages, requests, responses, acknowledgments, commands, interrupts, etc. between multiple components within integrated circuit 610 and one or more external processing units and peripheral devices. In various embodiments, communications between components of integrated circuit 610 include at least links 624 between unit 650 and chiplets 620a-620h, each link using a corresponding one of receiver front-end blocks 622a-622h.

[0045] As shown, links 624 have varying metal trace lengths based on the on-die location of corresponding ones of chiplets 620a-620h. Thus, the impedances of links 624 differ from one another. In addition to varying metal trace lengths, in some embodiments, the metal traces of transmission line 624 vary in metal layer thickness and spacing between metal traces. Thus, in some embodiments, links 624 are divided into subsets that use different equalization coefficients for multiple transmitters and receivers that use subsets of links 624.

[0046] The circuitry of interface 640 communicates with either external memory, an external peripheral device, another semiconductor chip, or the like. Interface 640 includes queues for storing requests and responses and circuitry for supporting a particular communication protocol. While a single interface is shown, it is possible and contemplated that integrated circuit 610 may use multiple interfaces. In various embodiments, multiple components of integrated circuit 610 support a cache memory subsystem that includes an integrated cache within chiplets 620a-620h.

[0047] Referring now to FIG. 7 , a generalized block diagram of a system-in-package (SiP) 700 for managing power dissipation between replicated chiplets of an integrated circuit is shown. In various embodiments, three-dimensional (3D) packaging is used within a computing system. This type of packaging is referred to as a system-in-package (SiP). A SiP contains one or more three-dimensional integrated circuits (3D ICs). A 3D IC contains two or more layers of active electronic elements integrated both vertically and / or horizontally into a single circuit. In one embodiment, interposer-based integration is used, whereby a 3D IC is placed next to a processing unit 710. Alternatively, a 3D IC is stacked directly on top of another IC.

[0048] Die stacking technology is a manufacturing process that allows multiple separate pieces of silicon (integrated chips) to be physically stacked together in the same package with high-bandwidth and low-latency interconnects. In some embodiments, the dies are stacked side-by-side on a silicon interposer or directly on top of each other vertically. One configuration for a SiP is to stack one or more semiconductor die (or dies) next to and / or above a processing unit, such as processing unit 710. In one embodiment, SiP 700 includes processing unit 710 and modules 740A-740B. Module 740A includes chiplet 720A and chiplets 722A-722B. In various embodiments, chiplets 720A and 722A-722B are multiple three-dimensional (3D) semiconductor dies. While a specific number of chiplets is shown, in other embodiments, any number of chiplets is used as a stacked 3D dies.

[0049] Chiplet 720A is fabricated on a corresponding silicon wafer, which is later diced to provide chiplet 720A. Each of chiplets 722A-722B is fabricated on a silicon wafer that is different from the silicon wafer used to provide chiplet 720A and that is separate from the silicon wafer used to provide processing unit 710. In some embodiments, chiplets 722A-722B include circuitry for rendering video frame data, which is then transmitted to a display controller (not shown). Each of chiplets 722A-722B has a separate power rail, which allows one or more of chiplets 722A-722B to be put to sleep by power manager 712 during an idle state that presents a static screen to the display device. In some embodiments, module 740B is a duplicate of module 740A. In various embodiments, power manager 712 has the functionality of power manager 440 (FIG. 4) and power manager 500 (FIG. 5). Power manager 712 may implement the steps for power management described with respect to devices 100-300 (FIGS. 1-3), method 1000 (FIG. 10), devices 800-900 (FIGS. 8-9), and method 1100 (FIG. 11).

[0050] Each of the modules 740A-740B communicates with the processing unit 710 through a horizontal low-latency interconnect 730. In various embodiments, the processing unit 710 is a general-purpose central processing unit, such as a graphics processing unit (GPU), an accelerated processing unit (APU), a field-programmable gate array (FPGA), or other data processing device. The horizontal low-latency interconnect 730 within the package reduces the length of the interconnect signals when a SiP is not used, compared to longer off-chip interconnects. The intra-package interconnect 730 uses specific signals and protocols for each chip, such as the processing unit 710 and modules 740A-740B, as if they were implemented in separate packages on a circuit board. In some embodiments, the SiP 700 further includes backside vias or bulk-through silicon vias 732 that reach package external connections 734. The package external connections 734 are used for input / output (I / O) and power signals.

[0051] In various embodiments, multiple device layers are stacked on top of each other with direct vertical interconnects 736 tunneling between them. In various embodiments, the vertical interconnects 736 are multiple through-silicon vias that are grouped together to form through-silicon buses (TSBs). TSBs are used as vertical electrical connections through a silicon wafer. TSBs are an alternative interconnect to wire bonds and flip chips. The size and density of the vertical interconnects 736 that can tunnel between different device layers varies based on the underlying technology used to fabricate the 3D IC. As shown, some of the vertical interconnects 736 do not pass through each of the modules 740A-740B. Thus, in some embodiments, the processing unit 710 does not have a direct connection to one or more dies, such as die 722D in the illustrated embodiment. Therefore, information routing relies on other dies in the SiP 700.

[0052] Referring to FIG. 8, a generalized block diagram of an apparatus 800 for managing power consumption among replicated chiplets of an integrated circuit is shown. Signals and circuits previously described are similarly numbered. Here, a designated subset of chiplets 110, 120, 130, and 140 and corresponding memories 114, 124, 134, and 144 store copies of portions "A" through "E." In this embodiment, the designated subset includes chiplets 110 and 120, or half of the total number of chiplets in apparatus 800. Rather than interleaving data storage for portions "A" through "E" between each of chiplets 110, 120, 130, and 140 and corresponding memories 114, 124, 134, and 144, a small fraction of the total number of chiplets 110, 120, 130, and 140 is statically designated for allocation. In some embodiments, device 800 is programmable to switch between storing a predetermined type of data, such as portions "A" through "E," in each of chiplets 110, 120, 130, and 140, and storing the predetermined type of data in a designated subset of chiplets 110, 120, 130, and 140. When using a subset of chiplets 110, 120, 130, and 140 as shown, in one embodiment, chiplet 110 stores portions "A," "C," and "E," and chiplet 120 stores portions "B" and "D." Here, the cache utilization threshold for storing the predetermined type of data is a value that indicates one byte less than three portions, rather than two portions as described above. The threshold may be stored in a programmable configuration and status register (CSR).

[0053] The trade-off between using dynamic reallocation and using static allocation is that using static allocation achieves faster transition to an idle state, but using static allocation degrades performance when device 800 is not in an idle state. With static allocation (subset designation), the power management circuitry (or other circuitry) does not need to dynamically identify which of the chiplets 110, 120, 130, 140 do not store data of a given type. The static assignment is set before processing a workload. Therefore, the transition of the chiplets 110, 120, 130, 140 to an idle state is faster using static assignment than using dynamic designation to initiate the transition to an idle state.

[0054] When device 800 is not idle, but rather rendering new video frame data, performance degrades due to using only chiplets 110 and 120. However, the power management circuitry (or other circuitry) predicts performance to exceed a performance threshold if storage of a predetermined type of data is restricted to a subset of chiplets, such as only chiplets 110 and 120. When the power management circuitry determines an idle state or receives an idle indication indicating a static screen on a display device, data of the predetermined type is not moved between chiplets 110, 120, 130, and 140. Rather, the power management circuitry can immediately transition each of chiplets 130 and 140 to a sleep state.

[0055] The power management circuitry assigns active state operating parameters to chiplets 110 and 120 and designates a sleep state for chiplets 130 and 140. To perform refresh operations during the idle state, the display device requests certain types of data (portions "A" through "E") from chiplets 110 and 120 of device 800. While still supporting refresh operations, device 800 reduces power consumption by transitioning chiplets 130 and 140 to a sleep state rather than maintaining chiplets 130 and 140 in an active state.

[0056] Referring to FIG. 9 , a generalized block diagram of an apparatus 900 for managing power consumption among replicated chiplets of an integrated circuit is shown. Signals and circuits previously described are similarly numbered. Here, a designated subset of chiplets 110, 120, 130, and 140, and corresponding memories 114, 124, 134, and 144, store copies of portions “A” through “D.” In this embodiment, the designated subset includes chiplet 110, or one-quarter of the total number of chiplets in apparatus 900. When apparatus 900 is not idle, but is rendering new video frame data, performance degrades due to using only chiplet 110. However, power management circuitry (or other circuitry) predicts that performance will exceed a performance threshold if storage of a predetermined type of data is restricted to a subset of chiplets, such as only chiplet 110.

[0057] When the power management circuit determines an idle state or receives an idle state indication that indicates a static display screen for the display device, data of a predetermined type is not transferred between the chiplets 110, 120, 130, and 140. Rather, the power management circuit can immediately transition each of the chiplets 120, 130, and 140 into a sleep state. The power management circuit assigns active state operating parameters to the chiplet 110 and designates the sleep state for the chiplets 120, 130, and 140. To perform refresh operations during the idle state, the display device requests data of a predetermined type (portions "A" through "D") from the chiplet 110 of the device 900. While still supporting refresh operations, the device 900 reduces power consumption by transitioning the chiplets 120, 130, and 140 into a sleep state rather than maintaining the chiplets 120, 130, and 140 in an active state.

[0058] In methods 1000 and 1100 (FIGS. 10-11), an integrated circuit includes multiple replicated chiplets. Each chiplet includes circuitry operable to use a separate power domain. Thus, the circuitry of a first chiplet shares at least the same first power rail and the same first clock reference signal. Similarly, the circuitry of a second chiplet shares at least the same second power rail and the same second clock reference signal. The second power rail is different from the first power rail, and the second clock reference signal is different from the first clock reference signal. Thus, at least the second chiplet uses a different power domain than the first chiplet, and therefore, the second chiplet can use different operating parameters than the first chiplet. For example, one of the first and second chiplets can be powered down or placed in a sleep state while the other chiplet remains in one of multiple active states.

[0059] When an MCM is used, one or more of the chiplets may be connected to separate power rails and therefore may use separate power domains. Similarly, when an SoC is used, one or more of the functional blocks may be connected to separate power rails and therefore may use separate power domains. Thus, the techniques and processes described above and below that address power management of multiple replicated chiplets arranged in an MCM are also applicable to power management of multiple replicated functional blocks arranged in an SoC.

[0060] 10, a generalized block diagram of a method 1000 for efficiently managing power consumption among replicated chiplets of an integrated circuit is shown. For purposes of explanation, the steps of this embodiment (and of FIG. 11) are shown sequentially. However, in other embodiments, some steps occur in a different order than that shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are absent.

[0061] Hardware, such as circuits of multiple chiplets of an integrated circuit, processes tasks of the workload using assigned operating parameters (block 1002). In various embodiments, a power manager assigns a respective power domain to each of the chiplets. Each power domain includes at least operating parameters such as an operating power supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to a clock generation circuit and a power reference. In one embodiment, the multiple chiplets process tasks of a video graphics workload, such as rendering video frame data for a display device. The predetermined type of data is video frame data of a frame buffer rendered by the multiple chiplets. The predetermined type of data is transmitted from the multiple chiplets to the display device.

[0062] The plurality of chiplets stores data of a predetermined type in an interleaved manner among each of the plurality of chiplets (block 1004). For example, a first portion of the predetermined type of data is stored in a first chiplet, and a second portion of the predetermined type of data, different from the first portion, is stored in a second chiplet. A third portion of the predetermined type of data, different from the first and second portions, is stored in a third chiplet, and so on. When the last chiplet of the plurality of chiplets has a portion of the predetermined type of data stored therein, the next portion of the predetermined type of data is stored in the first chiplet. Data storage of the predetermined type of data continues in this manner. In some embodiments, each portion is contiguous relative to the preceding portion, and each portion has the same size. In other embodiments, one or more portions have different sizes, and one or more portions are not contiguous relative to the preceding portion.

[0063] In various embodiments, the multiple chiplets store data in local memory devices, such as any of various types of DRAM. In addition, the multiple chiplets store copies of predetermined types of data in corresponding caches. In one embodiment, the caches are last-level caches in a cache memory subsystem hierarchy. The caches may support a write-back policy, or the caches may support a write-through policy. In some embodiments, a power manager determines when tasks of a workload enter an idle state. In other embodiments, the power manager receives an indication of the idle state. The idle state may indicate a static screen on a display device. For example, a video graphics application stops updating frame data viewed on the display device. The video graphics application may be paused or waiting for further user input, and during the wait time, the scene or picture is not updated on the display device. Thus, a video processing subsystem of a computing system including multiple chiplets enters an idle state even though the video graphics application has not stopped executing.

[0064] If the power manager circuitry determines that a transition to the idle state has not yet occurred (conditional branch 1006: “No”), control flow of method 1000 returns to block 1002, where the multiple chiplets of the integrated circuit process tasks of the workload using their assigned operating parameters. However, if the power manager determines that a transition to the idle state has occurred (conditional branch 1006: “Yes”), the power manager identifies a subset of the multiple chiplets that do not utilize their corresponding caches beyond a threshold for storing data of a predetermined type (block 1008). The threshold may be a value stored in a programmable configuration and status register (CSR). The power manager sends commands to the multiple chiplets to transfer data of a predetermined type among chiplets of the subset that previously stored data of the predetermined type until at least one chiplet of the subset no longer stores data of the predetermined type (block 1010). The power manager then transitions one or more chiplets that do not store data of the predetermined type into a sleep state (block 1012).

[0065] The power manager assigns (designates) active state operating parameters to one or more chiplets storing data of a predetermined type (block 1014). The active state may be associated with a lower-power performance state (P-state), but in the active state, the dies of these designated chiplets are still able to process tasks if requested. During the idle state, one or more chiplets storing data of a predetermined type process any generated requests targeting the predetermined type of data (block 1016). For example, a display device of a computing system may still perform refresh operations despite not requesting the rendering of new frame data. To do so, the display device requests data of a predetermined type from one or more chiplets storing data of a predetermined type that are in an active state, not a sleep state. In this case, the predetermined type of data is the rendered data of the frame to be last processed before transitioning to an idle state showing a still screen of the display device.

[0066] 11 , a generalized block diagram of a method 1100 for efficiently managing power consumption among replicated chiplets of an integrated circuit is shown. Hardware, such as circuitry, of multiple chiplets of the integrated circuit processes tasks of a workload using assigned operating parameters (block 1102). In various embodiments, a power manager assigns a respective power domain to each of the chiplets. In one embodiment, the multiple chiplets process tasks of a video graphics workload, such as rendering video frame data for a display device. The predetermined type of data is video frame data of a frame buffer rendered by the multiple chiplets. The predetermined type of data is transmitted from the multiple chiplets to the display device.

[0067] The plurality of chiplets store data of a predetermined type in an interleaved manner only among a subset of the plurality of chiplets (block 1104). For example, if only half of the chiplets are permitted to store data of a predetermined type, a first portion of the data of the predetermined type is stored in a first chiplet of the subset, and a second portion of the data of the predetermined type that is different from the first portion is stored in a second chiplet of the subset. A third portion of the data of the predetermined type that is different from the first and second portions is stored in a third chiplet of the subset, and so on. If the last chiplet of a subset, such as half of the plurality of chiplets, has some portion of the data of the predetermined type stored therein, then the next portion of the data of the predetermined type is stored in the first chiplet of the subset.

[0068] In an embodiment having eight chiplets, data of a given type is stored in only four of the eight chiplets. Thus, data storage for a given type of data is interleaved among four chiplets (e.g., chiplets with identifiers 0-3), and chiplets with identifiers 4-7 are not used for data storage. In one embodiment, if the video frame data does not fit into a designated subset of chiplets, after the memory devices of the subset of chiplets are filled with data storage, the video frame buffer data is sent to chiplets not in the subset for data storage. In other embodiments, the subset of chiplets is one-quarter the number of chiplets or another number of chiplets. The number of chiplets in a subset is based on design requirements.

[0069] In some embodiments, the power manager determines when the tasks of the workload enter an idle state. In other embodiments, the power manager receives an indication of the idle state. For example, a video graphics application stops updating video frame data viewed on a display device. If the power manager circuitry determines that a transition to the idle state has not yet occurred (conditional branch 1106: "No"), control flow of method 1100 returns to block 1102, where the multiple chiplets of the integrated circuit process the tasks of the workload using their assigned operating parameters. However, only a subset of the chiplets store data of a given type.

[0070] If the power manager determines that a transition to an idle state has occurred (conditional branch 1106: "yes"), the power manager transitions chiplets that are not in the subset to a sleep state (block 1112). Because the static assignment is set before processing the workload, the power manager does not need to dynamically identify which chiplets do not store data of a predetermined type. Therefore, transitioning chiplets to an idle state is faster using static assignment than using dynamic identification to initiate a transition to an idle state. The tradeoff is that maximum performance can be achieved by storing data of a predetermined type in each of multiple chiplets. If storage of data of a predetermined type is restricted to a subset of chiplets, performance is predicted to exceed a performance threshold.

[0071] The power manager assigns operating parameters of an active state to chiplets in the subset that store data of a predetermined type (block 1110). The active state may be associated with a lower-power performance state (P-state), but in the active state, the dies of these designated chiplets are still able to process tasks if required. During the idle state, one or more chiplets in the subset that store data of a predetermined type process any generated requests that target the data of the predetermined type (block 1112). For example, a display device of a computing system still performs refresh operations despite not requiring the rendering of new frame data.

[0072] Referring to FIG. 12 , a generalized block diagram of a computing system 1200 for managing power consumption among replicated chiplets of an integrated circuit is shown. The computing system 1200 includes a processor 1210 and memory 1230. Interfaces such as a memory controller, a bus or communication fabric, one or more phase-locked loops (PLLs) and other clock generation circuits, a power management unit, etc. are not shown for ease of illustration. It should be understood that in other embodiments, the computing system 1200 includes one or more of the following: other processors of the same or different type as the processor 1210, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some embodiments, the functionality of the computing system 1200 is incorporated onto a multi-chip module (MCM). The computing system 1200 may be used in any of a variety of computing devices, such as a desktop computer, a tablet computer, a laptop, a smartphone, a smartwatch, a game console, a personal assistant device, etc.

[0073] Processor 1210 includes hardware such as circuits. For example, processor 1210 includes at least one integrated circuit 1220. Integrated circuit 1220 includes chiplets 1222, one or more of which have the functionality of chiplets 110-140 (FIGS. 1-3 and 8-9) and chiplets 410A-410B (FIG. 4). Power manager 1224 has the same functionality as power manager 440 (FIG. 4) and power manager 500 (FIG. 5). Power manager 1224 can perform the operations described with respect to the discussion of power management by devices 100-300 (FIGS. 1-3) and devices 800-900 (FIGS. 8-9). In some embodiments, processor 1210 includes one or more processing units. In some embodiments, each of the processing units includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such an embodiment, processor 1210 is a central processing unit (CPU). In another embodiment, the processing cores are computational units, each of which has a highly parallel data microarchitecture with multiple parallel execution lanes and associated data storage buffers. In such an embodiment, processor 1210 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0074] In some embodiments, memory 1230 includes one or more of a hard disk drive, a solid state disk, other types of flash memory, a portable solid state drive, a tape drive, and the like. Memory 1230 stores an operating system (OS) 1232, one or more applications represented by code 1234, and at least source data 1236. Memory 1230 may also store intermediate and final result data generated by processor 1210 when executing a particular application of code 1234. While a single operating system 1232 and a single instance of code 1234 and source data 1236 are shown, in other embodiments, other numbers of these software components are stored in memory 1230. Operating system 1232 includes instructions for initiating the boot-up of processor 1210, assigning tasks to hardware circuitry, managing resources of computing system 1200, and hosting one or more virtual environments.

[0075] Each of the processor 1210 and memory 1230 includes an interface unit for communicating with each other and with any other hardware components included in the computing system 1200. The interface units include queues for handling memory requests and responses, and control circuitry for communicating with each other based on a particular communication protocol. The communication protocol determines various parameters such as supply voltage levels, power performance states that determine operating supply voltages and clock frequencies, data rates, one or more burst modes, etc.

[0076] It should be noted that one or more of the above-described embodiments include software. In such embodiments, program instructions implementing the methods and / or mechanisms are carried or stored on a computer-readable medium. Many types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (ROM, PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer-accessible storage medium may include magnetic or optical media (e.g., a disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray storage medium). Storage media further include volatile or non-volatile memory media such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), Double Data Rate (DDR, DDR2, DDR3, etc.) SDRAM, Low Power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), Static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface, etc. Storage media include Micro-Electro-Mechanical Systems (MEMS), and storage media accessible via a communication medium such as a network and / or wireless link.

[0077] Additionally, in various embodiments, the program instructions include a behavioral or register transfer level (RTL) description of the hardware functionality in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the system. The netlist can then be placed and routed to generate a data set that describes the geometric shapes that are applied to a mask. The mask can then be used in various semiconductor manufacturing processes to fabricate the semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set, as appropriate. Additionally, the instructions are utilized for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0078] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated, and it is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. 1. An integrated circuit comprising: a plurality of functional blocks, each functional block comprising circuitry configured to perform a task and a cache configured to store data; a power management circuit; The power management circuitry includes: assigning operational parameters to the plurality of function blocks; In response to an idle state of the plurality of function blocks, assigning a first operating parameter to one or more of the plurality of function blocks that do not store data of a predetermined type; assigning second operating parameters to one or more of the plurality of function blocks that store the predetermined type of data; and the first operating parameter results in lower power consumption than the second operating parameter; Integrated circuit.

2. the predetermined type of data is video frame data; 10. The integrated circuit of claim 1.

3. The power management circuitry includes: identifying a first subset of the plurality of functional blocks that do not utilize their corresponding caches above a threshold for storing a predetermined type of data; transferring data of the predetermined type between functional blocks of the first subset until at least one functional block of the first subset that previously stored data of the predetermined type no longer stores data of the predetermined type; configured to:

10. The integrated circuit of claim 1.

4. the power management circuitry is configured to transfer the predetermined type of data between the functional blocks of the first subset until at least one functional block of the first subset utilizes the cache above a threshold for storing the predetermined type of data; 4. The integrated circuit of claim 3.

5. One or more of the plurality of functional blocks When storing data in the cache, performing a write-back operation to store a copy of the data in memory; skipping execution of the write-back operation when writing data to the cache based on transferring data of the predetermined type between functional blocks of the first subset; configured to:

4. The integrated circuit of claim 3.

6. the plurality of functional blocks are configured to store the predetermined type of data in an interleaved manner between each of the plurality of functional blocks; 4. The integrated circuit of claim 3.

7. the plurality of functional blocks are configured to store the predetermined type of data in an interleaved manner among only a second subset of the plurality of functional blocks.

10. The integrated circuit of claim 1.

8. 1. A method comprising: the power management circuit assigning operating parameters to a plurality of functional blocks, each functional block comprising a circuit configured to perform a task and a cache configured to store data; In response to an idle state of the plurality of function blocks, the power management circuit assigning first operating parameters to one or more of the plurality of functional blocks that do not store data of a predetermined type; assigning second operating parameters to one or more of the plurality of function blocks that store the predetermined type of data; the first operating parameter results in lower power consumption than the second operating parameter; method.

9. the predetermined type of data is video frame data; 9. The method of claim 8.

10. the power management circuit identifying a first subset of the plurality of functional blocks that are not utilizing their corresponding caches above a threshold for storing a predetermined type of data; the power management circuitry transferring the predetermined type of data between the functional blocks of the first subset until at least one functional block of the first subset that previously stored the predetermined type of data no longer stores the predetermined type of data.

9. The method of claim 8.

11. the power management circuitry transferring the predetermined type of data between the functional blocks of the first subset until at least one functional block of the first subset utilizes the cache above a threshold for storing the predetermined type of data; The method of claim 10.

12. If one or more of the plurality of functional blocks stores data in the cache, performing a write-back operation to store a copy of the data in memory; skipping execution of the write-back operation if one or more of the plurality of functional blocks writes data to the cache based on transferring the predetermined type of data between functional blocks of the first subset. The method of claim 10.

13. the plurality of functional blocks storing the predetermined type of data in an interleaved manner among each of the plurality of functional blocks; The method of claim 10.

14. the plurality of functional blocks storing the predetermined type of data in an interleaved manner among only a second subset of the plurality of functional blocks; 9. The method of claim 8.

15. 1. A computing system comprising: a memory configured to store instructions for one or more tasks and source data to be processed by said one or more tasks; an integrated circuit configured to execute the instructions using the source data; The integrated circuit comprises: a plurality of functional blocks, each functional block comprising circuitry configured to perform a task and a cache configured to store data; a power management circuit; The power management circuitry includes: assigning operational parameters to the plurality of function blocks; In response to an idle state of the plurality of function blocks, assigning a first operating parameter to one or more of the plurality of function blocks that do not store data of a predetermined type; assigning second operating parameters to one or more of the plurality of function blocks that store the predetermined type of data; and the first operating parameter results in lower power consumption than the second operating parameter; Computing system.

16. the power management circuitry is configured to transition one or more functional blocks that do not store the predetermined type of data into a sleep state.

16. The computing system of claim 15.

17. The power management circuitry includes: identifying a first subset of the plurality of functional blocks that do not utilize their corresponding caches above a threshold for storing a predetermined type of data; transferring data of the predetermined type between functional blocks of the first subset until at least one functional block of the first subset that previously stored data of the predetermined type no longer stores data of the predetermined type; configured to:

16. The computing system of claim 15.

18. the power management circuitry is configured to transfer the predetermined type of data between the functional blocks of the first subset until at least one functional block of the first subset utilizes the cache above a threshold for storing the predetermined type of data; 20. The computing system of claim 17.

19. One or more of the plurality of functional blocks When storing data in the cache, performing a write-back operation to store a copy of the data in memory; skipping execution of the write-back operation when writing data to the cache based on transferring data of the predetermined type between functional blocks of the first subset; configured to:

20. The computing system of claim 17.

20. the plurality of functional blocks are configured to store the predetermined type of data in an interleaved manner between each of the plurality of functional blocks; 20. The computing system of claim 17.

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