Microelectronic and Memory Devices

Abstract

The microelectronic device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a central sub-region and two arm sub-regions extending from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank region is horizontally outside the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is vertically below the control circuitry structure and comprises an array of memory cells within the horizontal area of ​​the bank region. Additional microelectronic and memory devices are also described.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 63 / 480,623, filed January 19, 2023, the disclosure of which is incorporated herein by this reference in its entirety.

[0002] The present disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices and associated memory devices and electronic systems. [Background technology]

[0003] Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the size of individual features and by decreasing the separation distance between adjacent features. Furthermore, microelectronic device designers often desire to design architectures that are not only compact, but also offer performance advantages, as well as simpler, easier, and less expensive to manufacture designs.

[0004] An example of a microelectronic device is a memory device. Memory devices are commonly provided as internal integrated circuits within computers or other electronic devices. There are many types of memory devices, including, but not limited to, volatile memory devices. One type of volatile memory is a dynamic random access memory (DRAM) device. A DRAM device may include memory cells including DRAM cells arranged in a first horizontally extending row and a second horizontally extending column. In one design configuration, an individual DRAM cell includes an access device (e.g., a transistor) and a storage node device (e.g., a capacitor) electrically connected to the access device. The DRAM cells of the DRAM device are accessible through digit lines and word lines arranged along the rows and columns of the memory array and are in electrical communication with a control logic device within the base control logic structure of the DRAM device.

[0005] Control logic devices within a base control logic structure underlying the memory array of a DRAM device have been used to control operations on the DRAM cells of the DRAM device. The control logic devices of the base control logic structure may be provided in electrical communication with digit lines and word lines coupled to the DRAM cells by routing and contact structures. Unfortunately, the quantity, dimensions, and placement of different control logic devices used within the base control logic structure may undesirably hinder reductions in memory device size (e.g., horizontal footprint) and / or improvements in DRAM device performance (e.g., faster memory cell ON / OFF speeds, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption). Summary of the Invention

[0006] In some embodiments, the microelectronic device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a central sub-region and two arm sub-regions extending from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length in a second horizontal direction perpendicular to the first horizontal direction than the central sub-region. The bank region is horizontally outside the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is vertically below the control circuitry structure and comprises an array of memory cells within the horizontal area of ​​the bank region.

[0007] In an additional embodiment, a microelectronic device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises street sub-regions extending substantially linearly in a first horizontal direction and additional street sub-regions extending substantially linearly in a second horizontal direction orthogonal to the first horizontal direction. The additional street sub-regions horizontally intersect the street sub-regions. The bank regions are horizontally separated from each other by the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is vertically below the control circuitry structure and comprises an array of memory cells within the horizontal area of ​​the bank region.

[0008] In a further embodiment, a memory device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a central sub-region and at least two additional sub-regions extending horizontally from the central sub-region. The bank region is horizontally adjacent to the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is attached to and vertically offset from the control circuitry structure. The memory array structure comprises an array of memory cells within the horizontal area of ​​the bank region. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a simplified schematic block diagram of a microelectronic device according to some embodiments of the present disclosure. [Figure 2A] 2 is a simplified schematic diagram of the microelectronic device of FIG. 1 showing the general layout of different regions of the microelectronic device, according to some embodiments of the present disclosure. [Figure 2B] FIG. 2B is a simplified schematic diagram of the control circuitry structure of the microelectronic device shown in FIG. 2A, illustrating the placement of various circuitry of the control circuitry structure within different regions of the microelectronic device, according to some embodiments of the present disclosure. [Figure 2C] FIG. 2C is a simplified schematic diagram of a portion of the control circuitry structure shown in FIG. 2B, illustrating the placement of some circuitry of the control circuitry structure within the portion, according to some embodiments of the present disclosure. [Figure 2D] FIG. 2B is a simplified schematic diagram of a memory array structure of the microelectronic device shown in FIG. 2A, illustrating the placement of various circuit portions of the memory array structure in different regions of the microelectronic device, according to some embodiments of the present disclosure. [Figure 2E] FIG. 2E is a simplified schematic diagram of a portion of the memory array structure shown in FIG. 2D, illustrating the placement of some circuitry of the memory array structure within the portion, according to some embodiments of the present disclosure. [Figure 3A] 1 is a simplified schematic diagram of a microelectronic device according to some embodiments of the present disclosure, illustrating the general layout of different regions of the microelectronic device. [Figure 3B] FIG. 3B is a simplified schematic diagram of the control circuitry structure of the microelectronic device shown in FIG. 3A, illustrating the placement of various circuitry of the control circuitry structure within different regions of the microelectronic device, according to some embodiments of the present disclosure. [Figure 3C] FIG. 3B is a simplified schematic diagram of a memory array structure of the microelectronic device shown in FIG. 3A, illustrating the placement of various circuit portions of the memory array structure in different regions of the microelectronic device, according to some embodiments of the present disclosure. [Figure 4] 1 is a simplified schematic block diagram of an electronic system according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following description provides specific details, such as material compositions, material shapes, and material sizes, to provide a complete description of embodiments of the present disclosure. However, those skilled in the art will understand that embodiments of the present disclosure may be practiced without using these specific details. Indeed, embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices). The structures described below do not form complete microelectronic devices. Only the process operations and structures necessary to understand embodiments of the present disclosure are described in detail below. Additional operations to form a complete microelectronic device from the structure may be performed by conventional fabrication techniques.

[0011] The drawings presented herein are for illustrative purposes only and are not meant to be actual representations of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings are expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or regions shown, but rather include, for example, deviations in shape resulting from manufacturing. For example, a region shown or described as box-shaped may have rough and / or non-linear features, and a region shown or described as rounded may include some rough and / or linear features. Furthermore, sharp angles shown may be rounded, and vice versa. Therefore, regions shown in the figures are schematic in nature, and their shapes are not intended to represent the exact shape of the regions and do not limit the scope of the claims. The drawings are not necessarily to scale. Furthermore, elements common between figures may retain the same numerical designations.

[0012] As used herein, the term "memory device" means and includes a microelectronic device that exhibits, but is not necessarily limited to, a memory function. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memories (e.g., conventional volatile memories, conventional nonvolatile memories), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoCs)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0013] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates operation of one or more of the structures and devices in a predetermined manner.

[0014] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" refer to a major plane of a structure, not necessarily defined by the Earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the major plane of the structure. The major plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to a figure, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis, parallel to the indicated "X" axis, and / or parallel to the indicated "Y" axis, and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, or perpendicular to the indicated "Y" axis.

[0015] As used herein, features (e.g., regions, structures, devices) described as "neighboring" one another refer to and include features of the disclosed entities that are located most proximate (e.g., nearest) to one another. Additional features (e.g., additional regions, additional structures, additional devices) that do not correspond to the disclosed entities of the "neighboring" features may be disposed between the "neighboring" features. In other words, "neighboring" features may be positioned directly adjacent to one another such that no other features intervene between the "neighboring" features, or "neighboring" features may be positioned indirectly adjacent to one another such that at least one feature having an entity other than that connected to the at least one "neighboring" feature is disposed between the "neighboring" features. Thus, features described as "vertically neighboring" one another refer to and include features of the disclosed entities that are located most vertically proximate (e.g., nearest) to one another. Additionally, features described as "horizontally neighboring" one another mean and include features of the disclosed entities that are located most horizontally proximate (e.g., horizontally closest) to one another.

[0016] As used herein, the term "intersection" means and includes a location where two or more features (e.g., regions, structures, materials, devices) or alternatively, two or more portions of a single feature meet. For example, an intersection between a first feature extending in a first direction (e.g., the X direction) and a second feature extending in a second direction different from the first direction (e.g., the Y direction) may be a location where the first feature and the second feature meet.

[0017] As used herein, spatially relative terms such as "beneath," "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," and "right" may be used for ease of description to describe the relationship of one element or feature illustrated in the figures to another element or feature. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if material in a figure were inverted, an element described as "below" or "beneath" or "under" or "at the bottom of" another element or feature would then be oriented "above" or "on top" of the other element or feature. Thus, the term "below" can encompass both an orientation of above and below, depending on the context in which the term is used, as would be apparent to one skilled in the art. Materials may be oriented differently (e.g., rotated 90 degrees, flipped, inverted) and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0019] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] As used herein, the phrase "coupled to" refers to structures that are operably connected to one another, such as being electrically connected through a direct ohmic connection or through an indirect connection (e.g., by another structure).

[0021] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with some variance, such as within an acceptable tolerance. By way of example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

[0022] As used herein, "about" or "approximately" in reference to a numerical value for a particular parameter includes the numerical value and a degree of variation from the numerical value that one skilled in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" in reference to a numerical value may include additional numerical values ​​in the range of 90.0% to 110.0% of the numerical value, such as within 95.0% to 105.0% of the numerical value, within 97.5% to 102.5% of the numerical value, within 99.0% to 101.0% of the numerical value, within 99.5% to 100.5% of the numerical value, and within 99.9% to 100.1% of the numerical value.

[0023] FIG. 1 is a simplified schematic block diagram of a microelectronic device 100 (e.g., a memory device such as a DRAM device) according to some embodiments of the present disclosure. The microelectronic device 100 may include a control circuitry structure (e.g., a control circuitry wafer) that vertically overlies a memory array structure (e.g., a memory array wafer). The memory array structure may include one or more arrays of memory cells (e.g., volatile memory cells such as DRAM cells). The control circuitry structure may include a control logic device formed of and including complementary metal-oxide-semiconductor (CMOS) circuitry. At least a majority of the CMOS circuitry (and thus the control logic device) of the microelectronic device 100 may be located within the control circuitry structure (and thus outside the memory array structure). Furthermore, at least a portion of the CMOS circuitry may be located vertically above, within the horizontal area of, the array of memory cells. Thus, the microelectronic device 100 may be considered to have a so-called "CMOS above array (CaA)" configuration. In some embodiments, the control circuitry structure is formed at least partially separate from the memory array structure, and then the control circuitry structure is attached to the memory array structure using oxide-oxide bonding or a combination of oxide-oxide bonding and metal-metal bonding.

[0024] 1, dashed boxes are used to identify various features (e.g., various modules, devices, circuitry) that may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100 (as opposed to being located within the vertical boundaries of the memory array structure of microelectronic device 100). All of the features (e.g., various modules, devices, circuitry) within the horizontal area of ​​each dashed box shown in FIG. 1 may be housed within the control circuitry structure of microelectronic device 100, or some of the features (e.g., some modules, devices, some circuitry) within the horizontal area of ​​each dashed box may be housed within the control circuitry structure of microelectronic device 100 and some of the features within the horizontal area of ​​each dashed box may be housed within the memory array structure of microelectronic device 100. As described in more detail below, at least the banks of memory cells of microelectronic device 100 may be housed within the memory array structure and may be in electrical communication with various control logic circuitry (e.g., CMOS circuitry) and devices housed within the control circuitry structure of microelectronic device 100.

[0025] 1, microelectronic device 100 may include an assembly of features (e.g., devices, circuitry, structures). For example, microelectronic device 100 may include memory array 102, column address decoder 104, row address decoder 106, sense amplifiers 108, word line (WL) drivers 114, command and address (CA) input circuitry 115, control register circuitry 122, voltage generator circuitry 134, internal clock and timing generator circuitry 136, data I / O and control circuitry 138, and data path circuitry 140. CA input circuitry 115 may include, but is not limited to, CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120. The control register circuitry 122 may include, but is not limited to, CA decoder circuitry 124, a mode register 126, a test mode (TM) logic circuitry 128, a self-refresh circuitry 130, and a fuse circuitry 132. The data path circuitry 140 may include, but is not limited to, input / output (I / O) logic circuitry 112 and error correction code (ECC) circuitry 141. The microelectronic device 100 may further include terminals in electrical communication with external circuitry. For example, the microelectronic device 100 may include, but is not limited to, a CA terminal 142, a control input terminal 144, a clock input terminal 146, a data terminal 148, a calibration terminal 150, a power supply terminal 152, and an alarm terminal 153. These and additional features of the microelectronic device 100 are described in further detail below. Additionally, while Figure 2 illustrates a particular configuration of microelectronic device 100, it will be appreciated that microelectronic device 100 may include additional features (e.g., additional devices, additional circuitry, additional structures), different features (e.g., different devices, different circuitry, different structures), and / or different arrangements of features than those schematically illustrated in Figure 1. Figure 1 illustrates just one non-limiting example of microelectronic device 100.

[0026] The memory array 102 may include multiple banks. Each of the banks may include multiple word lines extending in a first horizontal direction, multiple digit lines extending in a second horizontal direction orthogonal to the first horizontal direction, and multiple memory cells disposed at intersections of the word lines and digit lines. Rows of the memory cells may be coupled to the word lines, and columns of the memory cells may be coupled to the digit lines. The memory cells of the memory array 102 may comprise, for example, DRAM cells, resistive random access memory (RRAM) cells, conductive bridge random access memory (conductive bridge RAM) cells, magnetic random access memory (MRAM) cells, phase change material (PCM) memory cells, phase change random access memory (PCRAM) cells, spin-torque-transfer random access memory (STTRAM) cells, oxygen vacancy-based memory cells, programmable conductor memory cells, or other types of memory cells. In some embodiments, the memory cells of memory array 102 are DRAM cells. Memory array 102, including word lines, digit lines, and its memory cells, may be arranged within a memory array structure (e.g., a memory array wafer) of microelectronic device 100.

[0027] The column address decoder 104 may be configured and operative to select a particular digit line of the memory array 102 based on a column address signal 154 received thereby. Optionally, the microelectronic device 100 may include column repair circuitry, in electrical communication with the column address decoder 104, configured and operative to replace a defective column of memory cells of the memory array 102 with a spare, non-defective column of memory cells of the memory array 102. The column repair circuitry may convert a column address signal 154 directed to the column address decoder 104 that identifies a defective column of memory cells into another column address signal that identifies a spare, non-defective column of memory cells. The defective column of memory cells may be determined, for example, using the TM logic circuitry 128 of the microelectronic device 100. The column address decoder 104 and the column repair circuitry (if present) may be located within a control circuitry structure (e.g., a control circuitry wafer) of the microelectronic device 100.

[0028] Sense amplifiers 108 may be configured and operative to receive digit line inputs from digit lines selected by column address decoder 104 and generate digital data values ​​during read operations. Sense amplifiers 108 may be connected to respective digit lines and respective pairs of local I / O lines of I / O logic circuitry 112. Sense amplifiers 108 may be located within the control circuitry structure of microelectronic device 100.

[0029] The row address decoder 106 may be configured and operative to select a particular word line of the memory array 102 based on a row address signal 156 received thereby. Optionally, the microelectronic device 100 may include row repair circuitry, in electrical communication with the row address decoder 106, configured and operative to replace a defective row of memory cells of the memory array 102 with a spare, non-defective row of memory cells of the memory array 102. The row repair circuitry may convert the row address signal 156 directed to the row address decoder 106 that identifies the defective row of memory cells into another row address signal that identifies the spare, non-defective row of memory cells. The defective row of memory cells may be determined using, for example, the TM logic circuitry 128 of the microelectronic device 100. The row address decoder 106 and the row repair circuitry (if present) may be located within the control circuitry structure of the microelectronic device 100.

[0030] The WL driver 114 may be in electrical communication with the row address decoder 106 and may be configured and operative to activate word lines of the memory array 102 based on word line select commands received from the row address decoder 106. The memory cell lines of the memory array 102 may be accessed by access devices (e.g., transistors) of the memory cells for reading or programming by voltages placed on the word lines using the WL driver 114. The WL driver 114 may be located within a control circuitry structure of the microelectronic device 100.

[0031] 1, CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120 of CA input circuitry 115 may be disposed within the vertical boundaries of the control circuitry structure of microelectronic device 100. CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120 are each described in further detail below. CA input circuitry 115 may be operably coupled to CA terminal 142, control input terminal 144, and clock input terminal 146 of microelectronic device 100, as also described in further detail below.

[0032] CA input buffer circuitry 116 of CA input circuitry 115 may be coupled to CA terminals 142. CA terminals 142 may receive external address signals and external command signals from an external memory controller, collectively referred to herein as, but not limited to, external CA signals 158. CA input buffer circuitry 116 may receive external CA signals 158 (e.g., external address signals, external command signals) from CA terminals 142 and may generate internal address signals and internal command signals, collectively referred to herein as internal CA signals 160. Internal CA signals 160 may be provided to CA decoder circuitry 124 of control register circuitry 122. In some embodiments, CA input buffer circuitry 116 may be coupled to TM logic circuitry 128 of control register circuitry 122 and may relay commands associated with various TM functions to TM logic circuitry 128. In some such embodiments, the TM functions may be referred to as or include aspects of design-for-test (DFT) functions such as trim setting functions (e.g., latching trim conditions without programming fuses), read / write timing functions, fuse access functions, built-in-self-test (BIST) functions, and connectivity test functions.

[0033] The control input buffer circuitry 118 of the CA input circuitry 115 may be coupled to the control input terminal 144. The control input terminal 144 may receive external control signals 162 from external circuitry, such as, but not limited to, an external chip selection (CS) signal, an external clock enable (CKE) signal, an external on-die termination (ODT) signal, and an external reset signal. The control input buffer circuitry 118 may receive the external control signals 162 (e.g., an external CS signal, an external CKE signal, an external ODT signal, and an external reset signal) from the control input terminal 144 and may generate associated internal control signals 164 (e.g., an internal CS signal, an internal CKE signal, an internal ODT signal, and an internal reset signal). The internal control signals 164 may be provided to the control register circuitry 122 for performance of memory operations. For example, the internal CS signal may be used to select the microelectronic device 100 to respond to an external CA signal 158 directed to the CA terminal 142. As another example, the internal CKE signal may be used to enable clock input buffer circuitry 120 to receive various external clock signals, for which clock input buffer circuitry 120 may then act to generate various internal clock signals, as described in further detail below.

[0034] The clock input buffer circuitry 120 of the CA input circuitry 115 may be coupled to a clock input terminal 146. The clock input terminal 146 may receive an external clock signal 166 from external circuitry, such as, but not limited to, an external clock (CK) signal, an external / CK signal, an external data clock (WCK) signal, and an external / WCK signal. The external CK and external / CK signals may be complementary, and the external WCK and external / WCK signals may also be complementary. The complementary clock signals may simultaneously have opposite clock levels and transitions between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level. Clock input buffer circuitry 120 may receive an external clock signal 166 (e.g., an external CK signal, an external / CK signal, an external WCK signal, an external / WCK signal) from clock input terminal 146 and may generate an associated internal clock signal 168 (e.g., an internal CK signal, an internal / CK signal, an internal WCK signal, an internal / WCK signal), which may be provided to internal clock circuitry to provide various phase- and frequency-controlled internal clock signals based on the received internal clock signal 168.

[0035] 1 , at least a portion (e.g., substantially all) of control register circuitry 122 may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100. For example, CA decoder circuitry 124, mode register 126, TM logic circuitry 128, self-refresh circuitry 130, and fuse circuitry 132 of control register circuitry 122 may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100.

[0036] CA decoder circuitry 124 may include circuitry configured and operative to decode internal CA signals 160 from CA input buffer circuitry 116 to generate various internal signals and commands for performing memory operations. CA decoder circuitry 124 may be configured and operative for address decoding and command decoding functions. For example, CA decoder circuitry 124 may receive and decode internal address signals from CA input buffer circuitry 116, provide column address signals 154 (which may also be referred to as “decoded column address signals”) to column address decoder 104, and provide row address signals 156 (which may also be referred to as “decoded row address signals”) to row address decoder 106. CA decoder circuitry 124 may receive bank address signals and provide the bank address signals to column address decoder 104 and row address decoder 106. As another example, CA decoder circuitry 124 may receive and decode internal command signals from CA input buffer circuitry 116 and may generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting digit lines. The internal command signals may include output and input activation commands, such as clocked commands.

[0037] The mode register 126 may be configured and operative to track various counts or values ​​(e.g., counts of refresh commands received by the microelectronic device 100 or self-refresh operations performed by the microelectronic device 100). In some embodiments, a portion of the mode register 126 is configured to store operating parameters to provide flexibility in implementing various functions, features, and modes, such as the TM function.

[0038] TM logic circuitry 128 may be configured and operative to implement various TM functions defined by the manufacturer of microelectronic device 100. Such TM functions may be used only by the manufacturer and not by entities that subsequently acquire microelectronic device 100 from the manufacturer. For example, the manufacturer may implement a connectivity test designed to accelerate testing of electrical continuity of pin interconnections between microelectronic device 100 and a host device (e.g., a memory controller). TM logic circuitry 128 may be coupled to one or more mode registers 126. In some embodiments, TM logic circuitry 128 reads mode register 126 to determine a particular TM function to implement based on data stored in mode register 126. In additional embodiments, TM logic circuitry 128 stores data in mode register 126 such that other functional blocks within microelectronic device 100 implement desired functions based on the data stored in mode register 126 (e.g., data associated with various TM and / or DFT functions).

[0039] The self-refresh circuitry 130 may be in electrical communication with the row address decoder 106 and may be configured and operative to periodically recharge the data stored in the memory array 102. During a self-refresh operation, the self-refresh circuitry 130 may be activated in response to an internal command signal and may generate different row address signals that may be transferred to the row address decoder 106. The row address decoder 106 may then select a particular word line based on the different row address signals received from the self-refresh circuitry 130. The row address decoder 106 may then communicate with the WL driver 114 to activate the selected word line, and the charge stored in a storage node (e.g., a capacitor) of the memory array 102 operably coupled to the selected word line may then be amplified by a sense amplifier and then stored back on the capacitor.

[0040] Fuse circuitry 132 may include an array of fuses, which may be one-time programmable nonvolatile memory elements. In some embodiments, fuse circuitry 132 may be replaced with an array of other nonvolatile memory elements, such as metal switches, fusible capacitor devices, transistors with fusible gate oxides, NAND memory cells, PCM cells, magnetic memory cells, etc. Fuse circuitry 132 may store various operational information for microelectronic device 100 by programming one or more fuses in fuse circuitry 132, such as trim settings including specific timing and / or voltage parameters, read / write clock conditions based on read / write timing results, control bits that enable or disable customer-specific features or functions, and redundancy information used to repair portions of memory array 102. In some embodiments, the fuses in fuse circuitry 132 may exhibit a high resistance state (e.g., logic 0) upon fabrication of microelectronic device 100 (e.g., by an oxide layer disposed between two conductive layers). One or more fuses in fuse circuit portion 132 may be programmed to exhibit a low resistance state (e.g., logic 1) upon application of a fuse programming voltage or current across one or more fuses (e.g., by physically altering an oxide layer with electrical stress so that the two conductive layers are connected by a conductive path). Thus, once a fuse is programmed (e.g., the oxide layer is broken to exhibit a low resistance state, logic 1), the programmed fuses may not be in an unprogrammed state (e.g., to restore their original high resistance state, logic 0). Such fuses may be referred to as antifuses.

[0041] 1, control register circuitry 122 may generate column address signals 154 and row address signals 156 that are provided to column address decoder 104 and row address decoder 106, respectively. As discussed hereinabove, row address decoder 106 may be coupled to WL drivers 114 that activate respective rows of memory cells in memory array 102 that correspond to the received row addresses. Additionally, selected digit lines corresponding to the received column addresses may be coupled by I / O data bus 170 to read / write circuitry that provides read data to data output buffers of I / O logic circuitry 112. Write data may be applied to memory array 102 through I / O logic circuitry 112 and data input buffers of the read / write circuitry.

[0042] The control register circuitry 122 may be in electrical communication with the alarm terminal 153 and, if a particular error is detected, may provide an alarm signal 172 to external circuitry (e.g., a system processor, a controller) in electrical communication with the alarm terminal 153. As a non-limiting example, the alarm signal 172 may be transmitted from the microelectronic device 100 if a cyclic redundancy check (CRC) error is detected.

[0043] Voltage generator circuitry 134 may be coupled to power supply terminals 152. Power supply terminals 152 may receive various potentials 174 from external circuitry, such as, but not limited to, a drain supply voltage (VDD) potential, a supply voltage (VCC) potential, and a ground (VSS) potential. Voltage generator circuitry 134 generates various internal potentials 176, such as, but not limited to, a pump precharge (VPP) potential (or read / write bias potential), a VOD potential, an array voltage (VARY) potential, a peripheral voltage (VPERI) potential, and a VPOP potential. As non-limiting examples, the VPP potential may be used for row address decoder 106, the VOD and VARY potentials may be used for sense amplifiers 108, the VPERI potential may be used for other circuitry blocks, and the VPOP potential may be used for fuse circuitry 132. Power supply terminals 152 and voltage generator circuitry 134 may be supplied with an output driver supply (VDDQ) potential and a VSSQ potential. VDDQ and VSSQ potentials may be supplied to data I / O and control circuitry 138. The VDDQ and VSSQ potentials may be the same as the VDD and VSS potentials, respectively, but the VDDQ and VSSQ potentials may be used for data I / O and control circuitry 138 so that power supply noise generated by data I / O and control circuitry 138 does not propagate to other circuitry. Voltage generator circuitry 134 may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100.

[0044] The internal clock and timing generator circuitry 136 may be configured to receive a clock signal (e.g., an internal clock signal, an external clock signal) and, in response, generate a phase-controlled internal clock signal 178. Without limitation, one or more of delay lock loop (DLL) circuitry and phase lock loop (PLL) circuitry may be used for the internal clock and timing generator circuitry 136. The DLL circuitry and PLL circuitry may serve similar purposes and may be used, respectively, to maintain constant timing relationships between signals in environments where process, voltage, and temperature variations cause these relationships to change over time. During operation, the DLL circuitry and PLL circuitry may continuously compare the relationship between two signals and provide feedback to adjust and maintain the constant relationship between the two signals. The DLL circuitry and PLL circuitry may be used to maintain the timing relationship between a clock signal and an output data signal. Maintaining the timing relationship between the clock and output data by the DLL circuitry and PLL circuitry provides improved timing margins and facilitates faster signaling speeds. In some embodiments, the internal clock and timing generator circuitry 136 includes at least DLL circuitry. The DLL circuitry may include, but is not limited to, one or more (e.g., each) of a DLL differential delay line and delay selection logic circuit, a DLL clock phase interpolator circuit, a DLL output clock comparator circuit, a DLL output circuit, a DLL phase detector circuit, a DLL clock inversion control circuit, a DLL control (coarse and fine control) logic circuit, a DLL bias generator control circuit, a DLL auto-reset block circuit, a DLL enable logic circuit, a bit line jitter circuit, and an Ltree stage circuit. The phase-controlled internal clock signal 178 generated by the internal clock and timing generator circuitry 136 may be provided to the data I / O and control circuitry 138, for example, and may be used as a timing signal to determine the output timing of read data.The internal clock and timing generator circuitry 136 may be located within the vertical boundaries of the control circuitry structure of the microelectronic device 100 .

[0045] Data I / O and control circuitry 138, which may be referred to herein as data queue (DQ) circuitry, may be coupled to data terminals 148 (e.g., DQ terminals, read data strobe (RDQS) terminals, data bus inversion (DBI) terminals, DMI terminals) and calibration terminals 150 (e.g., ZQ terminals). Additionally, data I / O and control circuitry 138 may be in electrical communication with control register circuitry 122, voltage generator circuitry 134, internal clock and timing generator circuitry 136, and data path circuitry 140. Data I / O and control circuitry 138 may receive and provide data signals 180 (e.g., DQ signals such as read DQ signals and write DQ signals, DBI signals, DMI signals) to data terminals 148 in response to different commands (e.g., read commands, write commands). Additionally, data I / O and control circuitry 138 may communicate with ECC circuitry 141 of data path circuitry 140 over global I / O data bus 186. Additionally, data I / O and control circuitry 138 may receive and act on, but is not limited to, phase-controlled internal clock signal 178 from internal clock and timing generator circuitry 136, calibration signal 182 from calibration terminal 150, and I / O control signal 184 from control register circuitry 122. The data I / O and control circuitry 138 may include, but is not limited to, read circuitry, write circuitry, write parallelization, read training control, input buffer circuitry, input buffer latch circuitry, decision feedback equalizer (DFE) circuitry, device interface board (DIB) circuitry, DQ shift (data queue pin connection / shifter) circuitry, data queue strobe (DQS) circuitry, DQS receiver path circuitry, phase generator circuitry, DCC circuitry, DCRC circuitry, clock and power control circuitry, read control circuitry, data serializer circuitry, and data output buffer circuitry. The data I / O and control circuitry 138 may be located within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

[0046] 1 , at least a portion (e.g., substantially all) of datapath circuitry 140 may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100. For example, I / O logic circuitry 112 and ECC circuitry 141 of datapath circuitry 140 may be located within the vertical boundaries of the control circuitry structure of microelectronic device 100.

[0047] I / O logic circuitry 112 may be configured and operative to receive data from digit lines selected by column address decoder 104 during read operations and to output data to digit lines selected by column address decoder 104 during write operations. During read operations, digital data values ​​generated by sense amplifiers 108 may be provided to data output buffers of I / O logic circuitry 112 over I / O data bus 170. Additionally, during write operations, write data from data input buffers of I / O logic circuitry 112 may be provided to memory array 102 over I / O data bus 170.

[0048] ECC circuitry 141 may be configured and operative to generate ECC codes (also known as “check bits”). The ECC codes may correspond to particular data values ​​and may be stored along with the data values ​​in memory cells of memory array 102. When the data values ​​are read back from the memory cells, another ECC code is generated and compared to the previously generated ECC code to access the memory cells. If non-zero, the difference between the previously generated ECC code and the newly generated ECC code indicates that an error has occurred. If an error condition is detected, ECC circuitry 141 may then be utilized to correct the erroneous data. ECC circuitry 141 may be in electrical communication with I / O logic circuitry 112 via intermediate I / O data bus 188 and with data I / O and control circuitry 138 via global I / O data bus 186.

[0049] During use and operation of microelectronic device 100, when a read command is issued and a row address and a column address are supplied in a timely manner by the read command, read data can be read from a memory cell in memory array 102 specified by the row address and column address. The read command can be received by CA decoder circuitry 124, which can provide an internal command to data I / O and control circuitry 138 to cause read / write amplifiers and data I / O and control circuitry 138 to output read data from data terminals 148 (e.g., data queue (DQ) terminals, read data strobe (RDQS) terminals, data bus inversion (DBI) terminals, DMI terminals) in accordance with a clock signal (e.g., an internal CK signal, an internal / CK signal). The read data can be provided at a time defined by read latency information that can be programmed in mode register 126 within microelectronic device 100. The read latency information can be defined in terms of clock periods of the clock signal. For example, the read latency information can be the number of clock periods of a signal after a read command is received by the microelectronic device 100 when the associated read data is provided.

[0050] Furthermore, during use and operation of microelectronic device 100, when a write command is issued and a row address and column address are provided in a timely manner by the write command, write data may be provided to data terminals 148 (e.g., data queue (DQ) terminals, read data strobe (RDQS) terminals, data bus inversion (DBI) terminals, DMI terminals) according to other clock signals (e.g., an internal WCK signal, an internal / WCK signal). The write command may be received by CA decoder circuitry 124, which may provide an internal command to data I / O and control circuitry 138 so that the write data is received by a data receiver within data I / O and control circuitry 138 and provided to memory array 102 by data I / O and control circuitry 138 and read / write amplifiers. The write data may be written to memory cells specified by the row address and column address. The write data may be provided to data terminals 148 at a time defined by write latency information. The write latency information may be programmed in the mode register 126 within the microelectronic device 100. The write latency information may be defined in terms of clock periods of a clock signal. For example, the write latency information may be the number of clock periods of a signal after a write command is received by the microelectronic device 100 when associated write data is received.

[0051] 2A-2E are simplified schematic diagrams of different portions of the microelectronic device 100 shown in FIG. 1 according to some embodiments of the present disclosure. FIG. 2A is a simplified schematic diagram of the microelectronic device 100 according to some embodiments of the present disclosure, showing the overall layout (e.g., floor plan) of different regions of the microelectronic device 100. FIG. 2B is a simplified schematic diagram of a control circuitry structure 200 of the microelectronic device 100 according to some embodiments of the present disclosure, showing the placement of various circuit portions of the control circuitry structure 200 within different regions of the microelectronic device 100. FIG. 2C is a simplified schematic diagram of portion A (indicated by the dashed box in FIG. 2B) of the control circuitry structure 200 shown in FIG. 2B according to some embodiments of the present disclosure, showing the placement of some circuit portions of the control circuitry structure 200 within portion A. 2D is a simplified schematic diagram of a memory array structure 300 of a microelectronic device 100 according to some embodiments of the present disclosure, illustrating the placement of various circuit portions of the memory array structure 300 within different regions of the microelectronic device 100. FIG. 2E is a simplified schematic diagram of portion B (indicated by the dashed box in FIG. 2D) of the memory array structure 300 shown in FIG. 2D according to some embodiments of the present disclosure, illustrating the placement of some circuit portions of the memory array structure 300 within portion B.

[0052] Referring to FIG. 2A, microelectronic device 100 may include a peripheral circuitry region 202 and a bank region 204. As described in further detail below, within control circuitry structure 200 (FIG. 2B), relatively speed-critical circuitry and devices may be arranged within the horizontal area of ​​peripheral circuitry region 202, and relatively non-speed-critical circuitry and devices may be arranged within the horizontal area of ​​bank region 204. The relatively speed-critical circuitry and devices of control circuitry structure 200 (FIG. 2B) include, for example, data bus (DB) circuitry, data bus strobe (DQS) circuitry, delay-locked loop (DLL) circuitry, phase-locked loop (PLL) circuitry, and command-address (CA) circuitry. The relatively non-speed-critical circuitry and devices of control circuitry structure 200 (FIG. 2B) include, for example, antifuse circuitry, repair circuitry, voltage generator circuitry, analog temperature distribution circuitry, and data junction multiplexer circuitry. The bank region 204 may include a first bank region 204A (e.g., an upper bank region) and a second bank region 204B (e.g., a lower bank region). The peripheral circuit region 202 may be interposed between the first bank region 204A and the second bank region 204B in the horizontal direction (e.g., in the Y direction).

[0053] The peripheral circuitry region 202 of the microelectronic device 100 may include a central subregion 202A, a first arm subregion 202B, and a second arm subregion 202C. As shown in FIG. 2A , the central subregion 202A may be integral with and connected to the first arm subregion 202B and the second arm subregion 202C and may be horizontally interposed between the first arm subregion 202B and the second arm subregion 202C in the X direction (e.g., a first horizontal direction). The first arm subregion 202B and the second arm subregion 202C may be disposed at or proximate to opposite corners (e.g., diagonally opposite corners) of the central subregion 202A relative to one another. For example, the first arm sub-region 202B may be disposed at or proximate a first corner of the central sub-region 202A, and the second arm sub-region 202C may be disposed at or proximate a second corner of the central sub-region 202A that is diagonally across (e.g., at a kitty corner) from the first corner. Thus, the peripheral circuitry region 202 may extend in a non-linear path in the X direction across the microelectronic device 100.

[0054] As shown in FIG. 2A , the central sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C may exhibit rectangular horizontal cross-sectional shapes that, in combination, provide the peripheral circuitry region 202 with an irregular horizontal cross-sectional shape. The rectangular horizontal cross-sectional shape of the central sub-region 202A may be different from the rectangular horizontal cross-sectional shapes of the first arm sub-region 202B and the second arm sub-region 202C. The rectangular horizontal cross-sectional shapes of the first arm sub-region 202B and the second arm sub-region 202C may be substantially the same as each other or may be different from each other. In some embodiments, the rectangular horizontal cross-sectional shapes of the first arm sub-region 202B and the second arm sub-region 202C are substantially the same as each other.

[0055] In some embodiments, the horizontal center of the central subregion 202A of the peripheral circuitry region 202 is substantially aligned with the horizontal center of the microelectronic device 100. For example, the horizontal centerline of the central subregion 202A in the Y direction may be substantially aligned with the horizontal centerline 210 of the microelectronic device 100 in the Y direction, and an additional horizontal centerline of the central subregion 202A in the X direction may be substantially aligned with the additional horizontal centerline 212 of the microelectronic device 100 in the X direction. The horizontal centerline 210 of the microelectronic device 100 in the Y direction may extend substantially linearly in the X direction, and the additional horizontal centerline 212 of the microelectronic device 100 in the X direction may extend substantially linearly in the Y direction. In additional embodiments, the horizontal center of the central subregion 202A of the peripheral circuitry region 202 is offset from the horizontal center of the microelectronic device 100. For example, the horizontal centerline in the Y direction of the central subregion 202A may be offset from the horizontal centerline in the Y direction 210 of the microelectronic device 100, and / or the additional horizontal centerline in the X direction of the central subregion 202A may be offset from the additional horizontal centerline in the X direction 212 of the microelectronic device 100.

[0056] The horizontal centers of the first arm sub-region 202B and the second arm sub-region 202C of the peripheral circuitry region 202 are offset from the horizontal center of the microelectronic device 100. The horizontal centerline in the Y direction of the first arm sub-region 202B may be offset from the horizontal centerline in the Y direction 210 of the microelectronic device 100 and the horizontal centerlines in the Y direction of each of the central sub-region 202A and the second arm sub-region 202C. The additional horizontal centerline in the X direction of the first arm sub-region 202B may be offset from the additional horizontal centerline in the X direction 212 of the microelectronic device 100 and the additional horizontal centerlines in the X direction of each of the central sub-region 202A and the second arm sub-region 202C. Furthermore, a horizontal centerline in the Y direction of the second arm sub-region 202C may be offset from a horizontal centerline in the Y direction 210 of the microelectronic device 100 and from the horizontal centerlines in the Y direction of each of the central sub-region 202A and the first arm sub-region 202B. An additional horizontal centerline in the X direction of the second arm sub-region 202C may be offset from an additional horizontal centerline in the X direction 212 of the microelectronic device 100 and from the additional horizontal centerlines in the X direction of each of the central sub-region 202A and the first arm sub-region 202B. In some embodiments, the horizontal centerlines in the Y direction of the first arm sub-region 202B and the second arm sub-region 202C are offset from the horizontal centerline in the Y direction of the central sub-region 202A by substantially the same horizontal distance (e.g., in the positive Y direction for the first arm sub-region 202B and in the negative Y direction for the second arm sub-region 202C). In additional embodiments, the horizontal centerlines in the Y direction of the first arm sub-region 202B and the second arm sub-region 202C are offset from the horizontal centerline in the Y direction of the central sub-region 202A by different horizontal distances.

[0057] 2A , the central subregion 202A of the peripheral circuitry region 202 has a first length L1 in the Y direction and a first width W1 in the X direction, the first arm subregion 202B of the peripheral circuitry region 202 has a second length L2 in the Y direction and a second width W2 in the X direction, and the second arm subregion 202C of the peripheral circuitry region 202 has a third length L3 in the Y direction and a third width W3 in the X direction. The first length L1 of the central subregion 202A may be greater than each of the second length L2 of the first arm subregion 202B and the third length L3 of the second arm subregion 202C. In some embodiments, the first length L1 of the central subregion 202A is greater than the combined length of the second length L2 of the first arm subregion 202B and the third length L3 of the second arm subregion 202C. The second length L2 of the first arm sub-region 202B may be substantially equal to the third length L3 of the second arm sub-region 202C, or the second length L2 of the first arm sub-region 202B may be different from the third length L3 of the second arm sub-region 202C. Furthermore, the first width W1 of the central sub-region 202A, the second width W2 of the first arm sub-region 202B, and the third width W3 of the second arm sub-region 202C may be substantially equal to one another, or at least one of the first width W1 of the central sub-region 202A, the second width W2 of the first arm sub-region 202B, and the third width W3 of the second arm sub-region 202C may be different (larger or smaller) than at least one other width (e.g., one other width, two other widths) of the central sub-region 202A, the second width W2 of the first arm sub-region 202B, and the second arm sub-region 202C. In some embodiments, the width W1 of the central sub-region 202A, the second width W2 of the first arm sub-region 202B, and the third width W3 of the second arm sub-region 202C are substantially equal to one another. In some embodiments, the second width W2 of the first arm sub-region 202B and the third width W3 of the second arm sub-region 202C are substantially equal to each other and different from (e.g., larger or smaller than) the width W1 of the central sub-region 202A.

[0058] 2A , bank regions 204 (e.g., first bank region 204A, second bank region 204B) may individually include a combination of first bank sub-regions 206 and second bank sub-regions 208. As described in further detail below, within the memory array structure 300 ( FIG. 2D ) of microelectronic device 100, banks of memory cells may be arranged within the horizontal areas of the first bank sub-regions 206 and second bank sub-regions 208 of bank region 204. The first bank sub-regions 206 may have a different horizontal geometry (e.g., different horizontal dimensions, different horizontal shape) than the second bank sub-regions 208. For example, each first bank sub-region 206 may be relatively longer in the Y direction and relatively narrower in the X direction than each second bank sub-region 208. However, as described in further detail below, the amount of memory cells in a bank of memory cells within the horizontal area of ​​each first bank sub-region 206 may be substantially equal to the amount of memory cells in an additional bank of memory cells within the horizontal area of ​​each second bank sub-region 208.

[0059] The bank regions 204 (e.g., first bank region 204A, second bank region 204B) of the microelectronic device 100 each include a group of first bank sub-regions 206 and a group of second bank sub-regions 208. For example, the first bank region 204A may include a group of first bank sub-regions 206 and a group of second bank sub-regions 208 horizontally adjacent to the group of first bank sub-regions 206 in the X direction (e.g., the positive X direction), and the second bank region 204B may include an additional group of first bank sub-regions 206 and an additional group of second bank sub-regions 208 horizontally adjacent to the additional group of first bank sub-regions 206 in the X direction (e.g., the negative X direction). For an individual bank region 204, the combination of its group of first bank sub-regions 206 and its group of second bank sub-regions 208 may provide the bank region 204 with an irregular horizontal cross-sectional shape, such as an “L-shaped” horizontal cross-sectional shape. The horizontal cross-sectional shape of the first bank region 204A (e.g., L-shaped horizontal cross-sectional shape) may be inverted (e.g., flipped) in the X direction relative to the horizontal cross-sectional shape of the second bank region 204B (e.g., L-shaped horizontal cross-sectional shape).

[0060] 2A, the group of first bank sub-regions 206 in the first bank region 204A may be completely horizontally offset in the X direction from the additional group of first bank sub-regions 206 in the second bank region 204B, and the group of first bank sub-regions 206 in the first bank region 204A may partially (e.g., not completely) overlap the additional group of first bank sub-regions 206 in the Y direction. Further, as shown in FIG. 2A, the group of second bank sub-regions 208 in the first bank region 204A may be completely horizontally offset in the Y direction from the additional group of second bank sub-regions 208 in the second bank region 204B, and the group of second bank sub-regions 208 in the first bank region 204A may partially (e.g., not completely) overlap the additional group of second bank sub-regions 208 in the X direction.

[0061] The central sub-region 202A of the peripheral circuit region 202 may be horizontally interposed in the X direction between the group of first bank sub-regions 206 of the first bank region 204A and the additional group of first bank sub-regions 206 of the second bank region 204B, and may partially (e.g., not completely) horizontally overlap each of the group of first bank sub-regions 206 of the first bank region 204A and the additional group of first bank sub-regions 206 of the second bank region 204B in the Y direction. Furthermore, the central sub-region 202A of the peripheral circuit region 202 may be horizontally interposed in the Y direction between the group of second bank sub-regions 208 of the first bank region 204A and the additional group of second bank sub-regions 208 of the second bank region 204B, and may partially (e.g., not completely) horizontally overlap each of the group of second bank sub-regions 208 of the first bank region 204A and the additional group of second bank sub-regions 208 of the second bank region 204B in the X direction.

[0062] The second arm sub-region 202C of the peripheral circuit region 202 may be horizontally interposed in the Y direction between the group of first bank sub-regions 206 of the first bank region 204A and the additional group of second bank sub-regions 208 of the second bank region 204B, and may overlap in the X direction with the group of first bank sub-regions 206 of the first bank region 204A and the additional group of second bank sub-regions 208 of the second bank region 204B. Furthermore, the first arm sub-region 202B of the peripheral circuit region 202 may be horizontally interposed in the Y direction between the additional group of first bank sub-regions 206 of the second bank region 204B and the group of second bank sub-regions 208 of the first bank region 204A, and may overlap in the X direction with the additional group of first bank sub-regions 206 of the second bank region 204B and the group of second bank sub-regions 208 of the first bank region 204A.

[0063] The first bank sub-regions 206 and the second bank sub-regions 208 of a bank region 204 (e.g., first bank region 204A, second bank region 204B) of the microelectronic device 100 may exhibit rectangular horizontal cross-sectional shapes. Each of the first bank sub-regions 206 may exhibit substantially the same rectangular horizontal cross-sectional shapes as one another, and each of the second bank sub-regions 208 may exhibit substantially the same rectangular horizontal cross-sectional shapes as one another. The rectangular horizontal cross-sectional shapes of each of the first bank sub-regions 206 may be different from the rectangular horizontal cross-sectional shapes of each of the second bank sub-regions 208.

[0064] 2A , each of the first bank sub-regions 206 may have a fourth length L4 in the Y direction and a fourth width W4 in the X direction, and each of the second bank sub-regions 208 may have a fifth length L5 in the Y direction and a fifth width W5 in the X direction. The fourth length L4 of each of the first bank sub-regions 206 may be greater than the fifth length L5 of each of the second bank sub-regions 208. In some embodiments, the fourth length L4 of each of the first bank sub-regions 206 is approximately twice (2×) greater than the fifth length L5 of each of the second bank sub-regions 208. Furthermore, the fourth width W4 of each of the first bank sub-regions 206 may be less than the fifth width W5 of each of the second bank sub-regions 208. In some embodiments, the fifth width W5 of each of the second bank sub-regions 208 is approximately two times (2×) greater than the fourth width W4 of each of the first bank sub-regions 206.

[0065] The bank regions 204 (e.g., first bank region 204A, second bank region 204B) may individually include a desired amount of first bank sub-regions 206 and a desired amount of second bank sub-regions 208. As shown in FIG. 2A , in some embodiments, the first bank region 204A includes one group of four (4) first bank sub-regions 206 and one group of four (4) second bank sub-regions 208, and the second bank region 204B includes one additional group of four (4) first bank sub-regions 206 and one additional group of four (4) second bank sub-regions 208. In additional embodiments, one or both (e.g., each) of the first bank region 204A and the second bank region 204B includes a different amount of first bank sub-regions 206 (e.g., more than four (4) first bank sub-regions 206, fewer than four (4) first bank sub-regions 206) and / or a different amount of second bank sub-regions 208 (e.g., more than four (4) second bank sub-regions 208, fewer than four (4) second bank sub-regions 208). For each bank region 204, the amount of its first bank sub-regions 206 may be substantially the same as the amount of its second bank sub-regions 208, or the amount of its first bank sub-regions 206 may be different (e.g., less than or greater than) the amount of its second bank sub-regions 208. Furthermore, the first bank region 204A and the second bank region 204B may have substantially the same amount of first bank sub-regions 206 and substantially the same amount of second bank sub-regions 208 as each other, or the first bank region 204A and the second bank region 204B may have different amounts of first bank sub-regions 206 and / or different amounts of second bank sub-regions 208 as each other.

[0066] Referring now to Figure 2B, an exemplary arrangement of various circuitry of control circuitry structure 200 within horizontal areas of peripheral circuitry region 202 and bank region 204 of microelectronic device 100 is shown. For ease of illustration and understanding of the drawings and associated discussion, not all features of microelectronic device 100 described above with reference to Figure 2A are shown in Figure 2B. However, it will be understood that any feature of microelectronic device 100 described with reference to one or more of Figures 2A-2E is applicable to one or more (e.g., all) of the other Figures 2A-2E.

[0067] As described hereinabove, within the horizontal area of ​​peripheral circuitry region 202 of microelectronic device 100, control circuitry structure 200 may house relatively speed-critical circuitry and devices. For example, within the horizontal area of ​​peripheral circuitry region 202 of microelectronic device 100, control circuitry structure 200 may include, but is not limited to, a data I / O and control section 214, an internal clock and timing generator section 216, a command and address (CA) section 218, a fuse section 220, a capacitor section 222, a voltage generator section 224, an analog section 226, a data junction section 228, and a package interface section 230. The above sections and their arrangement within the horizontal area of ​​peripheral circuitry region 202 of microelectronic device 100 are described in further detail below.

[0068] The data I / O and control section 214 of the control circuitry structure 200 may include the data I / O and control circuitry 138 described above with reference to FIG. 1. As a non-limiting example, the data I / O and control section 214 may include one or more (e.g., each) of a read circuit, a write circuit, write parallelism, read training control, an input buffer circuit, an input buffer latch circuit, a DFE circuit, a DIB circuit, a DQ shift circuit, a DQS circuit, a DQS receiver path circuit, a phase generator circuit, a DCC circuit, a DCRC circuit, a clock and power control circuit, a read control circuit, a data serializer circuit, and a data output buffer circuit. As shown in FIG. 2B, the data I / O and control section 214 may be located within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The data I / O and control section 214 may be located proximate to the horizontal center of the central sub-region 202A. In some embodiments, the data I / O and control section 214 is located proximate to a horizontal center of the microelectronic device 100 defined by the intersection of a horizontal centerline 210 in the Y direction of the microelectronic device 100 and an additional horizontal centerline 212 in the X direction of the microelectronic device 100. The data I / O and control circuitry 138 (FIG. 1) in a first half (e.g., above the horizontal centerline 210) of the data I / O and control section 214 of the control circuitry structure 200 may be utilized for a bank of memory cells of the memory array structure 300 (FIG. 2D) disposed within the horizontal area of ​​the first bank region 204A of the microelectronic device 100, and the data I / O and control circuitry 138 (FIG. 1) with a second half (e.g., below the horizontal centerline 210) of the data I / O and control section 214 of the control circuitry structure 200 may be utilized for an additional bank of memory cells of the memory array structure 300 (FIG. 2D) disposed within the horizontal area of ​​the second bank region 204B of the microelectronic device 100.

[0069] The internal clock and timing generator section 216 of the control circuitry structure 200 may include the internal clock and timing generator circuitry 136 described above with reference to FIG. 1. As a non-limiting example, the internal clock and timing generator section 216 may include one or more (e.g., each) of a DLL differential delay line and delay selection logic circuit, a DLL clock phase interpolator circuit, a DLL output clock comparator circuit, a DLL output circuit, a DLL phase detector circuit, a DLL clock inversion control circuit, a DLL control (coarse control and fine control) logic circuit, a DLL bias generator control circuit, a DLL auto-reset block circuit, a DLL enable logic circuit, a bitline jitter circuit, and an Ltree stage circuit. As shown in FIG. 2B, the internal clock and timing generator section 216 may be located within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The internal clock and timing generator section 216 may be located proximate to the horizontal center of the central sub-region 202A. In some embodiments, the internal clock and timing generator section 216 is located proximate to a horizontal center of the microelectronic device 100 defined by the intersection of the horizontal centerline 210 of the microelectronic device 100 in the Y direction and the additional horizontal centerline 212 of the microelectronic device 100 in the X direction. The internal clock and timing generator section 216 may be offset in the X direction from the data I / O and control section 214. For example, the internal clock and timing generator section 216 may be located horizontally on one side of the additional horizontal centerline 212 of the microelectronic device 100 in the X direction, and the data I / O and control section 214 may be located horizontally on another side of the additional horizontal centerline 212 of the microelectronic device 100 in the X direction.

[0070] The CA section 218 of the control circuitry structure 200 may include the CA input circuitry 115 and the CA decoder circuitry 124 described above with reference to FIG. 1. As a non-limiting example, the CA section 218 may include one or more (e.g., each) of a column address buffer circuit, a central driver circuit, an EpprMode register circuit, a Pcc control Wck circuit, an Ecs control circuit, a QED shifter circuit, a Clkgen refresh circuit, a column controller circuit, a command extender circuit, an Act_pre_cntl circuit, and a BARArray timer circuit. As shown in FIG. 2B, the CA section 218 may be disposed within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202. As a non-limiting example, two (2) CA sections 218 may be disposed within the central sub-region 202A of the peripheral circuitry region 202 at opposite horizontal boundaries of the internal clock and timing generator section 216 in the X direction. One of the CA sections 218 may be interposed horizontally in the X direction between the data I / O and control section 214 and the internal clock and timing generator section 216, and another of the CA sections 218 may be interposed horizontally in the X direction between the internal clock and timing generator section 216 and the fuse section 220. As another non-limiting example, the control circuitry structure 200 may include a single (e.g., only one) CA section 218 within a horizontal area of ​​the central subregion 202A of the peripheral circuitry region 202 of the microelectronic device 100. The single CA section 218 may be disposed horizontally in the X direction between the data I / O and control section 214 and the internal clock and timing generator section 216, or may be disposed horizontally in the X direction between the internal clock and timing generator section 216 and the fuse section 220.

[0071] 2B , the fuse section 220 of the control circuitry structure 200 may include the fuse circuitry 132 (e.g., antifuse circuitry) described above with reference to FIG. 1. The fuse section 220 may be disposed within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) fuse sections 220 may be disposed within the central sub-region 202A of the peripheral circuitry region 202. One (1) of the fuse sections 220 may be disposed at or proximate to the horizontal boundary of the data I / O and control section 214 and may be horizontally interposed in the X-direction between the data I / O and control section 214 and the first bank sub-region 206 of the first bank region 204A. Another one of the fuse sections 220 may be located at or near the horizontal boundary of one of the CA sections 218 adjacent to the internal clock and timing generator section 216, or may be horizontally interposed in the X-direction between the CA section 218 and the first bank sub-region 206 of the second bank region 204B. As another non-limiting example, the control circuitry structure 200 may include a single (e.g., only one) fuse section 220 within the horizontal area of ​​the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The single fuse section 220 may be located horizontally in the X-direction between the data I / O and control section 214 and the first bank sub-region 206 of the first bank region 204A, or may be located horizontally in the X-direction between one of the CA sections 218 and the first bank sub-region 206 of the second bank region 204B.

[0072] The capacitor section 222 of the control circuitry structure 200 may include circuitry (e.g., capacitors) constructed and arranged to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 100. For example, capacitor section 222 may include capacitors for a charge pump, an RC filter, capacitors for peaking amplifiers, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), and decoupling capacitors, as well as capacitors for powering one or more control logic devices, such as one or more digital signal acquisition (DSA) devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQU, DQL), one or more command address devices, one or more antifuse devices, one or more DLL devices, one or more delay enable devices (e.g., one or more dQ enable delay devices), one or more temperature sensors, one or more data junctions for conducting data to / from memory banks, and one or more additional control logic devices. The capacitors in capacitor section 222 of control circuitry structure 200 may be coupled to back-end-of-line (BEOL) structures of microelectronic device 100 .

[0073] The capacitor section 222 of the control circuitry structure 200 may be disposed within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) capacitor sections 222 may be disposed within the central sub-region 202A of the peripheral circuitry region 202. One (1) of the capacitor sections 222 may be disposed at or proximate to a first horizontal boundary in the Y direction of the data I / O and control section 214, the internal clock and timing generator section 216, the CA section 218, and the fuse section 220. Another (1) of the capacitor sections 222 may be disposed at or proximate to a second horizontal boundary in the Y direction of the data I / O and control section 214, the internal clock and timing generator section 216, the CA section 218, and the fuse section 220. Two (2) capacitor sections 222 are adjacent in the Y direction to the data I / O and control section 214, the internal clock and timing generator section 216, the CA section 218, and the fuse section 220. The capacitor sections 222 may individually horizontally overlap in the X direction each of the data I / O and control section 214, the internal clock and timing generator section 216, the CA section 218, and the fuse section 220. The capacitor sections 222 may individually extend horizontally in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the central subregion 202A of the peripheral circuitry region 202.

[0074] 2B , the voltage generator section 224 of the control circuitry structure 200 may include the voltage generator circuitry 134 described above with reference to FIG. 1 . The voltage generator section 224 may be disposed within a horizontal area of ​​a central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) voltage generator sections 224 may be disposed within the central sub-region 202A of the peripheral circuitry region 202. One (1) of the voltage generator sections 224 may be disposed at or near a horizontal boundary in the Y direction of one (1) of the capacitor sections 222, and another (1) of the voltage generator sections 224 may be disposed at or near a horizontal boundary in the Y direction of another (1) of the capacitor sections 222. The two (2) voltage generator sections 224 may be adjacent to the two (2) capacitor sections 222 in the Y direction. The voltage generator sections 224 may individually horizontally overlap in the X-direction the capacitor section 222 and each of the data I / O and control section 214, the internal clock and timing generator section 216, the CA section 218, and the fuse section 220. The voltage generator sections 224 may individually extend horizontally in the X-direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the central subregion 202A of the peripheral circuitry region 202.

[0075] The analog section 226 of the control circuitry structure 200 may include one or more of analog temperature distribution circuitry and circuitry configured to operate on and / or generate analog voltage signals during use and operation of the microelectronic device 100. By way of non-limiting example, the analog section 226 may include one or more circuits (analog temperature distribution circuits) that use analog components to control one or more temperatures of the microelectronic device 100. Such circuits include, for example, temperature sensors (e.g., thermistors, thermocouples) and amplifiers constructed and arranged to amplify the output of the temperature sensors. The amplified signals may be used to control one or more heating and cooling elements to maintain a desired temperature of the microelectronic device 100. As another example, the analog section 226 may include analog-to-digital conversion (ADC) devices and / or digital-to-analog conversion (DAC) devices in operative communication with the data I / O and control circuitry 138 and memory cells of the microelectronic device 100 described above with reference to FIG. 1 .

[0076] The analog sections 226 of the control circuitry structure 200 may be disposed within the horizontal areas of first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry region 202 may include two (2) analog sections 226 within its horizontal area, with one (1) of the analog sections 226 disposed within the first arm sub-region 202B and another (1) of the analog sections 226 disposed within the second arm sub-region 202C. The analog section 226 in the first arm sub-region 202B may overlap horizontally in the X-direction with the first bank sub-region 206 of the second bank region 204B, and the analog section 226 in the second arm sub-region 202C may overlap horizontally in the X-direction with the first bank sub-region 206 of the first bank region 204A. The analog section 226 in the first arm sub-region 202B may extend in the X-direction across at least a majority (e.g., greater than 50 percent, greater than 75 percent, greater than 90 percent, greater than 95 percent) of the first arm sub-region 202B, and the analog section 226 in the second arm sub-region 202C may extend in the X-direction across at least a majority (e.g., greater than 50 percent, greater than 75 percent, greater than 90 percent, greater than 95 percent) of the second arm sub-region 202C. In some embodiments, the analog section 226 at least partially horizontally overlaps, in the Y direction, the capacitor section 222 of the control circuitry structure 200 within the horizontal area of ​​the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100.

[0077] The data junction section 228 of the control circuitry structure 200 may include multiplexer (MUX) circuitry configured and operative to select one of several input signals and then route the selected input to a single line. For example, the package interface section 230 may include row MUX circuitry configured and operative to selectively route at least one row address signal from an external device to the row address decoder 106 (FIG. 1). As another example, the data junction section 228 may include column MUX circuitry configured and operative to selectively route at least one column address signal from an external device to the column address decoder 104 (FIG. 1). As another example, the data junction section 228 may include other MUX circuitry configured and operative to receive digital data values ​​generated by the I / O logic circuitry 112 (FIG. 1) and generate global data signals therefrom.

[0078] The data junction sections 228 of the control circuitry structure 200 may be disposed within the horizontal areas of the first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry region 202 may include two (2) data junction sections 228 within its horizontal area, with one (1) of the data junction sections 228 disposed within the first arm sub-region 202B and another (1) of the data junction sections 228 disposed within the second arm sub-region 202C. The data junction sections 228 may be individually horizontally interposed in the Y direction between one of the analog sections 226 of the control circuitry structure 200 and one of the bank regions 204 of the microelectronic device 100. For example, the data junction section 228 in the first arm sub-region 202B may be horizontally interposed in the Y direction between the analog section 226 in the first arm sub-region 202B and the second bank sub-region 208 of the first bank region 204A, and the data junction section 228 in the second arm sub-region 202C may be horizontally interposed in the Y direction between the analog section 226 in the second arm sub-region 202C and the second bank sub-region 208 of the second bank region 204B. The data junction section 228 in the first arm sub-region 202B may horizontally overlap the first bank sub-region 206 of the second bank region 204B in the X direction, and the data junction section 228 in the second arm sub-region 202C may horizontally overlap the first bank sub-region 206 of the first bank region 204A in the X direction.The data junction section 228 in the first arm sub-region 202B may extend in the X-direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the first arm sub-region 202B, and the data junction section 228 in the second arm sub-region 202C may extend in the X-direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the second arm sub-region 202C. In some embodiments, the data junction section 228 at least partially horizontally overlaps, in the Y-direction, the voltage generator section 224 of the control circuitry structure 200 within the horizontal area of ​​the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100.

[0079] The package interface section 230 of the control circuitry structure 200 includes structures and circuitry configured to facilitate electrical communication between the microelectronic device 100 and a relatively larger device package that includes the microelectronic device 100. For example, the package interface section 230 may include BEOL structures (e.g., pad structures such as bond pads, conductive routing) that are in electrical communication with the circuitry of the microelectronic device 100 and that are configured to interface with additional structures (e.g., wiring) that are in electrical communication with circuitry external to the microelectronic device 100.

[0080] The package interface sections 230 of the control circuitry structure 200 may be disposed within the horizontal areas of the first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry region 202 may include two (2) package interface sections 230 within its horizontal area, with one (1) of the package interface sections 230 disposed within the first arm sub-region 202B and another (1) of the package interface sections 230 disposed within the second arm sub-region 202C. The package interface sections 230 may be individually horizontally interposed in the Y direction between one of the analog sections 226 and one of the bank regions 204. For example, the package interface section 230 in the first arm sub-region 202B may be horizontally interposed in the Y direction between the analog section 226 in the first arm sub-region 202B and the first bank sub-region 206 of the second bank region 204B, and the package interface section 230 in the second arm sub-region 202C may be horizontally interposed in the Y direction between the analog section 226 in the second arm sub-region 202C and the first bank sub-region 206 of the first bank region 204A. The package interface section 230 in the first arm sub-region 202B may horizontally overlap the first bank sub-region 206 of the second bank region 204B in the X direction, and the package interface section 230 in the second arm sub-region 202C may horizontally overlap the first bank sub-region 206 of the first bank region 204A in the X direction.The package interface section 230 in the first arm sub-region 202B may extend in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the first arm sub-region 202B, and the package interface section 230 in the second arm sub-region 202C may extend in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the second arm sub-region 202C.

[0081] Within the horizontal area of ​​each first bank subregion 206 of the microelectronic device 100, the control circuitry structure 200 may include a transistor array section 232, a row decoder section 234, a column decoder section 236, a control logic device section 238, and a bank logic section 240. Within each first bank subregion 206, the row decoder section 234 may be horizontally adjacent to the transistor array section 232 in the X-direction. The row decoder sections 234 within some groups of two (2) first bank subregions 206 of a first bank subregion 206 that are horizontally adjacent to each other in the X-direction may be positioned proximate to each other in the X-direction (e.g., substantially “back-to-back”), such that the transistor array sections 232 within some groups of two (2) first bank subregions 206 of a first bank subregion 206 are not horizontally interposed between the row decoder sections 234 in the X-direction. The row decoder sections 234 in some other groups of two (2) first bank sub-regions 206 that are horizontally adjacent to one another in the X direction may be positioned relatively more distal from one another in the X direction, such that the transistor array sections 232 of some other groups of two (2) first bank sub-regions 206 are horizontally interposed between the row decoder sections 234 in the X direction. Furthermore, within each first bank sub-region 206, the transistor array sections 232 and the row decoder sections 234 may be horizontally interposed in the Y direction between a first column decoder section of the column decoder section 236 and a second column decoder section of the column decoder section 236. A first column decoder section of the column decoder section 236 may be positioned at or near a first end of the transistor array section 232 in the Y direction, and a second column decoder section of the column decoder section 236 may be positioned at or near a second end of the transistor array section 232 in the Y direction.The second column decoder section of the column decoder section 236 may be interposed horizontally in the Y direction between the control logic device section 238 and each of the transistor array section 232 and the row decoder section 234. Furthermore, the control logic device section 238 may be interposed horizontally in the Y direction between the column decoder section 236 and the bank logic section 240, and the bank logic section 240 may be interposed horizontally in the Y direction between the control logic device section 238 and one of the first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100.

[0082] The transistor array section 232 of the control circuitry structure 200 within the horizontal area of ​​an individual first bank sub-region 206 of the microelectronic device 100 may include multiple patch subsections of the microelectronic device 100 within that horizontal area. Within the horizontal area of ​​an individual patch subsection, the control circuitry structure 200 may include various control logic circuitry (e.g., sense amplifier (SA) circuitry, decoder circuitry such as column decoder circuitry, word line driver circuitry such as main word line driver (MWD) circuitry and sub-word line driver (SWD) circuitry). Non-limiting examples of the configuration of the control circuitry structure 200 within the horizontal area of ​​an individual patch subsection of the microelectronic device 100 are described in further detail below with reference to FIG. 2C .

[0083] The row decoder sections 234 of the control circuitry structure 200 within the horizontal area of ​​each first bank sub-region 206 of the microelectronic device 100 may include row decoder circuitry configured to perform at least some row operations on banks of memory cells within the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. The banks of memory cells may be located within the horizontal area of ​​the first bank sub-region 206 of the microelectronic device 100, as described in further detail below with reference to FIG. 2D . As shown in FIG. 2B , the row decoder sections 234 within the first bank sub-regions 206 may individually extend horizontally in the Y direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of each of the transistor array sections 232 of the first bank sub-region 206. The horizontal position in the X direction of the row decoder section 234 in each first bank sub-region 206 may facilitate a main word line (MWL) length in the X direction in each first bank sub-region 206 that is substantially equal to the MWL length in the X direction in each second bank sub-region 208 (described in further detail below). The consistent MWL lengths in the first bank sub-region 206 and the second bank sub-region 208 may facilitate, without limitation, driver sizing consistency, RC consistency, and timing consistency for the first bank sub-region 206 and the second bank sub-region 208, even when the first bank sub-region 206 has a different horizontal geometry (e.g., different horizontal dimensions in the X and Y directions) than the second bank sub-region 208.

[0084] The column decoder sections 236 of the control circuitry structure 200 within the horizontal area of ​​each first bank sub-region 206 of the microelectronic device 100 may include column decoder circuitry configured to perform at least some row operations on banks of memory cells in the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. As shown in FIG. 2B , the column decoder sections 236 within a first bank sub-region 206 may be disposed horizontally, in the Y direction, at or proximate opposite horizontal ends of the transistor array section 232 and the row decoder section 234. Each first bank sub-region 206 may include two (2) column decoder sections 236. One of the two (2) column decoder sections 236 may be disposed at or proximate a first horizontal end in the Y direction of the transistor array section 232 and the row decoder section 234, and the other of the two (2) column decoder sections 236 may be disposed at or proximate a second horizontal end in the Y direction of the transistor array section 232 and the row decoder section 234. The column decoder sections 236 may individually extend horizontally in the X direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the overall horizontal dimension (e.g., overall width in the X direction) of the combined transistor array section 232 and row decoder section 234 in the first bank sub-region 206. The quantity and horizontal position in the Y direction of the column decoder section 236 in each first bank sub-region 206 may facilitate column select (CS) line lengths and main input / output (MIO) line lengths in the Y direction in each first bank sub-region 206 that are substantially equal to the column select (CS) line lengths and main input / output (MIO) line lengths in the Y direction in each second bank sub-region 208.Consistent CS line lengths and consistent MIO line lengths within the first bank sub-region 206 and the second bank sub-region 208 may facilitate, without limitation, driver sizing consistency, RC consistency, and timing consistency within the first bank sub-region 206 and the second bank sub-region 208, even when the first bank sub-region 206 has a different horizontal geometric configuration (e.g., different horizontal dimensions in the X and Y directions) than the second bank sub-region 208.

[0085] The control logic device section 238 of the control circuitry structure 200 within the horizontal area of ​​an individual first bank sub-region 206 of the microelectronic device 100 may include various control logic circuitry for the microelectronic device 100, including, but not limited to, DSA circuitry and ECC circuitry. In some embodiments, the control logic device section 238 within an individual first bank sub-region 206 includes both ECC circuitry and DSA circuitry for associated operations on banks of memory cells within the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. The banks of memory cells may be located within the horizontal area of ​​the first bank sub-region 206 of the microelectronic device 100. In additional embodiments, the control logic device section 238 includes additional control logic circuitry, such as one or more of repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), test devices, MUX devices, self-refresh / wear leveling devices, redundant fuse and logic (DFM) devices, and DFT devices. As shown in FIG. 2B , the control logic device section 238 within the horizontal area of ​​each first bank sub-region 206 may be disposed horizontally in the Y direction at or proximate to a horizontal end of one of the column decoder sections 236. The control logic device section 238 may extend horizontally in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the column decoder section 236.

[0086] The bank logic section 240 of the control circuitry structure 200 within the horizontal area of ​​each first bank sub-region 206 of the microelectronic device 100 may include additional control logic circuitry to implement the operation of the control logic circuitry of the transistor array section 232, the row decoder section 234, and the column decoder section 236 within the first bank sub-region 206. As shown in FIG. 2B , the bank logic section 240 within the first bank sub-region 206 may be disposed horizontally in the Y direction at or proximate to the horizontal end of the control logic device section 238. The bank logic section 240 may extend horizontally in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the control logic device section 238 (and thus the column decoder section 236).

[0087] 2B , within the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100, the control circuitry structure 200 may include an additional transistor array section 242, an additional row decoder section 244, an additional column decoder section 246, an additional control logic device section 248, and an additional bank logic section 240. Within each second bank sub-region 208, the additional row decoder section 244 may be interposed horizontally in the X-direction between two (2) additional transistor array sections 242. Furthermore, within each second bank sub-region 208, the additional column decoder section 246 may be interposed horizontally in the Y direction between the additional control logic device section 248 and each of the additional transistor array section 242 and the additional row decoder section 244, the additional control logic device section 248 may be interposed horizontally in the Y direction between the additional column decoder section 246 and the additional bank logic section 250, and the additional bank logic section 250 may be interposed horizontally in the Y direction between the additional control logic device section 248 and one of the first and second arm sub-regions 202B, 202C of the peripheral circuit region 202 of the microelectronic device 100.

[0088] The additional transistor array section 242 of the control circuitry structure 200 within the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100 may include a first additional transistor array section 242A and a second additional transistor array section 242B horizontally offset in the X-direction from the first additional transistor array section 242A. The first additional transistor array section 242A and the second additional transistor array section 242B may exhibit substantially the same horizontal dimensions (e.g., length in the Y-direction, width in the X-direction) as each other and substantially the same horizontal cross-sectional shape as each other. The length in the Y-direction (e.g., first horizontal dimension) of each of the additional transistor array sections 242 of each second bank sub-region 208 may be relatively smaller than the length in the Y-direction (e.g., first horizontal dimension) of the transistor array section 232 within the horizontal area of ​​each first bank sub-region 206. In some embodiments, each of the additional transistor array sections 242 has a length in the Y-direction that is approximately half (½) or less of the length in the Y-direction of the transistor array section 232. Furthermore, the width in the X-direction (e.g., second horizontal dimension) of each of the additional transistor array sections 242 of each second bank subregion 208 may be substantially equal to the width in the X-direction (e.g., second horizontal dimension) of the transistor array section 232 within the horizontal area of ​​each first bank subregion 206. The additional transistor array sections 242 may individually include multiple patch subsections of the microelectronic device 100 within their horizontal areas. As discussed above, within the horizontal areas of each patch subsection, the control circuitry structure 200 may include various control logic circuitry (e.g., SA circuitry, decoder circuitry such as column decoder circuitry, word line driver circuitry such as MWD circuitry and SWD circuitry). A non-limiting example of the configuration of control circuitry structure 200 within the horizontal area of ​​an individual patch subsection of microelectronic device 100 is described in further detail below with reference to FIG. 2C.In some embodiments, each additional transistor array section 242 in each second bank sub-region 208 has about half (½) the number of patch subsections in the Y direction as the transistor array sections 232 in each first bank sub-region 206, and about the same amount of patch subsections in the X direction as the transistor array sections 232 in the first bank sub-region 206.

[0089] The additional row decoder section 244 within the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100 may include additional row decoder circuitry configured to perform at least some row operations on additional banks of memory cells in the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. The additional banks of memory cells may be located within the horizontal area of ​​the second bank sub-region 208 of the microelectronic device 100, as described in further detail below with reference to FIG. 2D . In some embodiments, the additional row decoder section 244 within each second bank sub-region 208 has a length in the Y direction (e.g., first horizontal dimension) that is approximately half (½) or less of the length in the Y direction (e.g., first horizontal dimension) of the row decoder section 234 within the first bank sub-region of one of the first bank sub-regions 206. As shown in FIG. 2B, the additional row decoder sections 244 within each second bank sub-region 208 may extend horizontally in the Y direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of each of the additional transistor array sections 242 of the second bank sub-region 208.

[0090] The additional column decoder section 246 in the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100 may include additional column decoder circuitry configured to perform at least some column operations on additional banks of memory cells in the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. In some embodiments, the additional column decoder section 246 in each second bank sub-region 208 has a width in the X-direction (e.g., second horizontal dimension) that is approximately twice (2 times) or more the width in the X-direction (e.g., second horizontal dimension) of one of the column decoder sections 236 in one of the first bank sub-regions 206. As shown in FIG. 2B , the additional column decoder section 246 in each second bank sub-region 208 may be disposed horizontally in the Y-direction at or proximate to the horizontal ends of the additional transistor array section 242 and the additional row decoder section 244. The additional column decoder section 246 may extend horizontally in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the overall horizontal dimension of the combination of the additional transistor array section 242 and the additional row decoder section 244 in the second bank sub-region 208.

[0091] The additional control logic device sections 248 within the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100 may include various control logic circuitry for the microelectronic device 100, including, but not limited to, the control logic circuitry described herein above in connection with the control logic device sections 238 within each first bank sub-region 206. In some embodiments, the additional control logic device sections 248 within each second bank sub-region 208 include at least one ECC device and at least one DSA device for associated operations on additional banks of memory cells within the memory array structure 300 ( FIG. 2D ) underlying the control circuitry structure 200. The additional banks of memory cells may be located within the horizontal area of ​​the second bank sub-region 208. The additional control logic device section 248 in each second bank sub-region 208 may have a width in the X-direction (e.g., second horizontal dimension) that is approximately twice (2x) or more the width in the X-direction (e.g., second horizontal dimension) of the control logic device section 238 of one of the first bank sub-regions 206. As shown in FIG. 2B , the additional control logic device section 248 in each second bank sub-region 208 may be disposed horizontally in the Y-direction at or proximate to the horizontal end of the additional column decoder section 246. The additional control logic device section 248 may extend horizontally in the X-direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the additional column decoder section 246.

[0092] The additional bank logic section 250 of the control circuitry structure 200 within the horizontal area of ​​each second bank sub-region 208 of the microelectronic device 100 may include additional control logic circuitry to implement the operation of the control logic circuitry of the additional transistor array section 242, the additional row decoder section 244, and the additional column decoder section 246 within the first bank sub-region 206. The additional bank logic section 250 within each second bank sub-region 208 may have a width in the X-direction (e.g., second horizontal dimension) that is approximately twice (2 times) or more the width in the X-direction (e.g., second horizontal dimension) of the bank logic section 240 of one of the first bank sub-regions 206. As shown in FIG. 2B , the additional bank logic section 250 within each second bank sub-region 208 may be positioned horizontally in the Y-direction at or proximate to the horizontal end of the additional control logic section 248. The additional bank logic section 250 may extend horizontally in the X direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the additional control logic device section 248 (and thus the additional column decoder section 246).

[0093] As mentioned above, FIG. 2C is a simplified schematic diagram of portion A (indicated by the dashed box in FIG. 2B) of control circuitry structure 200 of microelectronic device 100, according to an embodiment of the present disclosure. Part A illustrates the configuration of control circuitry structure 200 within the horizontal area of ​​a patch subsection 252 of microelectronic device 100. Patch subsection 252 may be located within the horizontal area of ​​one of second bank subregions 208 of one of bank regions 204 (e.g., first bank region 204A) of control circuitry structure 200. Each of second bank subregions 208 (FIG. 2B) of control circuitry structure 200 may include multiple (e.g., a group of multiple) patch subsections 252 within its horizontal area, and control circuitry structure 200 may exhibit a configuration similar to that illustrated in FIG. 2C within the horizontal area of ​​each patch subsection 252. Furthermore, within the horizontal area of ​​each first bank subregion 206 (FIG. 2B) of the microelectronic device 100, the control circuitry structure 200 may include multiple (e.g., a group of multiple) patch subsections 252, and the control circuitry structure 200 may exhibit a configuration similar to that shown in FIG. 2C within the horizontal area of ​​each patch subsection 252.

[0094] Within the horizontal area of ​​each patch subsection 252 of microelectronic device 100, control circuitry structure 200 is substantially free of memory cells. Instead, the memory cells of microelectronic device 100 are contained (e.g., confined) within a memory array structure 300 ( FIG. 2D ) of microelectronic device 100 that is vertically offset from (e.g., vertically below) control circuitry structure 200.

[0095] Each patch subsection 252 of microelectronic device 100 may include array regions 254, digit line exit regions 256 (also referred to as "digit line contact socket regions") interposed between pairs of array regions 254 that are horizontally adjacent to one another in the Y direction, and word line exit regions 258 (also referred to as "word line contact socket regions") interposed between additional pairs of array regions 254 that are horizontally adjacent to one another in an X direction orthogonal to the Y direction. The array regions 254, digit line exit regions 256, and word line exit regions 258 within individual patch subsections 252 of microelectronic device 100 are described in further detail below.

[0096] The array region 254 of the microelectronic device 100 may comprise a horizontal array of microelectronic devices 100 having an array of memory cells (e.g., an array of DRAM cells) within its horizontal boundaries. The array of memory cells may be vertically arranged within the memory array structure 300 (FIG. 2D) of the microelectronic device 100. Additionally, the array region 254 may have a desired placement of control logic devices within its horizontal boundaries. The control logic devices may be vertically arranged to be formed within the horizontal boundaries of the array region 254 within the memory array structure 200 (FIG. 2B) of the microelectronic device 100.

[0097] Individual patch subsections 252 of microelectronic device 100 may be formed to include any desired amount of array regions 254. For clarity and ease of understanding the drawings and associated description, Figure 2C illustrates an individual patch subsection 252 as including four (4) array regions 254: a first array region 254A, a second array region 254B, a third array region 254C, and a fourth array region 254D. 2C , the second array region 254B may be horizontally adjacent to the first array region 254A in the Y direction and horizontally adjacent to the fourth array region 254D in the X direction; the third array region 254C may be horizontally adjacent to the first array region 254A in the X direction and horizontally adjacent to the fourth array region 254D in the Y direction; and the fourth array region 254D may be horizontally adjacent to the third array region 254C in the Y direction and horizontally adjacent to the second array region 254B in the X direction. In additional embodiments, individual patch subsections 252 include different numbers of array regions 254. For example, patch subsections 252 may include more than four (4) array regions 254 or fewer than four (4) array regions 254.

[0098] Further, individual patch subsections 252 of the microelectronic device 100 may include a desired distribution of array regions 254. As shown in FIG. 2C , in some embodiments, the microelectronic device 100 is formed to include rows of array regions 254 extending in the X-direction and columns of array regions 254 extending in the Y-direction. The rows of array regions 254 may include, for example, a first row including a first array region 254A and a third array region 254C, and a second row including a second array region 254B and a fourth array region 254D. The columns of array regions 254 may include, for example, a first column including a first array region 254A and a second array region 254B, and a second column including a third array region 254C and a fourth array region 254D.

[0099] 2C , digit line exit region 256 of microelectronic device 100 may comprise a horizontal area of ​​microelectronic device 100 configured and arranged to terminate at least some digit lines (e.g., bit lines, data lines) horizontally within digit line exit region 256. For each digit line exit region 256, at least some formed digit lines operably coupled to array regions 254 adjacent to digit line exit region 256 (e.g., at opposing boundaries in the Y direction) may have ends within the horizontal boundary of digit line exit region 256. Furthermore, digit line exit region 256 may be configured and arranged to include contact structures and routing structures within its horizontal boundary that are operably coupled with at least some of the digit lines. Some of the contact structures within digit line exit region 256 may couple digit lines within the horizontal area of ​​array region 254 to control logic circuitry of a control logic device (e.g., an SA device). 2C , in some embodiments, the digit line exit regions 256 extend horizontally in the X direction and are horizontally interleaved in the Y direction between horizontally adjacent rows of the array region 254. The digit line exit regions 256 may, for example, horizontally alternate with the rows of the array region 254 in the Y direction.

[0100] Each digit line exit region 256 may be divided into multiple sub-regions. For example, as shown in FIG. 1 , each digit line exit region 256 may include a first digit line exit sub-region 256A and a second digit line exit sub-region 256B. In some embodiments, the first digit line exit sub-regions 256A horizontally alternate with the second digit line exit sub-regions 256B in the X direction. A pair (e.g., two) of horizontally adjacent array regions 254 within each column of array regions 254 may include one of the first digit line exit sub-regions 256A and one of the second digit line exit sub-regions 256B horizontally disposed between the pair in the Y direction. As a non-limiting example, the first array region 254A and the second array region 254B of the first column of the array region 254 may include one of the first digit line exit sub-regions 256A and one of the second digit line exit sub-regions 256B disposed between the array region 254A and the array region 254B in the Y direction. The one of the first digit line exit sub-regions 256A and one of the second digit line exit sub-regions 256B may be at least partially (e.g., substantially) bounded by the horizontal boundaries in the X direction of the first array region 254A and the second array region 254B.

[0101] Each first digit line exit sub-area 256A may be configured and arranged to facilitate electrical connection between a group of digit lines (e.g., odd digit lines or even digit lines) in the memory array structure 300 (FIG. 2D) and a group of control logic devices (e.g., odd SA devices or even SA devices) in the control circuitry structure 200 (FIG. 2B) that are operably coupled to a portion (e.g., half portion in the X direction) of one array area 254 (e.g., the first array area 254A) of a pair of horizontally adjacent array areas 254. The first digit line exit sub-region 256A may be configured and arranged to facilitate electrical connection between a group of additional digit lines (e.g., additional odd digit lines or additional even digit lines) in the memory array structure 300 (FIG. 2D) and a group of additional control logic devices (e.g., additional odd SA devices or additional even SA devices) in the control circuitry structure 200 (FIG. 2B) that are operably coupled to a corresponding portion (e.g., a corresponding half portion in the X direction) of an additional array region 254 (e.g., a second array region 254B) of a pair of horizontally adjacent array regions 254. Additionally, each second digit line exit sub-region 256B may be configured and arranged to facilitate electrical connection between an additional group of digit lines in the memory array structure 300 (FIG. 2D) and an additional group of control logic devices in the control circuitry structure 200 (FIG. 2B) that is operably coupled to another portion (e.g., another half portion in the X-direction) of one of the array regions 254 (e.g., the first array region 254A). The second digit line exit sub-region 256B may be configured and arranged to facilitate electrical connection between an even additional group of digit lines in the memory array structure 300 (FIG. 2D) and an even additional group of control logic devices in the control circuitry structure 200 (FIG. 2B) that is operably coupled to a corresponding another portion (e.g., a corresponding another half portion in the X-direction) of the additional array region 254 (e.g., the second array region 254B).

[0102] 2C , the wordline exit region 258 of the microelectronic device 100 may comprise a horizontal area of ​​the microelectronic device 100 configured and arranged to horizontally terminate at least some wordlines (e.g., access lines) within the wordline exit region 258. For an individual wordline exit region 258, at least some wordlines operably coupled to array regions 254 adjacent to the wordline exit region 258 (e.g., at opposing boundaries in the X-direction) may have ends within the horizontal boundaries of the wordline exit region 258. Furthermore, the wordline exit region 258 may be configured and arranged to include contact structures and routing structures within its horizontal boundaries that are operably coupled to the wordlines. Some of the contact structures within the wordline exit region 258 may couple the wordlines to control logic circuitry of additional control logic devices (e.g., SWD devices) within the horizontal area of ​​the array region 254. 2C, in some embodiments, the word line exit regions 258 extend horizontally in the Y direction and are horizontally interposed in the X direction between horizontally adjacent columns of array regions 254. The word line exit regions 258 may, for example, horizontally alternate with the columns of array regions 254 in the X direction.

[0103] Each word line exit region 258 may be divided into multiple subregions. For example, as shown in FIG. 1 , each word line exit region 258 may include a first word line exit subregion 258A and a second word line exit subregion 258B. In some embodiments, the first word line exit subregions 258A horizontally alternate with the second word line exit subregions 258B in the Y direction. A pair (e.g., two) of horizontally adjacent array regions 254 within each row of array regions 254 may include one of the first word line exit subregions 258A and one of the second word line exit subregions 258B horizontally disposed between the pair in the X direction. As a non-limiting example, the first array region 254A and the third array region 254C of the first row of the array region 254 may include one of the first word line exit sub-regions 258A and one of the second word line exit sub-regions 258B disposed between the array region 254A and the array region 254C in the X-direction. The one of the first word line exit sub-regions 258A and one of the second word line exit sub-regions 258B may be at least partially (e.g., substantially) bounded by horizontal boundaries in the Y-direction of the first array region 254A and the third array region 254C.

[0104] Each first word line exit sub-region 258A may be configured and arranged to facilitate electrical connection between a group of word lines (e.g., odd word lines or even word lines) in the memory array structure 300 (FIG. 2D) and a group of control logic devices (e.g., odd SWD devices or even SWD devices) in the control circuitry structure 200 (FIG. 2B) that are operably coupled to a portion (e.g., half portion in the Y direction) of one array region 254 (e.g., the first array region 254A) of a pair of horizontally adjacent array regions 254. The first wordline exit sub-regions 258A may be configured and arranged to facilitate electrical connection between a group of additional wordlines (e.g., additional odd wordlines or additional even wordlines) in the memory array structure 300 ( FIG. 2D ) and a group of additional control logic devices (e.g., additional odd SWD devices or additional even SWD devices) in the control circuitry structure 200 ( FIG. 2B ) operably coupled to a corresponding portion (e.g., a corresponding half portion in the Y direction) of an additional array region 254 (e.g., a third array region 254C) of a pair of horizontally adjacent array regions 254. Further, each second wordline exit sub-region 258B may be configured and arranged to facilitate electrical connection between a group of additional wordlines in the memory array structure 300 ( FIG. 2D ) and a group of additional control logic devices in the control circuitry structure 200 ( FIG. 2B ) operably coupled to another portion (e.g., another half portion in the Y direction) of one array region 254 (e.g., the first array region 254A). The second word line exit sub-region 258B may facilitate electrical connection between yet a further group of word lines in the memory array structure 300 (FIG. 2D) and yet a further group of control logic devices in the control circuitry structure 200 (FIG. 2B) that is operably coupled to a corresponding other portion (e.g., a corresponding other half portion in the Y direction) of the further array region 254 (e.g., the third array region 254C).

[0105] 2C , the control circuitry structure 200 of the microelectronic device 100 may include a desired arrangement of SA sections 260 and SWD sections 262 within the horizontal area of ​​each array region 254 of an individual patch subsection 252 of the microelectronic device 100. The SA sections 260 of the control circuitry structure 200 may individually include SA devices coupled to digit lines disposed within the memory array structure 300 ( FIG. 2D ) of the microelectronic device 100. The digit lines may be vertically (e.g., in the Z direction) below the SA devices in the SA sections 260 of the control circuitry structure 200. The SWD sections 262 may include SWD devices coupled to word lines disposed within the memory array structure 300 ( FIG. 2D ) of the microelectronic device 100. The word lines may be vertically (e.g., in the Z direction) below the SWD devices in the SWD sections 262 of the control circuitry structure 200.

[0106] The SA section 260 within a horizontal area of ​​an individual array region 254 (e.g., first array region 254A, second array region 254B, third array region 254C, and fourth array region 254D) of the microelectronic device 100 may include a first SA section 260A and a second SA section 260B. The individual first SA section 260A and the individual second SA section 260B of the control circuitry structure 200 within the horizontal area of ​​an individual array region 254 of the microelectronic device 100 may be disposed at or proximate to opposite corners (e.g., diagonally opposite corners) of the array region 254 from one another. For example, as shown in FIG. 2C, for an individual array region 254, a first SA section 260A may be positioned at or proximate to a first corner 264A of the array region 254, and a second SA section 260B may be positioned at or proximate to a second corner 264B of the array region 254 located diagonally opposite (e.g., at a kitty corner) the first corner 264A.

[0107] For each SA section 260 (e.g., first SA section 260A, second SA section 260B) of the control circuitry structure 200 within the horizontal area of ​​an individual array region 254 of the microelectronic device 100, the SA devices of the SA section 260 may be coupled by digit line routing and contact structures 266 to a group of digit lines within the memory array structure 300 (FIG. 2D) extending horizontally (e.g., in the Y direction) through the array region 254.

[0108] For an individual patch subsection 252 of the microelectronic device 100, the SA devices of the SA section 260 of the control circuitry structure 200 in array regions 254 that are horizontally adjacent to each other in the Y direction (e.g., the first array region 254A, the second array region 254B, the third array region 254C, the fourth array region 254D) may be coupled to different groups of digit lines. For example, each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 in the first array region 254A may include so-called “even” SA devices coupled to a group of even digit lines in the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 coupled to the SA sections 260, and each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 in the second array region 254B may include so-called “odd” SA devices coupled to odd digit lines in the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 coupled to the SA sections 260, or vice versa. The even digit lines of the memory array structure 300 (FIG. 2D) may alternate horizontally in the X direction with the odd digit lines of the memory array structure 300 (FIG. 2D). Each SA device of the SA section 260 of the control circuitry structure 200 in the horizontal area of ​​the first array region 254A may not be coupled to an odd digit line of the memory array structure 300 (FIG. 2D), and each SA device of the SA section 260 of the control circuitry structure 200 in the horizontal area of ​​the second array region 254B may not be coupled to an even digit line of the memory array structure 300 (FIG. 2D), or vice versa.Similarly, each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 in a horizontal area of ​​the third array region 254C horizontally adjacent to the first array region 254A in the X direction may include additional even SA devices coupled to additional even digit lines in the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 coupled to the SA sections 260, Each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 in a horizontal area of ​​the fourth array region 254D horizontally adjacent to the second array region 254B may include additional odd SA devices coupled to additional odd digit lines in the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 coupled to the SA section 260, or vice versa.

[0109] As shown in FIG. 2C, an SA device (e.g., an odd SA device or an even SA device) in an individual SA section 260 of an individual array area 254 may be coupled to a digit line (e.g., an odd digit line or an even digit line) extending horizontally through the array area 254, and may be coupled to an additional digit line (e.g., an additional odd digit line or an additional even digit line) extending horizontally through another array area 254 horizontally adjacent to the array area 254 in the Y direction. For example, some odd SA devices in the first SA section 260A of the second array region 254B may be coupled to odd digit lines extending horizontally through the second array region 254B by some digit line routing and contact structures 266 extending therethrough to a first digit line exit sub-region 256A horizontally adjacent to the second array region 254B in the Y direction, and some additional odd SA devices in the first SA section 260A of the second array region 254B may be coupled to additional odd digit lines extending horizontally through the first array region 254A by some additional digit line routing and contact structures 266 extending therethrough to the first digit line exit sub-region 256A. As another example, some even SA devices in the second SA section 260B of the first array region 254A may be coupled to even digit lines extending horizontally through the first array region 254A by some digit line routing and contact structures 266 extending therethrough to a second digit line exit sub-region 256B horizontally adjacent to the first array region 254A in the Y direction, and some additional even SA devices in the second SA section 260B of the first array region 254A may be coupled to additional even digit lines extending horizontally through the second array region 254B by some additional digit line routing and contact structures 266 extending therethrough to the second digit line exit sub-region 256B.

[0110] 2C , the SWD section 262 within a horizontal area of ​​an individual array region 254 (e.g., the first array region 254A, the second array region 254B, the third array region 254C, or the fourth array region 254D) of the microelectronic device 100 may include a first SWD section 262A and a second SWD section 262B. The individual first SWD section 262A and the individual second SWD section 262B of the control circuitry structure 200 within the horizontal area of ​​an individual array region 254 of the microelectronic device 100 may be located at or proximate a different corner of the array region 254 than the first SA section 260A and the second SA section 260B. Furthermore, the corner of the array region 254 connected to the first SWD section 262A may be opposite (e.g., diagonally opposite) the corner of the array region 254 connected to the second SWD section 262B. For example, as shown in FIG. 2C, for an individual array region 254, the first SWD section 262A may be positioned at or proximate to a third corner 264C of the array region 254, and the second SWD section 262B may be positioned at or proximate to a fourth corner 264D of the array region 254, located diagonally opposite (e.g., kitty corner) the third corner 264C.

[0111] For each SWD section 262 (e.g., first SWD section 262A and second SWD section 262B) of the control circuitry structure 200 within a horizontal area of ​​an individual array region 254 of the microelectronic device 100, the SWD devices of the SWD section 262 may be coupled to a group of word lines extending horizontally (e.g., in the X-direction) through the array region 254 by word line routing and contact structures 268.

[0112] For an individual patch subsection 252 of the microelectronic device 100, the SWD devices of the SWD section 262 of the control circuitry structure 200 in array regions 254 that are horizontally adjacent to each other in the X direction (e.g., the first array region 254A and the third array region 254C, the second array region 254B and the fourth array region 254D) may be coupled to different groups of word lines. For example, each of the SWD sections 262 (e.g., each of the first SWD section 262A and the second SWD section 262B) of the control circuit structure 200 in the first array region 254A may include a so-called “even” SWD device coupled to an even word line in the memory array structure 300 (FIG. 2D) by a word line routing and contact structure 268 coupled to the SWD section 262, and each of the SWD sections 262 (e.g., each of the first SWD section 262A and the second SWD section 262B) of the control circuit structure 200 in the third array region 254C may include a so-called “odd” SWD device coupled to an odd word line in the memory array structure 300 (FIG. 2D) by a word line routing and contact structure 268 coupled to the SWD section 262, or vice versa. The even word lines of the memory array structure 300 (FIG. 2D) may alternate horizontally in the Y direction with the odd word lines of the memory array structure 300 (FIG. 2D). Each SWD device of the SWD section 262 of the control circuitry structure 200 in the horizontal area of ​​the first array region 254A may not be coupled to an odd word line, and each SWD device of the SWD section 262 of the control circuitry structure 200 in the horizontal area of ​​the third array region 254C may not be coupled to an even word line, or vice versa.Similarly, each of the SWD sections 262 (e.g., each of the first SWD section 262A and the second SWD section 262B) of the control circuitry structure 200 in the second array region 254B horizontally adjacent to the first array region 254A in the Y direction may include additional even SWD devices coupled to additional even word lines in the memory array structure 300 (FIG. 2D) by word line routing and contact structures 268 coupled to the SWD sections 262, Each of the SWD sections 262 (e.g., each of the first SWD section 262A and the second SWD section 262B) of the control circuitry structure 200 in the fourth array region 254D horizontally adjacent to the third array region 254C may include additional odd SWD devices coupled to additional odd word lines in the memory array structure 300 (FIG. 2D) by word line routing and contact structures 268 coupled to the SWD sections 262, or vice versa.

[0113] As shown in FIG. 2C, an SWD device (e.g., an odd SWD device or an even SWD device) in an individual SWD section 262 of an individual array region 254 may be coupled to a word line (e.g., an odd word line or an even word line) extending horizontally through the array region 254, or may be coupled to an additional word line (e.g., an additional odd word line or an additional even word line) extending horizontally through another array region 254 horizontally adjacent to the array region 254 in the X direction. For example, some odd SWD devices in the first SWD section 262A of the third array region 254C may be coupled to odd word lines extending horizontally through the third array region 254C by some word line routing and contact structures 268 extending therethrough to a second word line exit sub-region 258B horizontally adjacent to the third array region 254C in the X direction, and some additional odd SWD devices in the first SWD section 262A of the third array region 254C may be coupled to additional odd word lines extending horizontally through the first array region 254A by some additional word line routing and contact structures 268 extending therethrough to the second word line exit sub-region 258B. As another example, some even SWD devices in the second SWD section 262B of the first array region 254A may be coupled to even word lines extending horizontally through the first array region 254A by some word line routing and contact structures 268 extending therethrough to a first word line exit sub-region 258A horizontally adjacent to the first array region 254A in the X direction, and some additional even SWD devices in the second SWD section 262B of the first array region 254A may be coupled to additional even word lines extending horizontally through the third array region 254C by some additional word line routing and contact structures 268 extending therethrough to the first word line exit sub-region 258A.

[0114] 2C , within the horizontal area of ​​an individual patch subsection 252 of microelectronic device 100, control circuitry structure 200 may include additional control logic sections that individually include additional control logic devices (e.g., control logic devices other than SA and SWD devices). For example, for each array region 254 within the horizontal area of ​​an individual patch subsection 252 of microelectronic device 100, control circuitry structure 200 may include an additional control logic section horizontally disposed between SA section 260 and SWD section 262 (e.g., at a relatively more horizontally central location within array region 254). The additional control logic section may include, but is not limited to, a column decoder device section that includes a column decoder device and an MWD section that includes an MWD device. In some embodiments, the additional control logic section of the control circuitry structure 200 within the horizontal area of ​​an individual patch subsection 252 of the microelectronic device 100 includes a column decoder device section that is horizontally adjacent inward (e.g., directly horizontally adjacent) to the SA section 260 in the Y direction, and an MWD section that is horizontally adjacent inward (e.g., directly horizontally adjacent) to the SWD section 262 in the X direction.

[0115] Referring now to Figure 2D, an exemplary arrangement of various circuitry of a memory array structure 300 within horizontal areas of the peripheral circuitry region 202 and bank regions 204 of the microelectronic device 100 is shown. For ease of understanding and clarity of the drawings and the associated discussion, not all features of the microelectronic device 100 described above with reference to Figure 2A are illustrated in Figure 2D. However, as noted herein above, it will be understood that any feature of the microelectronic device 100 described with reference to one or more of Figures 2A-2E is applicable to one or more (e.g., all) of the other Figures 2A-2E.

[0116] Within the horizontal area of ​​the peripheral circuitry region 202 of the microelectronic device 100, the memory array structure 300 may include at least one additional capacitor section 302 that includes circuitry (e.g., capacitors) configured and arranged to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 100. For example, the additional capacitor section 302 may include capacitors for a charge pump, an RC filter, capacitors for a peaking amplifier, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), decoupling capacitors, and capacitors for powering one or more control logic devices, such as one or more of the DSA devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command-address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQU, DQL), one or more command-address devices, one or more antifuse devices, one or more DLL devices, one or more delay enable devices (e.g., one or more dQ enable delay devices), one or more temperature sensors, one or more data junctions for conducting data to / from memory banks, and one or more additional control logic devices. The capacitors in the additional capacitor section 302 of the memory array structure 300 may be coupled to BEOL structures of the microelectronic device 100.

[0117] The additional capacitor section 302 of the memory array structure 300 may extend horizontally across one or more (e.g., each) of the central sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C of the peripheral circuitry region 202 of the microelectronic device 100. In some embodiments, a predetermined portion of the additional capacitor section 302 of the memory array structure 300 is disposed within the horizontal area of ​​each of the central sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C of the peripheral circuitry region 202 of the microelectronic device 100.

[0118] Within the horizontal area of ​​a first bank sub-region 206 of the microelectronic device 100, the memory array structure 300 may include memory array banks 304. Each first bank sub-region 206 of the microelectronic device 100 may include within its horizontal area an individual memory array bank 304 of the memory array structure 300. As described in more detail below, each of the memory array banks 304 may include one or more memory array regions that individually include an array of memory cells (e.g., an array of DRAM cells).

[0119] Within the horizontal area of ​​a second bank sub-region 208 of the microelectronic device 100, the memory array structure 300 may include additional memory array banks 306. Each second bank sub-region 208 of the microelectronic device 100 may include within its horizontal area an individual additional memory array bank 306 of the memory array structure 300. As described in more detail below, each of the additional memory array banks 306 may include one or more memory array regions each including an array of memory cells (e.g., an array of DRAM cells). The additional memory array banks 306 within an individual second bank sub-region 208 may be relatively smaller (e.g., shorter) in the Y direction than the memory array banks 304 within the horizontal area of ​​an individual first bank sub-region 206 and relatively larger (e.g., wider) in the X direction than the memory array banks 304 within the horizontal area of ​​the first bank sub-region 206. In some embodiments, the additional memory array bank 306 in each second bank sub-region 208 has a length in the Y direction (e.g., first horizontal dimension) that is approximately half (½) or less of the length in the Y direction (e.g., first horizontal dimension) of the memory array bank 304 within the horizontal area of ​​each first bank sub-region 206. Furthermore, in some embodiments, the additional memory array bank 306 in each second bank sub-region 208 has a width in the X direction (e.g., second horizontal dimension) that is approximately twice (2×) or more of the width in the X direction (e.g., second horizontal dimension) of the memory array bank 304 within the horizontal area of ​​each first bank sub-region 206.

[0120] As mentioned above, FIG. 2E is a simplified schematic diagram of portion B (indicated by the dashed box in FIG. 2D ) of the memory array structure 300 of the microelectronic device 100, according to an embodiment of the present disclosure. Part B illustrates the configuration of the memory array structure 300 within the horizontal area of ​​a patch subsection 252 of the microelectronic device 100. The patch subsection 252 may be disposed within the horizontal area of ​​one of the second bank subregions 208 of one of the bank regions 204 (e.g., the first bank region 204A) of the bank region 204 of the control circuitry structure 200. Each of the second bank subregions 208 ( FIG. 2D ) of the memory array structure 300 may include multiple (e.g., a group of multiple) patch subsections 252 within its horizontal area, and the memory array structure 300 may exhibit a configuration similar to that shown in FIG. 2E within the horizontal area of ​​each patch subsection 252. Furthermore, within the horizontal area of ​​each first bank subregion 206 (FIG. 2B) of the microelectronic device 100, the memory array structure 300 may include a variety of (e.g., a group of, a plurality of) patch subsections 252, and the memory array structure 300 may exhibit a configuration similar to that shown in FIG. 2E within the horizontal area of ​​each patch subsection 252.

[0121] As shown in FIG. 2E, the memory array structure 300 of the microelectronic device 100 may include an array of memory cells 308, digit lines 310, and word lines 312 within the horizontal area of ​​each array region 254 of an individual patch subsection 252 of the microelectronic device 100. The array of memory cells 308 may be coupled to the digit lines 310 and the word lines 312. The digit lines 310 may extend in the Y direction and may be coupled to SA devices in the SA section 260 (FIG. 2C) of the control circuitry structure 200 (FIG. 2C). The word lines 312 may extend in the X direction and may be coupled to SWD devices in the SWD section 262 (FIG. 2C) of the control circuitry structure 200 (FIG. 2C).

[0122] For an individual patch subsection 252 of microelectronic device 100, digit lines 310 in memory array structure 300 may include odd digit lines 310A and even digit lines 310B. As discussed herein above with reference to FIG. 2C , odd digit lines 310A may be coupled to odd SA devices of SA section 260 of control circuitry structure 200, and even digit lines 310B may be coupled to even SA devices of SA section 260 of control circuitry structure 200.

[0123] For an individual patch subsection 252 of the microelectronic device 100, the word lines 312 in the memory array structure 300 may include odd word lines 312A and even word lines 312B. As discussed herein above with reference to Figure 2C, the odd word lines 312A may be coupled to odd SWD devices in the SWD section 262 (Figure 2C) of the control circuitry structure 200 (Figure 2C), and the even word lines 312B may be coupled to even SWD devices in the SWD section 262 (Figure 2C) of the control circuitry structure 200 (Figure 2C).

[0124] Thus, according to an embodiment of the present disclosure, a microelectronic device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a central sub-region and two arm sub-regions extending from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length in a second horizontal direction perpendicular to the first horizontal direction from the central sub-region. The bank region is horizontally outside the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is vertically below the control circuitry structure and comprises an array of memory cells within the horizontal area of ​​the bank region.

[0125] In additional embodiments, microelectronic device 100 is configured to have a different configuration than that described hereinabove with reference to Figures 2A-2E. Microelectronic device 100 may have a different overall layout of regions than that described hereinabove with reference to Figure 2A, for example, and may have a different arrangement of various circuitry within its control circuitry structure 200 (Figure 2B) and memory array structure 300 (Figure 2D). By way of non-limiting example, Figures 3A-3C are simplified schematic diagrams of different portions of microelectronic device 400 (e.g., a memory device such as a DRAM device) according to additional embodiments of the present disclosure. Microelectronic device 400 may have an overall configuration substantially similar to that of microelectronic device 100 described above with reference to Figure 1, but may have an arrangement of various features (e.g., regions, circuitry, devices, structures) that differs from that of microelectronic device 100 described above with reference to Figures 2A-2E. Figure 3A is a simplified schematic diagram of a microelectronic device 400 according to some embodiments of the present disclosure, showing the overall layout (e.g., floor plan) of different regions of the microelectronic device 400. Figure 3B is a simplified schematic diagram of a control circuitry structure 500 of the microelectronic device 400 according to some embodiments of the present disclosure, showing the placement of various circuit portions of the control circuitry structure 500 within different regions of the microelectronic device 400. Figure 3C is a simplified schematic diagram of a memory array structure 600 of the microelectronic device 400 according to some embodiments of the present disclosure, showing the placement of various circuit portions of the memory array structure 600 within different regions of the microelectronic device 400.

[0126] 3A, microelectronic device 400 may include a peripheral circuitry region 402 and a bank region 408. As described in further detail below, within control circuitry structure 500 (FIG. 3B), relatively speed-critical circuitry and devices may be located within the horizontal area of ​​peripheral circuitry region 402, and relatively less speed-critical circuitry and devices may be located within the horizontal area of ​​bank region 408.

[0127] The peripheral circuitry region 402 of the microelectronic device 400 may include a street subregion 404 and an additional street subregion 406 that is integral and contiguous with the street subregion 404. The additional street subregion 406 may horizontally intersect the street subregion 404. The location where the street subregion 404 intersects and horizontally overlaps the additional street subregion 406 may be considered a central subregion of the peripheral circuitry region 402. The street subregion 404 may extend in a substantially linear path in the X direction and may be further divided in the X direction into a first street subregion portion 404A and a second street subregion portion 404B. The additional street subregion 406 may extend in a substantially linear path in the Y direction and may be further divided in the Y direction into a first additional street subregion portion 406A and a second additional street subregion portion 406B.

[0128] 3A, the street sub-regions 404 and additional street sub-regions 406 of the peripheral circuitry region 402 may exhibit a rectangular horizontal cross-sectional shape. The combination of the street sub-regions 404 and additional street sub-regions 406 may provide the peripheral circuitry region 402 with an irregular horizontal cross-sectional shape, such as a shape similar to that of a plus sign (+).

[0129] In some embodiments, the horizontal centerline in the Y direction of the street sub-region 404 is substantially aligned with the horizontal centerline in the Y direction 412 of the microelectronic device 400, and the additional horizontal centerline in the X direction of the additional street sub-region 406 is substantially aligned with the additional horizontal centerline in the X direction 414 of the microelectronic device 400. The horizontal centerline in the Y direction 412 of the microelectronic device 400 may extend substantially linearly in the X direction, and the additional horizontal centerline in the X direction 414 of the microelectronic device 400 may extend substantially linearly in the Y direction. The additional horizontal centerline in the X direction 414 of the microelectronic device 400 may divide the street sub-region 404 into a first street sub-region portion 404A and a second street sub-region portion 404B. A horizontal centerline 412 in the Y direction of the microelectronic device 400 may divide the additional street sub-region 406 into a first additional street sub-region portion 406A and a second additional street sub-region portion 406B. In additional embodiments, the horizontal centerline in the Y direction of the street sub-region 404 is offset from the horizontal centerline 412 in the Y direction of the microelectronic device 400 and / or the additional horizontal centerline in the X direction of the additional street sub-region 406 is offset from the additional horizontal centerline 414 in the X direction of the microelectronic device 400.

[0130] 3A , the street sub-regions 404 of the peripheral circuitry region 402 may extend continuously in the X-direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the microelectronic device 400 and may have a first length L10 in the Y-direction. Further, the additional street sub-regions 406 of the peripheral circuitry region 402 may extend continuously in the Y-direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the microelectronic device 400 and may have a first width W10 in the X-direction. In some embodiments, the first width W10 in the X-direction of the additional street sub-regions 406 is substantially equal to the first length L10 in the Y-direction of the street sub-regions 404. In an additional embodiment, the first width W10 in the X direction of the additional street sub-region 406 is different from (eg, smaller than, larger than) the first length L10 in the Y direction of the street sub-region 404.

[0131] 3A , the bank regions 408 of the microelectronic device 400 may be horizontally separated from one another by the peripheral circuitry region 402 of the microelectronic device 400. The microelectronic device 400 may include, for example, four (4) bank regions 408: a first bank region 408A, a second bank region 408B, a third bank region 408C, and a fourth bank region 408D. The second bank region 408B may be horizontally adjacent to the first bank region 408A in the Y direction and horizontally adjacent to the fourth bank region 408D in the X direction. The third bank region 408C may be horizontally adjacent to the first bank region 408A in the X direction and horizontally adjacent to the fourth bank region 408D in the Y direction. The fourth bank region 408D may be horizontally adjacent to the third bank region 408C in the Y direction and may be horizontally adjacent to the second bank region 208B in the X direction. In additional embodiments, the microelectronic device 400 includes a different number of bank regions 408. For example, the microelectronic device 400 may include more than four (4) bank regions 408 or fewer than four (4) bank regions 408.

[0132] Each of the bank regions 408 (e.g., first bank region 408A, second bank region 408B, third bank region 408C, fourth bank region 408D) of the microelectronic device 400 may exhibit a rectangular horizontal cross-sectional shape. As shown in FIG. 3A, each of the bank regions 408 may have a second length L11 in the Y direction and a second width W11 in the X direction.

[0133] Each bank region 408 of the microelectronic device 400 may include a bank sub-region 410 and at least one throat sub-region 413. The throat sub-region 413 of the bank region 408 may extend in a substantially linear path in the Y direction and may be interposed in the X direction between some (e.g., one group) of the plurality of bank sub-regions 410 of the bank region 408 and other (e.g., additional groups) of the plurality of bank sub-regions 410 of the bank region 408. As described in further detail below, within the memory array structure 600 ( FIG. 3C ) of the microelectronic device 400, banks of memory cells may be arranged within the horizontal areas of the bank sub-regions 410 of the bank region 408.

[0134] The bank sub-regions 410 of the bank region 408 (e.g., the first bank region 408A, the second bank region 408B, the third bank region 408C, and the fourth bank region 408D) of the microelectronic device 400 may exhibit rectangular horizontal cross-sectional shapes. In some embodiments, the bank sub-regions 410 exhibit substantially the same rectangular horizontal cross-sectional shapes as one another. As shown in FIG. 3A , each of the bank sub-regions 410 may have a third length L12 in the Y direction and a third width W12 in the X direction.

[0135] The bank regions 408 (e.g., first bank region 408A, second bank region 408B, third bank region 408C, fourth bank region 408D) of the microelectronic device 400 may individually include a desired amount of bank sub-regions 410. As shown in FIG. 3A , in some embodiments, an individual bank region 408 includes eight (8) bank sub-regions 410 within its horizontal area. The eight (8) bank sub-regions 410 may include a first group of four (4) bank sub-regions 410 disposed on one side of a throat sub-region 413 of the bank region 408 and a second group of four (4) bank sub-regions 410 disposed on another opposing side of the throat sub-region 413 of the bank region 408. The four (4) bank sub-regions 410 of the first group may be substantially aligned with each other in the X-direction. The second group of four (4) bank sub-regions 410 may also be substantially aligned with one another in the X-direction. A throat sub-region 413 of the bank region 408 horizontally separates the first group of four (4) bank sub-regions 410 in the X-direction from the second group of four (4) bank sub-regions 410. In additional embodiments, one or more (e.g., each) of the bank regions 408 individually include a different amount of bank sub-regions 410 within its horizontal area (e.g., more than eight (8) bank sub-regions 410, less than eight (8) bank sub-regions 410).

[0136] Referring now to Figure 3B, an exemplary arrangement of various circuitry of control circuitry structure 500 within horizontal areas of peripheral circuitry region 402 and bank region 408 of microelectronic device 400 is shown. For ease of illustration and understanding of the drawings and associated discussion, not all features of microelectronic device 400 described above with reference to Figure 3A are shown in Figure 3B. However, it will be understood that any feature of microelectronic device 400 described with reference to one or more of Figures 3A-3C is applicable to one or more (e.g., all) of the other Figures 3A-3C.

[0137] As described hereinabove, within the horizontal area of ​​the peripheral circuitry region 402 of the microelectronic device 400, the control circuitry structure 500 may house relatively speed-critical circuitry and devices. For example, within the horizontal area of ​​the peripheral circuitry region 402 of the microelectronic device 400, the control circuitry structure 500 may include, but is not limited to, an internal clock and timing generator section 502, a data I / O and control section 504, a command and address (CA) section 506, a data junction section 508, an analog section 510, a capacitor section 512, a fuse section 514, a voltage generator section 516, and a package interface section 518. The above sections and their arrangement within the horizontal area of ​​the peripheral circuitry region 402 of the microelectronic device 400 are described in further detail below.

[0138] The internal clock and timing generator section 502 of the control circuitry structure 500 may include devices and circuitry substantially similar to those of the internal clock and timing generator section 216 ( FIG. 2B ) of the control circuitry structure 200 described hereinabove with reference to FIG. 2B . As shown in FIG. 3B , the internal clock and timing generator section 216 may be located at or near the horizontal center of the horizontal area of ​​the peripheral circuitry region 402, such as at or near the intersection of a street sub-region 404 and an additional street sub-region 406 of the peripheral circuitry region 402. In some embodiments, the internal clock and timing generator section 502 is located at or near the horizontal center of the microelectronic device 400 defined by the intersection of a horizontal centerline 412 in the Y direction of the microelectronic device 400 ( FIG. 3A ) and an additional horizontal centerline 414 in the X direction of the microelectronic device 400 ( FIG. 3A ).

[0139] The data I / O and control section 504 of the control circuitry structure 500 may include devices and circuitry substantially similar to those of the data I / O and control section 214 (FIG. 2B) of the control circuitry structure 200 (FIG. 2B) described hereinabove with reference to FIG. 2B. As shown in FIG. 3B, the data I / O and control section 504 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. The data I / O and control section 504 may include, for example, a first data I / O and control section 504A and a second data I / O and control section 504B. In some embodiments, the first data I / O and control section 504A and the second data I / O and control section 504B may each be disposed within a horizontal area of ​​the first street sub-region portion 404A of the peripheral circuitry region 402 of the microelectronic device 400. The first data I / O and control section 504A may be located relatively closer to the internal clock and timing generator section 502 in the X-direction, and the second data I / O and control section 504B may be located relatively more distal from the internal clock and timing generator section 502 in the X-direction. The first data I / O and control section 504A and the second data I / O and control section 504B may be horizontally offset from each other in the X-direction by one or more other sections of the control circuitry structure 500 (e.g., one of the data junction sections 508), as described in further detail below. The data I / O and control circuitry 138 ( FIG. 1 ) in the first data I / O and control section 504A of the control circuitry structure 500 may be utilized for a bank of memory cells of a memory array structure 600 ( FIG. 3C ) located within a horizontal area of ​​a first half of the microelectronic device 400 (e.g., the top half of the horizontal centerline 412 ( FIG. 3A )).The data I / O and control circuitry 138 (FIG. 1) in the second data I / O and control section 504B of the control circuitry structure 500 may be utilized for banks of memory cells of the memory array structure 600 (FIG. 3C) located within a horizontal area of ​​a second, different half of the microelectronic device 400 (e.g., the lower half of the horizontal centerline 412 (FIG. 3A)).

[0140] The CA section 506 of the control circuitry structure 500 may include the CA input circuitry 115 and the CA decoder circuitry 124 described above with reference to FIG. 1. By way of non-limiting example, the CA section 506 may include one or more (e.g., each) of a column address buffer circuit, a central driver circuit, an EpprMode register circuit, a Pcc control Wck circuit, an Ecs control circuit, a QED shifter circuit, a Clkgen refresh circuit, a column controller circuit, a command extender circuit, an Act_pre_cntl circuit, and a BARArray timer circuit. As shown in FIG. 3B , the CA section 506 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, the CA section 506 is disposed within a horizontal area of ​​a second street sub-region portion 404B of the peripheral circuitry region 402 of the microelectronic device 400. The CA section 506 may be positioned proximate to the internal clock and timing generator section 502 in the X direction, such as directly horizontally adjacent to the internal clock and timing generator section 502 in the X direction.

[0141] The data junction section 508 of the control circuitry structure 500 may include devices and circuitry substantially similar to that of the data junction section 228 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The data junction section 508 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. The data junction section 508 may include, for example, a first data junction section 508A and a second data junction section 508B. In some embodiments, the first data junction section 508A is disposed within the horizontal area of ​​the first street sub-region portion 404A of the peripheral circuitry region 402, and the second data junction section 508B is disposed within the horizontal area of ​​the second street sub-region portion 404B of the peripheral circuitry region 402. The first data junction section 508A may be interposed in the X direction between the first data I / O and control section 504A and the second data I / O and control section 504B. The second data junction section 508B may be interposed in the X direction between the CA section 506 and the analog section 510. As shown in FIG. 3B , the first data junction section 508A may horizontally overlap the throat sub-regions 413 of the first bank region 408A and the second bank region 408B of the microelectronic device 400 in the X direction, and the second data junction section 508B may horizontally overlap the throat sub-regions 413 of the third bank region 408C and the fourth bank region 408D of the microelectronic device 400 in the X direction.

[0142] The analog section 510 of the control circuitry structure 500 may include devices and circuitry substantially similar to those of the analog section 226 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The analog section 510 may be disposed within a horizontal area of ​​the street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, the analog section 510 is disposed within a horizontal area of ​​a second street sub-region portion 404B of the peripheral circuitry region 402 of the microelectronic device 400. The analog section 510 may be disposed proximal to the second data junction section 508B in the X-direction, such as directly horizontally adjacent to the second data junction section 508B in the X-direction.

[0143] The capacitor section 512 of the control circuitry structure 500 may include devices and circuitry substantially similar to that of the capacitor section 222 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The capacitor section 512 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, the capacitor section 512 is disposed within a horizontal area of ​​a second street sub-region portion 404B of the peripheral circuitry region 402 of the microelectronic device 400. The capacitor section 512 may be disposed proximate to the analog section 510 in the X-direction, such as directly horizontally adjacent to the analog section 510 in the X-direction.

[0144] The fuse section 514 of the control circuitry structure 500 may include devices and circuitry substantially similar to that of the fuse section 220 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The fuse section 514 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, the fuse section 514 is disposed within a horizontal area of ​​a second street sub-region portion 404B of the peripheral circuitry region 402 of the microelectronic device 400. The fuse section 514 may be disposed proximate to the capacitor section 512 in the X-direction, such as directly horizontally adjacent to the capacitor section 512 in the X-direction.

[0145] The voltage generator section 516 of the control circuitry structure 500 may include devices and circuitry substantially similar to those of the voltage generator section 224 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The voltage generator section 516 may be disposed within a horizontal area of ​​a street sub-region 404 of the peripheral circuitry region 402 of the microelectronic device 400. The voltage generator section 516 may include, for example, a first voltage generator section 516A and a second voltage generator section 516B. In some embodiments, the first voltage generator section 516A is disposed within a horizontal area of ​​a first street sub-region portion 404A of the peripheral circuitry region 402, and the second voltage generator section 516B is disposed within a horizontal area of ​​a second street sub-region portion 404B of the peripheral circuitry region 402. The first voltage generator section 516A may be positioned proximate to the first data I / O and control section 504A in the X direction, such as directly horizontally adjacent to the first data I / O and control section 504A in the X direction. The second voltage generator section 516B may be positioned proximate to the fuse section 514 in the X direction, such as directly horizontally adjacent to the fuse section 514 in the X direction.

[0146] The package interface section 518 of the control circuitry structure 500 may include devices and circuitry substantially similar to that of the package interface section 224 ( FIG. 2B ) of the control circuitry structure 200 ( FIG. 2B ) described hereinabove with reference to FIG. 2B . The package interface section 518 may be disposed within a horizontal area of ​​an additional street sub-region 406 of the peripheral circuitry region 402 of the microelectronic device 400. The package interface section 518 may include, for example, a first package interface section 518A and a second package interface section 518B. In some embodiments, the first package interface section 518A is disposed within the horizontal area of ​​the first additional street sub-region portion 406A of the peripheral circuitry region 402, and the second package interface section 518B is disposed within the horizontal area of ​​the second additional street sub-region portion 406B of the peripheral circuitry region 402. The first package interface section 518A and the second package interface section 518B may each be positioned proximate to the internal clock and timing generator section 502 in the Y direction, such as directly horizontally adjacent to the internal clock and timing generator section 502 in the Y direction. The internal clock and timing generator section 502 may be interposed between the first package interface section 518A and the second package interface section 518B in the Y direction. The internal clock and timing generator section 502 may horizontally overlap the first package interface section 518A and the second package interface section 518B in the X direction.

[0147] Within the horizontal area of ​​each bank sub-region 410 of each bank region 408 of the microelectronic device 400, the control circuitry structure 500 may include a transistor array section 520, a row decoder section 522, a column decoder section 524, and a bank logic section 526. Within each bank sub-region 410, the row decoder section 522 may be disposed horizontally adjacent to the transistor array section 520 in the Y direction, and the column decoder section 524 may be horizontally interposed in the X direction between the bank logic section 526 and each of the transistor array section 520 and the row decoder section 522.

[0148] The transistor array section 520 of the control circuitry structure 500 within the horizontal area of ​​an individual bank subregion 410 of an individual bank region 408 of the microelectronic device 400 may include multiple patch subsections of the microelectronic device 400 within that horizontal area. The patch subsections of the microelectronic device 400 may be substantially similar to the patch subsections 252 (FIG. 2C) of the microelectronic device 100 (FIG. 2C) described hereinabove with reference to FIG. 2C. Within the horizontal area of ​​an individual patch subsection of the microelectronic device 400, the control circuitry structure 500 may include various control logic circuitry (e.g., SA circuitry, decoder circuitry such as column decoder circuitry, word line driver circuitry such as MWD circuitry and SWD circuitry). As a non-limiting example, within the horizontal area of ​​an individual patch subsection of the microelectronic device 400, the control circuitry structure 500 may exhibit the configuration described hereinabove with reference to FIG. 2C.

[0149] The row decoder section 522 of the control circuitry structure 500 within the horizontal area of ​​an individual bank sub-region 410 of the microelectronic device 400 may include row decoder circuitry configured to perform at least some row operations on banks of memory cells within the memory array structure 600 ( FIG. 3C ) underlying the control circuitry structure 500. The banks of memory cells may be located within the horizontal area of ​​the bank sub-region 410 of the microelectronic device 400, as described in further detail below with reference to FIG. 3C . As shown in FIG. 3B , the row decoder section 522 within the bank sub-region 410 may extend horizontally in the X-direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the transistor array section 520 within the bank sub-region 410. 3B , row decoder sections 522 of control circuitry structure 500 within pairs of horizontal areas of bank sub-regions 410 that are adjacent to each other in the Y direction and aligned with each other in the X direction may be positioned proximate (e.g., directly adjacent to) each other in the Y direction. The row decoder circuitry of row decoder sections 522 positioned proximate to each other in the Y direction may be shared by other circuitry of microelectronic device 400 within pairs of horizontal areas of bank sub-regions 410 of microelectronic device 400.

[0150] The column decoder section 524 of the control circuitry structure 500 within the horizontal area of ​​an individual bank sub-region 410 of the microelectronic device 400 may include column decoder circuitry configured to perform at least some column operations on banks of memory cells in the memory array structure 600 ( FIG. 3C ) underlying the control circuitry structure 500. As shown in FIG. 3B , the column decoder section 524 within the bank sub-region 410 may be disposed horizontally in the X-direction at or proximate to the horizontal ends of the transistor array section 520 and the row decoder section 522. The column decoder section 524 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the overall horizontal dimension (e.g., overall width in the Y-direction) of the combined transistor array section 520 and row decoder section 522 within the bank sub-region 410.

[0151] The bank logic section 526 of the control circuitry structure 500 within the horizontal area of ​​an individual bank sub-region 410 of the microelectronic device 400 may include additional control logic circuitry for implementing the operation of the control logic circuitry of the transistor array section 520, the row decoder section 522, and the column decoder section 524 within the bank sub-region 410. As shown in FIG. 3B , the bank logic section 526 within a bank sub-region 410 may be disposed horizontally in the X-direction at or proximate to the horizontal ends of the column decoder section 524. The bank logic section 526 may extend horizontally in the Y-direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of the column decoder section 524.

[0152] 3B , within the horizontal area of ​​each throat subregion 413 of each bank subregion 408 of the microelectronic device 400, the control circuitry structure 500 may include a control logic device section 528. Each control logic device section 528 may include various control logic circuitry for the microelectronic device 400, including, but not limited to, DSA circuitry and ECC circuitry. In some embodiments, each control logic device section 528 includes both DSA circuitry and ECC circuitry within its horizontal area. As shown in FIG. 3B , each throat subregion 413 may include multiple control logic device sections 528 substantially aligned with one another in the X-direction. As a non-limiting example, within the horizontal area of ​​each throat subregion 413 of each bank subregion 408, the control circuitry structure 500 may include a column of four (4) control logic device sections 528. An individual control logic device section 528 may overlap two (2) bank sub-regions 410 of a bank region 408 in the Y-direction or may be interposed between two (2) bank sub-regions 410 of a bank region 408 in the X-direction. The control logic circuitry (e.g., DSA circuitry and ECC circuitry) of an individual control logic device section 528 may be shared by other circuitry of the microelectronic device 400 within the horizontal area of ​​the two (2) bank sub-regions 410 horizontally adjacent to the control logic device section 528. An individual control logic device section 528 may extend horizontally in the Y-direction across at least a majority (e.g., more than 50 percent, 75 percent or more, 90 percent or more, 95 percent or more) of each of the two (2) bank sub-regions 410 horizontally adjacent to the control logic device section 528.

[0153] Referring now to Figure 3C, an exemplary arrangement of various circuitry of a memory array structure 600 within horizontal areas of the peripheral circuitry region 402 and bank region 408 of a microelectronic device 400 is shown. For ease of drawing and understanding of the drawings and associated discussion, not all features of the microelectronic device 400 described above with reference to Figure 3A are shown in Figure 3C. However, it will be understood that any feature of the microelectronic device 400 described with reference to one or more of Figures 3A-3C is applicable to one or more (e.g., all) of the other Figures 3A-3C.

[0154] Within the horizontal area of ​​the peripheral circuitry region 402 of the microelectronic device 400, the memory array structure 600 may include at least one additional capacitor section 602 that includes circuitry (e.g., capacitors) configured and arranged to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 400. For example, the additional capacitor section 602 may include capacitors for a charge pump, an RC filter, capacitors for a peaking amplifier, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), and decoupling capacitors, as well as capacitors for powering one or more control logic devices, such as one or more of the DSA devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command-address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQU, DQL), one or more command-address devices, one or more antifuse devices, one or more DLL devices, one or more delay enable devices (e.g., one or more dQ enable delay devices), one or more temperature sensors, one or more data junctions for conducting data to / from memory banks, and one or more additional control logic devices. The capacitors in the additional capacitor section 602 of the memory array structure 600 may be coupled to BEOL structures of the microelectronic device 400.

[0155] The additional capacitor section 602 of the memory array structure 600 may extend horizontally across one or more (e.g., each) of the street sub-regions 404 and additional street sub-regions 406 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, a predetermined portion of the additional capacitor section 602 of the memory array structure 600 is disposed within the horizontal area of ​​each of the first street sub-region portion 404A, the second street sub-region portion 404B, the first additional street sub-region portion 406A, and the second additional street sub-region portion 406B of the peripheral circuitry region 402 of the microelectronic device 400.

[0156] Within the horizontal area of ​​a bank subregion 410 of the microelectronic device 400, the memory array structure 600 may include memory array banks 604. Each bank subregion 410 of the microelectronic device 400 may include within its horizontal area an individual memory array bank 604 of the memory array structure 600. A memory array bank 604 of the memory array structure 600 within the horizontal area of ​​an individual bank subregion 410 of the microelectronic device 400 may include within its horizontal area multiple patch subsections of the microelectronic device 400. The patch subsections of the microelectronic device 400 may be substantially similar to the patch subsection 252 of the microelectronic device 100 (FIG. 2C) described herein above with reference to FIG. 2C. Within the horizontal area of ​​an individual patch subsection of the microelectronic device 400, the memory array structure 600 may include various circuit portions (e.g., memory cell arrays, digit lines, word lines). As a non-limiting example, within the horizontal area of ​​an individual patch subsection of microelectronic device 400, memory array structure 600 may exhibit the configuration described herein above with reference to FIG. 2E.

[0157] Thus, according to an embodiment of the present disclosure, a microelectronic device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a street sub-region extending substantially linearly in a first horizontal direction and an additional street sub-region extending substantially linearly in a second horizontal direction orthogonal to the first horizontal direction. The additional street sub-region horizontally intersects the street sub-region. The bank regions are horizontally separated from each other by the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is vertically below the control circuitry structure and comprises an array of memory cells within the horizontal area of ​​the bank region.

[0158] Further, in accordance with an embodiment of the present disclosure, a memory device comprises a peripheral circuitry region, a bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry region comprises a central sub-region and at least two additional sub-regions extending horizontally from the central sub-region. The bank region is horizontally adjacent to the peripheral circuitry region. The control circuitry structure comprises relatively speed-critical circuitry within the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry within the horizontal area of ​​the bank region. The memory array structure is attached to and vertically offset from the control circuitry structure. The memory array structure comprises an array of memory cells within the horizontal area of ​​the bank region.

[0159] Microelectronic devices according to embodiments of the present disclosure (e.g., microelectronic device 100, microelectronic device 400) may be used in embodiments of electronic systems of the present disclosure. For example, FIG. 4 is a simplified schematic block diagram illustrating an electronic system 700 according to embodiments of the present disclosure. The electronic system 700 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as an iPad® or SURFACE® tablet, an e-book, a navigation device, etc. The electronic system 700 includes at least one memory device 702. The memory device 702 may comprise, for example, a microelectronic device described hereinabove (e.g., microelectronic device 100, microelectronic device 400). The electronic system 700 may further include at least one electronic signal processor device 604 (often referred to as a “microprocessor”). Electronic signal processor device 704 may optionally comprise a microelectronic device described herein above (e.g., microelectronic device 100, microelectronic device 400). Although memory device 702 and electronic signal processor device 704 are shown as two (2) separate devices in FIG. 1, in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of memory device 702 and electronic signal processor device 704 is included in electronic system 700. In such embodiments, the memory / processor device may comprise a microelectronic device described herein above (e.g., microelectronic device 100, microelectronic device 400).Electronic system 700 may further include one or more input devices 706 for inputting information into electronic system 700 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. Electronic system 700 may further include one or more output devices 708 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, a display, a printer, an audio output jack, speakers, etc. In some embodiments, input device(s) 706 and output device(s) 708 comprise a single touchscreen device that can be used to both input information into electronic system 700 and output visual information to the user. Input device(s) 706 and output device(s) 708 may be in electrical communication with one or more of memory device 702 and electronic signal processor device 704.

[0160] The structures, devices, and methods of the present disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), further component miniaturization, and increased packaging density compared to conventional structures, devices, and methods. The structures, devices, and methods of the present disclosure may also offer improved scalability, efficiency, and simplicity compared to conventional structures, devices, and methods.

[0161] Additional non-limiting exemplary embodiments of the present disclosure are described below.

[0162] Embodiment 1: A microelectronic device comprising: a peripheral circuitry region comprising a central sub-region and two arm sub-regions extending from the central sub-region in a first horizontal direction, each of the two arm sub-regions having a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction; a bank region horizontally outside the peripheral circuitry region; a control circuitry structure comprising relatively speed critical circuitry in the horizontal area of ​​the peripheral circuitry region and relatively non-speed critical circuitry in the horizontal area of ​​the bank region; and a memory array structure vertically below the control circuitry structure, comprising an array of memory cells in the horizontal area of ​​the bank region.

[0163] Embodiment 2: A microelectronic device as described in embodiment 1, wherein the two arm sub-regions of the peripheral circuit region include a first arm sub-region extending substantially linearly from a first side surface of the central sub-region in a first horizontal direction, wherein a centerline of the first arm sub-region in a second horizontal direction is offset from a centerline of the central sub-region in the second horizontal direction, and a second arm sub-region extending substantially linearly from a second side surface of the central sub-region in the first horizontal direction, wherein a centerline of the second arm sub-region in the second horizontal direction is offset from each of the centerlines of the first arm sub-region and the central sub-region.

[0164] Embodiment 3: A microelectronic device as described in embodiment 2, wherein the central sub-region of the peripheral circuitry region has a first length in a second horizontal direction, and each of the first arm sub-region and the second arm sub-region of the peripheral circuitry region has a second length in the second horizontal direction that is less than the first length.

[0165] Embodiment 4: A microelectronic device as described in any of embodiments 2 and 3, wherein within a horizontal area of ​​a central sub-region of the peripheral circuitry region, the control circuitry structure comprises: a data I / O and control section comprising data I / O and control circuitry; an internal clock and timing generator section adjacent to the data I / O and control section in a first horizontal direction and comprising internal clock and timing generator circuitry; a command and address (CA) section adjacent to the internal clock and timing generator section in the first horizontal direction and comprising CA circuitry; and voltage generator sections adjacent to each of the data I / O and control section, the internal clock and timing generator section, and the CA section in a second horizontal direction, each voltage generator section comprising voltage generator circuitry.

[0166] Embodiment 5: A microelectronic device as described in embodiment 4, wherein within a central sub-region of the peripheral circuitry region, the control circuitry structure further comprises a fuse section adjacent to the CA section in a first horizontal direction and comprising antifuse circuitry, a voltage generator section, and a capacitor section comprising a plurality of capacitors interposed in a second horizontal direction between each of the data I / O and control section, the internal clock and timing generator section, the CA section, and the fuse section.

[0167] Embodiment 6: A microelectronic device as described in any of embodiments 4 and 5, wherein within each horizontal area of ​​the first arm sub-region and the second arm sub-region of the peripheral circuit region, the control circuitry structure comprises: a data junction section comprising multiplexer (MUX) circuitry; a package interface section comprising package interface circuitry; and an analog section interposed between the data junction and the package interface section in the second horizontal direction and comprising one or more of an analog temperature distribution circuitry, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device.

[0168] Embodiment 7: A microelectronic device as described in any one of embodiments 2 to 6, wherein each of the bank regions comprises first bank sub-regions, each having a first width in a first horizontal direction and a first length in a second horizontal direction perpendicular to the first horizontal direction, and second bank sub-regions, each having a second width in the first horizontal direction that is greater than the first width and a second length in the second horizontal direction that is less than the first length.

[0169] Embodiment 8: A microelectronic device as described in embodiment 7, wherein within each horizontal area of ​​the first bank sub-region, the control circuitry structure comprises a transistor array section, a row decoder section comprising row decoder circuitry adjacent to the transistor array section in a first horizontal direction, and column decoder sections each comprising column decoder circuitry adjacent opposite ends of the transistor array section and the row decoder section in a second horizontal direction.

[0170] Embodiment 9: A microelectronic device as described in embodiment 8, wherein within each horizontal area of ​​the second bank sub-region, the control circuitry structure comprises an additional transistor array section, an additional row decoder section comprising additional row decoder circuitry interposed between the additional transistor array sections in the first horizontal direction, and an additional column decoder section comprising additional column decoder circuitry adjacent to the additional transistor array section and the additional row decoder section in the second horizontal direction.

[0171] Embodiment 10: A microelectronic device as described in any one of embodiments 1 to 9, wherein within the horizontal area of ​​the peripheral circuitry region, the memory array structure comprises capacitors constructed and arranged to assist in powering some devices in the control circuitry structure.

[0172] Embodiment 11: A microelectronic device comprising: a peripheral circuitry region comprising street sub-regions extending substantially linearly in a first horizontal direction and additional street sub-regions extending substantially linearly in a second horizontal direction orthogonal to the first horizontal direction, the additional street sub-regions horizontally intersecting the street sub-regions; bank regions horizontally separated from each other by the peripheral circuitry region; control circuitry structures comprising relatively speed critical circuitry in the horizontal area of ​​the peripheral circuitry region and relatively non-speed critical circuitry in the horizontal area of ​​the bank regions; and a memory array structure vertically below the control circuitry structure and comprising an array of memory cells in the horizontal area of ​​the bank regions.

[0173] Embodiment 12: The microelectronic device of embodiment 11, wherein a centerline of a street sub-region in a first horizontal direction is substantially aligned with a centerline of an additional street sub-region in the first horizontal direction, and an additional centerline of a street sub-region in a second horizontal direction is substantially aligned with an additional centerline of an additional street sub-region in the second horizontal direction.

[0174] Embodiment 13: A microelectronic device as described in any of embodiments 11 and 12, wherein within a horizontal area of ​​a street sub-region of the peripheral circuitry region, the control circuitry structure comprises: an internal clock and timing generator section comprising internal clock and timing generator circuitry, the internal clock and timing generator section at least partially horizontally overlapping an additional street sub-region of the peripheral circuitry region in a first horizontal direction; a data I / O and control section comprising data I / O and control circuitry adjacent to a first side of the internal clock and timing generator section in the first horizontal direction; and a command and address (CA) section comprising CA circuitry adjacent to a second side of the internal clock and timing generator section in the first horizontal direction.

[0175] Embodiment 14: A microelectronic device as described in embodiment 13, wherein within the horizontal area of ​​the street sub-region of the peripheral circuitry region, the control circuitry structure further comprises: a first data junction section comprising a multiplexer (MUX) circuit portion horizontally interposed between two data I / O and control sections of the data I / O and control sections in the first horizontal direction; a second data junction section comprising an additional MUX circuit portion horizontally adjacent to the CA section in the first horizontal direction; a first voltage generator section comprising a voltage generator circuit portion adjacent to one of the two data I / O and control sections of the data I / O and control sections in the first horizontal direction; and a second voltage generator section comprising an additional voltage generator circuit portion adjacent to the second data junction section in the first horizontal direction.

[0176] Embodiment 15: A microelectronic device as described in embodiment 14, wherein within the horizontal area of ​​the street sub-region of the peripheral circuit region, the control circuit structure further comprises: an analog section interposed in the first horizontal direction between the second data junction and the second voltage generator section and comprising one or more of an analog temperature distribution circuit section, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device; a capacitor section interposed in the first horizontal direction between the analog section and the second voltage generator section and comprising a plurality of capacitors; and a fuse section interposed in the first horizontal direction between the capacitor section and the second voltage generator section and comprising an antifuse circuit section.

[0177] Embodiment 16: A microelectronic device as described in any one of embodiments 11 to 15, wherein within the horizontal area of ​​the additional street sub-region of the peripheral circuitry region, the control circuitry structure comprises package interface sections each comprising a package interface circuitry.

[0178] Embodiment 17: A microelectronic device as described in any one of embodiments 11 to 16, wherein each of the bank regions comprises a bank sub-region and a throat region interposed in a first horizontal direction between a first group of bank sub-regions and a second group of bank sub-regions.

[0179] Embodiment 18: A microelectronic device as described in embodiment 17, wherein within each horizontal area of ​​each bank sub-region of the bank region, the control circuitry structure comprises: a transistor array section; a row decoder section comprising row decoder circuitry adjacent to the transistor array section in a second horizontal direction; a column decoder section comprising column decoder circuitry adjacent to the transistor array section and the row decoder section in a first horizontal direction; and a bank logic section comprising bank logic circuitry adjacent to the column decoder section in the first horizontal direction; and within the horizontal area of ​​each throat region of the bank region, the control circuitry structure comprises control logic device sections each comprising digital signal acquisition (DSA) circuitry and error correction code (ECC) circuitry.

[0180] Embodiment 19: A memory device comprising: a peripheral circuitry region having a central sub-region and at least two additional sub-regions extending horizontally from the central sub-region; a bank region horizontally adjacent to the peripheral circuitry region; a control circuitry structure having relatively speed-critical circuitry in the horizontal area of ​​the peripheral circuitry region and relatively non-speed-critical circuitry in the horizontal area of ​​the bank region; and a memory array structure attached to and vertically below the control circuitry structure, the memory array structure comprising an array of memory cells in the horizontal area of ​​the bank region.

[0181] Embodiment 20: The memory device of embodiment 19, wherein the array of memory cells comprises an array of dynamic random access memory (DRAM) cells.

[0182] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives that come within the scope of the following appended claims and their legal equivalents. For example, elements and features disclosed in connection with one embodiment may be combined with elements and features disclosed in connection with other embodiments of the present disclosure.

Claims

1. 1. A microelectronic device comprising: A peripheral circuit area, a central sub-region, and a peripheral circuitry region including two arm sub-regions extending from the central sub-region in a first horizontal direction, each of the two arm sub-regions having a length different from that of the central sub-region in a second horizontal direction perpendicular to the first horizontal direction; a bank region located horizontally outside the peripheral circuit region; A control circuit structure, a circuit portion that places emphasis on speed within a horizontal area of ​​the peripheral circuit portion region; and a control circuitry structure including relatively non-speed critical circuitry within a horizontal area of ​​the bank region; a memory array structure vertically below the control circuitry structure and comprising an array of memory cells within the horizontal area of ​​the bank region; A microelectronic device comprising:

2. The two arm sub-regions of the peripheral circuit region are a first arm sub-region extending substantially linearly from a first side of the central sub-region in the first horizontal direction, wherein a centerline of the first arm sub-region in the second horizontal direction is offset from a centerline of the central sub-region in the second horizontal direction; a second arm sub-region extending substantially linearly from a second side of the central sub-region in the first horizontal direction, wherein a centerline of the second arm sub-region in the second horizontal direction is offset from each of the centerline of the first arm sub-region and the centerline of the central sub-region; The microelectronic device of claim 1 , comprising:

3. the central sub-region of the peripheral circuit portion region has a first length in the second horizontal direction; 3. The microelectronic device of claim 2, wherein each of the first arm sub-region and the second arm sub-region of the peripheral circuitry region has a second length in the second horizontal direction that is less than the first length.

4. Within the horizontal area of ​​the central sub-region of the peripheral circuitry region, the control circuitry structure comprises: a data I / O and control section comprising data I / O and control circuitry; an internal clock and timing generator section adjacent to the data I / O and control section in the first horizontal direction, the internal clock and timing generator section comprising internal clock and timing generator circuitry; a command and address (CA) section adjacent to the internal clock and timing generator section in the first horizontal direction and including CA circuitry; a voltage generator section adjacent to each of the data I / O and control section, the internal clock and timing generator section, and the CA section in the second horizontal direction, each of the voltage generator sections comprising a voltage generator circuit portion; The microelectronic device of claim 2 , comprising:

5. Within the central sub-region of the peripheral circuitry region, the control circuitry structure comprises: a fuse section adjacent to the CA section in the first horizontal direction and including an antifuse circuit portion; a capacitor section including a plurality of capacitors interposed in the second horizontal direction between the voltage generator section, the data I / O and control section, the internal clock and timing generator section, the CA section, and the fuse section, respectively; The microelectronic device of claim 4 further comprising:

6. Within each horizontal area of ​​the first arm sub-region and the second arm sub-region of the peripheral circuitry region, the control circuitry structure a data junction section including a multiplexer (MUX) circuit portion; a package interface section including package interface circuitry; an analog section interposed between the data junction and the package interface section in the second horizontal direction, the analog section including one or more of an analog temperature distribution circuit, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device; The microelectronic device of claim 4 , comprising:

7. Each of the bank areas is a first bank sub-region, a first width in the first horizontal direction; and first bank sub-regions each including a first length in a second horizontal direction orthogonal to the first horizontal direction; a second bank sub-region, a second width in the first horizontal direction that is greater than the first width; and second bank sub-regions each including a second length in the second horizontal direction that is less than the first length; The microelectronic device of claim 2 , comprising:

8. Within each horizontal area of ​​the first bank sub-region, the control circuitry structure comprises: a transistor array section; a row decoder section including row decoder circuitry adjacent to the transistor array section in the first horizontal direction; column decoder sections each including a column decoder circuit portion adjacent to an opposite end of the transistor array section and the row decoder section in the second horizontal direction; The microelectronic device of claim 7 , comprising:

9. Within each horizontal area of ​​the second bank sub-region, the control circuitry structure comprises: an additional transistor array section; additional row decoder sections including additional row decoder circuitry interposed between the additional transistor array sections in the first horizontal direction; an additional column decoder section including additional column decoder circuitry adjacent to the additional transistor array section and the additional row decoder section in the second horizontal direction; The microelectronic device of claim 8 , comprising:

10. 10. The microelectronic device of claim 1, wherein within the horizontal area of ​​the peripheral circuitry region, the memory array structure comprises capacitors constructed and arranged to help power several devices in the control circuitry structure.

11. 1. A microelectronic device comprising: A peripheral circuit area, a street sub-region extending substantially linearly in a first horizontal direction; and a peripheral circuitry region including additional street sub-regions extending substantially linearly in a second horizontal direction perpendicular to the first horizontal direction, the additional street sub-regions horizontally intersecting the street sub-regions; bank regions separated from each other in the horizontal direction by the peripheral circuitry region; A control circuit structure, a circuit portion that places emphasis on speed within a horizontal area of ​​the peripheral circuit portion region; and a control circuitry structure including relatively non-speed critical circuitry within a horizontal area of ​​the bank region; a memory array structure vertically below the control circuitry structure and comprising an array of memory cells within the horizontal area of ​​the bank region; A microelectronic device comprising:

12. a centerline of the street sub-area in the first horizontal direction is substantially aligned with a centerline of the additional street sub-area in the first horizontal direction; The microelectronic device of claim 11 , wherein an additional centerline of the street sub-region in the second horizontal direction is substantially aligned with an additional centerline of the additional street sub-region in the second horizontal direction.

13. Within the horizontal area of ​​a street sub-region of the peripheral circuitry region, the control circuitry structure comprises: an internal clock and timing generator section including internal clock and timing generator circuitry, the internal clock and timing generator section at least partially horizontally overlapping an additional street sub-region of the peripheral circuitry region in the first horizontal direction; a data I / O and control section including data I / O and control circuitry adjacent to a first side of the internal clock and timing generator section in the first horizontal direction; a command and address (CA) section comprising CA circuitry adjacent to a second side of the internal clock and timing generator section in the first horizontal direction; The microelectronic device of claim 11 , comprising:

14. Within the horizontal area of ​​a street sub-region of the peripheral circuitry region, the control circuitry structure comprises: a first data junction section including multiplexer (MUX) circuitry interposed horizontally between two of the data I / O and control sections in the first horizontal direction; a second data junction section comprising additional MUX circuitry horizontally adjacent to the CA section in the first horizontal direction; a first voltage generator section comprising voltage generator circuitry adjacent one of the two data I / O and control sections in the first horizontal direction; a second voltage generator section comprising an additional voltage generator circuit portion adjacent to the second data junction section in the first horizontal direction; The microelectronic device of claim 13 further comprising:

15. Within the horizontal area of ​​a street sub-region of the peripheral circuitry region, the control circuitry structure comprises: an analog section interposed between the second data junction and the second voltage generator section in the first horizontal direction, the analog section comprising one or more of an analog temperature distribution circuitry, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device; a capacitor section interposed between the analog section and the second voltage generator section in the first horizontal direction, the capacitor section including a plurality of capacitors; a fuse section interposed between the capacitor section and the second voltage generator section in the first horizontal direction and including an antifuse circuit portion; The microelectronic device of claim 14 further comprising:

16. 16. The microelectronic device of claim 11, wherein within the horizontal area of ​​the additional street sub-region of the peripheral circuitry region, the control circuitry structure comprises package interface sections each comprising package interface circuitry.

17. Each of the bank areas is a bank sub-region; a throat region interposed in the first horizontal direction between the first group of bank sub-regions and the second group of bank sub-regions; The microelectronic device according to any one of claims 11 to 15, comprising:

18. Within each horizontal area of ​​the bank sub-regions of each of the bank regions, the control circuitry structure comprises: a transistor array section; a row decoder section including row decoder circuitry adjacent to the transistor array section in the second horizontal direction; a column decoder section including a column decoder circuit portion adjacent to the transistor array section and the row decoder section in the first horizontal direction; a bank logic section including a bank logic circuit portion adjacent to the column decoder section in the first horizontal direction; Equipped with Within the horizontal area of ​​the throat region of each of the bank regions, the control circuitry structure includes control logic device sections each including digital signal acquisition (DSA) circuitry and error correction code (ECC) circuitry.

20. The microelectronic device of claim 17, comprising:

19. 1. A memory device comprising: A peripheral circuit area, a central sub-region, and a peripheral circuitry region comprising at least two additional sub-regions extending horizontally from the central sub-region; a bank region adjacent to the peripheral circuit region in a horizontal direction; A control circuit structure, a circuit portion that places emphasis on speed within a horizontal area of ​​the peripheral circuit portion region; and A circuit portion in the horizontal area of ​​the bank region where speed is not a priority a control circuit structure comprising: a memory array structure attached to and vertically below the control circuitry structure, the memory array structure comprising an array of memory cells within the horizontal area of ​​the bank region; A memory device comprising:

20. 20. The memory device of claim 19, wherein the array of memory cells comprises an array of dynamic random access memory (DRAM) cells.

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