High-end memory chip asynchronous test system based on distributed architecture

Abstract

The invention discloses a high-end memory chip asynchronous test system based on a distributed architecture, which relates to the technical field of chip testing, and comprises a state modeling module, a master control end initialization and test end access, memory chip test task pool construction, test end state analysis in combination with historical test load and historical fault information, and memory chip asynchronous test. Generating an optimized scheduling strategy; the scheduling module is used for performing task division and asynchronous scheduling on the memory chip test task pool by adopting an intelligent scheduling algorithm based on an optimized scheduling strategy to generate an asynchronous data flow queue; according to the issuing module, the test end receives the asynchronous data flow queue in an asynchronous mode to carry out protocol unpacking and task mapping, and a memory chip function test task is obtained and issued; according to the method, the test throughput rate and the resource utilization rate are improved by asynchronously sequencing and scheduling tasks, the task scheduling delay is reduced, the load of each test end is balanced, and meanwhile, the horizontal expansibility and the fault-tolerant capability are enhanced.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to an asynchronous testing system for high-end memory chips based on a distributed architecture. Background Technology

[0002] With the continuous evolution of integrated circuit manufacturing processes and the increasing complexity of high-end memory chip architectures, existing functional testing methods face unprecedented challenges. Current memory chip testing technologies typically rely on centralized test control systems, using static task scheduling and serial test processes to execute instruction-driven operations and acquire responses for each functional module during functional verification. Typical testing methods include using protocol controllers for single-threaded command issuance and acquiring test data through fixed sampling periods. This architecture is feasible for handling chip testing tasks of moderate complexity, capable of performing basic verification of modules such as data transmission links, logical functions, address decoding, and read / write operations, and the supporting test environment and hardware interfaces are relatively mature.

[0003] While some attempts have been made to implement distributed testing architectures, mitigating test load issues to some extent by adding ATE nodes or employing time-sharing multiplexing, existing distributed solutions often still require frequent synchronization and coordination between nodes, resulting in persistent test latency and resource contention problems. For example, test tasks must wait for all test nodes to complete the same test phase before proceeding to the next phase, and result uploading and verification rely on centralized aggregation, limiting the scalability and elasticity of the testing system. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides an asynchronous testing system for high-end memory chips based on a distributed architecture to solve the problems of insufficient synchronization and coordination between nodes in the testing system, which leads to idle test channels and limited scalability.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: This invention provides an asynchronous testing system for high-end memory chips based on a distributed architecture, which includes a state modeling module, which initializes the master control terminal and connects to the test terminal, constructs a memory chip test task pool, analyzes the test terminal status by combining historical test load and historical fault information, and generates an optimized scheduling strategy. The scheduling module, based on an optimized scheduling strategy, uses an intelligent scheduling algorithm to divide and asynchronously schedule the memory chip test task pool, generating an asynchronous data stream queue. In the distribution module, the test end receives the asynchronous data stream queue in an asynchronous manner, performs protocol unpacking and task mapping, obtains the memory chip functional test task, and then distributes it. The acquisition module compiles test paths and generates signals for the memory chip functional test task, obtains test control information, drives the test terminal to perform memory chip functional tests, and acquires test data for preprocessing. The output module uploads the preprocessed memory chip test data to the main control unit for aggregation and structural unification, obtains categorized test information, and performs consistency verification and functional status determination through a multi-channel cross-validation algorithm to obtain the asynchronous test results of the structured memory chip.

[0007] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the specific steps for initializing the master control terminal and connecting it to the test terminal, and constructing a memory chip test task pool, are as follows: Initialize the main control terminal, connect multiple test terminals to establish communication links, load test terminal configuration parameters and test capability identifiers, and generate test resource descriptions; A memory chip test task pool is constructed by utilizing test resource descriptions and memory chip test task requirements.

[0008] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the specific steps for generating the optimized scheduling strategy are as follows: Based on the memory chip test task pool and test resource description, historical test load information and historical fault information are called to collect operation indicators and evaluate performance of the test terminal, and obtain the test terminal analysis set. The test-end status evaluation algorithm is used to analyze the running status and model the performance indicators of the test-end analysis set to obtain the test-end status information. For the test terminal status information and memory chip test task pool, task-state feature matching and scheduling constraint extraction are performed to generate a scheduling optimization rule base, which is then called to obtain the optimized scheduling strategy.

[0009] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the historical test load information is obtained by extracting task load and statistically analyzing resource usage from historical test data. The historical fault information is obtained by identifying fault types and structuring events from historical test data.

[0010] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the step of using an intelligent scheduling algorithm to divide and asynchronously schedule the memory chip test task pool based on an optimized scheduling strategy, and generating an asynchronous data stream queue, includes the following specific steps: For the optimized scheduling strategy and memory chip test task pool, task features are extracted and scheduling dimensions are calibrated to generate a task partitioning parameter set; Through intelligent scheduling algorithms, the task priority is sorted and asynchronous scheduling paths are generated by dividing the task parameter set, and the scheduling execution instruction set is output. Based on the scheduling and execution instruction set, test tasks are organized in the memory chip test task pool, an asynchronous task execution process is constructed, and task priority sorting and resource allocation are performed to generate an asynchronous data stream queue.

[0011] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the testing terminal receives an asynchronous data stream queue in an asynchronous manner, performs protocol unpacking and task mapping to obtain memory chip functional test tasks, and then distributes them. The specific steps are as follows. The test end receives the asynchronous data stream queue in an asynchronous manner, performs protocol parsing and content extraction operations, and generates a protocol unpacking result set. The protocol unpacking result set is used to identify tasks, match functions, and calibrate test terminal resources to generate memory chip functional test tasks, which are then assigned to the corresponding test terminals.

[0012] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the steps of compiling test paths and generating signals for the memory chip functional testing task to obtain test control information, driving the test terminal to perform memory chip functional testing, and collecting test data for preprocessing are as follows. For memory chip functional testing tasks, path extraction, operation sequence construction, and execution logic parsing are performed to generate a test path structure; For the test path structure, test signal rules are retrieved and trigger sequence is reconstructed to generate test control information, drive the test terminal to perform memory chip functional testing, and collect test data for preprocessing.

[0013] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the test data includes voltage waveform data, timing response data, memory output status data, and functional test comparison result data. The preprocessing includes denoising, structured mapping, and anomaly removal.

[0014] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the steps for uploading the preprocessed memory chip test data to the main control terminal for aggregation and structural unification to obtain categorized test information are as follows: The preprocessed test data is uploaded to the main control terminal for reception and caching, generating cached test data; The cached test data is aggregated for test content, aligned for time series, and categorized for structural tags to generate unified test data. Then, content filtering and multi-dimensional result extraction are performed to obtain categorized test information.

[0015] As a preferred embodiment of the high-end memory chip asynchronous testing system based on a distributed architecture described in this invention, the specific steps for obtaining the asynchronous test results of the structured memory chip through a multi-channel cross-validation algorithm for consistency verification and functional status determination are as follows. By using a multi-channel cross-validation algorithm, the classification test information is compared and similarity is measured between channels to generate a consistency verification information set. By mapping the consistency verification information set and the categorized test information to multi-dimensional functional states and making multi-condition judgments, asynchronous test results for structured memory chips are generated.

[0016] The beneficial effects of this invention are as follows: By real-time collection and evaluation of test terminal load and fault status, intelligent scheduling rules are generated and scheduling tasks are asynchronously sorted, generating an asynchronous data stream queue. This achieves dynamic adaptive matching between test tasks and test terminal capabilities. Then, the asynchronous data stream queue drives each test terminal to initiate functional verification in parallel, eliminating synchronous waiting bottlenecks and ensuring that test tasks can be efficiently distributed and executed in a multi-channel environment. This improves test throughput and resource utilization, reduces task scheduling latency, balances the load of each test terminal, and enhances horizontal scalability and fault tolerance. Furthermore, it improves the accuracy and traceability of test results, reduces hardware resource investment costs, and decreases test development and maintenance workload. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of an asynchronous testing system for high-end memory chips based on a distributed architecture.

[0019] Figure 2 A flowchart for constructing a memory chip test task pool.

[0020] Figure 3 This is a flowchart for signal generation and test execution.

[0021] Figure 4A flowchart for obtaining asynchronous test results of structured memory chips. Detailed Implementation

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0024] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0025] Reference Figures 1-4 This is one embodiment of the present invention, which provides an asynchronous testing system for high-end memory chips based on a distributed architecture, comprising the following steps: The state modeling module initializes the main control terminal and connects it to the test terminal, constructing a memory chip test task pool.

[0026] Initialize the main control terminal, connect multiple test terminals to establish communication links, load test terminal configuration parameters and test capability identifiers, and generate test resource descriptions.

[0027] Specifically, the main control processing environment is initialized, the running process is started and the control program configuration file is loaded; the number of test terminals, communication ports and authentication information specified in the configuration file are parsed, the specified IP segments in the local area network are scanned in sequence, and handshake signal packets are sent to each test terminal through the Ethernet interface and the unique device identification code, network status code and timestamp information in the response packet are received; Verify the consistency between the authentication field content in the response packet and the authorization code in the test terminal configuration parameter file. If the match is successful, write it to the master control terminal's cached connection list. Establish persistent TCP connections between the master control terminal and each test terminal, start the connection maintenance process, and set the communication heartbeat interval, exemplarily set to 30 seconds. Send a test terminal configuration parameter synchronization command through the persistent connection channel to retrieve the number of test channels, signal sampling capabilities, supported test type identifiers, and test script execution format description files stored by each test terminal. Classify the obtained test terminal configuration parameter content and test capability identifiers according to the test terminal number to obtain the test resource description.

[0028] A memory chip test task pool is constructed by utilizing test resource descriptions and memory chip test task requirements.

[0029] Specifically, the process involves reading the number of test channels, test signal sampling capability, supported test type identifiers, and test script execution format description file content corresponding to each test terminal number in the test resource description; extracting the test task number, required test type, test execution frequency, test signal sampling accuracy requirements, and test script format requirements for each test task in the memory chip test task requirements; performing field-level item-by-item matching operations; precisely comparing the test type required by the test task with the test type identifiers supported by the test terminal in the test resource description; numerically comparing the test signal sampling accuracy requirements in the test task with the test signal sampling capability in the test resource description, ensuring that the test signal sampling accuracy requirement is not higher than the test signal sampling capability; and verifying the consistency between the test script format requirements in the test task and the test script execution format description file content. Add the test task number that successfully matches the test resource description with the memory chip test task requirements to the memory chip test task sublist corresponding to the current test terminal number; after traversing and filtering all test task numbers, create memory chip test task sublists according to the test terminal number; combine and organize all memory chip test task sublists according to the test task number to generate a memory chip test task pool. It should be noted that the memory chip test task requirements are obtained by reading the preset task scheduling configuration file. The memory chip test task requirements include information such as memory chip test task number, test target type, test signal type, execution frequency, sampling accuracy, script format requirements, and expected test duration.

[0030] By combining historical test load and historical fault information, the status of the test terminal is analyzed, and an optimized scheduling strategy is generated.

[0031] Based on the memory chip test task pool and test resource description, historical test load information and historical fault information are called to collect operation indicators and evaluate performance of the test terminal, and obtain the test terminal analysis set.

[0032] Specifically, according to the test terminal number in the test resource description, the corresponding historical test load information and historical fault information are retrieved; for each test terminal, the task execution frequency, resource utilization and response latency are collected to obtain the operation indicator data, with an example collection cycle of once per hour; Based on the operational metrics data, obtain the performance metrics of each test terminal, including load rate, failure frequency, and average recovery time; score the performance metrics, for example, a load rate exceeding 80% is considered high load, and a failure frequency exceeding 5% is considered high failure rate, and obtain the performance score results, which are used to reflect the current performance status of the test terminal; integrate the performance score results with the operational metrics data to generate a test terminal analysis set containing test terminal identifiers, performance scores, and operational metrics data.

[0033] By using the test-end status evaluation algorithm, the test-end analysis set is analyzed for its running status and performance indicators are modeled to obtain the test-end status information.

[0034] Specifically, for each test terminal identifier in the test terminal analysis set, task execution frequency, resource utilization rate, and response latency are extracted; the task execution frequency is standardized to convert the number of tasks executed by each test terminal per unit time into a normalized numerical range; the average value of each sub-resource indicator in the resource utilization rate is processed to extract the total resource occupancy ratio as a resource load reference; and the average value of the response latency over the past three periods is taken as the current response level benchmark. Using standardized task execution frequency, average resource utilization, and response latency as input factors, a composite performance index is generated through a weighted average. For example, the weights for task execution frequency, resource utilization, and response latency are set to 0.4, 0.3, and 0.3 respectively. Based on the composite performance index results and performance scores, the test endpoint status is classified. For example, when the composite performance index is higher than 0.75, the load rate exceeds 80%, and the failure frequency exceeds 5%, it is classified as "abnormal high-pressure state." For instance, when the composite performance index is between 0.4 and 0.75, the load rate does not exceed 80%, and the failure frequency does not exceed 5%, it is classified as "stable operating state." For instance, when the composite performance index is lower than 0.4, it is classified as "inefficient idle state." The test endpoint identifier is then associated with the classified status to output the test endpoint status information. It should be noted that the expression for generating the composite performance index using standardized task execution frequency, average resource utilization, and response latency as input factors, and weighted by input weights, is as follows: ; in, It is a composite performance index. It is a standardized task frequency. It is the resource utilization rate. It is response delay.

[0035] For the test terminal status information and memory chip test task pool, task-state feature matching and scheduling constraint extraction are performed to generate a scheduling optimization rule base, which is then called to obtain the optimized scheduling strategy.

[0036] Specifically, it iterates through each test task in the memory chip test task pool and extracts the test type, task complexity, resource requirements, and maximum tolerable response latency as task features; it iterates through each test terminal identifier in the test terminal status information and extracts the corresponding status classification label, standardized task execution frequency, average resource utilization, and response latency as status features. The test task characteristics and test terminal status characteristics are compared one by one at the feature level. For example, if the task complexity does not exceed 0.8 times the upper limit of the execution frequency, it is considered to be suitable. For example, if the resource utilization rate plus the resource demand does not exceed 85%, it is considered to be suitable. For example, if the response latency is less than 90% of the upper limit of the tolerable response latency, it is considered to be suitable. For each set of test tasks and test terminals, a test terminal adaptation score is calculated. For example, 1 point is awarded for each successful adaptation, and a score of 3 indicates a perfect match. Test terminals with the status category label "stable operation" are extracted as priority candidates. Task allocation combinations that perfectly match these test terminals are selected, and the corresponding test task number, test terminal identifier, and test terminal adaptation score are recorded. All assignment combinations of test tasks and test terminals are summarized to generate a scheduling optimization rule base. Rule entries include task characteristic parameters, test terminal status parameters, test terminal adaptation scores, and allocation priorities. When generating the optimized scheduling strategy, test terminals are sorted from high to low according to their adaptation scores. The test terminal with the highest priority is selected for task mapping to achieve the optimal allocation of tasks and test terminals, and the optimized scheduling strategy is output.

[0037] Historical test load information is obtained by extracting task load and statistically analyzing resource usage from historical test data.

[0038] Specifically, the process involves: reading each task execution record from the historical test data; categorizing each task execution record by test endpoint identifier to form task execution sequences corresponding to different test endpoints; iterating through the time intervals of adjacent tasks in each task execution sequence and extracting consecutive tasks with an interval not exceeding 10 seconds (as exemplified) as a load segment; counting the number of tasks within each load segment to determine the task load of that segment; summing the resource usage of all tasks within each load segment to determine the total resource usage of that segment; recording the task load and total resource usage of all load segments to obtain the historical task load sequence and resource usage statistics sequence for the corresponding test endpoint; and outputting historical test load information based on the task load sequence and resource usage statistics sequence.

[0039] Historical fault information is obtained by identifying fault types and structuring events from historical test data.

[0040] Specifically, the process involves reading the status information, error information, and output result information recorded at different time points from historical test data, extracting abnormal status content and abnormal output feature information from the test terminal, comparing the standard output data sequence with the actual output data sequence from the test terminal, marking the location segments with deviations and their corresponding signal labels, extracting the abnormal response relationship between the associated control signals and controlled response signals from the test terminal, and extracting the evolution pattern in the time dimension by combining the first deviation time, duration, and response sequence of the abnormal status content and abnormal output feature information to form signal failure timing features. Based on the abnormal response relationship and signal failure timing features, the process matches the corresponding fault event type, groups similar events according to the fault event type classification standard, and uses the event number, occurrence time, affecting signal, abnormal status information, and test terminal location information to form standardized event entries. All standardized event entries are sorted according to the test terminal number and timestamp order to generate historical fault information. It should be noted that "abnormal status content" refers to the abnormal operating status information (such as error codes, warning signs, and abnormal status bits) recorded by the test terminal when a fault occurs, while "abnormal output characteristic information" refers to signal values, logical results, or data patterns in the historical test terminal test data that have significant deviations from normal output.

[0041] The scheduling module, based on an optimized scheduling strategy, uses an intelligent scheduling algorithm to divide and asynchronously schedule the memory chip test task pool, generating an asynchronous data stream queue.

[0042] For the optimized scheduling strategy and memory chip test task pool, task features are extracted and scheduling dimensions are calibrated to generate a task partitioning parameter set.

[0043] Specifically, based on task characteristics, and combined with the test task number, test terminal identifier, and test terminal adaptation score recorded in the optimized scheduling strategy, the three key scheduling dimensions of task complexity, resource requirements, and maximum tolerable response latency are calibrated according to the adaptation of the test terminal corresponding to the task characteristics. The task complexity scheduling dimension calculates the difference between the task complexity and the standardized task execution frequency of the matched test server, with an acceptable range of 0.8 (for example). The resource requirement scheduling dimension uses the average resource utilization rate of the matched test server combined with the resource requirement, with an acceptable range of 85% (for example). The maximum tolerable response latency scheduling dimension calculates the difference between the response latency of the matched test server and the maximum tolerable response latency, with an acceptable range of 0.9 (for example). Based on the calculation results of these key dimensions—task complexity, resource requirement, and maximum tolerable response latency—the task number, the values ​​of the three scheduling dimensions, and their corresponding acceptable scheduling range labels are extracted for each test task to generate a task partitioning parameter set.

[0044] The intelligent scheduling algorithm is used to sort the task priority and generate asynchronous scheduling paths by dividing the task parameter set, and output the scheduling execution instruction set.

[0045] Specifically, through an intelligent scheduling algorithm, the task complexity is normalized and mapped to the complexity dimension values ​​of all tasks within the task partitioning parameter set to obtain a standardized complexity value, and then sorted in ascending order according to the standardized complexity value to form a basic sorting sequence. Next, the resource demand is summed with the average resource utilization rate of the corresponding matching test end. If the sum exceeds the example value of 85%, it is labeled as high resource; otherwise, it is labeled as acceptable resource. The high resource labeled task is moved three positions to the right in the sorting sequence to reflect the resource scarcity. The ratio of the maximum tolerable response latency to the response latency of the matching test end is calculated. If the ratio exceeds the exemplary ratio of 0.9, a high latency sensitive label is marked, and the task marked with the high latency sensitive label is moved two places forward in the sorting sequence to prioritize scheduling efficiency. The adjusted sorting sequence is used as the final task priority order. Based on the final task priority order and the test terminal adaptation score of each test task, a one-to-one mapping is performed between the test terminal and the task. Under the condition of ensuring the uniqueness of the mapping, asynchronous scheduling paths are generated sequentially. The asynchronous scheduling paths are recorded in the form of task number and test terminal identifier pairs, and the scheduling execution instruction set is output in combination with the start scheduling time point.

[0046] Based on the scheduling and execution instruction set, test tasks are organized in the memory chip test task pool, an asynchronous task execution process is constructed, and task priority sorting and resource allocation are performed to generate an asynchronous data stream queue.

[0047] Specifically, the task number and corresponding test terminal identifier pair are extracted from the scheduling execution instruction set. The scheduling time point is used as the task start time marker. All test task information in the test task pool is read sequentially. Test tasks to be executed are filtered in order of final task priority. The test terminal adaptation score and the assigned test terminal identifier of each test task are read for consistency verification. Test tasks with adaptation scores higher than the exemplary 0.6 are bound to the target test terminal and marked as schedulable. The resource parameters required for the execution of each test task are extracted and compared with the available resource values ​​of the corresponding test terminal at the scheduling time point to obtain the resource load ratio. If any resource load ratio exceeds the exemplary 85%, the corresponding task is marked as resource-intensive and the scheduling time is postponed for five units. If all resource load ratios are lower than the exemplary 85%, the test task is included in the executable queue of the current time period. The scheduling information of all executable tasks and their corresponding test terminals is grouped and arranged according to the scheduling time point and an asynchronous data stream queue is generated.

[0048] The delivery module receives the asynchronous data stream queue in an asynchronous manner, performs protocol unpacking and task mapping, obtains the memory chip functional test task, and then delivers it.

[0049] The test server receives the asynchronous data stream queue asynchronously, performs protocol parsing and content extraction operations, and generates a protocol unpacking result set.

[0050] Specifically, it receives an asynchronous data stream queue, reads test task scheduling information one by one in the order of scheduling time, reads the test terminal identifier in each scheduling information and matches the test terminal number to confirm that the received task belongs to the test terminal; extracts the test task number bound in the scheduling information and calls the test task information with the corresponding number in the task pool, and parses the test task content fields including test item code, test parameter configuration, resource usage parameters and task start instruction fields. The test task content fields are broken down into standard protocol segments. Each protocol segment is arranged in field order to generate a protocol structure block. For each protocol structure block, the key values ​​of instructions, parameter values, and test item numbers are extracted using protocol field mapping rules and combined to form a protocol content item set. Each protocol content item is compared with the corresponding test protocol format of the test terminal for field consistency, and the field position, length, and content structure are recorded. Valid fields are extracted to form a protocol instruction sequence. The protocol instruction sequence is used as the protocol unpacking result of the current task, numbered and labeled according to the task number, and stored as a protocol unpacking result set.

[0051] The protocol unpacking result set is used to identify tasks, match functions, and calibrate test terminal resources to generate memory chip functional test tasks, which are then assigned to the corresponding test terminals.

[0052] Specifically, based on the task number bound to each protocol instruction sequence in the protocol unpacking result set, the basic information of the test task with the same number in the memory chip test task pool is read, and the test task name, test function description and required test resource type are extracted. Based on the test item number field in the protocol content item set, match the function item entries recorded in the test function item parameter table to obtain the test instruction parameter group and target function logic required for each test item; compare the value range of the standard values ​​of the parameters in the protocol content item set with those in the test function item parameter table, and compare the standard value range of the corresponding test item in the protocol content item set with those in the test function item parameter table; If the set of protocol content entries falls within the range of the exemplary settings, such as 3.3 to 3.7, and the enumerated parameters belong to the exemplary setting set, such as {"ENABLE", "DISABLE"}, and meet the exemplary setting format, such as an 8-digit hexadecimal string starting with "0x", then the protocol content entries are determined to conform to the parameter specifications and are retained; otherwise, they are discarded. The filtered protocol content items are clustered and grouped according to the test item number to form a test task function item set. For each function item in the test task function item set, test terminal numbers with a function adaptability greater than the exemplary setting of 0.8 are selected as the available test terminal set. Combining the number of available resources, the number of tasks being executed, and the average execution time of tasks recorded in the current resource status table of the test terminal, the available test terminal set is sorted by resource idleness. The test terminal number with the highest ranking and the ability to execute all test functions is selected as the final test terminal allocation number for the test task function item set. The basic information of the test task, the test task function item set, and the final test terminal allocation number are bound together to form a complete memory chip functional test task, which is submitted to the corresponding test terminal according to the task number.

[0053] The acquisition module compiles test paths and generates signals for the memory chip functional test task, obtains test control information, drives the test terminal to perform memory chip functional tests, and collects test data for preprocessing.

[0054] For memory chip functional testing tasks, path extraction, operation sequence construction, and execution logic parsing are performed to generate a test path structure.

[0055] Specifically, based on the set of test task functions in the memory chip functional test task, the memory array address range and row and column number information corresponding to each test task function item are located, and the transmission path identifier of the test signal from the test end to the physical memory array is determined, including the target row selection signal, the address decoding path and the data bus path. For example, when the target address of the function item is 0x1000 to 0x1FFF, the row selection path of the second chip, the address decoder LUT index number 5 and the data bus channel 3 are selected. Based on the path extraction results and the test task function item set, extract the instruction parameter group corresponding to the test item number from the protocol content item set of the protocol unpacking result set, and combine the test command sequence according to the execution order of the function items. For example, the function item is first arranged into the "ACTIVATE-address-WRITE-data-PRECHARGE" command, and then the corresponding command is concatenated according to the next function item number in the test task function item set. All commands form a continuous operation frame and are attached with start delay and command interval time parameters. For each test command in the operation sequence, the dependencies and branching logic between commands are analyzed according to the description in the test function parameter table. The result judgment steps after the "READ" command are refined into conditional branches: when the return value obtained by the test end from the target storage array by executing the "READ" command matches the example (such as 0x00FF), the next command is executed; otherwise, the retry logic is triggered and the number of retryes is recorded. The retry logic and the normal logic path are uniformly encapsulated into a state machine format. All commands, branches and retry nodes, together with the path identifier, constitute the test path structure.

[0056] For the test path structure, test signal rules are retrieved and trigger sequence is reconstructed to generate test control information, drive the test terminal to perform memory chip functional testing, and collect test data for preprocessing.

[0057] Specifically, the test commands, signal transmission paths, and identification information contained in the test path structure are read, and the target address information, the address decoder logic path to be traversed, the target row strobe signal channel number, and the data bus channel number corresponding to each test command are obtained one by one. The control signal activation conditions, triggering order, and time interval parameters corresponding to each test command are searched in the signal control rule set. Based on the found signal control rules, each test command sequence arranged in the path structure is mapped one-to-one with the control rules to obtain timing parameters such as the type of control signal to be activated, the signal triggering order, the duration of the control signal, and the minimum interval between adjacent commands required for the actual execution of each test command. Based on the mapping results, the commands are rearranged and combined to form a complete test control flow, generating test control information. The test terminal initiates and executes functional test tasks based on the test control information. During the test, the test data and time stamp information collected by the test terminal are combined and matched according to the test command number to obtain test data, which is then preprocessed to obtain preprocessed test data.

[0058] The test data includes voltage waveform data, timing response data, stored output status data, and functional test comparison results data.

[0059] Preprocessing includes denoising, structured mapping, and anomaly removal.

[0060] Specifically, the median filtering method is used to smooth the test data sequence with a sampling window size of 5 points as an example. After removing random noise, the data is standardized and the maximum and minimum values ​​are used as mapping boundaries. For example, the minimum value is 0.2 and the maximum value is 4.6, and the response value is linearly mapped to the [0,1] interval. The standardized test data is mapped to the address identifier, data channel number, and chip number dimensions of the test path structure according to the test command number, forming structured data entries. The difference between the average value of the sampling points and the expected response template is extracted. If the difference between the average value of the sampling points and the expected response template exceeds the example of 0.8, it is judged as an anomaly and is removed, thus obtaining the preprocessed test data.

[0061] The output module uploads the preprocessed memory chip test data to the main control unit for aggregation and structural unification, resulting in categorized test information.

[0062] The preprocessed test data is uploaded to the main control unit for reception and caching, generating cached test data.

[0063] Specifically, the test command number, response value, and timestamp contained in the preprocessed memory chip test data are recombined according to the order of the test command number. The test end data upload interface is called to upload the test command number, response value, and timestamp together to the designated address buffer of the main control end. After receiving each group of test command number, response value, and timestamp, the main control end writes them into the corresponding data fields in sequence. After the preprocessed memory chip test data arrives, the timing control logic of the main control end starts the buffer process, writes the received test command number, response value, and timestamp into the built-in storage unit of the test data buffer and completes the position mapping. The cached test data is formed by continuously filling data and arranging it in the order of command number.

[0064] The cached test data is aggregated for test content, aligned for time series, and categorized for structural tags to generate unified test data. Then, content filtering and multi-dimensional result extraction are performed to obtain categorized test information.

[0065] Specifically, the test command number, response value, and timestamp are extracted from the cached test data. The same test content is aggregated according to the test command number. All timestamps corresponding to each aggregated test command number are arranged in chronological order to generate time-series aligned response value groups. A set of structure tags is set for each test command number, and the corresponding response value groups and time series are written into the corresponding fields of the structure tags. This generates unified test data containing test command number, aligned response value sequence, time tag sequence, and structure tag fields. A response value filtering range is set for each test command number in the unified test data. For example, the filtering range is set to a value range within 5% above and below the historical average response value of each test command number. Records with response values ​​exceeding the filtering range are marked as abnormal response values ​​and removed from the response value sequence. The minimum, maximum, mean, standard deviation, duration, and fluctuation frequency of the remaining valid response values ​​in each test command number are calculated and written into the classification field. Finally, categorized test information containing aggregation information, aligned time series, structure tags, and statistical characteristics is generated by summarizing the test command numbers.

[0066] A multi-channel cross-validation algorithm is used to perform consistency verification and functional status determination, thereby obtaining asynchronous test results for the structured memory chip.

[0067] By using a multi-channel cross-validation algorithm, the results of the categorized test information are compared and similarity measures are taken between channels to generate a consistency verification information set.

[0068] Specifically, statistical features such as minimum, maximum, mean, standard deviation, duration, and fluctuation frequency are extracted from the categorized test information for multiple test channels. The categorized test information of different test channels is matched based on the test command numbers with the same or similar functions. The similarity of the categorized test information between each test channel is calculated using the Pearson correlation coefficient. The consistency of the test results of each channel is judged by comparing the similarity. Test results with a similarity higher than the example of 0.85 are marked as consistent and pass. Otherwise, they are marked as inconsistent and fail. For the abnormal cases, the abnormal channel number and abnormal type are recorded. The similarity and consistency marks of all channels are summarized to form a consistency verification information set. It should be noted that the Pearson correlation coefficient is used to calculate the similarity of the categorized test information among the test channels: ; in, This is the Pearson correlation coefficient, with a value ranging from -1 to 1. The closer it is to (-1, 1), the stronger the similarity of the classification test information between the test channels. It is the number of test information categorized across all test channels. It is an index variable for classifying test information across test channels. It is the first Classify test information among individual test channels variables, It is a classification of test information between test channels. The average variable value, It is the first Classify test information among individual test channels variables, It is a classification of test information between test channels. The average variable value.

[0069] By mapping the consistency verification information set and the categorized test information to multi-dimensional functional states and making multi-condition judgments, asynchronous test results for structured memory chips are generated.

[0070] By mapping the consistency verification information set and the categorized test information to multi-dimensional functional states and making multi-condition judgments, asynchronous test results for structured memory chips are generated.

[0071] Specifically, based on the consistency verification information set and the classification test information, statistical features and consistency markers such as minimum, maximum, mean, standard deviation, duration, and fluctuation frequency corresponding to each test command number are extracted. Combined with the memory chip asynchronous test function mapping rule base, the function status of each test command number is mapped separately. The classification test information and consistency verification information of each test command number are compared in turn. First, it is determined whether the abnormal response value ratio exceeds the exemplary 10%. If it exceeds, it is marked as a fault. Otherwise, it is further determined whether the similarity between test channels is lower than the exemplary 0.85. If it is lower, it is marked as a warning. If it does not meet the requirements, it is further compared whether the duration exceeds the exemplary normal range of 10%. If it exceeds, it is marked as a warning. Otherwise, it is marked as normal. The function status of each test command number is classified and integrated according to the test task order to generate the structured memory chip asynchronous test results. It should be noted that the construction process of the memory chip asynchronous test function mapping rule library is as follows: collect historical test results and corresponding functional status information of different test function items of memory chips; organize the mapping relationship between each test function item and functional status, and establish the correspondence rules between functional status and test response characteristics; set the judgment and classification conditions in the mapping rules; and store the organized functional status mapping rules in a structured manner according to the test function items to form the memory chip asynchronous test function mapping rule library.

[0072] In summary, this invention achieves dynamic adaptive matching between test tasks and test terminal capabilities by: real-time acquisition and evaluation of test terminal load and fault status; intelligent generation of scheduling rules and asynchronous sorting of scheduling tasks; and generation of an asynchronous data stream queue. Then, the asynchronous data stream queue drives each test terminal to initiate functional verification in parallel, eliminating synchronous waiting bottlenecks. This ensures efficient distribution and execution of test tasks in a multi-channel environment, improving test throughput and resource utilization, reducing task scheduling latency, balancing the load of each test terminal, and enhancing horizontal scalability and fault tolerance. Furthermore, it improves the accuracy and traceability of test results, reduces hardware resource investment costs, and decreases test development and maintenance workload.

[0073] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An asynchronous testing system for high-end memory chips based on a distributed architecture, characterized in that: include, The state modeling module initializes the main control terminal and connects to the test terminal, constructs a memory chip test task pool, analyzes the test terminal status by combining historical test load and historical fault information, and generates an optimized scheduling strategy. The scheduling module, based on an optimized scheduling strategy, uses an intelligent scheduling algorithm to divide and asynchronously schedule the memory chip test task pool, generating an asynchronous data stream queue. In the distribution module, the test end receives the asynchronous data stream queue in an asynchronous manner, performs protocol unpacking and task mapping, obtains the memory chip functional test task, and then distributes it. The acquisition module compiles test paths and generates signals for the memory chip functional test task, obtains test control information, drives the test terminal to perform memory chip functional tests, and acquires test data for preprocessing. The output module uploads the preprocessed memory chip test data to the main control unit for aggregation and structural unification, obtains categorized test information, and performs consistency verification and functional status determination through a multi-channel cross-validation algorithm to obtain the asynchronous test results of the structured memory chip.

2. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 1, characterized in that: The steps for initializing the main control terminal and connecting it to the test terminal to build a memory chip test task pool are as follows: Initialize the main control terminal, connect multiple test terminals to establish communication links, load test terminal configuration parameters and test capability identifiers, and generate test resource descriptions; A memory chip test task pool is constructed by utilizing test resource descriptions and memory chip test task requirements.

3. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 1, characterized in that: The specific steps for generating the optimized scheduling strategy are as follows: Based on the memory chip test task pool and test resource description, historical test load information and historical fault information are called to collect operation indicators and evaluate performance of the test terminal, and obtain the test terminal analysis set. The test-end status evaluation algorithm is used to analyze the running status and model the performance indicators of the test-end analysis set to obtain the test-end status information. For the test terminal status information and memory chip test task pool, task-state feature matching and scheduling constraint extraction are performed to generate a scheduling optimization rule base, which is then called to obtain the optimized scheduling strategy.

4. The asynchronous testing system for high-end memory chips based on a distributed architecture as described in claim 3, characterized in that: The historical test load information is obtained by extracting task load and statistically analyzing resource usage from historical test data. The historical fault information is obtained by identifying fault types and structuring events from historical test data.

5. The asynchronous testing system for high-end memory chips based on a distributed architecture as described in claim 3, characterized in that: The process involves optimizing the scheduling strategy and employing an intelligent scheduling algorithm to divide and asynchronously schedule tasks within the memory chip test task pool, generating an asynchronous data stream queue. The specific steps are as follows: For the optimized scheduling strategy and memory chip test task pool, task features are extracted and scheduling dimensions are calibrated to generate a task partitioning parameter set; The intelligent scheduling algorithm is used to divide the task parameter set, sort the task priority and generate asynchronous scheduling paths, and output the scheduling execution instruction set. Based on the scheduling and execution instruction set, test tasks are organized in the memory chip test task pool, an asynchronous task execution process is constructed, and task priority sorting and resource allocation are performed to generate an asynchronous data stream queue.

6. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 5, characterized in that: The test terminal receives asynchronous data stream queues in an asynchronous manner, performs protocol unpacking and task mapping to obtain memory chip functional test tasks, and then distributes them. The specific steps are as follows. The test end receives the asynchronous data stream queue in an asynchronous manner, performs protocol parsing and content extraction operations, and generates a protocol unpacking result set. The protocol unpacking result set is used to identify tasks, match functions, and calibrate test terminal resources to generate memory chip functional test tasks, which are then assigned to the corresponding test terminals.

7. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 6, characterized in that: The process of compiling test paths and generating signals for the memory chip functional test task to obtain test control information, driving the test terminal to perform memory chip functional tests, and collecting test data for preprocessing are detailed below. For memory chip functional testing tasks, path extraction, operation sequence construction, and execution logic parsing are performed to generate a test path structure; For the test path structure, test signal rules are retrieved and trigger sequence is reconstructed to generate test control information, drive the test terminal to perform memory chip functional testing, and collect test data for preprocessing.

8. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 7, characterized in that: The test data includes voltage waveform data, timing response data, stored output status data, and functional test comparison results data; The preprocessing includes denoising, structured mapping, and anomaly removal.

9. The high-end memory chip asynchronous testing system based on a distributed architecture as described in claim 7, characterized in that: The preprocessed memory chip test data is uploaded to the main control unit for aggregation and structural unification to obtain categorized test information. The specific steps are as follows: The preprocessed test data is uploaded to the main control terminal for reception and caching, generating cached test data; The cached test data is aggregated for test content, aligned for time series, and categorized for structural tags to generate unified test data. Then, content filtering and multi-dimensional result extraction are performed to obtain categorized test information.

10. The asynchronous testing system for high-end memory chips based on a distributed architecture as described in claim 9, characterized in that: The asynchronous test results of the structured memory chip are obtained by performing consistency verification and functional status determination through a multi-channel cross-validation algorithm. The specific steps are as follows. By using a multi-channel cross-validation algorithm, the classification test information is compared and similarity is measured between channels to generate a consistency verification information set. By mapping the consistency verification information set and the categorized test information to multi-dimensional functional states and making multi-condition judgments, asynchronous test results for structured memory chips are generated.

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