Electro-optical analog-to-digital conversion

Abstract

Electro-optical conversion of the input analog signal and optical modulation of the optical signal produces two beams of light with different intensity levels. n n-bit digital output values ​​can be coded into n-bit digital output values. Sample rates can exceed 10 GHz (rates exceeding 100 GHz are possible) and the electronics can be much simpler.

Description

[Technical Field]

[0001] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 620,922, filed January 15, 2024, and U.S. Provisional Patent Application No. 63 / 485,322, filed February 16, 2023. U.S. Patent No. 11,885,675 issued January 30, 2024, and also claims priority to U.S. Provisional Patent Application No. 63 / 485,322, filed February 16, 2023.

[0002] This application relates to high speed analog-to-digital conversion. [Background technology]

[0003] A high-speed analog-to-digital converter (ADC) is a circuit that converts an analog signal into a digital value. The input signal is applied to one input and an ascending reference voltage is applied to the other input. n The ascending reference voltage is a two-comparator array with a voltage applied to one end and the other end connected to ground. n The signal from the comparator is input to the encoder, and the resistors are connected in series to generate the signal. n The signals are converted into n bits.

[0004] Here, n is the resolution of the conversion circuit.

[0005] Speed ​​is the clock rate at which the circuit operates, i.e., the rate at which the input analog signal is sampled. The input signal is reconstructed by sampling it at twice the frequency of its highest frequency component (the Nyquist frequency).

[0006] As n increases from n to n+1, the complexity of this circuit doubles: the number of resistors and comparators doubles, increasing noise and distance, both of which affect the maximum achievable speed for a given resolution.

[0007] The most significant issue here is not the semiconductor technology used to implement the circuit (although this is also a limitation), but the n The components affected by the increase in Summary of the Invention

[0008] The applicant uses electro-optical conversion of the input analog signal and optical modulation of the optical signal to n We propose that different intensity levels of light can be applied to each photodetector site, and the output can be encoded as an n-bit digital output value, with a sample rate exceeding 10 GHz (possibly even exceeding 100 GHz), which would significantly simplify the electronic circuitry.

[0009] In some embodiments, a light source having an analog electrical input and an optical output at an output optical power level that is variable as a function of the level of the electrical input, a waveguide connected at an input end to the optical output and emitting at a detection plane an optical power at a level that is attenuated proportionally to the output optical power level, and two semiconductor substrates coupled to the detection plane of the waveguide. n an array of two photodetector circuit elements, each having a binary digital output corresponding to light intensity and positioned to receive different levels of optical power depending on its position within the array; n an array of light receiving circuit elements; n an encoder responsive to the binary digital outputs from each of the light receiving circuit elements and having an n-bit digital value output is provided.

[0010] The device may include a preamplifier connected to the analog electrical input for amplifying the analog input. n The array of photodetector circuit elements may include photodiodes, and each photodetector circuit element may include a comparator that receives an output from the photodiode and compares it with a threshold to generate the binary digital output.

[0011] The photodiode may be germanium on silicon.The device is operable to provide the digital value output at frequencies above 10 GHz, preferably above 100 GHz.

[0012] Part 2 n The array of photodetector circuit elements and the encoder may be formed of germanium.

[0013] The waveguide may be a continuously graded neutral density waveguide.

[0014] The digital value output may be linearly proportional to the level of the electrical input.

[0015] the light source, the waveguide, n The array of photodetector circuit elements and the encoder may be integrated into a common package.

[0016] In some embodiments, a method for converting an analog electrical signal to a digital value is provided, the method comprising: converting an electrical input signal into an optical signal having an intensity corresponding to an analog level of the electrical input signal; modulating the optical signal in the detection region to have an intensity that locally varies as a function of position within the detection region; and modulating the optical signal in the detection region to have an intensity that locally varies as a function of position within the detection region. n 2 corresponding to the level n 2 in the detection area to obtain a bit n detecting a light intensity threshold at the second point; n and converting the bits into an n-bit digital value. [Brief explanation of the drawings]

[0017] The present invention will be better understood from the following detailed description of embodiments of the invention, taken in conjunction with the accompanying drawings.

[0018] [Figure 1] 1 is a system overview diagram of the solution described in the present disclosure.

[0019] [Figure 2] 1 shows the window of a continuous gradient neutral density device and its corresponding characteristic profile.

[0020] [Figure 3] 1 is a plot showing laser power output versus drive current for a laser and an LED.

[0021] [Figure 4] A photodetector array.

[0022] [Figure 5] 1 shows the arrangement of the photodetector array and the CGND device.

[0023] [Figure 6] A photodetector array and encoder combination circuit.

[0024] [Figure 7] 1 illustrates the layout of components in an integrated analog-to-digital converter according to one embodiment.

[0025] [Figure 8] There are 2n elements in the photodetector array.

[0026] [Figure 9] 10 is a flowchart showing the sensitivity calibration of each light-receiving element of the photodetector array.

[0027] [Figure 10A] 10 is a table showing the binary states of 2n light receiving elements. [Figure 10B] 10 is a table showing the binary states of 2n light receiving elements.

[0028] [Figure 11] 1 is a logic circuit for a photodetector array. DETAILED DESCRIPTION OF THE INVENTION

[0029] The invention disclosed in this specification is n This provides a solution to the speed and resolution limitations of the input stage, which detects the value of an input signal, i.e., its voltage, through parallel comparison with two different reference voltages. The limitations are due to the connections and resistors and comparators required to do this. n The logic transformation that encodes n into n is done in the digital domain and is therefore not constrained by the same factors as a comparator circuit.

[0030] FIG. 1 shows a schematic block diagram of an ADC device 10 having an analog input 12 and an optional amplifier 14. The amplifier 14 amplifies the input 12 to drive a light source 15, such as a semiconductor LED or laser, to generate an output power 16. The output 16 is then coupled to a modulator 20. The modulator 20 has an output window 22 across which variations in output intensity may occur. The output 22 of the modulator 20 is optically coupled to a photodetector array 24. The photodetector array 24 generates a separate digital bit for each photodetector in response to different light levels at the output 22. The number of photodetectors 24 is a power of two, i.e., 2 n The encoder 26 may be n The bits may be converted into an n-bit digital value or word 28. For example, 4096 detector bits may be encoded by encoder 26 into a 12-bit value 2, which allows for reasonable precision for the input signal while maintaining a manageable amount of data. Each such 12-bit value may be stored in memory (e.g., a register array such as RAM, ROM, etc.), which may be included in encoder 26.

[0031] Thus, an input analog signal 12 is first converted into light 16 by modulating a light source 15, such as an LED or laser, at the desired bandwidth.

[0032] The light source 15 may be butt-coupled to an optical modulator 20, for example, a continuous gradient neutral density (CGND) device. This device 20 may attenuate the light 16 so that the light intensity at the output window 22 varies linearly with distance from one end of the device to the other (see FIG. 2). The range of light intensity versus voltage may be Vmax-Vmin=D. The relationship between voltage and current may be determined by the VI curve (FIG. 3) of the device 15 used to generate the light.

[0033] The CGND device 20 can be a light guide with longitudinal absorption, attenuating light as it propagates. It can be a long, narrow fused silica waveguide with a circular, square, or rectangular cross section. One end of the device can have a very narrow window along its length, slightly larger than the detector array and at least as long as the detector array. The window can have a coating with a density that increases continuously from one end of the device to the other. As a result, light entering the device at one end can exit the window with gradually increasing or decreasing intensity. The intensity range reflects the coating range of a neutral density filter. Typical coatings with continuous gradient density range from 0-0.4D to 0-4D, where D represents one order of magnitude.

[0034] Thus, the properties of the optical modulator may be such that over a distance X, which corresponds to the length of the device, the total absorption can be between 0.5D and 4D (ie, 0.5 to 10,000).

[0035] Another example is a waveguide or optical fiber that has side losses such that the intensity of light emitted laterally along the waveguide is reduced. Such variations do not need to rely on absorbing filter coatings.

[0036] Another example is a waveguide made of a material that gradually absorbs light of a desired wavelength so that the light attenuates along the length of the waveguide. Tinted glass can have desired properties for wavelengths other than the apparent color of the glass. The effect can be to create the behavior of a continuous gradient neutral density device for specific wavelengths.

[0037] The optical modulator may alternatively be based on free space optics, although optical modulators are preferred as they are more amenable to being co-packaged with the light source and photodetector array.

[0038] In either case, the value of the density / intensity modulation range may depend on the photodetector array, where resolution is desired but limited by the photodetector characteristics, including sensitivity, detector width, and detector response speed.

[0039] The calculation is (density range / 2 n )×(light intensity at the input).

[0040] Device length l = photodetector width × 2 n It can be said that:

[0041] The height of the output window may be at least twice the height of the detector.

[0042] The window of CGND may be coupled to the photodetector array (FIG. 5).

[0043] The voltage-to-light conversion and light intensity detection via a photodetector array of the present disclosure can eliminate the constraints of manufacturing technology for high-speed and higher-resolution analog-to-digital converters. n It can be configured as an array of identical photodetectors with threshold detection circuits and buffers connected to a paired n-bit logic encoder.

[0044] In a preferred embodiment, an output of the photodetector array 24 is generated when the intensity of the light provided by the output 22 of the modulator 20 exceeds a predetermined light intensity threshold that depends on the amplitude of the input signal. n The pairs can be fabricated monolithically with the n-bit encoder and stored in the memory (eg, RAM, ROM, SSD, etc.) of the encoder 26 at addresses corresponding to the n-bit words.

[0045] The electron mobility of the semiconductor used to fabricate the photodetector can determine the maximum speed and resolution achievable.

[0046] In a preferred embodiment, germanium on silicon (Ge on Si) is used as the semiconductor technology, which can achieve transistor speeds of 500 GHz and photodetector responses of 5 picoseconds.

[0047] 2 n A one-dimensional photodetector array can be closely positioned next to a CGND device (optical modulator), allowing each photodetector to detect light from a different position within a variable gradient relative to the light from the CGND (Figure 2).

[0048] Each detector may be connected to an amplifier or a buffer. n The amplifiers or buffers are then n The inputs are fed into an encoder circuit (Figure 5) which encodes the n inputs into n outputs.

[0049] The speed of this analog-to-digital converter device may depend on the speed of the detector, amplifier, and encoder technologies. The system bandwidth may be determined by the smallest bandwidth of the signal path: the receiving buffer / amplifier, photodetector, photodetector buffer / amplifier, and combinatorial logic circuitry that make up the encoder. The photodetector and combinatorial logic encoder can be integrated and fabricated as a monolithic device on a semiconductor substrate.

[0050] One embodiment (see FIG. 7) may be a germanium-on-silicon semiconductor technology for implementing the circuit of FIG. 6, capable of 100 GHz operation. The resolution depends on the number of detectors in the array, where n=antilog(2 n )

[0051] As shown in FIG. 6, a photodiode 24a can be used. The photodiode can be connected to a voltage source that can be common to all detectors. Resistors R0-R2n can be connected between the output of the photodiode and ground. Multiple comparators 24b can be connected to the output of the photodiode to generate binary values ​​on multiple wires 24c. In this way, an optical threshold detection circuit can be provided. The multiple comparators function as an amplifier / buffer circuit, each outputting one bit. This type of circuit is well known in the art and has very high reproducibility and performance.

[0052] Phototransistors can be used instead of photodiodes, but photodiodes are easier to implement. Note that the photodiodes (PD) can be connected in series with a resistor R. Depending on the order, the measured voltage can be zero at zero light or zero at full light. Preferably, all comparators 24b transition between their Boolean outputs 0 and 1 at the same voltage level. A common reference voltage can be used for this purpose.

[0053] The layout of components in one embodiment of an integrated analog-to-digital converter is shown in Figure 7. As shown, a photodetector array 22 can be disposed on a semiconductor substrate, and an optical modulator 20 can be mounted on the photodetector array 22. A light source 15 can be connected to the modulator 20 above the substrate and connected to an amplifier / buffer 14 on the substrate via wirebond connections 14b. Note that the light source can alternatively be located on the substrate surface (e.g., a vertical cavity surface emitting laser), with the modulator 20 adapted to redirect light from the light source 15.

[0054] Figure 8 shows two ordered n The photodetector array 24 shown is comprised of 2 elements. 12 A photodetector array consisting of (4096) photosensitive elements can be arranged on a substrate (eg, germanium-on-silicon) over an area 20 mm long and 2 mm wide, i.e., with a spacing between photosensitive elements of approximately 4.9 microns.

[0055] Each light-receiving element of the photodetector array 24 can be in an "off" or "on" state, where the "off" and "on" states of a light-receiving element refer to whether the photodiode generates a voltage / current below or above the threshold required for operation of the respective element when exposed to a given light intensity.

[0056] Each light-sensitive element of the photodetector array 24 can be connected in series with a resistor (see, for example, FIG. 11). The resistor can be implemented as a thin-film resistor using a thin metal layer, such as a nickel-chromium alloy, or as a thin metal oxide layer, typically tin oxide. Both types of resistors can be disposed on a glass, ceramic, or silicon substrate. As previously mentioned, the light-sensitive elements (e.g., photodiodes) can be germanium-on-silicon, so that the substrate doubles as the resistor. Alternatively, the light-sensitive elements can be disposed on one side of a silicon substrate, with the resistors associated with each element disposed on the other side of the same substrate. Alternatively, the silicon substrate can be replaced by other suitable semiconductor substrates.

[0057] 2 12In an analog-to-digital converter with a photodetector array having (4096) photosensitive elements, to obtain a 12-bit digital word, the sensitivity of any given photosensitive element to light must be (1 / 4096) × 100% ≈ 0.02% of the sensitivity of the entire array. This means that each photosensitive element must have a sensitivity tolerance of approximately ±0.01%, which is very difficult to achieve in the manufacturing process. It would be beneficial to be able to place the photosensitive elements and their associated electronic comparators and logic in close proximity on a single substrate. Nevertheless, it may be advantageous to laser trim the resistors associated with each photosensitive element.

[0058] In some embodiments, the resistors can be located on a silicon substrate, which improves integration, precision, thermal performance, and reliability. The silicon substrate also provides a stable platform for the resistors during a laser trimming process (or other suitable technique), allowing for precision resistance adjustment. The latter can determine a reference voltage / current (referred to herein as Vref) that is used to future compare the voltage / current of each photodetector.

[0059] The laser trimming process uses a laser to selectively remove or modify resistive material on a resistor, thereby changing its resistance. Such adjustments are typically achieved by removing small amounts of material in a controlled manner until the desired resistance value is achieved. Laser trimming is a highly controlled process, allowing the resistance value to be adjusted to a specific value depending on the intensity and duration of laser irradiation, rather than essentially increasing or decreasing. More specifically, modifying the resistor material can be achieved by annealing, a process in which a laser is used to heat specific areas of the resistor to modify its electrical properties without physically removing the resistive material. Alternatively, doping can be used to introduce or modify doping elements (i.e., specific impurities) into the resistor material, thereby changing its electrical conductivity. During laser trimming, the resistor's resistance is monitored in real time, i.e., real-time feedback is collected, and laser parameters are dynamically adjusted to achieve the desired resistance value. In some embodiments, the change in resistance is measured not directly but rather via sensing a change in the sensing state of a photodetector and associated circuitry.

[0060] In some embodiments, a laser trimming process may be applied directly to a continuous gradient neutral density waveguide to adjust or fine-tune its optical properties, for example, by selectively removing portions of the waveguide coating, such as a thin film. As an example, if the top surface of the waveguide 20 has a reflective metal coating, laser ablation of the coating can be used to increase loss at any desired light detection site. Laser trimming also generally enables wavelength tuning, refractive index tuning, and optical loss reduction, allowing for guiding and filtering of specific wavelength bands to achieve desired light propagation along the waveguide. Because laser trimming is a highly controlled process, the waveguide's properties can be adjusted with high precision, which may eliminate the need for additional laser trimming of resistors corresponding to the light-receiving elements.

[0061] 9 illustrates a flow chart showing the sensitivity calibration of each light receiving element of the photodetector array 24. At the start, all light receiving elements of the array 24 are in the "off" state. In this example, the array 24 is 12 The photodetector array includes (4096) photodetectors. To begin the calibration process, the intensity of the analog signal generated by the modulator 20 is adjusted by the amplifier 14 so that only the first photodetector in the photodetector array responds. This can be considered as adjusting a base level or offset (e.g., a constant voltage added to the amplifier output signal regardless of the input signal). Therefore, the intensity value is adjusted to (1 / 4096) × 100% ≒ 0.02% of the intensity value required to cause all photodetectors to respond, which is considered the minimum intensity value. Next, the nominal gain (i.e., the amplification factor expected or designed under normal operating conditions, which can be given as the ratio of output voltage to input voltage) of the amplifier 14 can be set by adjusting the gain so that the 4096th photodetector begins to change state using a 100% intensity value. The output of the amplifier 14 is coupled to a continuous gradient neutral density waveguide, allowing the analog signal input to reach each photodetector. It will be appreciated that the offset of amplifier 14 is adjusted to enable detection of the input signal by the first element of the photodetector array, and the gain of amplifier 14 is adjusted so that the nth element can be switched from an "off" to an "on" state by setting the analog signal input strength to 100% (maximum signal strength).

[0062] After determining the maximum input signal strength required to elicit a response from all array elements, it may be necessary to adjust each resistor corresponding to each photodetector element using a laser trimming process to achieve an orderly response to the input signal. In this case, starting with the first element in the array, the input analog signal strength is increased by 0.02% of the maximum intensity value for each subsequent element in the array. However, when an analog signal of this strength is applied to the photodetector array, the photodetector element that responds may not necessarily be the next intended array element. This means that the sensitivity of each array element must be taken into account, and each photodetector element may be adjusted to respond to increasing intensity in a predetermined order. To achieve this, the resistance value of each resistor corresponding to each subsequent photodetector element can be adjusted, one at a time, to find the point at which that photodetector element switches from an "off" state to an "on" state. Once the resistance value of each resistor has been adjusted, the calibration process stops.

[0063] In this example, we assume that the light intensity increases linearly over time. However, the intensity of the input signal may increase nonlinearly depending on the desired sequence in which the array elements are turned "on." In the case of a nonlinear ADC, the intensity values ​​of the analog input signal as each individual photodetector element changes state can be recorded in encoder 26.

[0064] 10A and 10B show the n 2 shows a table containing the binary states of five light-receiving elements m-2, m-1, m, m+1, and m+2 of photodetector array 24. To illustrate the resulting output, five array elements m-2, m-1, m, m+1, and m+2 of photodetector array 24 are shown, which are then stored in encoder 26 and then processed to generate a corresponding n-bit word. The "off" or "on" state of each light-receiving element of photodetector array 24, and the associated output registered with encoder 26, are given as binary logic values ​​0 and 1. It will be understood that the assignment of these binary values ​​here and in the following description is arbitrary; however, circuit logic achieves accurate analog-to-digital conversion in response to such assignments.

[0065] 11 shows the logic circuitry of the photodetector array 24. The output 22 received from the modulator 20 and amplified by the amplifier 14 is input to two of the photodetector arrays. n elements, here illustrated as three consecutive elements m-1, m, and m+1. Because the photodiode and its corresponding resistor may be located on opposite sides of the silicon substrate, the continuous graded neutral density waveguide is shown as a dashed section passing between the photodiode and the resistor.

[0066] Each array element (e.g., photodiode) may include (or be connected to) a comparator for comparing the photodiode's output voltage / current with an intensity threshold voltage / current value. The threshold value should be the same for all photodiodes in the array. The threshold light intensity level is achieved by a continuous neutral density layer of density D, which can be adjusted using a neutral density filter. The sensitivity of each comparator must also be the same for all corresponding photodiodes to ensure accurate current / voltage comparisons.

[0067] In this example, the "off" or "on" state of each light-receiving element (hereafter referred to as a photodiode for simplicity) of the photodetector array 24 is represented by a binary value of 0 and 1, respectively. Furthermore, if the voltage / current of a photodiode is below a threshold, the output of the corresponding comparator may be 0, and otherwise may be 1. As noted above, such binary value assignments are arbitrary and may be changed without affecting the circuit logic described below. Regardless of whether the current / voltage of a photodiode is below or above a threshold, the photodiode is still operational, i.e., in an "on" state.

[0068] The output of the comparator is passed as an input to a corresponding AND gate, which may also include a comparator, and registered with encoder 26. The AND gate also receives as input the output of the NOT gate associated with the immediately preceding photodiode. However, for the first photodiode activated by the input signal (e.g., element 0 in FIGS. 10A and 10B), there is no NOT gate output from the immediately preceding photodiode contributing to the corresponding AND gate input. Thus, when the photodiode current / voltage is below a threshold, the output of the comparator is 0, which is passed to one input of a two-input AND gate, resulting in an AND gate output of 0. This output is registered with encoder 26 and then passed to the NOT gate. The NOT gate outputs 1 if the output of the immediately preceding AND gate is 0, and 1 otherwise. This means that for the next element in the array activated by the signal, the current AND gate will have two inputs: the output of the corresponding comparator and the output of the immediately preceding NOT gate (e.g., element 1 in FIGS. 10A and 10B).

[0069] As mentioned above, when the voltage / current of a photodiode is below the threshold, the output of the corresponding comparator is 0, and the output of the corresponding AND gate is also 0 (see the states and outputs of photodiodes 0, 1, 2, m-2, and m-1 in FIGS. 10A and 10B). This output is passed to a NOT gate, where it is inverted to 1. When the voltage / current of a photodiode exceeds the threshold, the output of the corresponding comparator is 1. As a result, the output of the corresponding AND gate is also 1 (see the state and output of photodiode m in FIGS. 10A and 10B). This means that the next NOT gate receives 1 as input and outputs 0, which is passed as input to the AND gate associated with the next photodiode responsive to the input signal. If the current / voltage of the next photodiode is below the threshold, then by the same logic, the output of the AND gate is 0 (see elements m+1, m+2, etc. in FIG. 10A). In this case, element m is the last element to exceed the threshold, and its output further determines the resulting n-bit word. For example, if the current / voltage of photodiode m is above the threshold, the next photodiode m+1 is "below threshold," and the subsequent photodiode m+2 is again "above threshold" (see FIG. 10B), two outputs with a logic value of 1 may result. This may be due to the sensitivity of the corresponding comparator, slight variations in the characteristics of the corresponding resistor, and the photodiode's current / voltage values ​​being very close to the threshold value. In this case, photodiode m is still considered the last "above threshold" photodiode, and its corresponding output of 1 contributes to the n-bit word. Once the last "above threshold" photodiode is determined, the remaining photodiodes that have not yet been activated are considered to be in the "off" state.

[0070] It should be understood that the logic circuit elements (such as NOT gates and AND gates) in this example may be replaced with combinations of other circuit logic elements (e.g., NAND, OR, NOR gates, etc.) to achieve equivalent functionality of the device. Furthermore, in the above example, the output of the AND gate associated with one photodiode is compared with the output of the AND gate for the next photodiode to determine the last photodiode with a voltage / current above the light intensity threshold level. It will be apparent to those skilled in the art that logic circuits can be designed to, for example, compare the outputs of adjacent AND gates to more accurately determine the last photodiode that exceeds the threshold.

Claims

1. An analog-to-digital conversion device, a light source having an analog electrical input and having an optical output at an output optical power level that is variable as a function of the level of the electrical input; a waveguide connected at an input end to said optical output and emitting at a detection plane a level of optical power that is attenuated proportionally to said output optical power level; Two waveguides on a single semiconductor substrate are bonded to the sensing surface of the waveguide. ｎ an array of two photodetector circuit elements, each having a binary digital output corresponding to light intensity and positioned to receive different levels of optical power depending on its position within the array; ｎ an array of photodetector circuit elements; 2. ｎ an encoder responsive to the binary digital outputs from each of the light receiving circuit elements and having an n-bit digital value output.

2. 10. The apparatus of claim 1, further comprising a preamplifier connected to the analog electrical input for amplifying the analog input.

3. The two semiconductor substrates ｎ 3. The apparatus of claim 1, wherein the array of photodetector circuit elements comprises photodiodes.

4. 4. The apparatus of claim 3, wherein each light receiving circuit element includes a comparator that receives the output from the photodiode, compares it with a threshold, and generates the binary digital output.

5. 5. The device of claim 3, wherein the photodiode is germanium on silicon.

6. 6. Apparatus according to any one of claims 1 to 5, operable to provide the n-bit digital value output at a frequency exceeding 10 GHz.

7. The apparatus of claim 6 , wherein the frequency is greater than 100 GHz.

8. 2. ｎ 8. The apparatus of claim 6 or 7, wherein the array of photodetector circuit elements and the encoder are formed from germanium.

9. 9. The apparatus of claim 1, wherein the waveguide is a continuous gradient neutral density waveguide.

10. The optical parameters of the waveguide are adjusted to the two wavelengths by laser trimming, which allows for the delivery of sufficient energy to that location of the waveguide to achieve the desired waveguide performance. ｎ 10. The apparatus of claim 1, wherein the wavelength is adjusted by selectively modifying a coating of the waveguide at locations associated with individual photodetector circuit elements.

11. 11. The apparatus of claim 1, wherein the n-bit digital value output is linearly proportional to the level of the electrical input.

12. The light source, the waveguide, ｎ 12. The apparatus of claim 1, wherein the array of photodetector circuit elements and the encoder are integrated into a common package.

13. 2. ｎ 13. The apparatus of claim 1, wherein each of the light receiving circuit elements comprises a light receiving element whose conductivity varies with light level and which is connected in series with a resistor and a common voltage, and wherein a voltage drop across one of the light receiving element and the resistor varies in response to the light level.

14. 14. The apparatus of claim 13, wherein the resistors are spaced apart on the single semiconductor substrate to allow adjustment of resistance value by laser trimming.

15. 15. Apparatus according to any preceding claim, wherein the encoder further comprises a series of registers.

16. 2. ｎ 16. The apparatus of claim 15, wherein each of the photodetector circuit elements comprises an AND gate having inputs from successive pairs of photodetectors and outputting a logic level when the binary digital output changes state.

17. 17. The apparatus of claim 16, wherein the AND gate further comprises a comparator for comparing the voltage drop to a common reference voltage.

18. 18. Apparatus according to claim 16 or 17, wherein each successive pair of 2n-1 AND gates includes a connection to a NOT gate.

19. The encoder ｎ 20. The apparatus of claim 18, further comprising a light intensity tracking logic circuit that receives as input the binary digital outputs of the comparators, the AND gates, and the NOT gates associated with each of the light receiving circuit elements and generates a resulting binary digital output that is stored in at least one of the series of registers and then converted to the n-bit digital value output.

20. 20. The analog-to-digital conversion device according to claim 1, wherein the first and second inputs are connected to the first and second inputs. ｎ 1. A method of calibrating photodetector circuit elements, comprising: The minimum intensity level of the analog electrical input is set to (1 / 2) of the maximum analog electrical signal value. ｎ ) × 100% and 2. ｎ adjusting an offset of the light source until a first one of the light receiving circuit elements is responsive to the analog electrical input; Set the maximum intensity level of the analog electrical input, ｎ adjusting the gain of the light source until a last one of the light receiving circuit elements detects the analog electrical input; For each successive light receiving circuit element, the light intensity is (1 / 2 ｎ ) × 100% increments to respond to the input light intensity in a predetermined order. ｎ and laser trimming at least one of the resistors and at least a portion of the waveguide coating at a location associated with the photoreceiver circuit element.

21. 1. A method for converting an analog electrical signal into a digital value, comprising: converting an electrical input signal into an optical signal having an intensity corresponding to an analog level of the electrical input signal; modulating the optical signal in a detection region to have an intensity that varies locally as a function of position within the detection region; The analog level of the electrical input signal is ｎ 2 corresponding to the level ｎ Two bits are obtained by ｎ detecting a light intensity threshold at the location; 2. ｎ and converting the bits to an n-bit digital value.

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