A generalized c-2c structure multi-section capacitive array and its application
By promoting the C-2C structure multi-segment capacitor array, the problem of parasitic capacitance influence of capacitor array in traditional C-2C structure is solved, realizing the reduction of capacitor array area and improvement of accuracy in high-precision analog-to-digital converters and digital-to-analog converters, and simplifying the design process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2022-08-08
- Publication Date
- 2026-06-09
AI Technical Summary
In high-precision analog-to-digital converters and digital-to-analog converters, when the bridging capacitor of the traditional C-2C segmented capacitor structure is an integer multiple of the unit capacitance, parasitic capacitance severely affects linearity, limits resolution, and cannot be widely used in high-precision converters. Furthermore, the capacitor array design is difficult to balance the effective number of bits and chip area.
The widely adopted C-2C structure multi-segment capacitor array is used, including capacitor array, bridging capacitor, redundant capacitor, input stage and output stage. By setting each segment capacitor to an integer multiple of the unit capacitor, and connecting bridging capacitor and redundant capacitor in parallel, binary relationship is ensured, the impact of capacitor mismatch is reduced, and the design process is simplified.
It effectively reduces the area of the capacitor array in high-precision analog-to-digital converters or digital-to-analog converters, alleviates the contradiction between accuracy and area, improves design flexibility, reduces the impact of capacitor mismatch, and improves linearity, making it applicable to high-precision converters.
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Figure CN115425981B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, specifically to a widely adopted C-2C structure multi-segment capacitor array and its applications. Background Technology
[0002] Capacitor arrays are widely used in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), using the different weights of each capacitor in the array to convert digital signals into corresponding analog signals. Capacitor arrays are divided into unsegmented and segmented arrays. Unsegmented arrays consist of all capacitors connected in parallel, while segmented arrays consist of each parallel capacitor connected in series with a bridging capacitor. With current integrated circuit manufacturing processes, segmented capacitor arrays, compared to unsegmented arrays, can reduce chip area while achieving the same bit accuracy.
[0003] For current high-precision analog-to-digital converters or digital-to-analog converters (12-24 bits), due to the limitations of integrated circuit manufacturing processes and chip area, large capacitors cannot be accommodated in the circuit. Therefore, segmented capacitor arrays are required in the design.
[0004] The design challenge of segmented capacitor arrays lies in ensuring that the bridging capacitance is an integer multiple of the unit capacitance while satisfying the binary relationship between each segment. Traditional C-2C segmented capacitor structures achieve this by ensuring the bridging capacitance is an integer multiple of the unit capacitance (2C) while maintaining the binary relationship between each segment (unit capacitance C). However, the parasitic capacitances on the interconnect nodes of traditional C-2C segmented structures severely affect linearity, limiting their resolution to 6-10 bits. Therefore, they cannot be widely used in high-precision analog-to-digital converters (ADCs) or digital-to-analog converters (DACs). Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides a widely applicable C-2C structure multi-segment capacitor array and its application, which alleviates the conflict between the effective number of bits of the capacitor array and the chip area in high-precision analog-to-digital converters and digital-to-analog converters, while also improving the capacitor matching problem of traditional C-2C structures.
[0006] The technical solution of this invention is as follows:
[0007] A widely adopted C-2C structure multi-segment capacitor array includes a capacitor array, bridging capacitors, redundant capacitors, an input stage, and an output stage. The capacitor array comprises n segments, each segment including S-position capacitors connected in parallel. All capacitors in the capacitor array are connected to the input stage. Bridging capacitors are provided between the S-position capacitors of the n segments of the capacitor array. The first segment of the capacitor array is connected to a redundant capacitor, and the nth segment is connected to the output stage.
[0008] In the above, n is the number of segments in the capacitor array, and S is the number of bits in each segment of the capacitor array.
[0009] Preferably, the unit capacitance of each segment of the capacitor array, except for the first segment, is twice the unit capacitance of the segment preceding it. S-1 times, that is
[0010] C0 i Let represent the unit capacitance of the i-th segment of the capacitor array, where i represents any segment of the capacitor array.
[0011] Preferably, each bridging capacitor in the capacitor array is twice the unit capacitance of its corresponding segmented capacitor array. S times, that is
[0012] C a i This represents the i-th bridging capacitor.
[0013] Preferably, the value of the redundant capacitor is the unit capacitance of the first segment of the capacitor array, i.e., C. d 1 =C0 1 Redundant capacitors ensure that the weight of each bit in the segmented capacitor array satisfies the binary relationship.
[0014] C d 1 This indicates redundant capacitors.
[0015] Preferably, the sum of the number of S-bit capacitors in the n segments of the capacitor array is the total number of bits M, i.e., M = n * S.
[0016] Preferably, the input stage is a sampling circuit or a switching circuit, and the output stage is a comparator input circuit or a digital-to-analog converter output circuit.
[0017] The application of the C-2C structure multi-segment capacitor array promoted above follows these steps:
[0018] (1) Determine the total number of bits M of the capacitor array based on the accuracy of the designed analog-to-digital converter or digital-to-analog converter;
[0019] (2) Determine the number of segments n and the number of bits S of each segment of the capacitor array based on the area of the designed capacitor array, so as to ensure that the sum of the bits of the n segments of the capacitor array is equal to the total number of bits M.
[0020] (3) Calculate the value of each capacitor in the segmented capacitor array, i.e.
[0021]
[0022] (4) Calculate the value of the bridging capacitor for each bit of the segmented capacitor array, i.e.
[0023]
[0024] (5) Connect the S-position capacitors of each segment of the capacitor array in parallel. The upper plate of the first segment of the capacitor array and the upper plate of the redundant capacitor are connected to the lower plate of the first bridging capacitor. The upper plate of the second segment of the capacitor array is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor, respectively. The upper plate of the third segment of the capacitor array is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor, respectively. And so on. The upper plate of the nth segment of the capacitor array is connected to the upper plate of the (n-1)th bridging capacitor and the output stage, respectively. The lower plates of the M-position capacitors of the capacitor array are all connected to the input stage.
[0025] In this invention, the upper end of the vertical capacitor is set as the upper plate and the lower end as the lower plate; the right end of the horizontal capacitor is set as the upper plate and the left end as the lower plate.
[0026] The beneficial effects of this invention are as follows:
[0027] 1. Compared with traditional binary capacitor array technology, this invention can reduce the area of the capacitor array in high-precision analog-to-digital converters or digital-to-analog converters, alleviate the contradiction between the accuracy and area of analog-to-digital converters and digital-to-analog converters, and all capacitors are integer multiples of unit capacitance, reducing the impact of capacitor mismatch on overall accuracy.
[0028] 2. Compared with the traditional segmented capacitor design method, this invention solves the problem that the bridging capacitor value of the traditional segmented capacitor array is a fractional value, reduces the impact of capacitor mismatch, improves design flexibility, and simplifies the complexity of the design process.
[0029] 3. Compared with the traditional C-2C capacitor array structure, the solution proposed in this invention alleviates the influence of node parasitic capacitance, making it applicable to high-precision analog-to-digital converters and digital-to-analog converters. Attached Figure Description
[0030] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.
[0031] Figure 1 This is a schematic diagram of the C-2C structure M-bit n-segmented capacitor array according to the present invention;
[0032] Figure 2 This is a schematic diagram of a C-2C structure 16-bit 4-segment capacitor array according to Embodiment 1 of the present invention;
[0033] Figure 3 This is a schematic diagram of a C-2C structure 20-bit 4-segment capacitor array according to Embodiment 2 of the present invention. Detailed Implementation
[0034] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.
[0035] Example 1
[0036] like Figure 2 As shown, this embodiment provides a 4-segment 16-bit C-2C multi-segment capacitor array for analog-to-digital converters, including a capacitor array consisting of 4 segments of 4-bit capacitors connected in parallel, 3 bridging capacitors and 1 redundant capacitor, a switching circuit as the input stage, and a comparator input circuit as the output stage.
[0037] In this segmented capacitor array, the four capacitors in each segment are connected in parallel. The upper plate of the first segment and the upper plate of the redundant capacitor are both connected to the lower plate of the first bridging capacitor. The upper plate of the second segment is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plate of the third segment is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. The upper plate of the fourth segment, the upper plate of the third bridging capacitor, and the comparator input are connected. The lower plates of the 16 capacitors in the four-segment capacitor array are all connected to the switching circuit. The lower plate of the redundant capacitor is connected to ground. The four capacitors in the fourth segment and the upper plate of the third bridging capacitor are connected to the comparator output circuit through a switch.
[0038] In the diagram, switch S0 is the reset switch, Comp is the comparator, segments 1, 2, 3, and 4 represent the four segments of the 16-bit capacitor array, GND represents the ground terminal, and S1, S2, S3, S4, S5, S6, S7, S8, S9, and S1 are the input terminals of the 16-bit capacitor array. 10 S 11 S 12 S 13 S 14 S 15 and S 16 These represent the control switches for capacitors 1 through 16, responsible for signal sampling and conversion during the operation of the analog-to-digital converter.
[0039] The symbol C is used in the diagram. a 1 The bridging capacitor between the first and second segments of the segmented capacitor array is represented by the symbol C. a 2 The bridging capacitor between the second and third segments of the segmented capacitor array is represented by the symbol C. a 3 The bridging capacitor between the third and fourth segments of the segmented capacitor array is represented by the symbol C0. 1The unit capacitance of the first segment of the capacitor array is represented by the symbol C0. 2 The unit capacitance of the second segment of the capacitor array is represented by the symbol C0. 3 The unit capacitance of the third segment of the capacitor array is represented by the symbol C0. 4 The unit capacitance of the fourth segment of the capacitor array is represented by the symbol C. d i Let i represent the redundant capacitors of the segmented capacitor array, where i represents any segment of the capacitor array, and 1≤i≤4.
[0040] The unit capacitance of each segment of the 4-segment 16-bit capacitor array, except for the first segment, is twice the unit capacitance of the segment preceding it. 3 times, that is
[0041] Each bridging capacitor of the 4-segment 16-bit capacitor array satisfies 2 4 The unit capacitance of its corresponding segment is times that of the previous segment.
[0042] The redundant capacitance of the 4-segment 16-bit capacitor array is the unit capacitance of the first segment of the capacitor array, i.e., C. d 1 =C0 1 The purpose of redundant capacitors is to ensure that the weight of each bit in the segmented capacitor array satisfies the binary relationship.
[0043] The sum of the number of bits in the four segments of the multi-segment capacitor array is 16, i.e., 16 = 4 * 4.
[0044] The application of the C-2C structure multi-segment capacitor array promoted above follows these steps:
[0045] (1) Determine the total number of bits (16 bits) of the multi-segment capacitor array based on the 16-bit conversion precision of the designed analog-to-digital converter or digital-to-analog converter;
[0046] (2) Based on the area of the designed capacitor array, the number of segments required for the capacitor array is determined to be 4 and the number of bits in each segment is 4, and the sum of the bits in the 4 segments is equal to the total number of bits, 16.
[0047] (3) Calculate the value of each capacitor in the segmented capacitor array using the calculation method proposed in this invention, i.e.
[0048]
[0049] The values of the first to fourth capacitors in the first segment of the capacitor array can be calculated as follows: The capacitance values of the fifth to eighth capacitors in the second capacitor array are respectively... The values of the ninth to twelfth capacitors in the third segment of the capacitor array are respectively... The capacitance values of the thirteenth to sixteenth capacitors in the fourth capacitor array are respectively Take redundant capacitors The capacitance value
[0050] (4) Calculate the value of each bridging capacitor in the segmented capacitor array using the calculation method proposed in this invention, i.e.
[0051]
[0052] Calculation yields The value is Pick The value is Pick The value is
[0053] (5) The four capacitors in each segment of the segmented capacitor array are connected in parallel. The upper plate of the first segment of the capacitor array and the redundant capacitor is connected to the lower plate of the first bridging capacitor. The upper plate of the second segment of the capacitor array is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plate of the third segment of the capacitor array is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. The upper plate of the fourth segment of the capacitor array is connected to the upper plate of the third bridging capacitor and the comparator input. The lower plates of the 16 capacitors in the multi-segmented capacitor array are all connected to the switching circuit. The lower plate of the redundant capacitor is connected to the ground. The upper plates of the 16 capacitors in the multi-segmented capacitor array are all connected to the comparator output through the switch.
[0054] In this embodiment, the upper end of the vertical capacitor is designated as the upper plate, and the lower end as the lower plate; the right end of the horizontal capacitor is designated as the upper plate, and the left end as the lower plate. The figures shown, from right to left, represent the 1st redundant capacitor to the 16th capacitor.
[0055] The total capacitance required for the 4-segment 16-bit capacitor array proposed in this embodiment is [value missing]. The total capacitance required by a traditional 16-bit binary capacitor array is [value missing]. Therefore, its area is only 7.587% of that of a traditional binary capacitor array structure. Moreover, compared to the traditional segmented structure where the bridging capacitor values may be in fractional form, the capacitor array proposed in this embodiment has all capacitors that are integer multiples of unit capacitance, making capacitor matching easier.
[0056] Example 2
[0057] like Figure 3As shown, this embodiment provides a 4-segment 20-bit C-2C multi-segment capacitor array for analog-to-digital converters, including a capacitor array consisting of 4 segments of 5-bit capacitors connected in parallel, 4 bridging capacitors and 1 redundant capacitor, a switching circuit as the input stage, and a comparator input circuit as the output stage.
[0058] In this configuration, the 5-bit capacitors in each segment of the segmented capacitor array are connected in parallel. The upper plate of the first segment of the capacitor array and the redundant capacitor are connected to the lower plate of the first bridging capacitor. The upper plate of the second segment of the capacitor array is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plate of the third segment of the capacitor array is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. The upper plate of the fourth segment of the capacitor array is connected to the upper plate of the third bridging capacitor and the comparator input. The lower plates of all 20-bit capacitors in the 4-segment capacitor array are connected to the switching circuit. The lower plates of the redundant capacitors are connected to ground. The upper plates of all 20-bit capacitors in the multi-segment capacitor array are connected to the comparator output via switches.
[0059] In the diagram, switch S0 is the reset switch, Comp is the comparator, segments 1, 2, 3, and 4 represent the four segments of the 20-bit capacitor array, GND represents the ground terminal, and S1, S2, S3, S4, S5, S6, S7, S8, S9, and S1 are the input terminals of the 20-bit capacitor array. 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 and S 20 These represent the control switches for capacitors 1 through 20, responsible for signal sampling and conversion during the operation of the analog-to-digital converter.
[0060] The symbol C is used in the diagram. a 1 The bridging capacitor between the first and second segments of the segmented capacitor array is represented by the symbol C. a 2 The bridging capacitor between the second and third segments of the segmented capacitor array is represented by the symbol C. a 3 The bridging capacitor between the third and fourth segments of the segmented capacitor array is represented by the symbol C0. 1 The unit capacitance of the first segment of the capacitor array is represented by the symbol C0. 2 The unit capacitance of the second segment of the capacitor array is represented by the symbol C0. 3 The unit capacitance of the third segment of the capacitor array is represented by the symbol C0. 4The unit capacitance of the fourth segment of the capacitor array is represented by the symbol C. d i Let i represent the redundant capacitors of the segmented capacitor array, where i represents any segment of the capacitor array, and 1≤i≤4.
[0061] The unit capacitance of each segment of the 4-segment 20-bit capacitor array, except for the first segment, is twice the unit capacitance of the segment preceding it. 4 times, that is
[0062] Each bridging capacitor of the 4-segment 20-bit capacitor array satisfies 2 5 The unit capacitance of its corresponding segment is times that of the previous segment.
[0063] The redundant capacitance of the 4-segment 20-bit capacitor array is the unit capacitance of the first segment of the capacitor array, i.e., C. d 1 =C0 1 The purpose of redundant capacitors is to ensure that the weight of each bit in the segmented capacitor array satisfies the binary relationship.
[0064] The sum of the number of bits in the four segments of the multi-segment capacitor array is 20, i.e., 20 = 4 * 5.
[0065] The application of the C-2C structure multi-segment capacitor array promoted above follows these steps:
[0066] (1) Determine the total number of bits (20 bits) of the multi-segment capacitor array based on the 20-bit conversion precision of the designed analog-to-digital converter or digital-to-analog converter;
[0067] (2) Based on the comprehensive consideration of the designed capacitor array area, the number of segments required for the capacitor array is determined to be 4 and the number of bits in each segment is 5, and the sum of the bits in the 4 segments is equal to the total number of bits 20.
[0068] (3) Calculate the value of each capacitor in the segmented capacitor array using the calculation method proposed in this invention, i.e.
[0069]
[0070] The values of the first to fifth capacitors in the first segment of the capacitor array can be calculated as follows: The values of the sixth to tenth capacitors in the second capacitor array are respectively... The capacitance values of the eleventh to fifteenth capacitors in the third capacitor array are respectively... The capacitance values of the sixteenth to twentieth capacitors in the fourth capacitor array are respectively Take redundant capacitors The capacitance value
[0071] (4) Calculate the value of each bridging capacitor in the segmented capacitor array using the calculation method proposed in this invention, i.e.
[0072]
[0073] Calculation yields The value is Pick The value is Pick The value is
[0074] (5) The 5-bit capacitors of each segment of the segmented capacitor array are connected in parallel. The upper plate of the first segment of the capacitor array and the redundant capacitor is connected to the lower plate of the first bridging capacitor. The upper plate of the second segment of the capacitor array is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor. The upper plate of the third segment of the capacitor array is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor. The upper plate of the fourth segment of the capacitor array is connected to the upper plate of the third bridging capacitor and the comparator input. The lower plates of all 20-bit capacitors in the multi-segmented capacitor array are connected to the switching circuit. The lower plate of the redundant capacitor is connected to ground. The upper plates of all 20-bit capacitors in the multi-segmented capacitor array are connected to the comparator output through the switch.
[0075] The total capacitance required for the 4-segment 20-bit capacitor array proposed in this embodiment is [value missing]. The total capacitance required by a traditional 16-bit binary capacitor array is [value missing]. Therefore, its area is only 6.875% of that of a traditional binary capacitor array structure. Moreover, compared to the traditional segmented structure where the bridging capacitor values may be in fractional form, the capacitor array proposed in this embodiment has all capacitors that are integer multiples of a unit capacitance, making capacitor matching easier.
[0076] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0077] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A widely adopted C-2C structure multi-segment capacitor array, characterized in that, It includes a capacitor array, bridging capacitors, redundant capacitors, an input stage, and an output stage. The capacitor array consists of n segments, each of which includes S-position capacitors connected in parallel. All capacitors in the capacitor array are connected to the input stage. Bridging capacitors are provided between the S-position capacitors in the n segments of the capacitor array. The first segment of the capacitor array is connected to a redundant capacitor, and the nth segment is connected to the output stage. The unit capacitance of each segment of the capacitor array, except for the first segment, is twice the unit capacitance of the segment preceding it. S-1 times, that is , Let represent the unit capacitance of the i-th segment of the capacitor array, where i represents any segment of the capacitor array.
2. The promoted C-2C structure multi-segment capacitor array as described in claim 1, characterized in that, Each bridging capacitor in the capacitor array is twice the unit capacitance of its corresponding segmented capacitor array. S times, that is , This represents the i-th bridging capacitor.
3. The promoted C-2C structure multi-segment capacitor array as described in claim 2, characterized in that, The value of the redundant capacitor is the unit capacitance of the first segment of the capacitor array, that is... , This indicates redundant capacitors.
4. The promoted C-2C structure multi-segment capacitor array as described in claim 3, characterized in that, The sum of the number of S-bit capacitors in the n segments of the capacitor array is the total number of bits M, i.e., M = n * S.
5. The extended C-2C structure multi-segment capacitor array as described in claim 1, characterized in that, The input stage is a sampling circuit or a switching circuit, and the output stage is a comparator input circuit or a digital-to-analog converter output circuit.
6. An application of the extended C-2C structure multi-segment capacitor array as described in claim 4, characterized in that, The steps are as follows: (1) Determine the total number of bits M of the capacitor array based on the accuracy of the designed analog-to-digital converter or digital-to-analog converter; (2) Determine the number of segments n and the number of bits S of each segment of the capacitor array based on the area of the designed capacitor array, so as to ensure that the sum of the bits of the n segments of the capacitor array is equal to the total number of bits M. (3) Calculate the value of each capacitor in the segmented capacitor array, i.e.; ； (4) Calculate the value of the bridging capacitor for each bit of the segmented capacitor array, i.e.; ； (5) Connect the S-position capacitors of each segment of the capacitor array in parallel. The upper plate of the first segment of the capacitor array and the upper plate of the redundant capacitor are connected to the lower plate of the first bridging capacitor. The upper plate of the second segment of the capacitor array is connected to the upper plate of the first bridging capacitor and the lower plate of the second bridging capacitor, respectively. The upper plate of the third segment of the capacitor array is connected to the upper plate of the second bridging capacitor and the lower plate of the third bridging capacitor, respectively. And so on. The upper plate of the nth segment of the capacitor array is connected to the upper plate of the (n-1)th bridging capacitor and the output stage, respectively. The lower plates of the M-position capacitors of the capacitor array are all connected to the input stage.