Wafer-level packaging structure for filters with device layer sidewall protection and manufacturing method thereof

Abstract

The present disclosure also provides a wafer-level packaging structure for a filter with device layer sidewall protection, the wafer-level packaging structure comprising: a substrate having at least one active area and at least one exposed area, the active area being covered with a composite thin film, the exposed area being provided with a recessed filling portion, the filling portion being proximate to an edge of the exposed area that contacts the active area; and a first thin film layer formed on at least a portion of the exposed area and the composite thin film, filling the filling portion. Correspondingly, the present disclosure also provides a method for manufacturing a wafer-level packaging structure for a filter with device layer sidewall protection, which solves the problems of the conventional two-layer film structure, such as the possibility of delamination, low packaging reliability, and wafer warpage.

Description

[Technical Field]

[0001] This application claims priority to Chinese patent application No. 2023104533790, filed on April 25, 2023, entitled "Wafer-level packaging structure of filter with device layer sidewall protection and manufacturing method thereof," the entire contents of which are incorporated herein by reference. The present invention relates to the field of chip packaging of filters, and more particularly to a wafer level packaging structure of filters with device layer sidewall protection and its manufacturing method. [Background technology]

[0002] Surface acoustic wave filters achieve their filtering properties by using the excitation, propagation, and reception of surface acoustic waves in piezoelectric materials. Surface acoustic waves have wavelengths in the 100µm-2µm range and are mechanical waves that are very sensitive to their propagation surface. To allow the surface acoustic waves in acoustic wave devices to propagate without interference, a cavity is required above the chip surface during packaging.

[0003] Currently, the main packaging technologies for filters are still ceramic, metal, plastic packaging using wire bonding and flip-chip packaging. For example, CN201910039927.9 discloses a wafer-level packaging structure for acoustic filters. The conventional filter wafer-level packaging structure has problems such as large warpage and relatively low product yield. In addition, the double-layer film structure of the conventional filter wafer-level packaging structure may cause delamination problems, resulting in low packaging reliability for the filter wafer-level packaging structure and relatively low reliability between them. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of the significant technical problems of large warpage and low reliability in the wafer-level packaging structure of filters in the prior art, this application proposes a wafer-level packaging structure of filters with device layer sidewall protection and a manufacturing method thereof, which solves the problems of the conventional two-layer film structure being susceptible to delamination, low packaging reliability, and prone to wafer warpage. [Means for solving the problem]

[0005] A wafer-level packaging structure for a filter with device layer sidewall protection, comprising: a substrate having at least one effective area and at least one exposed area, the effective area being covered with a composite thin film, the exposed area being provided with a recessed filling portion, the filling portion being adjacent to an edge of the exposed area that contacts the effective area; and a first thin film layer formed on at least a portion of the exposed area and the composite thin film, filling the filling portion.

[0006] In the above technical solution, the first thin film layer encases the composite thin film, thereby reducing the possibility of delamination occurring in the two-layer structure of the composite thin film; and since the composite thin film only covers the effective area, warping is less likely to occur compared to a structure in which the composite thin film covers the entire substrate. By combining the above technical solutions, the wafer-level packaging structure of the filter with device layer sidewall protection of the present application has high packaging reliability and product yield.

[0007] In one possible implementation, the filling portion is located at the edge of the exposed area and the effective area and contacts the composite membrane. By this means, the first membrane layer can more tightly encase the composite membrane.

[0008] In one possible implementation, the wafer-level packaging structure of the filter with device layer sidewall protection further includes a second thin film layer formed on the surface of the first thin film layer away from the substrate, and the composite thin film, the opening in the first thin film layer, and the second thin film layer form a resonant cavity. In the above technical solution, the composite thin film, the opening in the first thin film layer, and the second thin film layer form the resonant cavity, which is simple in configuration.

[0009] In one possible implementation, the depth of the fill is 0.5 μm-20 μm.

[0010] With the above technical solution, the first membrane layer can better encase the composite membrane after entering the filling part, and the reliability is improved.

[0011] In one possible implementation, the dicing streets of the substrate and at least some areas of the edges of the chips are exposed areas.

[0012] The above technical solution makes it easier to cut the wafer-level packaging structure in the subsequent processing steps, which is beneficial to improving the reliability of the product.

[0013] In addition, the present application S1, forming a composite thin film on a surface of a substrate; S2: removing a portion of the composite thin film to form at least one effective area and at least one exposed area on the surface of the substrate, the effective area being the area covered with the composite thin film and the exposed area being the area from which the composite thin film has been removed; S3, providing a bonding pad and a resonator on the composite thin film; S4, forming a recessed filler in the exposed area, the filler being adjacent to an edge of the exposed area that borders the effective area; S5: forming a first thin film layer on at least a part of the exposed area and the composite thin film, the first thin film layer filling the filling portion and having openings exposing a part of the surface of the bonding pad and the resonator, and the area of ​​the opening exposing the resonator is larger than the area of ​​the resonator; S6: forming a second thin film layer on the surface of the first thin film layer away from the substrate, the second thin film layer having an opening for exposing the terminal, and the composite thin film, the opening for exposing the resonator of the first thin film layer and the second thin film layer form a resonant cavity; S7: providing a terminal on the bonding pad, and then forming a soldering portion on the end of the terminal away from the bonding pad, where the soldering portion is a solder ball or electroless plated nickel / gold.

[0014] By using the above technical solutions, the first thin film layer can better wrap the composite thin film in the vertical and horizontal directions, thereby reducing the possibility of delamination in the two-layer structure of the composite thin film. In addition, since the composite thin film only covers the effective area, warping is less likely to occur compared to a structure in which the composite thin film covers the entire substrate. By combining the above technical solutions, the wafer-level packaging structure of the filter with device layer sidewall protection of the present application has high packaging reliability and product yield.

[0015] In one possible implementation, the filler is located at the edge of the exposed and active areas and contacts the composite membrane.

[0016] The above technical solution allows the first membrane layer to encase the composite membrane more tightly.

[0017] In one possible implementation, the depth of the fill is 0.5 μm-20 μm.

[0018] With the above technical solution, the first membrane layer can better encase the composite membrane after entering the filling part, and the reliability is improved.

[0019] In one possible implementation, the dicing streets of the substrate and at least some areas of the edges of the chips are exposed areas.

[0020] The above technical solution makes it easier to cut the wafer-level packaging structure in the subsequent processing steps, which is beneficial to improving the reliability of the product. [Effects of the Invention]

[0021] The present disclosure provides a wafer-level packaging structure for a filter with device layer sidewall protection and a manufacturing method thereof, which partially removes the composite film, thereby reducing warpage in the wafer-level packaging structure and improving the yield of the product manufacturing process. Furthermore, by providing a filling section in the exposed area, covering the composite film with a first thin film layer, and filling the filling section, the composite film can be wrapped horizontally and vertically, effectively protecting the substrate structure, avoiding the risk of delamination of the composite film, improving the device's resistance to the external environment, and significantly improving product reliability. [Brief explanation of the drawings]

[0022] The drawings are included to provide a further understanding of the embodiments, and are incorporated herein as part of this specification. The drawings illustrate the embodiments and, together with the description, serve to explain the principles of the present disclosure. It will be readily appreciated that other embodiments and many of the expected advantages of the embodiments will be better understood by reference to the following detailed description. Elements in the drawings are not necessarily to scale. Like reference numerals indicate corresponding like parts.

[0023] [Figure 1] 1 shows a structural schematic diagram of a conventional wafer-level packaging structure of a filter with device layer sidewall protection. [Figure 2] 1 shows a schematic diagram of a packaging structure for a filter according to one embodiment of the present disclosure. [Figure 3] 1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. [Figure 4] 1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. [Figure 5] 1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. [Figure 6] 1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. [Figure 7]1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. [Figure 8] 1A-1C show schematic diagrams of intermediate structures during the manufacture of a filter packaging structure in one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present application will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of interpreting the relevant disclosure, and are not intended to limit the disclosure. Furthermore, for the sake of convenience, only the relevant parts of the relevant disclosure are shown in the drawings.

[0025] It should be noted that the embodiments and features of the embodiments of the present application can be combined with each other unless there is a contradiction. The present application will be described in detail below with reference to the drawings and embodiments.

[0026] In a wafer-level packaging structure, the composite thin film is typically a two-layer structure (not shown), and this two-layer structure may experience delamination due to the influence of the external environment during actual use, resulting in reduced product reliability. For example, as can be seen from the wafer-level packaging structure of a filter with conventional device layer sidewall protection shown in Figure 1, in the prior art, the first thin film layer 200 only covers the top surface of the composite thin film and does not encase the composite thin film 140, making the composite thin film 140 prone to delamination.

[0027] To address the above-mentioned problems, the present application provides a wafer-level packaging structure for a filter with device layer sidewall protection and a manufacturing method thereof.

[0028] FIG. 2 shows a wafer level packaging structure of a filter with device layer sidewall protection according to one embodiment of the present application, which includes a wafer 100 , a first thin film layer 200 , a second thin film layer 300 and terminals 500 .

[0029] The substrate 110 of the wafer 100 includes an active area 120 covered with a composite thin film 140 and an exposed area 130 not covered with the composite thin film 140, and a bonding pad 141 and a resonator 142 are provided on the surface of the composite thin film 140 facing away from the substrate 110 of the wafer 100. Dicing streets (not shown) are provided in the exposed area 130, and in subsequent processing, the wafer-level packaging structure can be cut into multiple chips by cutting the dicing streets. The exposed area 130 further includes a recessed filling portion 131, at least a portion of which surrounds the active area 120.

[0030] In this embodiment, the dicing streets divide the wafer 100 into multiple squares, and the wafer 100 can be packaged and cut to obtain square chips, but in other possible implementations, the dicing streets may divide the wafer 100 into other polygonal patterns.

[0031] The first thin film layer 200 is formed on the composite thin film 140 and the exposed region, and fills the filling portion 131 of the exposed region 130. The first thin film layer 200 fills the filling portion 131 and covers the composite thin film 140, thereby encasing the composite thin film 140, which makes it less likely for delamination of the composite thin film 140 to occur and improves the reliability of the wafer level packaging structure.

[0032] In this embodiment, the filling portions 131 are formed on the edges of the exposed region 130 that contact the effective region 120, and are in close contact with the effective region 120, allowing the first thin film layer 200 to more tightly encase the composite thin film 140, further improving packaging reliability. In this embodiment, the filling portions 131 are formed around the edges of the exposed region 130 that contact the effective region 120, forming a linear pattern with closed ends around the periphery of the composite thin film 140; in other possible implementations, the filling portions 131 may be open and elongated. In this embodiment, the depth of the filling portions 131 is 1 μm; in other possible implementations, the depth of the filling portions 131 may be 0.5 μm-20 μm.

[0033] The second thin film layer 300 is formed on the surface of the first thin film layer 200 away from the substrate 110 and has an opening 301 exposing the terminal 500. At the positions of the bonding pad 141 and the resonator 142 of the first thin film layer 200, openings 201 exposing a portion of the surface of the bonding pad 141 and the resonator 142 are formed, respectively. The area of ​​the opening 201 exposing the resonator 142 is larger than the area of ​​the resonator 142, and the composite thin film 140, the opening 201 exposing the resonator 142 of the first thin film layer 200, and the second thin film layer 300 collectively form a resonant cavity 400.

[0034] In this embodiment, the shape of the filling portion 131 is triangular, but in other possible implementations, the shape of the filling portion 131 is not limited as long as it can form a pit for filling the first thin film layer 200 and can enable the first thin film layer 200 to vertically wrap the composite thin film 140. The second thin film layer 300 has an opening 301 that is larger than the opening 201 of the first thin film layer 200, which is advantageous for installing the terminal 500 and improves product yield.

[0035] The materials of the first thin film layer 200 and the second thin film layer 300 are selected from polymer materials, silicon, ceramics, and glass, respectively. When the material is polymer material, the opening 201 or the hole 301 is formed by exposure, and when other materials are selected, the opening 201 or the hole 301 is formed by laser. The area of ​​the hole 301 in the second thin film layer 300 is equal to or greater than the area of ​​the opening 201 exposing a portion of the surface of the bonding pad 141 in the first thin film layer 200.

[0036] One end of the terminal 500 is connected to the bonding pad 141, and the other end is used for soldering. A soldering portion 501 may be formed on the end of the terminal 500 for soldering, and the material of the soldering portion 501 may be a solder ball or electroless plated nickel / gold. Furthermore, the terminal 500 may be solid or hollow.

[0037] The material of the substrate 110 may be silicon or spinel, and the composite thin film 140 may be a silicon oxide thin film and a lithium tantalate thin film, or the composite thin film 140 may be a silicon oxide thin film and a lithium niobate thin film.

[0038] In this embodiment, the composite thin film 140 is a silicon oxide thin film and a lithium tantalate thin film, and the thickness of the silicon oxide thin film and the lithium tantalate thin film is 1 μm. In other possible implementations, the thickness of the silicon oxide thin film may be 0.1 μm-5 μm, and the thickness of the lithium tantalate thin film or the lithium niobate thin film may be 0.5 μm-10 μm.

[0039] Referring to FIGS. 2-8, the manufacturing method of the wafer-level packaging structure of the filter with device layer sidewall protection in this embodiment includes the following steps.

[0040] S1: forming a composite thin film 140 on the surface of a substrate 110, as shown in FIG.

[0041] 4, a portion of the composite thin film 140 is removed to form at least one effective area 120 and at least one exposed area 130 on the surface of the substrate 110. The effective area 120 is the area covered with the composite thin film 140, and the exposed area 130 is the area where the composite thin film 140 has been removed. In the above step, the operation of removing a portion of the composite thin film 140 can be achieved by laser or etching.

[0042] S3: As shown in FIG. 5, a bonding pad 141 and a resonator 142 are provided on a composite thin film 140.

[0043] S4: As shown in FIG. 6, a filling portion 131 recessed inward is formed in the exposed region 130, and the filling portion 131 is close to the edge of the exposed region 130 that contacts the effective region 120.

[0044] S5, as shown in FIG. 7, a first thin film layer 200 is formed on the composite thin film 140 and the exposed region 130, and the first thin film layer 200 fills the filling portion 131. By performing exposure drilling or laser drilling on the first thin film layer 200, an opening 201 is formed that exposes a portion of the surface of the bonding pad 141 and the resonator 142, respectively, and the area of ​​the opening 201 that exposes the resonator 142 is larger than the area of ​​the resonator 142.

[0045] 8, a second thin film layer 300 is formed on the surface of the first thin film layer 200 away from the substrate 110, the second thin film layer 300 having an opening 301 exposing the terminal 500, and the composite thin film 140, the opening 201 exposing the resonator 142 of the first thin film layer 200, and the second thin film layer 300 form a resonant cavity 400, thereby obtaining the structure shown in FIG. 4. In this embodiment, the area of ​​the opening 301 of the second thin film layer 300 is the same as the area of ​​the opening 201 exposing a portion of the surface of the bonding pad 141 of the first thin film layer 200. In other possible implementations, the area of ​​the opening 301 of the second thin film layer 300 may be larger than the area of ​​the opening 201 exposing a portion of the surface of the bonding pad 141 of the first thin film layer 200.

[0046] S7: Provide terminals 500 on the bonding pads 141, then form soldering portions 501 at the ends of the terminals 500 away from the bonding pads 141, the soldering portions 501 being solder balls or electroless plated nickel / gold, to obtain a wafer-level packaging structure of a filter with device layer sidewall protection as shown in Figure 2.

[0047] In another possible implementation, the order of operations S6 and S7 may be interchanged.

[0048] The composite thin film 140 is composed of at least two thin films. In a conventional method for manufacturing a wafer-level packaging structure for a filter with device layer sidewall protection, the composite thin film 140 is directly coated with a first thin film layer 200 and then cut into chips. In this manufacturing method, the first thin film layer 200 can only cover one surface of the composite thin film 140 and cannot fully encase the composite thin film 140, which can lead to separation between the different thin films of the composite thin film 140. In contrast, the manufacturing method of the present application first removes the composite thin film 140 from the non-functional area (i.e., the active area 120 of the present application), then provides a filler portion 131 at the edge of the composite thin film 140 and fills the filler portion 131 with the first thin film layer 200. This further ensures that the first thin film layer 200 protects the composite thin film 140 in the vertical direction, reduces the possibility of delamination in the composite thin film 140, and thereby improves product yield.

[0049] Although specific embodiments of the present application have been described above, the scope of protection of the present application is not limited thereto, and all modifications and substitutions that can be easily conceived by those skilled in the art without departing from the technical scope disclosed in the present application are included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be in accordance with the scope of protection of the claims.

[0050] In the description of this application, orientations or positional relationships indicated by terms such as "upper," "lower," "inner," and "outer" are based on the drawings and are merely for convenience and simplification of the description of this application. They do not indicate or imply that such devices or elements necessarily have a particular orientation or are constructed and operated in a particular orientation, and therefore should not be understood as limiting the application. The word "comprises" does not exclude the presence of elements or steps not explicitly stated in a claim. The word "a" or "one" preceding an element does not exclude the presence of a plurality of such elements. The mere fact that several measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to improve the invention. Any signs in the claims should not be construed as limiting the scope. [Explanation of symbols]

[0051] 100—wafer, 110—substrate, 120—active area, 130—exposed area, 131—filled portion, 140—composite thin film, 140″—composite thin film in prior art, 141—bonding pad, 142—resonator, 200—first thin film layer, 200″—first thin film layer in prior art, 201—opening, 300—second thin film layer, 301—opening, 400—resonant cavity, 500—terminal, 501—soldering portion.

Claims

1. 1. A wafer level packaging structure for a filter with device layer sidewall protection, comprising: A wafer-level packaging structure for a filter with device layer sidewall protection, comprising: a substrate having at least one effective area and at least one exposed area, the effective area being covered with a composite thin film, the exposed area being provided with a filling portion recessed inward, the filling portion being adjacent to an edge of the exposed area that contacts the effective area; and a first thin film layer formed on at least a portion of the exposed area and on the composite thin film, filling the filling portion.

2. The wafer-level packaging structure of claim 1 , wherein the filling portion is located at the edges of the exposed area and the effective area and contacts the composite thin film.

3. a bonding pad and a resonator are provided on a surface of the composite thin film that faces away from the wafer substrate; 3. The wafer-level packaging structure for a filter with device layer sidewall protection according to claim 1, wherein the first thin film layer covers a portion of the surface of the bonding pad and the periphery of the resonator, and has openings that expose a portion of the surface of the bonding pad and the resonator, respectively, and the area of ​​the opening that exposes the resonator is larger than the area of ​​the resonator.

4. 4. The wafer-level packaging structure of claim 3, further comprising a second thin film layer formed on a surface of the first thin film layer away from the substrate, wherein the composite thin film, the opening exposing the resonator in the first thin film layer, and the second thin film layer form a resonant cavity.

5. 3. The wafer level packaging structure of a filter with device layer sidewall protection according to claim 1, wherein the depth of the filling part is 0.5 μm-20 μm.

6. 3. The wafer-level packaging structure of a filter with device layer sidewall protection according to claim 1, wherein at least a part of the dicing street of the substrate and the edge of the chip are the exposed areas.

7. 1. A method for manufacturing a wafer level packaging structure for a filter with device layer sidewall protection, comprising: S1, forming a composite thin film on a surface of a substrate; S2. A step of removing a portion of the composite thin film to form at least one effective area and at least one exposed area on the surface of the substrate, the effective area being an area covered with the composite thin film, and the exposed area being an area from which the composite thin film has been removed; S3. providing a bonding pad and a resonator on the composite thin film; S4. forming a recessed filler portion in the exposed area, the filler portion being adjacent to an edge of the exposed area that borders the effective area; S5: forming a first thin film layer on at least a portion of the exposed region and the composite thin film, the first thin film layer filling the filling portion and having openings exposing a portion of the surface of the bonding pad and the resonator, the area of ​​the opening exposing the resonator being larger than the area of ​​the resonator; S6: forming a second thin film layer on a surface of the first thin film layer away from the substrate, the second thin film layer having an opening for exposing the terminal, and the composite thin film, the opening for exposing the resonator of the first thin film layer, and the second thin film layer form a resonant cavity; S7. A method for manufacturing a wafer-level packaging structure for a filter with device layer sidewall protection, comprising the steps of: providing a terminal on the bonding pad; and then forming a soldering portion on the end of the terminal away from the bonding pad, the soldering portion being a solder ball or electroless plated nickel / gold.

8. 8. The method for manufacturing a wafer-level packaging structure for a filter with device layer sidewall protection according to claim 7, wherein the filling portion is located at the edges of the exposed area and the effective area and contacts the composite thin film.

9. 8. The method for manufacturing a wafer-level packaging structure for a filter with device layer sidewall protection as claimed in claim 7, wherein the depth of the filling portion is 0.5 μm-20 μm.

10. 8. The method for manufacturing a wafer-level packaging structure of a filter with device layer sidewall protection according to claim 7, wherein at least a part of the dicing street of the substrate and the edge of the chip are the exposed areas.

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