Fault-tolerant quantum error correction using physical transport of qubits

Abstract

The quantum computing system includes a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and communicate with the computing entity. The controller causes the execution of a syndrome circuit segment to generate a syndrome of the logical qubit. The syndrome circuit segment is implemented, at least in part, by causing the execution of a series of transport operations and interactions of at least two physical qubits. Each transport operation in the series of transport operations causes physical transport of at least one of a respective data qubit or a respective ancillary qubit of the logical qubit to a respective interaction zone defined by the quantum processor. Each interaction of the at least two physical qubits is performed within the respective interaction zone. At least one quantum error correction is determined using the syndrome, and the controller causes a classical memory to be updated based on the syndrome and / or the quantum error correction.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Application No. 18 / 347,054, filed July 5, 2023, which claims priority to U.S. Application No. 63 / 368,421, filed July 14, 2022, the contents of which are incorporated herein by reference in their entireties.

[0002] Various embodiments relate to fault-tolerant quantum error correction using physical transport of one or more qubits. Various embodiments relate to fault-tolerant quantum error correction for quantum processors with high qubit connectivity and / or variable relative qubit positions and no defined nearest neighbor qubits. [Background technology]

[0003] Complex quantum computations require a level of precision not possible with conventional quantum computers due to, for example, imperfect control and noise in the gate operations between data qubits. Through a great deal of effort, ingenuity, and innovation, many of the shortcomings of previous systems have been overcome by deploying solutions constructed in accordance with embodiments of the present invention, many examples of which are described in detail herein. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Application No. 63 / 235,022 Summary of the Invention [Means for solving the problem]

[0005] Exemplary embodiments provide methods, systems, apparatus, computer program products, controllers configured to control the operation of a quantum processor, etc., for implementing fault-tolerant quantum computation and / or fault-tolerant quantum error correction, wherein implementing a syndrome circuit segment and / or applying physical quantum error correction includes physical transport of one or more qubits (e.g., data qubits and / or ancillary qubits of a logical qubit).

[0006] According to a first aspect, a method for implementing fault-tolerant quantum error correction using physical transport of qubits is provided. In an exemplary embodiment, the method is implemented by a quantum computing system including a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and is in communication with the classical computing entity. In an exemplary embodiment, the method includes causing, by the controller, the implementation of at least one syndrome circuit segment to generate a syndrome of the logical qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing the implementation of a series of transport operations and at least two-physical qubit interactions (e.g., interactions between two or more physical qubits, such as a two-qubit gate). Each transport operation and at least two-physical qubit interaction in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit or (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that at least one of the respective data qubit of the logical qubit or (b) a respective ancillary qubit is disposed within a respective interaction zone defined by the quantum processor, and a respective at least two-physical qubit interaction is implemented therein. The method further comprises determining, by the classical computational entity, at least one quantum error correction based at least in part on the syndrome of the logical quantum bit, and causing, by the controller, a classical memory of at least one of the controller or the classical computational entity to be updated based on at least one of the syndrome or the at least one quantum error correction.

[0007] In an exemplary embodiment, the method further comprises causing, by the controller, at least one quantum error correction to be applied to the logical qubit.

[0008] In an example embodiment, causing at least one quantum error correction to be applied to the logical qubit comprises at least one of: (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction; (b) causing a physical correction to be performed on one or more data qubits of the logical qubit; or (c) causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified based at least in part on the at least one quantum error correction.

[0009] In an example embodiment, causing the physical correction to be performed on one or more data qubits of the logical qubit comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported into at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

[0010] In an exemplary embodiment, the implementation of at least one syndrome circuit segment comprises an implementation of a plurality of syndrome circuit segments.

[0011] In an exemplary embodiment, causing execution of at least one syndrome circuit segment comprises causing execution of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining whether to cause execution of a second plurality of syndrome circuit segments based at least in part on the results of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments selected from the defined set of syndrome circuit segments; causing execution of the second plurality of syndrome circuit segments in response to the determination to cause execution of the second plurality of syndrome circuit segments; and determining at least one quantum error correction based at least in part on the results of each of the first plurality of syndrome circuit segments in response to the determination not to cause execution of the second plurality of syndrome circuit segments.

[0012] In an exemplary embodiment, the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

[0013] In an exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as the flag qubit.

[0014] In an exemplary embodiment, the method further comprises tracking the value of the flag qubit using at least a classical qubit registry, and causing execution of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

[0015] In an example embodiment, updating the classical memory based on at least one of the syndrome or the at least one quantum error correction comprises tracking the syndrome of the logical qubits in the classical memory.

[0016] In an exemplary embodiment, coherence of each data qubit of a logical qubit is maintained during the execution of at least one syndrome circuit segment.

[0017] In an example embodiment, the method further comprises causing execution of a state preparation circuit segment to prepare a state of each ancillary quantum bit before causing execution of the at least one syndrome circuit segment, and causing each ancillary quantum bit to be read after execution of a series of transport operations and interactions of at least two physical quantum bits, wherein a syndrome of the logical quantum bit is generated based at least in part on a result of the reading of each ancillary quantum bit.

[0018] According to another aspect, a quantum computing system configured to perform fault-tolerant quantum error correction using physical transport of qubits is provided. In an exemplary embodiment, the quantum computing system includes a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and is in communication with the classical computing entity. In an exemplary embodiment, the controller is configured to cause the execution of at least one syndrome circuit segment to generate a syndrome of a logical qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing the execution of a series of transport operations and interactions of at least two physical qubits. Each transport operation and interaction of the at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit or (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that at least one of the respective data qubit of the logical qubit or (b) a respective ancillary qubit is disposed within a respective interaction zone defined by the quantum processor, and a respective interaction of the at least two physical qubits is performed therein. The classical computational entity is configured to determine, by the classical computational entity, at least one quantum error correction based at least in part on the syndrome of the logical qubit, and the controller is further configured to cause a classical memory of at least one of the controller or the classical computational entity to be updated based on at least one of the syndrome or the at least one quantum error correction.

[0019] In an exemplary embodiment, the controller is further configured to cause at least one quantum error correction to be applied to the logical qubit.

[0020] In an example embodiment, causing at least one quantum error correction to be applied to the logical qubit comprises at least one of (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction, (b) causing a physical correction to be performed on one or more data qubits of the logical qubit, or (c) causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified based at least in part on the at least one quantum error correction.

[0021] In an example embodiment, causing the physical correction to be performed on one or more data qubits of a logical qubit comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

[0022] In an exemplary embodiment, the implementation of at least one syndrome circuit segment comprises an implementation of a plurality of syndrome circuit segments.

[0023] In an example embodiment, causing the execution of at least one syndrome circuit segment comprises: causing the execution of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining whether to cause the execution of a second plurality of syndrome circuit segments based at least in part on an outcome of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments selected from the defined set of syndrome circuit segments; causing the execution of the second plurality of syndrome circuit segments in response to determining to cause the execution of the second plurality of syndrome circuit segments; and determining at least one quantum error correction based at least in part on the outcome of each of the first plurality of syndrome circuit segments in response to determining not to cause the execution of the second plurality of syndrome circuit segments.

[0024] In an exemplary embodiment, the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

[0025] In an exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as the flag qubit.

[0026] In an exemplary embodiment, the controller is further configured to track the value of the flag qubit using at least a classical qubit registry, and to cause execution of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

[0027] In an example embodiment, updating the classical memory based on at least one of the syndrome or the at least one quantum error correction comprises tracking the syndrome of the logical qubits in the classical memory.

[0028] In an exemplary embodiment, coherence of each data qubit of a logical qubit is maintained during the execution of at least one syndrome circuit segment.

[0029] In an example embodiment, the controller is further configured to cause execution of a state preparation circuit segment to prepare a state of each ancillary quantum bit before causing execution of the at least one syndrome circuit segment, such that each ancillary quantum bit is read after execution of a series of transport operations and interactions of at least two physical quantum bits, and the syndrome of the logical quantum bit is generated based at least in part on a result of the reading of each ancillary quantum bit.

[0030] According to another aspect, a controller is provided that controls operation of a quantum processor and is configured to cause fault-tolerant quantum error correction to be performed using physical transport of qubits. In an exemplary embodiment, the controller is configured for communication with a classical computation entity. In an exemplary embodiment, the controller is configured (and / or programmed) to cause the execution of at least one syndrome circuit segment to generate a syndrome for a logical qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing the execution of a series of transport operations and interactions of at least two physical qubits. Each transport operation and interaction of the at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit or (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that at least one of the data qubit of the logical qubit or the ancillary qubit is disposed within a respective interaction zone defined by the quantum processor, and a respective interaction of the at least two physical qubits is performed therein. The controller is further configured to cause the classical computation entity to determine at least one quantum error correction based, at least in part, on the syndrome of the logical qubit. The controller is further configured to cause at least one quantum error correction to be applied to the logical qubit.

[0031] In an example embodiment, causing at least one quantum error correction to be applied to the logical qubit comprises at least one of (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction, (b) causing a physical correction to be performed on one or more data qubits of the logical qubit, or (c) causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified based at least in part on the at least one quantum error correction.

[0032] In an example embodiment, causing the physical correction to be performed on one or more data qubits of a logical qubit comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

[0033] In an exemplary embodiment, the implementation of at least one syndrome circuit segment comprises an implementation of a plurality of syndrome circuit segments.

[0034] In an example embodiment, causing the execution of at least one syndrome circuit segment comprises: causing the execution of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining whether to cause the execution of a second plurality of syndrome circuit segments based at least in part on an outcome of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments selected from the defined set of syndrome circuit segments; causing the execution of the second plurality of syndrome circuit segments in response to determining to cause the execution of the second plurality of syndrome circuit segments; and determining at least one quantum error correction based at least in part on the outcome of each of the first plurality of syndrome circuit segments in response to determining not to cause the execution of the second plurality of syndrome circuit segments.

[0035] In an exemplary embodiment, the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

[0036] In an exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as the flag qubit.

[0037] In an exemplary embodiment, the controller is further configured to track the value of the flag qubit using at least a classical qubit registry, and to cause execution of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

[0038] In an example embodiment, updating the classical memory based on at least one of the syndrome or the at least one quantum error correction comprises tracking the syndrome of the logical qubits in the classical memory.

[0039] In an exemplary embodiment, coherence of each data qubit of a logical qubit is maintained during the execution of at least one syndrome circuit segment.

[0040] In an example embodiment, the controller is further configured to cause execution of a state preparation circuit segment to prepare a state of each ancillary quantum bit before causing execution of the at least one syndrome circuit segment, such that each ancillary quantum bit is read after execution of a series of transport operations and interactions of at least two physical quantum bits, and the syndrome of the logical quantum bit is generated based at least in part on a result of the reading of each ancillary quantum bit.

[0041] According to another aspect, a computer program product is provided comprising at least one non-transitory computer-readable medium. The at least one computer-readable memory stores computer-executable instructions that, when executed by a processing element of a controller, cause the controller to control operation of a quantum processor and to cause fault-tolerant quantum error correction using physical transport of qubits. In an exemplary embodiment, the computer-executable instructions, when executed by a processing element of the controller, cause the controller to cause execution of at least one syndrome circuit segment to generate a syndrome of a logical qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing execution of a series of transport operations and interactions of at least two physical qubits. Each transport operation and interaction of the at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit and (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that the respective data qubit of the logical qubit and (b) a respective ancillary qubit are disposed within respective interaction zones defined by the quantum processor, and a respective interaction of the at least two physical qubits is performed therein. The computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to cause a classical computational entity in communication with the controller to determine at least one quantum error correction based at least in part on the syndrome of the logical qubit, and to cause a classical memory of at least one of the controller or the classical computational entity to be updated based on at least one of the syndrome or the at least one quantum error correction.

[0042] In an exemplary embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to cause at least one quantum error correction to be applied to the logical qubit.

[0043] In an example embodiment, causing at least one quantum error correction to be applied to the logical qubit comprises at least one of (a) updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction, (b) causing a physical correction to be performed on one or more data qubits of the logical qubit, or (c) causing a logical operation to be performed at least in part on one or more data qubits of the logical qubit to be modified based at least in part on the at least one quantum error correction.

[0044] In an example embodiment, causing the physical correction to be performed on one or more data qubits of a logical qubit comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

[0045] In an exemplary embodiment, the implementation of at least one syndrome circuit segment comprises an implementation of a plurality of syndrome circuit segments.

[0046] In an example embodiment, causing the execution of at least one syndrome circuit segment comprises: causing the execution of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining whether to cause the execution of a second plurality of syndrome circuit segments based at least in part on an outcome of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments selected from the defined set of syndrome circuit segments; causing the execution of the second plurality of syndrome circuit segments in response to determining to cause the execution of the second plurality of syndrome circuit segments; and determining at least one quantum error correction based at least in part on the outcome of each of the first plurality of syndrome circuit segments in response to determining not to cause the execution of the second plurality of syndrome circuit segments.

[0047] In an exemplary embodiment, the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

[0048] In an exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as the flag qubit.

[0049] In an example embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to track values ​​of flag qubits using at least one classical qubit registry, and to cause implementation of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

[0050] In an example embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to at least one of: (a) track syndromes of the logical qubits in a memory of the controller; or (b) cause the classical computational entity to track syndromes of the logical qubits in a memory of the classical computational entity.

[0051] In an exemplary embodiment, coherence of each data qubit of a logical qubit is maintained during the execution of at least one syndrome circuit segment.

[0052] In an example embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to cause execution of a state preparation circuit segment to prepare a state of each ancillary quantum bit before causing execution of at least one syndrome circuit segment, such that each ancillary quantum bit is read after performance of a series of transport operations and interactions of at least two physical quantum bits, and wherein a syndrome of the logical quantum bit is generated based at least in part on a result of the reading of each ancillary quantum bit.

[0053] According to another aspect, a method for implementing a logical multi-qubit gate (a logical gate between two or more logical qubits) is provided. In an exemplary embodiment, the method includes, by a controller configured to control operation of a quantum processor, causing the quantum processor to implement a first portion of the logical multi-qubit gate by causing a first group of at least two-physical qubit interactions to be performed on at least a first subset of the physical qubits of a set of physical qubits. The set of physical qubits includes a data qubit of a first logical qubit, a data qubit of a second physical qubit, and one or more ancillary qubits. The logical multi-qubit gate is implemented on at least the first logical qubit and the second logical qubit. The method further includes: causing the quantum processor, by the controller, to implement a multi-qubit quantum error correction cycle comprising implementation of at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction; and causing the quantum processor, by the controller, to implement a second portion of the logical multi-qubit gate by causing a second group of at least two-physical qubit interactions to be performed on at least a second subset of the physical qubits of the set of physical qubits.

[0054] In an exemplary embodiment, at least one at least two-physical qubit interaction of the second group of at least two-physical qubit interactions is modified based at least in part on at least one quantum error correction.

[0055] In an example embodiment, the method further comprises at least one of: (a) causing a physical correction to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate based on the at least one quantum error correction; or (b) causing an operation to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate is modified based at least in part on the at least one quantum error correction.

[0056] In an exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit prior to performing the second group of interactions of the at least two physical qubits.

[0057] In an exemplary embodiment, the method further comprises causing tracking of at least one of the at least one syndrome or the at least one quantum error correction in the classical memory.

[0058] In an example embodiment, performing at least one of the first group of interactions of at least two physical qubits, the at least one syndrome circuit segment, or the second group of interactions of at least two physical qubits comprises causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor.

[0059] According to another aspect, a controller is provided that controls operation of a quantum processor and is configured to cause fault-tolerant quantum error correction to be performed using physical transport of qubits. In an exemplary embodiment, the controller is configured (and / or programmed) to cause the quantum processor to perform a first portion of a logical multi-qubit gate by causing a first group of at least two physical qubit interactions to be performed on at least a first subset of the physical qubits of the set of physical qubits. The set of physical qubits comprises a data qubit of a first logical qubit, a data qubit of a second logical qubit, and one or more ancillary qubits. The logical multi-qubit gate is performed on at least the first logical qubit and the second logical qubit. The controller is further configured to cause the quantum processor to perform a multi-qubit quantum error correction cycle comprising implementation of at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction, and to cause the quantum processor to perform a second portion of the logical multi-qubit gate by causing a second group of at least two physical qubit interactions to be performed on at least a second subset of the physical qubits of the set of physical qubits.

[0060] In an exemplary embodiment, at least one at least two-physical qubit interaction of the second group of at least two-physical qubit interactions is modified based at least in part on at least one quantum error correction.

[0061] In an example embodiment, the controller is further configured to at least one of: (a) causing a physical correction to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate based on the at least one quantum error correction; or (b) causing an operation to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate is modified based at least in part on the at least one quantum error correction.

[0062] In an exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit prior to performing the second group of interactions of the at least two physical qubits.

[0063] In an example embodiment, the controller is further configured to cause tracking of at least one of the at least one syndrome or the at least one quantum error correction in the classical memory.

[0064] In an example embodiment, performing at least one of the first group of interactions of at least two physical qubits, the at least one syndrome circuit segment, or the second group of interactions of at least two physical qubits comprises causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor.

[0065] According to another aspect, a computer program product is provided comprising at least one non-transitory computer-readable medium. The at least one computer-readable memory stores computer-executable instructions that, when executed by a processing element of a controller, cause the controller to control operation of a quantum processor and cause performance of a fault-tolerant quantum logic operation using physical transport of qubits. In an exemplary embodiment, the computer-executable instructions, when executed by a processing element of the controller, are configured to cause the controller to cause the quantum processor to perform a first portion of a logical multi-qubit gate by causing performance of a first group of interactions of at least two physical qubits on at least a first subset of physical qubits of a set of physical qubits. The set of physical qubits comprises a data qubit of a first logical qubit, a data qubit of a second logical qubit, and one or more ancillary qubits. The logical multi-qubit gate is performed on at least the first logical qubit and the second logical qubit. The controller is further configured to cause the quantum processor to perform a multi-qubit quantum error correction cycle comprising implementing at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction, and to cause the quantum processor to perform a second portion of the logical multi-qubit gate by causing implementation of a second group of at least two physical qubit interactions for at least a second subset of the physical qubits of the set of physical qubits.

[0066] In an exemplary embodiment, at least one at least two-physical qubit interaction of the second group of at least two-physical qubit interactions is modified based at least in part on at least one quantum error correction.

[0067] In an example embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to at least one of: (a) cause a physical correction to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate based on the at least one quantum error correction; or (b) cause an operation to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate is corrected based at least in part on the at least one quantum error correction.

[0068] In an exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit prior to performing the second group of interactions of the at least two physical qubits.

[0069] In an example embodiment, the computer-executable instructions, when executed by a processing element of the controller, are further configured to cause the controller to track at least one of the at least one syndrome or the at least one quantum error correction in the classical memory.

[0070] In an example embodiment, performing at least one of the first group of interactions of at least two physical qubits, the at least one syndrome circuit segment, or the second group of interactions of at least two physical qubits comprises causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor.

[0071] Having thus generally described the invention, reference is now made to the accompanying drawings, which are not necessarily drawn to scale. [Brief explanation of the drawings]

[0072] [Figure 1] FIG. 1 is a schematic diagram illustrating an exemplary quantum computing system, according to an exemplary embodiment. [Figure 2A] 1A-1C are top views of a portion of an example confinement device of an example quantum processor at different times, according to an example embodiment; [Figure 2B] 1A-1C are top views of a portion of an example confinement device of an example quantum processor at different times, according to an example embodiment; [Figure 3] 2 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum computing system, such as the quantum computing system of FIG. 1, for example, to implement a quantum circuit, according to various embodiments. [Figure 4] 1 is a schematic diagram of an example controller configured to control the operation of a containment device, according to an example embodiment. [Figure 5] 5 is a flowchart illustrating various processes, operations, and / or procedures performed by a controller, such as the controller of FIG. 4, for example, to perform a quantum error correction cycle, according to various embodiments. [Figure 6] 5 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by a controller, such as the controller of FIG. 4, for example, to determine a syndrome of a logical qubit, according to various embodiments. [Figure 7] 10 is a flowchart illustrating various processes, operations, and / or procedures performed by a controller, such as the controller of FIG. 4 , possibly in conjunction with the classical computational entity of FIG. 9 , for example, to determine syndromes for one or more logical qubits, according to various embodiments. [Figure 8] 5 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by a controller, such as the controller of FIG. 4, for example, to determine a syndrome of a logical qubit, according to various embodiments. [Figure 9]1 is a schematic diagram of an example computing entity that may be used, according to an example embodiment; [Figure 10] 5 is a flowchart illustrating various processes, operations, and / or procedures performed by a controller, such as the controller of FIG. 4 , for example, to implement a fault-tolerant logic multi-qubit gate, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0073] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the invention are shown. Indeed, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term "or" (also written " / ") is used herein in both the alternative and connective sense, unless otherwise indicated. The terms "illustrative" and "exemplary" are used as examples without denoting a level of quality. The terms "generally," "substantially," and "approximately" refer to within processing and / or manufacturing tolerances and / or the user's measurement capabilities, unless otherwise indicated. Like numbers refer to like elements throughout.

[0074] Exemplary embodiments provide methods, systems, apparatus, computer program products, and controllers configured to control the operation of a quantum processor or the like to perform fault-tolerant quantum computation and / or fault-tolerant quantum error correction, where the implementation of syndrome circuit segments and / or application of physical quantum error correction involves physical transport of one or more qubits (e.g., data qubits and / or ancillary qubits of logical qubits). For example, in various embodiments, the implementation of a quantum program, algorithm, or circuit (referred to herein as a quantum circuit) comprises the implementation of one or more quantum error correction cycles. For example, quantum error correction cycles may be performed at various times during the implementation of the quantum circuit.

[0075] During a quantum error correction cycle, one or more syndrome circuit segments are implemented to generate, determine, and / or extract syndromes from one or more logical qubits used in implementing the quantum circuit. In various embodiments, the logical qubits comprise a plurality of data qubits and form binary logic elements of the quantum processor. In various embodiments, the quantum error correction cycle may further include determining one or more quantum error corrections based on the generated, determined, and / or extracted syndromes and applying the one or more quantum error corrections to the respective logical qubits.

[0076] In various embodiments, at least one syndrome circuit segment is implemented to generate a syndrome for each logical qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing a series of transport operations and interactions of at least two physical qubits to occur. Each transport operation and interaction of the at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit and (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that the respective data qubit and the respective ancillary qubit are disposed within the respective interaction zones defined by the quantum processor, and the respective at least two physical qubit interactions are performed therein. At least one quantum error correction is determined and applied to the logical qubit based, at least in part, on the syndrome of the logical qubit.

[0077] In various embodiments, the quantum error correction comprises a software correction applied by tracking quantum errors experienced by a logical qubit in a classical qubit registry corresponding to the logical qubit, physically applying the correction to one or more data qubits of the logical qubit, and / or modifying a logical operation performed on one or more data qubits of the logical qubit based at least in part on the determined quantum error correction.

[0078] Exemplary Quantum Computing System 1 illustrates an exemplary quantum computing system configured to implement fault-tolerant quantum error correction using data qubit transport. As will be appreciated, various embodiments relate to various types of quantum computing systems in which the physical locations of the qubits are not fixed (e.g., the physical qubit registers are reconfigurable). For example, various embodiments relate to quantum computing systems that use ions, neutral atoms, quantum dots, quantum particles, etc. as qubits.

[0079] 1 illustrates an exemplary quantum charge-coupled device (QCCD)-based quantum computing system 100. Quantum computing system 100 includes a classical computing entity 10, a controller 30, and a quantum processor 115. Controller 30 is configured to control the operation of quantum processor 115. Controller 30 and classical computing entity 10 communicate with each other via direct wired and / or wireless connections and / or via one or more wired and / or wireless networks 20.

[0080] In the illustrated embodiment, quantum processor 115 includes a containment device 120 used to confine a manipulable object so that various functions can be performed on the manipulable object. For example, in various embodiments, containment device 120 is an ion trap or the like. For example, in various embodiments, the manipulable object is an ion, a multipolar molecule, and / or a charged molecule, a charged particle, or the like. Various functions can be performed on the manipulable object, such as state preparation, performing logic gates, reading / determining a state, cooling, transporting between different locations in containment device 120, and the like. In various embodiments, the logic gate performed on the manipulable object includes a transversal gate. A transversal gate is a gate where an error-correcting code can achieve a transformation on a logical qubit by applying the gate to each of the data qubits of the logical qubit. For example, in a five-qubit code, a Hadamard gate is a transversal gate if a logical Hadamard on the logical qubit can be achieved by applying a Hadamard to each of the five data qubits of the logical qubit. In various embodiments, a logic gate that is not a transversal gate is used.

[0081] In various embodiments, the manipulable object comprises an ancillary qubit and a plurality of data qubits organized into one or more logical qubits. In various embodiments, the ancillary qubits are used to interrogate the data qubits and / or logical qubits to determine one or more syndromes thereof. For example, the ancillary qubits are used to interrogate the data qubits and / or logical qubits such that the coherence of each data qubit of each logical qubit is maintained during implementation of the syndrome circuit segments. This allows for the generation, determination, and / or tracking of syndromes of logical qubits without breaking the coherence of each data qubit of the logical qubit.

[0082] In various embodiments, quantum system controller 30 is configured, programmed, etc. to control quantum processor 115. For example, quantum processor 115 comprises confinement device 120 configured to confine a plurality of manipulable objects. Quantum system controller 30 is configured to control the operation of confinement device 20. In an exemplary embodiment, quantum processor 115 comprises a plurality of qubits (e.g., physical data qubits organized into logical qubits, ancillary qubits, etc.). In various embodiments, the data qubits and the ancillary qubits are each embodied by a respective manipulable object of a plurality of manipulable objects confined by confinement device 120. In various embodiments, quantum computer 110 includes or communicates with a database and / or program (not shown) of quantum error decoders and / or quantum error correction decision applications, programs, etc. (e.g., stored by and / or operating on classical computational entity 10). For example, the database may be stored by one or more classical computational entities 10 in communication with the controller 30 via one or more wired and / or wireless networks 20 and / or by memory local to the controller 30.

[0083] In various embodiments, quantum processor 115 comprises means for controlling the evolution of the quantum states of qubits. For example, in one exemplary embodiment, quantum processor 115 comprises a cryostat and / or vacuum chamber 40 surrounding confinement device 120 (e.g., an ion trap, etc.), one or more manipulation sources 60, one or more voltage sources 50, and / or one or more optical collection systems 70. For example, cryostat and / or vacuum chamber 40 may be a temperature- and / or pressure-controlled chamber. In one exemplary embodiment, one or more manipulation sources 60 may comprise one or more lasers (e.g., optical lasers, microwave sources, etc.). In various embodiments, one or more manipulation sources 60 are configured to manipulate and / or cause a controlled quantum state evolution of one or more manipulable objects within confinement device 120. In various embodiments, the manipulable objects within confinement device 120 (e.g., ions trapped in an ion trap) act as data qubits and / or ancillary qubits for quantum processor 115 of quantum computer 110. For example, in exemplary embodiments in which one or more manipulation sources 60 comprise one or more lasers, the lasers may provide one or more laser beams to manipulable objects trapped within confinement device 120 in cryostat and / or vacuum chamber 40. For example, manipulation source 60 may generate and / or provide laser beams configured to ionize manipulable objects, initialize manipulable objects within a defined two-state qubit space of a quantum processor, perform gates (e.g., logical gates for logical qubits and / or physical gates for physical qubits) on one or more qubits of a quantum processor, read the quantum states of one or more qubits of a quantum processor, etc.

[0084] In various embodiments, quantum computer 110 comprises a light collection system 70 configured to collect and / or detect photons generated by qubits (e.g., during a readout procedure). Light collection system 70 may comprise one or more optical elements (e.g., lenses, mirrors, waveguides, fiber optic cables, etc.) and one or more photodetectors. In various embodiments, the photodetectors may be photodiodes, photomultiplier tubes, charge-coupled device (CCD) sensors, complementary metal-oxide semiconductor (CMOS) sensors, microelectromechanical systems (MEMS) sensors, and / or other photodetectors that sense light at the expected fluorescence wavelengths of the data qubits and / or ancillary qubits of quantum computer 110. In various embodiments, the detectors may be in electronic communication with quantum system controller 30, such as via one or more A / D converters 425 (see FIG. 4 ).

[0085] In various embodiments, quantum computer 110 includes one or more voltage sources 50. For example, voltage source 50 may include multiple voltage drivers and / or voltage sources and / or at least one RF driver and / or voltage source. For example, in various embodiments, voltage source 50 includes multiple arbitrary waveform generators (AWGs). In an exemplary embodiment, voltage source 50 may be electrically coupled to corresponding potential-generating elements (e.g., electrodes) of containment device 120.

[0086] In various embodiments, classical computational entity 10 is configured to allow a user to provide input to quantum computer 110 (e.g., via a user interface of computational entity 10) and receive, view, etc. output from quantum computer 110. In various embodiments, classical computational entity 10 is configured to perform one or more classical computations in real time or near real time in conjunction with the implementation of a quantum circuit by quantum computer 10. For example, during the implementation of a quantum circuit, controller 30 may provide one or more syndromes of one or more logical qubits, and classical computational entity 10 determines and provides one or more corresponding quantum error corrections such that controller 30 can perform the quantum error corrections in real time while the quantum circuit is being implemented.

[0087] Classical computational entity 10 is referred to herein as being “classical” because it performs classical computational operations using semiconductor-based hardware. Classical computational entity 10 may be in communication with quantum system controller 30 of quantum computer 110 via one or more wired or wireless networks 20 and / or via direct wired and / or direct wireless communication. In an exemplary embodiment, classical computational entity 10 may convert, configure, format, etc., information / data, quantum computing algorithms and / or circuits, etc., into a computational language, executable instructions, command set, etc. that quantum system controller 30 can understand and / or implement. For example, controller 30 may be configured to generate machine-code-level commands that, when executed by appropriate components of quantum computer 110, are configured to cause quantum computer 110 to perform quantum circuits. In various embodiments, classical computational entity 10 may provide quantum computing algorithms and / or circuits in a computational language that quantum system controller 30 resolves into individual or sets of operations and / or machine-code-level commands.

[0088] In various embodiments, classical computational entity 10 and controller 30 are communicatively coupled in a low-latency manner. For example, controller 30 may be configured to invoke classical operations, programs, modules, functions, etc. running on classical computational entity 10 (e.g., using a foreign function interface (FFI), an application program interface (API), or other suitable interface). The results of these exchanges between controller 30 and classical computational entity 10 may be used to dynamically modify and / or act on the quantum circuit implemented by quantum processor 115 in real time, in-circuit, etc. Thus, in certain exemplary embodiments, communication latency between classical computational entity 10 and controller 30 is minimized.

[0089] In various embodiments, quantum system controller 30 is configured to control voltage source 50, a cryostat system and / or vacuum system that controls the temperature and pressure within cryostat and / or vacuum chamber 40, manipulation source 60, and / or other systems that control various environmental conditions (e.g., temperature, pressure, etc.) within cryostat and / or vacuum chamber 40 and / or that are configured to manipulate and / or cause the controlled evolution of the quantum states of one or more manipulable objects within confinement device 120. For example, quantum system controller 30 may cause the controlled evolution of the quantum states of one or more manipulable objects within confinement device 120 to execute a quantum circuit and / or algorithm. For example, quantum system controller 30 may cause the implementation of a readout procedure comprising coherent shelving, possibly as part of executing a quantum circuit and / or algorithm. Additionally, quantum system controller 30 is configured to communicate and / or receive input data from light collection system 70, corresponding to the readout of the quantum states of physical data qubits and / or ancillary qubits of quantum computer 110. In various embodiments, the manipulable objects confined within containment device 120 are used as data qubits and / or auxiliary qubits of quantum computer 110. In various embodiments, the data qubits are organized into logical qubits, and the auxiliary qubits are used to non-invasively interrogate the data qubits and / or logical qubits.

[0090] In various embodiments, the implementation of the quantum circuit comprises the performance of one or more quantum error correction cycles. During the quantum error correction cycle, one or more syndrome circuit segments are implemented to generate and / or extract a syndrome from one or more logical qubits used in the implementation of the quantum circuit. The syndrome circuit segments are implemented, at least in part, by causing a series of transport operations and interactions of at least two physical qubits to be performed. Each transport operation and interaction of at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit and (b) a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that the respective data qubit of the logical qubit and the respective ancillary qubit are disposed within the respective interaction zones defined by the quantum processor, and the respective at least two physical qubit interactions are performed therein. The interactions between the respective ancillary qubits and the one or more data qubits of the logical qubit cause information about the one or more data qubits of the logical qubit to be encoded by the ancillary qubit non-invasively (e.g., without breaking the coherence of the one or more data qubits). Thus, the state of the ancillary qubit can be used to determine and / or extract the syndrome of the logical qubit.

[0091] 2A shows a top view of a portion of containment device 120 at a first time t1 during implementation of a syndrome circuit segment. The shown portion of containment device 120 includes radio frequency (RF) rails 122A, 122B and three series of control electrodes 124A, 124B, 124C. Each series of control electrodes 124 includes a plurality of control electrodes 126.

[0092] In various embodiments, the RF voltage sources of voltage source 50 generate and provide RF voltage signals that are applied to RF rails 122A, 122B to generate pseudopotentials that define one or more linear confinement regions (e.g., a two-dimensional or three-dimensional array of one-dimensional confinement regions). Manipulable objects confined by confinement device 120 are confined to one or more linear confinement regions.

[0093] The manipulable object can be transported between different locations in confinement device 120 through application of a set of voltage signal sequences to control electrodes 126. For example, at time t1, a manipulable object used as a first data qubit 5A and a manipulable object used as an ancillary qubit 8 are disposed within interaction zone 128 of confinement device 120. The first data qubit 5A is part of a logical qubit, and an interaction of at least two physical qubits can be performed on the first data qubit 5A and the ancillary qubit 8 as part of a syndrome circuit segment to generate, determine, and / or extract a syndrome for the logical qubit.

[0094] At a first time t1, the second data qubit 5B is located outside the interaction zone 128. After performing an at least two-physical qubit interaction with the first data qubit 5A and the ancillary qubit 8, the first data qubit 5A is transported out of the interaction zone 128 and the second data qubit 5B is transported into the interaction zone 128. For example, as shown in FIG. 2B , at a second time t2, the second data qubit 5B and the ancillary qubit 8 are disposed within the interaction zone 128, and the first data qubit is located outside the interaction zone 128. An at least two-physical qubit interaction may then be performed with the second data qubit 5B and the ancillary qubit 8 as part of performing a syndrome circuit segment.

[0095] Exemplary Operation of a Quantum Computing System 3 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum computing system, such as quantum computing system 100, to, for example, implement a quantum circuit, according to various embodiments. For example, the quantum circuit may be obtained (e.g., accessed from memory 410, received via communications interface 420, etc. (see FIG. 4)) and compiled by controller 30. Controller 30 may then cause quantum computing system 100 to begin executing the quantum circuit (possibly via user input received via classical computing entity 10 and / or via a user interface of controller 30).

[0096] Starting at block 302, a physical qubit state is prepared. As used herein, the term physical qubit refers to a qubit embodied by a respective manipulable object. Each physical qubit is a data qubit or an ancillary qubit. For example, data qubits and ancillary qubits are examples of physical qubits. One or more logical qubits, each comprising a respective plurality of data qubits, each form a respective binary logic element of the quantum processor.

[0097] In various embodiments, controller 30 controls operation of voltage source 50 to generate and provide voltage signals that cause physical qubits to be transported into and out of respective interaction zones defined by quantum processor 115 (e.g., locations of confinement device 120 configured to intersect respective manipulation signals with physical qubits such that physical qubits located in the interaction zones are affected by the respective manipulation signals). Controller 30 further controls operation of one or more manipulation sources 60 to provide respective manipulation signals to respective interaction zones defined by the quantum processor to prepare respective quantum states of the respective physical qubits. For example, in various embodiments, state preparation comprises bringing the quantum states of one or more physical qubits into known states in a defined two-state qubit space of the energy structure of the respective manipulable object.

[0098] In one example embodiment, the state preparation operation is not fault-tolerant. However, because quantum information has not yet been encoded into data qubits at this point in implementing the quantum circuit (e.g., implementation of logic gates for the physical qubits and / or logical qubits for which state preparation is being performed has not yet begun), the state preparation operation may be implemented as a circuit segment that iterates until successful, ensuring in real time that the state of each qubit is fault-tolerantly prepared. For example, execution of a syndrome circuit segment may be used to determine whether the state preparation operation performed successfully.

[0099] In step / act 304, one or more logical operations are performed on the logical qubits in accordance with at least a portion of the quantum circuit. For example, controller 30 may cause quantum processor 115 to perform one or more logical operations on the logical qubits of quantum processor 115 in accordance with the quantum circuit. For example, performing one or more logical operations on the logical qubits comprises transporting one or more data qubits of the logical qubits into and / or out of respective interaction zones, inducing interactions between respective data qubits of the logical qubits, performing single and / or at least two-physical qubit gates (e.g., gates that cause interactions of two or more physical qubits) on respective data qubits of the logical qubits, etc. in accordance with the quantum circuit. In various embodiments, the physical qubits (data qubits and ancillary qubits) of quantum computing system 100 may be physically transportable within confinement device 120 such that any selected pair of physical qubits may be transported to the same interaction zone and interact with each other (e.g., to have a two-qubit gate performed thereon). For example, the quantum circuit indicates which gates should be performed on which logical qubits and in what order.

[0100] In various embodiments, the implemented gate is a transversal gate. For example, a single-qubit gate is implemented for a logical qubit by implementing a corresponding single-qubit gate for each of a plurality of data qubits of a logical qubit in series, in parallel, and / or a combination thereof. In various embodiments, a two-qubit gate is implemented for a first logical qubit and a second logical qubit by causing a corresponding two-qubit gate to be implemented for each pair of a first data qubit of a first logical qubit and a second data qubit of a second logical qubit.

[0101] In various embodiments, at least one non-transversal gate is used. For example, in an exemplary embodiment, a logic gate (e.g., a single logic gate and / or at least two logical qubit gate) of a quantum circuit and / or one or more gates of a syndrome circuit segment are non-transversal gates. For example, at least one gate may be used (e.g., in a quantum circuit and / or syndrome circuit segment) where a first set of operators is applied to a first subset of the data qubits of the logical qubits and a second (different) set of operators is applied to a second subset of the data qubits of the logical qubits to implement the gate. For example, in an exemplary embodiment, a set of physical gates that result in the implementation of a respective logical operation on one or more logical qubits is used to implement the logical operation.

[0102] At various times during implementation of the quantum circuit, syndromes of one or more logical qubits are generated, determined, and / or extracted. Specifically, in step / act 306, ancillary qubits are used to perform syndrome extraction. For example, one or more ancillary qubits are used to non-invasively interrogate data qubits and / or logical qubits. For example, interactions between each ancillary qubit and one or more data qubits of the logical qubits cause information about one or more data qubits of the logical qubit to be encoded by the ancillary qubit non-invasively (e.g., without breaking the coherence of the one or more data qubits).

[0103] In various embodiments, syndrome extraction is performed through the implementation of a syndrome circuit segment. The implementation of the syndrome circuit segment comprises the implementation of a series of transport operations and interactions of at least two physical qubits. Each transport operation and interaction of at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of a logical qubit or a respective ancillary qubit to a respective interaction zone defined by quantum processor 115, such that the respective data qubit and (b) respective ancillary qubit are disposed within the respective interaction zone. Respective at least two physical qubit interactions are then performed with the data qubit and the ancillary qubit in the interaction zone, such that information about the data qubit is encoded into the quantum state of the ancillary qubit without disturbing the quantum state of the data qubit. In various embodiments, the implementation of the syndrome circuit segment may include performing various aspects of lattice surgery and / or interaction between two or more ancillary qubits.

[0104] In various embodiments, the syndrome circuit segment is implemented using one or more ancillary qubits and one or more data qubits of a logical qubit to generate, determine, and / or extract a syndrome for the logical qubit. The syndrome circuit is a relatively short circuit (compared to a quantum circuit) configured to encode information about one or more data qubits of a logical qubit into the quantum state of one or more ancillary qubits such that the ancillary qubits can be read to determine the syndrome of the logical qubit comprising the one or more data qubits without destroying the coherence and / or quantum information stored in the one or more data qubits of the logical qubit. For example, the syndrome of a logical qubit is configured to provide information about the occurrence, location, and / or type of error experienced by the logical qubit.

[0105] For example, one or more quantum error correction cycles may be performed to generate, determine, and / or extract a syndrome for one or more logical qubits in a fault-tolerant manner. As used herein, fault tolerance refers to a design principle that ensures that faults do not propagate too quickly through a quantum circuit and result in uncorrectable logical errors. For example, each quantum error correction cycle includes the implementation of one or more syndrome circuit segments. In various embodiments, generating, determining, and / or extracting a syndrome for one or more logical qubits in a fault-tolerant manner comprises performing multiple syndrome extraction cycles for each logical qubit and comparing results of the multiple syndrome extraction cycles. For example, the fault tolerance of quantum error correction may be probability-based fault tolerance.

[0106] In various embodiments, one or more of the quantum error correction cycles include implementation of one or more flagged syndrome circuit segments. In an exemplary embodiment, when a current value (e.g., quantum state) of an ancillary qubit utilized as a flag in an implementation of a flagged syndrome circuit for a logical qubit is determined to differ from a previous value (e.g., quantum state) of the ancillary qubit utilized as a flag in a previous implementation of a flagged syndrome circuit for the logical qubit, an unflagged syndrome circuit segment is implemented to gather additional information regarding one or more errors experienced by the logical qubit. For example, in an exemplary embodiment, a quantum error decoder (e.g., operating on classical computation entity 10 and / or controller 30) is invoked to determine one or more quantum error corrections only when an implementation of an unflagged syndrome circuit is triggered. For example, the quantum error decoder is configured to receive a syndrome for the logical qubit generated, determined, and / or extracted using an unflagged syndrome circuit segment to determine one or more quantum error corrections for the logical qubit.

[0107] Continuing with FIG. 3 , in step / act 308, one or more respective quantum error corrections for one or more logical qubits are determined based on respective syndromes generated, determined, and / or extracted therefrom. For example, one or more syndromes generated, determined, and / or extracted from the logical qubits during the syndrome extraction step (e.g., step / act 306) are provided to a quantum error decoder operating on classical computation entity 10 and / or controller 30. The quantum error decoder is a program, application, etc. configured to determine one or more quantum error corrections for the logical qubits based on the one or more syndromes for the logical qubits. In certain exemplary embodiments, the quantum error decoder is embodied as one or more look-up tables. In various embodiments, the quantum error decoder is configured to determine one or more quantum error corrections based on the one or more syndromes in real time, or near real time, with respect to receiving the one or more syndromes as input.

[0108] In various embodiments, in various scenarios, the determined quantum error correction is an identity operation. For example, when no error is detected and / or when one or more syndromes for a logical qubit do not indicate the presence of an error, the determined quantum error correction is to not make any adjustments or changes to the qubit. For example, the determined quantum error correction can be to apply a software correction that is equivalent to applying an identity operator to the classical qubit registry corresponding to the logical qubit.

[0109] In step / operation 310, a classical qubit registry (e.g., stored in memory 410 and / or memories 922, 924) is updated based on the extracted syndrome and / or the determined quantum error correction. For example, controller 30 may cause the extracted syndrome and / or the determined quantum error correction to be tracked (e.g., in classical memory). In an exemplary embodiment, the value of the syndrome (and flag, if important) and / or the determined quantum error correction are stored for the entire implementation of the quantum circuit. In an exemplary embodiment, the value of the syndrome and / or the determined quantum error correction are tracked for a certain time frame (e.g., for a set length of time, or for a certain number of logic gates, until a triggering event is identified and the corresponding error correction is applied, etc.).

[0110] In step / operation 312, one or more quantum error corrections for the logical qubit are applied to the logical qubit. For example, controller 30 controls the operation of various components of quantum processor 115 (e.g., voltage source 50, manipulation source 60, etc.) to cause the one or more quantum error corrections to be applied to the logical qubit. In various embodiments, the quantum error correction comprises a software correction applied by tracking quantum errors experienced by the logical qubit in a classical qubit registry corresponding to the logical qubit (e.g., stored in a memory of controller 30 and / or a memory of classical computation entity 10), physically applying the correction to one or more data qubits of the logical qubit (e.g., through one or more single-qubit and / or two-qubit gates applied to various data qubits of the logical qubit), and / or modifying a logical operation performed on one or more data qubits of the logical qubit based at least in part on the determined quantum error correction.

[0111] In various embodiments, the quantum error correction is not applied immediately after the quantum error correction is determined. For example, in various embodiments, the syndrome and quantum error correction are tracked (e.g., in memory 410 and / or memories 922, 924) for a period of time and / or until a triggering event is identified. For example, in one exemplary embodiment, the syndrome and / or quantum error correction are tracked in a classical qubit registry.

[0112] In an exemplary embodiment, the triggering event corresponds to a determination that a logic gate (e.g., in an exemplary embodiment, a non-Clifford gate) that does not commute with one or more of the quantum error corrections is to be implemented on a logical qubit. For example, it may be determined that the controller schedules and / or the quantum circuit directs the future implementation of a logic gate (e.g., in an exemplary embodiment, a non-Clifford gate) that does not commute with one or more of the quantum error corrections on the logical qubit. Once the triggering event is identified, any needed physical corrections may be scheduled (prior to the implementation of the gate that does not commute with the one or more quantum error corrections) and / or the implementation of the gate that does not commute with the one or more quantum error corrections may be scheduled in a modified manner such that the implementation of the gate is modified to take into account and / or include one or more quantum error corrections.

[0113] As will be appreciated, some quantum error correction is an update of the classical representation of the Pauli frame of the qubit, applied to the logical qubit through an update to the classical qubit registry (e.g., software quantum error correction).

[0114] In various embodiments, the process of performing one or more logical operations on one or more logical qubits, performing syndrome generation / determination / extraction, determining quantum error correction, and applying quantum error correction is repeated multiple times until the logical operations of the quantum circuit are completed. For example, completing a quantum circuit may include preparing the states of physical qubits, performing a logical operation, performing a quantum error correction cycle, performing a logical operation, performing a quantum error correction cycle, performing a logical operation, performing a quantum error correction cycle, ..., and reading the logical qubits after all of the logical operations of the quantum circuit have been performed. As will be appreciated, in various embodiments, and in certain exemplary embodiments, state preparation of ancillary qubits is performed between each quantum error correction cycle and / or between performing quantum error correction cycles for different logical qubits.

[0115] Thus, once it is determined that all of the logical operations of the quantum circuit have been performed, the process continues to step / operation 314. In step / operation 314, one or more of the logical qubits are read out according to the quantum circuit. For example, the data qubits of a logical qubit may be transported (serial and / or parallel) to a respective readout zone (which may or may not be in the same physical part of confinement device 120 as interaction zone 128). According to the quantum circuit and readout, each data qubit may be rotated into a desired readout frame.

[0116] For example, a read operation may include incidenting an operation signal on a physical qubit (e.g., a data qubit). Depending on which state the physical qubit is in in two-state qubit space, the physical qubit either fluoresces or does not fluoresce in response to the operation signal being incident on it. Based on the fluorescence observed (or not observed) by light collection system 70, the quantum state of the physical qubit is determined. Based on the quantum states of the logical qubit's data qubit, the state of the logical qubit is determined. The state of the logical qubit is then used to determine the outcome of the quantum circuit.

[0117] In step / operation 316, in various embodiments, final syndrome extraction, final correction determination, and final correction application are performed. For example, the final syndrome of a logical qubit is determined based on the results of reading the logical qubit's data qubit. For example, the distribution of quantum states of the logical qubit's data qubit provides an indication of the error experienced by the logical qubit. The final syndrome of the logical qubit is then used (e.g., by a quantum error decoder) to determine the final correction. In various embodiments, the final correction is a software quantum error correction. For example, because the data qubit has been read, the quantum information stored by the data qubit is corrupted. Therefore, a physical correction cannot be applied. For example, in one exemplary embodiment, the final correction is a software correction, such as a Pauli frame rotation. The final correction is applied by updating the classical qubit registry corresponding to the logical qubit based on the final correction.

[0118] In step / act 318, after each final correction has been applied to each of the logical qubits, the output of the quantum circuit is provided. For example, controller 30 may provide the output of the quantum circuit to classical computational entity 10. In another example, classical computational entity 10 may provide an indication of the output of the quantum circuit via its user interface (e.g., display 916) and / or transmit an indication of the output of the quantum circuit to another computational entity (e.g., via transmitter 904 and / or network interface 920).

[0119] Exemplary Controller for a Quantum Computing System In various embodiments, quantum computer 110 comprises a quantum system controller 30 and a quantum processor 115. Quantum system controller 30 is configured to control various components of quantum processor 115. For example, controller 30 is configured to control the operation of the components of quantum processor 115 to cause the implementation of a quantum circuit that includes multiple quantum error correction cycles. For example, various embodiments are configured to implement one or more quantum error corrections on one or more data qubits in real time and / or near real time with respect to the occurrence of one or more quantum errors experienced by the one or more data qubits, which may be evaluated as a condition block.

[0120] In various embodiments, quantum system controller 30 is in communication with light collection system 70 such that it is configured to receive input data captured and / or generated by light collection system 70. Quantum system controller 30 is further configured to perform quantum error correction via software-based correction and / or via physical application of quantum error correction to one or more qubits (e.g., by control of one or more voltage sources 50 and / or manipulation sources 60). In various embodiments, quantum system controller 30 is further configured to control the cryostat system and / or vacuum system, which control the temperature and pressure within cryostat and / or vacuum chamber 40, the cooling system, and / or other systems that control environmental conditions (e.g., temperature, humidity, pressure, etc.) within cryostat and / or vacuum chamber 40.

[0121] As shown in FIG. 4 , in various embodiments, quantum system controller 30 may comprise various quantum system controller elements, including processing element 405, memory 410, driver controller element 415, communication interface 420, analog-to-digital (A / D) converter 425, etc. In various embodiments, quantum system controller 30 is configured to receive input data generated by the light collection system via A / D converter 425. In various embodiments, processing element 405 is configured to operate as described herein. In various embodiments, quantum system controller 30 may include additional quantum system controller elements configured to perform various functions described herein. In one exemplary embodiment, controller 30 is similar to the controller described in U.S. Application No. 63 / 235,022, filed August 19, 2021, the contents of which are incorporated herein by reference in their entirety.

[0122] In various embodiments, processing element 405 comprises one or more processing devices, such as a processor, a programmable logic device (CPLD), a microprocessor, a coprocessing entity, an application specific instruction set processor (ASIP), an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, other processing elements and / or circuits. The term circuit may refer to an entirely hardware embodiment or a combination of hardware and a computer program product. In one exemplary embodiment, processing element 405 of quantum system controller 30 comprises and / or is in communication with a clock.

[0123] In various embodiments, memory 410 comprises non-transitory memory such as volatile and / or non-volatile memory storage, such as one or more of a hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. In various embodiments, memory 410 may store queues of commands to be executed to invoke quantum algorithms and / or circuits to be executed (e.g., executable queues), qubit records corresponding to qubits of the quantum computer (e.g., in a qubit record data store, qubit record database, qubit record table, etc.), calibration tables, computer program code (e.g., code in one or more computer languages, a specialized quantum system controller language, etc.), etc. In an exemplary embodiment, execution (e.g., by processing element 405) of at least a portion of the computer program code stored in memory 410 causes quantum system controller 30 to perform one or more steps, operations, processes, procedures, etc. to generate one or more sets of commands configured to cause quantum processor 115 to implement at least a portion of a quantum circuit, update one or more qubit registries, etc. In an exemplary embodiment, execution of at least a portion of the computer program code stored in memory 410 causes quantum system controller 30 to perform the one or more commands. In various embodiments, the computational program code stored in memory 410 comprises quantum assembly (QASM) and / or quantum intermediate representation (QIR) code, and / or binary and / or machine code generated by compiling the QASM and / or QIR code.

[0124] In various embodiments, driver controller element 415 includes one or more drivers and / or a quantum system controller element each configured to control one or more drivers. In various embodiments, driver quantum system controller element 415 may comprise a driver and / or a driver controller. For example, a driver controller may be configured to cause one or more corresponding drivers to operate according to executable instructions, commands, etc., generated, scheduled, and executed by quantum system controller 30. For example, processing element 405 may generate one or more commands to be implemented by a first driver.

[0125] In various embodiments, driver controller element 415 enables quantum system controller 30 to operate voltage sources 50, manipulation sources 60, cooling systems, vacuum systems, etc. In various embodiments, a driver may be a laser driver (e.g., configured to operate and / or control one or more manipulation sources 60), a vacuum component driver, a driver for controlling the flow of current and / or voltage applied to electrodes used to maintain and / or control the trapping potential of confinement device 120 (e.g., configured to operate and / or control one or more voltage sources 50) (and / or other devices for providing sequences of driver activity to potential-generating elements of the confinement device), a cryostat and / or vacuum system component driver, a cooling system driver, etc.

[0126] Each driver controller element 415 corresponds to an endpoint in the system (e.g., a component of the operation source 60, a component of the voltage source 50 (e.g., a radio frequency voltage source, an arbitrary waveform generator (AWG), a direct digital synthesizer (DDS), and / or other waveform generators), a component of the cooling and / or vacuum system, a component of the light collection system 70, etc.). Each endpoint in the quantum computer 110 represents an individual hardware control device. In various embodiments, each endpoint has a unique set of accepted microcommands. Examples include, but are not limited to, the voltage source 50, such as a direct digital synthesizer (DDS), a component of the light collection system 70, such as a photomultiplier tube (PMT), a component of the operation source 60, such as a laser driver and / or optical modulator switch, and / or a general-purpose output (GPO). Individual commands for the DDS allow for setting the power level, frequency, and phase of the control signal generated thereby. In various embodiments, commands for the PMT interface include start / stop photon counting and reset counting. Commands for a GPO endpoint include setting and / or clearing one or more output lines, which can be used to control external hardware in a manner synchronous with quantum circuit execution.

[0127] In various embodiments, quantum system controller 30 comprises means for communicating and / or receiving signals from one or more optical receiver components (e.g., of light collection system 70). For example, quantum system controller 30 may comprise one or more analog-to-digital (A / D) converters 425 configured to receive signals from one or more optical receiver components (e.g., photodetectors of light collection system 70), calibration sensors, etc. In various embodiments, A / D converter 425 is configured to write input data to memory 410 generated by converting received signals generated by one or more optical receiver components of light collection system 70.

[0128] In various embodiments, quantum system controller 30 may comprise a communications interface 420, for example, for interfacing with and / or communicating with classical computational entity 10. For example, quantum system controller 30 may comprise a communications interface 420 for receiving executable instructions, command sets, etc. from computational entity 10, and for providing to computational entity 10 outputs received from quantum computer 110 (e.g., from light collection system 70) and / or results of processing the outputs. In various embodiments, computational entity 10 and quantum system controller 30 may communicate via direct wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0129] Exemplary Operation of a Controller for a Quantum Computing System 5 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by controller 30, for example, to perform a quantum error correction cycle, according to various embodiments. For example, in various embodiments, the processes, operations, and / or procedures illustrated in FIG. 5 are performed at various times during implementation of the quantum circuit.

[0130] Beginning at step / operation 502, controller 30 causes the execution of one or more syndrome circuit segments to determine one or more respective syndromes for one or more logical qubits. For example, controller 30 comprises means, such as processing element 405, memory 410, driver controller element 415, A / D converter 425, etc., for causing the execution of one or more syndrome circuit segments to determine one or more respective syndromes for one or more logical qubits.

[0131] For example, quantum computing system 100 may implement a quantum circuit comprising hundreds to hundreds, or thousands to thousands, of logical qubits. Each logical qubit comprises a plurality of data qubits, each embodied as a respective manipulable object that is physically transportable within confinement device 120. For example, the physical qubits (data qubits and ancillary qubits) of quantum computing system 100 may be physically transportable within confinement device 120 such that any selected pair of physical qubits may be transported to the same interaction zone and interact with each other (e.g., have a two-qubit gate performed thereon). In other words, quantum processor 115 has a reconfigurable physical qubit register. This feature of quantum computing system 100 is referred to herein as all-to-all connectivity. In various embodiments, controller 30 causes syndrome circuit segments to be implemented, at least in part, by triggering a series of transport operations and the performance of interactions of at least two physical qubits. Each transport operation in the series of transport operations and interactions of the at least two physical qubits causes physical transport of at least one of (a) the respective data qubit of the logical qubit and (b) the respective auxiliary qubit to their respective interaction zones defined by quantum processor 115, such that the respective data qubit or the respective auxiliary qubit is disposed within the respective interaction zones defined by quantum processor 115, and the interaction of the respective at least two physical qubits is performed therein (e.g., by causing appropriate operation signals to be incident on the data qubit and / or the auxiliary qubit within the interaction zone, as the case may be).

[0132] Specifically, interactions between the data qubits and the ancillary qubits are configured to not corrupt the quantum information stored by the data qubits, but to encode information corresponding to the data qubits (and / or the data qubits of the logical qubit as a whole) into the quantum states of the ancillary qubits. For example, the syndrome circuit segment may include implementations of one or more two-qubit gates called controlled-NOT (CNOT) gates for each data qubit and ancillary qubit.

[0133] In various embodiments, a syndrome circuit segment terminates with a read of one or more ancillary qubits used in the syndrome circuit segment. For example, the quantum states of one or more ancillary qubits used to implement the syndrome circuit segment may be read and / or determined. Controller 30 receives signals from light collection system 70 indicative of the results of reading one or more ancillary qubits used to implement the syndrome circuit segment. Based on the received signals, in one exemplary embodiment, controller 30 determines one or more syndromes for the respective logical qubits. In another embodiment, controller 30 provides an indication of the respective quantum states of one or more ancillary qubits used to implement the syndrome circuit segment to classical computation entity 10, which determines one or more syndromes for the respective logical qubits. In one exemplary embodiment, the syndrome is a set of binary values ​​(e.g., binary values ​​read from one or more ancillary qubits), a function of the values ​​read from one or more ancillary qubits, etc.

[0134] In various embodiments, the syndrome determined for each logical qubit by implementation of the syndrome circuit segment is compared to a previously known value of the syndrome. For example, the syndrome determined for each logical qubit may be compared to the initial value (e.g., the ready state) of the ancillary qubit for the first quantum error correction cycle of the quantum circuit. For example, the syndrome determined for each logical qubit may be compared to a previously determined value of the syndrome for the respective logical qubit. For example, it may be determined whether the value of the syndrome has changed since the last time the value of the syndrome was determined.

[0135] For example, in an exemplary embodiment, in step / operation 504, controller 30 determines whether the value of the syndrome determined for each logical qubit through implementation of the syndrome circuit segments in step / operation 502 has changed (e.g., from a (most recently) known value). In an exemplary embodiment, controller 30 may cause classical computation entity 10 to determine whether the value of the syndrome determined for each logical qubit through implementation of the syndrome circuit segments has changed. For example, providing classical computation entity 10 with the syndrome and / or information from which the syndrome can be determined may prompt classical computation entity 10 to determine whether the value of the syndrome for each logical qubit has changed.

[0136] For example, controller 30 and / or classical computation entity 10 store (e.g., in memory 410 and / or memories 922, 924) a classical qubit registry that includes information corresponding to each logical qubit. The classical qubit registry is referred to herein as being “classical” because it is a data structure stored by a classical (e.g., semiconductor-based) memory, and to distinguish the classical qubit registry (stored in memory 410 and / or memories 922, 924) from a physical qubit register. For example, the classical qubit registry corresponding to each logical qubit may include information identifying the data qubits that make up each logical qubit, the organization of the data qubits that make up each logical qubit, one or more previously determined syndrome values ​​for each logical qubit, one or more software corrections (e.g., Pauli frame rotations, etc.) to be applied to each logical qubit, tracking of quantum error corrections to be physically performed on each logical qubit at some future point in time, etc. Controller 30 and / or classical computation entity 10 compares the determined syndrome for each logical quantum bit with the syndrome value for each logical quantum bit stored in the classical quantum bit registry corresponding to each logical quantum bit to determine whether the value of the syndrome has changed.

[0137] In various embodiments, controller 30 comprises means, such as processing element 405, memory 410, communication interface 420, for determining whether the syndrome for each logical quantum bit has changed and / or for causing a determination of whether the syndrome for each logical quantum bit has changed.

[0138] In an exemplary embodiment, when the syndrome for the respective logical qubit is determined to be unchanged in step / operation 504 (and / or in response to determining in step / operation 504), it is determined that the quantum error correction cycle for the respective logical qubit is complete. For example, in an exemplary embodiment, when the syndrome for the respective logical qubit is determined to be unchanged, it is determined that quantum error correction for the respective logical qubit does not need to be determined and / or applied.

[0139] In an exemplary embodiment, when it is determined in step / act 504 that the syndrome for the respective logical qubit has changed (and / or in response to determining in step / act 504), the process continues to step / act 506.

[0140] In step / operation 506, controller 30 determines and / or causes the determination of one or more quantum error corrections for each logical qubit based at least in part on the syndrome for each logical qubit generated, determined, and / or extracted in step / operation 502. For example, controller 30 may operate, or cause classical computation entity 10 to operate, the quantum error decoder to determine one or more quantum error corrections for each logical qubit. The one or more quantum error corrections may be determined based on the value of the syndrome for each logical qubit, changes to the syndrome for each logical qubit, etc. In various embodiments, the quantum error decoder is configured to determine the one or more quantum error corrections based on the one or more syndromes in real time or near real time with respect to receiving the one or more syndromes as input. In one exemplary embodiment, the quantum error decoder is embodied as one or more look-up tables.

[0141] For example, controller 30 includes means, such as processing element 405, memory 410, communication interface 420, etc., for determining and / or causing the determination of one or more quantum error corrections for each logical quantum bit based at least in part on the syndrome for the respective logical quantum bit.

[0142] In various embodiments, controller 30 is configured to invoke one or more classical programs, modules, operations, functions, etc. (e.g., operating on classical computational entity 10). For example, controller 30 may use a foreign function interface (FFI) to invoke a quantum error decoder (e.g., operating on classical computational entity 10) and one or more syndromes for each logical qubit to the quantum error decoder. In response, the controller may receive one or more quantum error corrections for each logical qubit (e.g., via an FFI response or FFI call).

[0143] In step / operation 508, controller 30 causes one or more quantum error corrections to be applied to the logical qubits. For example, controller 30 includes means, such as processing element 405, memory 410, driver controller element 415, communications interface 420, etc., for causing one or more quantum error corrections to be applied to the logical qubits. In various embodiments, the quantum error corrections are applied to the quantum error corrections and / or quantum circuits, as appropriate, prior to further implementation of the quantum circuit and / or are tracked to be applied at a later point during implementation of the quantum circuit. In various embodiments, the one or more quantum error corrections to be applied to the logical qubits include a first quantum error correction to be performed on a first subset of the data qubits of the logical qubits, a second quantum error correction to be performed on a second subset of the data qubits of the logical qubits, etc. In an example embodiment, the first subset of data qubits and the second subset of data qubits do not overlap (e.g., these two subsets have an empty intersection), and the first quantum error correction is different from the second quantum error correction.

[0144] For example, in step / operation 508A, controller 30 applies and / or causes the application of software quantum error correction. For example, the classical qubit registry corresponding to each logical qubit (stored in memory 410 and / or memories 922, 924) may be updated. For example, one or more Pauli frame rotations may be added to and / or applied to the classical qubit registry corresponding to each logical qubit and / or element thereof.

[0145] For example, in step / operation 508B, controller 30 physically applies one or more quantum error corrections to one or more data qubits of each logical qubit. For example, one or more single-qubit or two-qubit gates may be implemented on one or more data qubits of each logical qubit. For example, one or more data qubits may be transported to respective interaction zones and have an interaction implemented thereon (e.g., through application of appropriate manipulation signals) to cause one or more quantum error corrections to be applied to the one or more data qubits. In various embodiments, the transport and interaction operations of physically applying quantum error corrections to one or more data qubits are implemented in parallel, serially, and / or combinations thereof. For example, the physical application of quantum error corrections may cause a rotation of one or more data qubits of each logical qubit, a modification of the phase of each quantum state of one or more data qubits of each logical qubit, etc.

[0146] For example, in step / operation 508C, controller 30 modifies one or more logical operations to be performed on each logical qubit based at least in part on the determined quantum error correction. For example, controller 30 may cause a single-qubit gate or a two-qubit gate to be performed on each logical qubit (and / or its one or more data qubits) to be rotated with respect to the reference frame of the respective logical qubit (and / or its one or more data qubits).

[0147] 6 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by controller 30, for example, to determine the syndrome of a logical qubit, according to various embodiments. For example, in an exemplary embodiment, the processes, operations, and / or procedures of FIG. 6 may be performed as part of step / operation 502.

[0148] Beginning at step / operation 602, controller 30 causes a state preparation operation to be performed on one or more ancillary qubits. For example, performing a state preparation operation on the ancillary qubits causes the quantum states of the ancillary qubits to become known (e.g., a particular state in two-state qubit space). For example, controller 30 may control the operation of one or more voltage sources 50, manipulation sources 60, etc. to position one or more ancillary qubits at appropriate positions in confinement device 120 such that one or more manipulation signals are incident on each of the one or more ancillary qubits such that the quantum states of each of the one or more ancillary qubits become known.

[0149] In various embodiments, one or more ancillary qubits may be used to generate, determine, and / or extract syndromes from a plurality of logical qubits. For example, in one exemplary embodiment, an ancillary qubit is used to implement a syndrome circuit segment for two or more logical qubits of the plurality of logical qubits. In such an embodiment, previous syndrome values ​​are stored in a classical qubit registry (stored in memory 410 or memories 922, 924), and the ancillary qubits can be reinitialized and used again through performance of a state preparation operation. This reduces the overall number of physical qubits required to implement a quantum circuit, since each logical qubit does not need to have a dedicated ancillary qubit. In various embodiments, this technical improvement is enabled, at least in part, by the all-to-all connectivity of the physical qubits.

[0150] In step / operation 604, controller 30 causes a series of transport operations and an interaction of at least two physical qubits to be performed in accordance with the syndrome circuit segment. In various embodiments, the particular series of transport operations and the interaction of at least two physical qubits is controlled by the positions of each of the physical qubits in quantum processor 115 at the time the syndrome circuit segment is initiated and the specific interaction required by the syndrome circuit segment. In various embodiments, the interaction of at least two physical qubits can be an interaction of two or more ancillary qubits, an interaction of two or more data qubits, an interaction of at least one ancillary qubit and at least one data qubit, etc., in accordance with the quantum circuit and / or syndrome circuit segment.

[0151] Each transport operation and interaction of the at least two physical qubits in the series of transport operations causes physical transport of at least one of (a) a respective data qubit of the logical qubit or a respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that the respective data qubit and (b) respective ancillary qubit are disposed within the respective interaction zones defined by the quantum processor. The interaction of the at least two physical qubits in each of the series of transport operations and interactions of the at least two physical qubits causes a non-invasive transfer of information regarding the quantum state of the data qubit to the ancillary qubit (e.g., such that the quantum information stored by the data qubit is not corrupted).

[0152] In one exemplary embodiment, ancillary qubits are maintained within respective interaction zones, and data qubits are transported into and out of the interaction zones to enable interaction of at least two physical qubits of the syndrome circuit segments.

[0153] In step / operation 606, one or more ancillary qubits are read out. For example, a data qubit of a logical qubit may be transported out of the interaction zone containing the ancillary qubits, and / or the ancillary qubits may be moved to a readout zone defined by quantum processor 115. Controller 30 then controls the operation of one or more manipulation sources 60 to cause one or more appropriate manipulation signals to be incident on each of the ancillary qubits. Controller 30 then controls the operation of light collection system 70 to observe any fluorescence emitted by the ancillary qubits, so that the quantum states of each of the ancillary qubits may be determined.

[0154] In step / operation 608, the syndrome of each logical qubit is determined based on the quantum states determined for the ancillary qubits through the read operation. For example, controller 30 determines the quantum state of each ancillary qubit based on signals received from elements of light collection system 70 corresponding to the position of the respective ancillary qubit. For example, if a photodetector configured to monitor the position of a first ancillary qubit observes significant fluorescence during a read operation of the first ancillary qubit, the first ancillary qubit is determined to be in a first state of the two-state qubit space. If a photodetector configured to monitor the position of a second ancillary qubit does not observe significant fluorescence during a read operation of the second ancillary qubit, the second ancillary qubit is determined to be in a second state of the two-state qubit space. In one exemplary embodiment, the syndrome of each logical qubit depends on one or more quantum states of the ancillary qubits. Thus, controller 30 determines the syndrome for each logical qubit based on the determined quantum states of each of the ancillary qubits.

[0155] In an exemplary embodiment, a syndrome circuit segment is performed more than once to determine whether the syndromes generated, determined, and / or extracted through multiple instances of the syndrome circuit segment are the same and / or to determine a representative syndrome based on multiple instances of performing the syndrome circuit segment. For example, in an exemplary embodiment, steps / operations 602-606 are performed multiple times, and step / operation 608 includes processing and / or analyzing the distribution of syndromes generated, determined, and / or extracted through multiple instances of performing steps / operations 602-606 to determine a respective syndrome for each logical qubit. For example, a first syndrome circuit segment may be performed multiple times, and the distribution of generated, determined, and / or extracted syndromes may be analyzed and / or processed to determine a representative syndrome corresponding to the first syndrome circuit segment to be used in determining quantum error corrections for the respective logical qubits, to be used to update the classical qubit registry for the respective logical qubits, etc. For example, by repeating the first syndrome circuit segment multiple times, uncertainties in a measurement, an interaction of at least two physical qubits, a read operation, etc. may be "averaged out."

[0156] In an exemplary embodiment, one or more syndromes generated, determined, and / or extracted from each logical quantum bit through implementation of a syndrome circuit segment are distinct from the corresponding one or more syndromes stored in a classical quantum bit registry corresponding to each logical quantum bit (e.g., stored in memory 410 and / or memories 922, 924), and the classical quantum bit registry is updated to reflect and / or include the most recently determined (representative) syndrome.

[0157] In various embodiments, several syndrome circuit segments are implemented to generate, determine, and / or extract multiple syndromes for each logical quantum bit. For example, different syndrome circuit segments are configured to identify and / or characterize different quantum errors that each logical quantum bit may experience. In various embodiments, controller 30 is programmed to be capable of implementing each of a defined set of syndrome circuit segments. In an exemplary embodiment, each of the syndrome circuit segments of the defined set of syndrome circuit segments is implemented during each quantum error correction cycle. In an exemplary embodiment, a first plurality of syndrome circuit segments are implemented, and based on the results, controller 30 determines whether (and possibly which) additional syndrome circuit segments of the defined set of syndrome circuit segments need to be implemented.

[0158] 7 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by controller 30, possibly in conjunction with classical computation entity 10, to determine syndromes for one or more logical qubits, for example, where results of a first plurality of syndrome circuit segments are used to determine whether and / or which second plurality of syndrome circuit segments should be performed. In an exemplary embodiment, the processes, operations, and / or procedures of FIG. 7 are performed as part of step / operation 502.

[0159] Beginning at step / operation 702, a first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments. In an exemplary embodiment, controller 30 and / or classical computation entity 10 select the first plurality of syndrome circuit segments from the defined set of syndrome circuit segments randomly and / or based on a stochastic process. In an exemplary embodiment, controller 30 and / or classical computation entity 10 selects the first plurality of syndrome circuit segments from the defined set of syndrome circuit segments based at least in part on one or more syndromes previously generated, determined, and / or extracted from a respective logical qubit or another logical qubit used in the implementation of the quantum circuit. For example, controller 30 and / or classical computation entity 10 selects the first plurality of syndrome circuit segments from the defined set of syndrome circuit segments based at least in part on errors previously observed and / or expected to be present in the implementation of the quantum circuit. In an exemplary embodiment, the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments prior to the start of implementation of the quantum circuit based on quantum errors identified in a previous implementation of the quantum circuit, user input, etc.

[0160] In step / operation 704, controller 30 causes the implementation of the first plurality of syndrome circuit segments. For example, controller 30 controls the operation of various elements of quantum processor 115 to cause the first plurality of syndrome circuit segments to be implemented such that respective syndromes are generated, determined, and / or extracted from respective logical qubits. For example, a process similar to that described with respect to FIG. 6 may be performed for each syndrome circuit segment of the first plurality of syndrome circuit segments.

[0161] In step / operation 706, the results of the first plurality of syndrome circuit segments are processed and / or analyzed by controller 30 and / or classical computation entity 10. For example, a distribution of syndromes, a distribution of syndrome changes, etc. may be determined and processed. For example, in an exemplary embodiment, the results of the first plurality of syndrome circuit segments are processed using probabilistic techniques to determine and / or predict whether all, most, and / or dominant errors experienced by each logical qubit have been captured and / or characterized through implementation of the first plurality of syndrome circuit segments.

[0162] In step / operation 708, based on the results of processing and / or analyzing the results of the first plurality of syndrome circuit segments, controller 30 and / or classical computation entity 10 determines whether the syndrome extraction process of the quantum error cycle is complete. For example, when the results of processing and / or analyzing the results of the first plurality of syndrome circuit segments indicate that all, most, and / or dominant errors experienced by each logical qubit have been captured and / or characterized through implementation of the first plurality of syndrome circuit segments, the syndrome extraction process of the quantum error cycle is determined to be complete. For example, when the results of processing and / or analyzing the results of the first plurality of syndrome circuit segments indicate that some, most, and / or dominant errors experienced by each logical qubit have not been captured and / or characterized through implementation of the first plurality of syndrome circuit segments, the syndrome extraction process of the quantum error cycle is determined to be incomplete, and the process continues at step / operation 710.

[0163] In another example, the syndrome extraction process for a quantum error cycle is determined to be complete when it is determined that a sufficient amount of information has been extracted from one or more logical qubits such that a quantum error decoder operating on classical computation entity 10 can determine an appropriate quantum error correction for the logical qubit. For example, when it is determined that there is not a sufficient amount of information for a quantum error decoder operating on classical computation entity 10 to confidently determine an appropriate quantum error correction for the logical qubit, it is determined that the syndrome extraction process for a quantum error cycle is not complete, and the process continues at step / action 710.

[0164] In step / operation 710, a second plurality of syndrome circuit segments is selected from the defined set of syndrome circuit segments. In an exemplary embodiment, controller 30 and / or classical computation entity 10 selects the second plurality of syndrome circuit segments from the defined set of syndrome circuit segments randomly and / or based on a stochastic process. In an exemplary embodiment, controller 30 and / or classical computation entity 10 selects the second plurality of syndrome circuit segments from the defined set of syndrome circuit segments based at least in part on the results of implementing the first plurality of syndrome circuit segments. For example, controller 30 and / or classical computation entity 10 selects the second plurality of syndrome circuit segments from the defined set of syndrome circuit segments based at least in part on errors already observed and / or expected to be present in the quantum circuit implementation, additional information needed for the quantum error decoder to confidently determine appropriate quantum error correction, etc. In certain exemplary embodiments, the second plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments prior to the start of implementation of the quantum circuit based on quantum errors identified in a previous implementation of the quantum circuit, user input, etc. In various embodiments, there may be overlap between the first plurality of syndrome circuit segments and the second plurality of syndrome circuit segments. In certain exemplary embodiments, the first plurality of syndrome circuit segments do not overlap with the second plurality of syndrome circuit segments.

[0165] At step / operation 712, controller 30 causes the implementation of the second plurality of syndrome circuit segments. For example, controller 30 controls the operation of various elements of quantum processor 115 to cause the second plurality of syndrome circuit segments to be implemented such that respective syndromes are generated, determined, and / or extracted from respective logical qubits. For example, a process similar to that described with respect to FIG. 6 may be performed for each syndrome circuit segment of the second plurality of syndrome circuit segments.

[0166] In step / operation 714, the results of the second plurality of syndrome circuit segments are processed and / or analyzed by controller 30 and / or classical computation entity 10. For example, a syndrome distribution, a syndrome change distribution, etc. may be determined and processed. For example, in an exemplary embodiment, the results of the second plurality of syndrome circuit segments are processed using probabilistic techniques to determine and / or predict whether all, most, and / or dominant errors experienced by each logical qubit have been captured and / or characterized through implementation of the first and second plurality of syndrome circuit segments. In an exemplary embodiment, controller 30 and / or classical computation entity 10 may determine whether a third plurality of syndrome circuit segments should be implemented. In an exemplary embodiment, the syndrome extraction of a quantum error correction cycle is determined to be complete once implementation of the second plurality of syndrome circuit segments is complete.

[0167] In various embodiments, the defined set of syndrome circuit segments includes flagged syndrome circuit segments and unflagged syndrome circuit segments. The flagged syndrome circuit segments use an ancillary qubit as a flag qubit (or one or more ancillary qubits as flag qubits). The value of the flag qubit is configured to indicate the presence or absence of one or more particular types of errors in the quantum circuit and / or the respective logical qubit. In various embodiments, the flagged syndrome circuit segments are configured to determine a specific syndrome for the respective logical qubit using fewer ancillary qubits than the corresponding conventional and / or unflagged syndrome circuit segments. In one exemplary embodiment, the flag qubit is configured to indicate when an error occurs during implementation of the syndrome circuit segment.

[0168] 8 is a flowchart illustrating various processes, operations, and / or procedures that may be performed by controller 30 to determine the syndrome of a logical qubit, e.g., using a combination of flagged and unflagged syndrome circuit segments, according to various embodiments. For example, flagged syndrome circuit segments may be used to identify the presence (and / or absence) of a Hook error, where an interaction between an ancillary qubit and a data qubit is causing the propagation of a logical error. For example, in an exemplary embodiment, the process, operations, and / or procedures of FIG. 8 may be performed as part of step / operation 502.

[0169] Beginning at step / operation 802, controller 30 causes a first flagged syndrome circuit segment to be implemented. For example, controller 30 controls operation of various elements of quantum processor 115 to cause the first flagged syndrome circuit segment to be implemented such that a first flagged syndrome is generated, determined, and / or extracted from a respective logical qubit. For example, a first set of flag qubit values ​​is determined through the implementation of the first flagged syndrome circuit segment. For example, a process similar to that described with respect to FIG. 6 may be implemented to cause the implementation of the first flagged syndrome circuit segment.

[0170] In various embodiments, the first flagged syndrome circuit segment examines a first set of aspects of each logical qubit. For example, the first flagged syndrome circuit segment examines a first set of stabilizers. For example, when stabilizer codes are used to implement fault-tolerant quantum error correction, a commutative set of operators called stabilizers is measured and / or used to detect errors experienced by each logical qubit. The stabilizer measurements form error syndromes that can be processed using a quantum error decoder to determine one or more quantum error corrections. Thus, in one exemplary embodiment, the first flagged syndrome circuit segment is configured to examine these first set of stabilizers.

[0171] In step / operation 804, a first set of flag qubit values ​​(e.g., a set of values ​​indicating each quantum state of an ancillary qubit used as a flag qubit in the first flagged syndrome circuit segment) is compared to a previous first set of flag qubit values ​​stored in a classical qubit registry corresponding to each logical qubit. For example, controller 30 and / or classical computation entity 10 compare the determined first set of flag qubit values ​​with the first set of flag qubit values ​​stored in the classical qubit registry to determine whether the first set of flag qubit values ​​has changed from the (immediately) previously determined first set of flag qubit values.

[0172] When the determined first set of flag qubit values ​​and the first set of flag qubit values ​​stored in the classical qubit registry are the same, the corresponding syndrome is unchanged. When the determined first set of flag qubit values ​​and the first set of flag qubit values ​​stored in the classical qubit registry are not the same, the corresponding syndrome is changing.

[0173] When it is determined in step / operation 804 (and / or in response to determining) that the first set of flag qubit values ​​has changed from the (immediately) previously determined first set of flag qubit values, the process continues to step / operation 810. When it is determined in step / operation 804 (and / or in response to determining) that the first set of flag qubit values ​​has not changed from the (immediately) previously determined first set of flag qubit values, the process continues to step / operation 806.

[0174] In step / operation 806, controller 30 causes the implementation of a second flagged syndrome circuit segment. For example, controller 30 controls the operation of various elements of quantum processor 115 to cause the second flagged syndrome circuit segment to be implemented so that a second flagged syndrome is generated, determined, and / or extracted from each logical qubit. For example, a second set of flag qubit values ​​is determined through the implementation of the second flagged syndrome circuit segment. For example, a process similar to that described with respect to FIG. 6 may be performed to cause the implementation of the second flagged syndrome circuit segment.

[0175] In various embodiments, the second flagged syndrome circuit segment examines a second set of aspects of the respective logical qubits. For example, the second flagged syndrome circuit segment examines a second set of stabilizers. For example, in one exemplary embodiment, the second flagged syndrome circuit segment is configured to examine the second set of stabilizers. In various embodiments, the first set of stabilizers and the second set of stabilizers do not overlap. In one exemplary embodiment, the first set of stabilizers and the second set of stabilizers are orthogonal to each other and / or examine orthogonal frames of the respective logical qubits.

[0176] In step / operation 808, the second set of flag qubit values ​​(e.g., values ​​indicative of the quantum state of the ancillary qubit used as the flag qubit in the second flagged syndrome circuit segment) are compared to a previous second set of flag qubit values ​​stored in a classical qubit registry corresponding to the respective logical qubit. For example, controller 30 and / or classical computation entity 10 compare the determined second set of flag qubit values ​​with the second set of flag qubit values ​​stored in the classical qubit registry to determine whether the second set of flag qubit values ​​has changed from the (most recently) determined second set of flag qubit values.

[0177] When the determined second set of flag qubit values ​​and the second set of flag qubit values ​​stored in the classical qubit registry are the same, the corresponding syndrome has not changed. When the determined second set of flag qubit values ​​and the second set of flag qubit values ​​stored in the classical qubit registry are not the same, the corresponding syndrome has changed.

[0178] When it is determined in step / operation 808 (and / or in response to determining) that the second set of flag qubit values ​​has changed from the (immediately) previously determined second set of flag qubit values, the process continues to step / operation 810. When it is determined in step / operation 808 (and / or in response to determining) that the second set of flag qubit values ​​has not changed from the (immediately) previously determined second set of flag qubit values, the quantum error correction cycle for the respective qubit is determined to be complete. For example, it may be determined that because the first set of flag qubit values ​​has not changed and the second set of flag qubit values ​​has not changed from their respective previously determined values ​​stored in the classical qubit registry, no new quantum error correction needs to be determined and applied.

[0179] In step / operation 810, controller 30 causes the execution of the unflagged syndrome circuit segments. In one exemplary embodiment, the unflagged syndrome circuit segments measure and / or determine values ​​corresponding to each ballast in the set of ballasts. For example, the result of the unflagged syndrome circuit segments is a syndrome set that includes a syndrome for each ballast in the set of ballasts. For example, a process similar to that described with respect to FIG. 6 may be performed to cause the execution of the unflagged syndrome circuit segments.

[0180] In step / operation 812, a classical qubit registry for each logical qubit (e.g., stored in memory 410 and / or memories 922, 924) is updated with the determined first and / or second sets of flag qubit values ​​and the determined syndrome. For example, the classical qubit registry for each logical qubit is updated based on the results of implementing the first flagged syndrome circuit segment, the second flagged syndrome circuit segment, and / or the unflagged syndrome circuit segment. For example, controller 30 and / or classical computation entity 10 update the classical qubit registry for each logical qubit based on the results of implementing the first flagged syndrome circuit segment, the second flagged syndrome circuit segment, and / or the unflagged syndrome circuit segment.

[0181] Exemplary Computational Entities 9 provides an illustrative schematic diagram depicting an exemplary classical computational entity 10 (also referred to herein as a computational entity) that may be used with embodiments of the present disclosure. In various embodiments, classical computational entity 10 is a classical (e.g., semiconductor-based) computer configured to allow a user to provide input to quantum computer 110 (e.g., via a user interface of computational entity 10) and receive, display, analyze, etc., output from quantum computer 110. In one exemplary embodiment, classical computational entity 10 is part of controller 30.

[0182] 9, classical computational entity 10 may include an antenna 912, a transmitter 904 (e.g., wireless), a receiver 906 (e.g., wireless), and a processing element 908 that provides signals to transmitter 904 and receives signals from receiver 906. The signals provided to transmitter 904 and received from receiver 906 may include information / data signaling in accordance with applicable wireless system air interface standards for communicating with various entities, such as quantum system controller 30, other computational entities 10, etc. Computational entity 10 may also include a network interface 920, which may provide signals and receive signals in accordance with applicable network system interface standards for communicating with various entities, such as quantum system controller 30, other computational entities 10, etc.

[0183] In this regard, computing entity 10 may be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. For example, computing entity 10 may be configured to receive and / or provide communications using a wired data transmission protocol, such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol.Similarly, the computing entity 10 may be configured to support general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High-Speed ​​Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), ultra-wideband It may be configured to communicate over a wireless external communications network using any of a variety of protocols, such as Ultra Wideband (UWB), infrared (IR) protocol, near field communication (NFC) protocol, Wibree, Bluetooth protocol, wireless universal serial bus (USB) protocol, and / or any other wireless protocol.Computing entity 10 may use such protocols and standards to communicate using Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), HyperText Markup Language (HTML), and the like.

[0184] Through these communication standards and protocols, computing entity 10 can communicate with various other entities using concepts such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identity Module Dialer (SIM Dialer), etc. Computing entity 10 can also download modifications, add-ons, and updates to its firmware, software (including, e.g., executable instructions, applications, program modules), and operating system, for example.

[0185] Computing entity 10 may also comprise user interface devices comprising one or more user input / output interfaces (e.g., a display 916 and / or speaker / speaker driver coupled to processing element 908, a touchscreen coupled to processing element 908, a keyboard, a mouse, and / or a microphone). For example, the user output interface may be configured to provide an application, browser, user interface, interface, dashboard, screen, webpage, page, and / or similar terms used interchangeably herein running on and / or accessible through computing entity 10 to cause a display or audible presentation of information / data and for interaction therewith via one or more user input interfaces. The user input interface may comprise any of several devices that enable computing entity 10 to receive data, such as a keypad 918 (hard or soft), a touch display, a voice / speech or motion interface, a scanner, reader, or other input device. In embodiments including a keypad 918, the keypad 918 may include (or cause the display of) conventional numeric keys (0-9) and related keys (#, *), as well as other keys used to operate the computing entity 10, or may include a full set of alphanumeric keys or a set of keys that can be actuated to provide a full set of alphanumeric keys. In addition to providing input, the user input interface may be used to enable or disable certain features, such as, for example, a screen saver and / or sleep mode. Through such input, the computing entity 10 may collect information / data, user interaction / input, etc.

[0186] Computational entity 10 may also include volatile storage or memory 922 and / or non-volatile storage or memory 924, which may be embedded and / or removable. For example, non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, etc. Volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, registered memory, etc. Volatile and non-volatile storage or memory may store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, etc. to implement the functionality of computational entity 10.

[0187] In various embodiments, classical computation entity 10 is configured to receive information from controller 30 (e.g., ancillary qubit values, data qubit and / or logical qubit values, syndromes corresponding to each logical qubit, etc.) and perform various operations based thereon. For example, classical computation entity 10 may receive ancillary qubit values ​​and determine one or more syndromes for one or more logical qubits. For example, classical computation entity 10 may operate a quantum error decoder and / or otherwise determine one or more quantum error corrections for one or more logical qubits based on the one or more respective syndromes for the one or more logical qubits. For example, classical computation entity 10 may determine one or more quantum error corrections for each logical qubit and provide (e.g., transmit) the quantum error corrections so that controller 30 can receive and trigger implementation of the quantum error corrections. In an exemplary embodiment, classical computation entity 10 stores and / or updates one or more qubit registries (e.g., in memories 922, 924) based on the one or more quantum error corrections.

[0188] Exemplary Operation of a Controller of a Quantum Computing System for Implementing Fault-Tolerant Logical Multi-Qubit Gates In various embodiments, quantum computer 110 is configured to implement a fault-tolerant logical multi-qubit gate. For example, controller 30 is configured to control quantum processor 115 to cause quantum processor 115 to implement a fault-tolerant logical multi-qubit gate (e.g., a logic gate implemented in a fault-tolerant manner for two or more logical qubits).

[0189] In various embodiments, the implementation of a logical multi-qubit gate comprises implementing a series of at least two physical qubit interactions between respective physical qubits of a set of physical qubits comprising a data qubit of the logical qubit on which the gate is implemented and one or more ancillary qubits. In various embodiments, the series of at least two physical qubit interactions is divided into two or more groups such that the logical multi-qubit gate is implemented in portions. Between successive portions, a multi-qubit quantum error correction cycle may be implemented. In various embodiments, the multi-qubit quantum error correction cycle is similar to the quantum error correction cycles described elsewhere herein.

[0190] In various embodiments, as a result of performing a multi-qubit quantum error correction cycle, the interaction of one or more of the at least two physical qubits of successive portions of the logical multi-qubit gate may be corrected based on the determined quantum error correction. In various embodiments, the one or more quantum error corrections are performed between performances of successive portions of the logical multi-qubit gate and / or after performance of the logical multi-qubit gate.

[0191] In various embodiments, the controller causes tracking of syndromes and / or quantum error corrections determined during multi-qubit quantum error correction cycles in the classical memory.

[0192] In various embodiments, implementing at least one of the groups of at least two-physical qubit interactions and / or at least one syndrome circuit segment of a multi-qubit quantum error correction cycle includes causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor.

[0193] FIG. 10 provides a flowchart illustrating various processes, procedures, operations, etc., performed by controller 30 to, for example, cause quantum processor 115 to perform a fault-tolerant logical multi-qubit gate for at least a first logical qubit and a second logical qubit.

[0194] Starting at step / operation 1002, the controller causes the quantum processor to implement a first portion of a logical multi-qubit gate. In various embodiments, causing the implementation of the first portion of the logical multi-qubit gate comprises causing the implementation of a first group of at least two physical qubit interactions for at least a first subset of physical qubits of a set of physical qubits. The set of physical qubits comprises a data qubit of a first logical qubit, a data qubit of a second logical qubit, and one or more ancillary qubits. The logical multi-qubit gate is implemented for at least the first logical qubit and the second logical qubit.

[0195] At step / action 1004, the controller causes the quantum processor to perform a multi-qubit quantum error correction cycle. In various embodiments, performing the multi-qubit quantum error correction cycle comprises implementing at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction. For example, the syndrome circuit segments may be implemented as described elsewhere herein to determine the respective syndromes, and the quantum error corrections may be determined based on the determined syndromes (e.g., using a quantum error decoder operating on classical computation entity 10).

[0196] In various embodiments, the multi-qubit quantum error correction cycle may result in the determination of one or more syndromes for the first logical qubit and / or one or more syndromes for the second logical qubit. In various embodiments, the multi-qubit quantum error correction cycle may result in the determination of one or more quantum error corrections for the first logical qubit and / or one or more quantum error corrections for the second logical qubit. In various embodiments, the multi-qubit quantum error correction cycle results in the determination of one or more syndromes that describe a combination of errors and corresponding quantum error corrections present in the first logical qubit and the second logical qubit. For example, the first logical qubit and the second logical qubit may be treated separately and / or independently during the multi-qubit quantum error correction cycle, or may be treated as a combined set of physical qubits during the multi-qubit quantum error correction cycle.

[0197] In step / operation 1006, the controller may cause the syndromes and / or quantum error corrections determined through multi-qubit quantum error correction cycles to be tracked in classical memory (e.g., memory 410 and / or memories 922, 924). As will be appreciated, tracking the syndromes and / or quantum error corrections may include applying software corrections to a classical qubit registry stored in classical memory (e.g., memory 410 and / or memories 922, 924).

[0198] In step / operation 1008, the controller causes one or more physical corrections to be made to one or more data qubits of the first logical qubit and / or the second logical qubit, and / or causes modification of one or more interactions of at least two physical qubits of the second portion (or third portion or other successive portion) of the logical multi-qubit gate based on the determined quantum error correction. For example, in an exemplary embodiment, at least one at least two-physical qubit interaction of the second group of at least two-physical qubit interactions is modified based at least in part on the at least one quantum error correction. For example, in an exemplary embodiment, a physical correction is made to at least one of the first logical qubit or the second logical qubit prior to performing the second group of interactions of the at least two physical qubits.

[0199] In step / action 1010, the controller causes the quantum processor to perform a second portion of the logical multi-qubit gate. For example, the controller causes the quantum processor to perform the second portion of the logical multi-qubit gate by causing the performance of a second group of interactions of at least two physical qubits on at least a second subset of physical qubits of the set of physical qubits.

[0200] In step / operation 1012, the controller causes a quantum error correction (e.g., determined during a multi-qubit quantum error correction cycle) to be performed on the first logical qubit and / or the second logical qubit. For example, in an exemplary embodiment, the controller causes at least one of: (a) a physical correction to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate based on the at least one quantum error correction; or (b) an operation to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical multi-qubit gate based at least in part on the at least one quantum error correction.

[0201] In various embodiments, performing at least one of the first group of at least two physical qubit interactions, the at least one syndrome circuit segment, or the second group of at least two physical qubit interactions comprises causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor to enable performing a respective at least two physical qubit interaction within each of the one or more interaction zones.

[0202] Technical Advantages Complex quantum computations require a level of precision not possible with conventional quantum computers due, for example, to imperfect control and noise in gate operations between data qubits. Proposed schemes for quantum error correction involve the extraction of syndromes, which generally involve the interaction of ancillary qubits with the data qubits of a logical qubit. However, if not carefully implemented, such interactions between ancillary qubits and data qubits can catastrophically propagate faults, leading to logical errors that would otherwise be correctable given the initial weights. Thus, technical problems exist regarding how to perform quantum computations with a level of precision sufficient to perform complex computations. Furthermore, technical problems exist regarding how to extract the information needed to diagnose and correct errors from the logical qubits without causing further propagation of the error.

[0203] Various embodiments provide technical solutions to such technical problems. For example, various embodiments realize the implementation of fault-tolerant quantum computation and / or fault-tolerant quantum error correction using physical transportation of physical qubits. For example, a syndrome may be generated, determined, and / or extracted from a logical qubit through the interaction of the data qubit of the logical qubit with an auxiliary qubit. The data qubit and / or the auxiliary qubit may be physically transported into and / or out of an interaction zone such that the auxiliary qubit may interact with multiple data qubits of the logical qubit. Additionally, the auxiliary qubit may be used to implement syndrome circuit segments for multiple logical qubits (in turn). Thus, various embodiments realize fault-tolerant quantum error correction with minimal and / or fewer auxiliary qubits. By minimizing and / or reducing the number of auxiliary qubits required, the number of physical qubits used can be reduced and / or more of the physical qubits of quantum processor 115 may be available as data qubits, allowing a larger number of logical qubits to be used. Additionally, in various embodiments, using flagged syndrome circuit segments to determine when or whether implementation of unflagged syndrome circuit segments is warranted allows for identification of when additional error propagation is occurring and allows for mitigation thereof. Thus, various embodiments provide an improvement over conventional quantum error correction schemes.

[0204] conclusion Many modifications and other embodiments of the inventions defined herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. It is to be understood, therefore, that the inventions are not to be limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense and not for purposes of limitation. [Explanation of symbols]

[0205] 10 Classical Computational Entities 20 Wired / Wireless Networks 30 Controllers 40 Cryostat / Vacuum Chamber 50 Voltage Source 60 Operation source 70 Optical Collection System 100 Quantum Computing System 110 Quantum Computer 115 Quantum Processor 120 Confinement Device 122 RF Rail 124 Control electrode 126 Control electrode 128 Interaction Zone 405 Processing Elements 410 memory 415 Driver Controller Elements 420 Communication Interface 425 A / D converter 904 Transmitter 906 Receiver 908 Processing Elements 912 Antenna 916 Display 918 keypad 920 network interface 922 Volatile Memory 924 Non-volatile Memory

Claims

1. 1. A method implemented by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor, the controller configured to (a) control operation of the quantum processor and (b) communicate with the classical computing entity, the method comprising: causing, by the controller, the performance of at least one syndrome circuit segment to generate a syndrome of a logical qubit, the at least one syndrome circuit segment being performed, at least in part, by causing the performance of a series of transport operations and interactions of at least two physical qubits, each transport operation and interaction of at least two physical qubits of the series of transport operations causing physical transport of at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancillary qubit is disposed within the respective interaction zone, and a respective interaction of at least two physical qubits is performed therein; determining, by the classical computational entity, at least one quantum error correction based at least in part on the syndrome of the logical qubit; and causing, by the controller, a classical memory of at least one of the controller or the classical computation entity to be updated based on at least one of the syndrome or the at least one quantum error correction.

2. 10. The method of claim 1, further comprising causing the controller to apply the at least one quantum error correction to the logical qubit.

3. causing the at least one quantum error correction to be applied to the logical qubit; updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction; causing a physical correction of the logical qubit to be implemented on one or more data qubits; or causing a logical operation to be performed at least in part on one or more data qubits of the logical qubits to be modified based at least in part on the at least one quantum error correction. The method of claim 2 , comprising at least one of:

4. 4. The method of claim 3, wherein causing the physical correction to be made to the one or more data qubits of the logical qubit comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported into at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

5. The method of claim 1 , wherein the at least one syndrome circuit segment implementation comprises a plurality of syndrome circuit segment implementations.

6. causing execution of the at least one syndrome circuit segment; causing implementation of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments being selected from a defined set of syndrome circuit segments using a stochastic selection process; determining whether to cause execution of a second plurality of syndrome circuit segments based at least in part on the results of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments being selected from the defined set of syndrome circuit segments; causing execution of the second plurality of syndrome circuit segments in response to determining to cause execution of the second plurality of syndrome circuit segments; and determining the at least one quantum error correction based at least in part on the respective results of the first plurality of syndrome circuit segments in response to determining not to cause execution of the second plurality of syndrome circuit segments.

7. 10. The method of claim 1, wherein the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

8. 10. The method of claim 1, wherein the at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as a flag qubit.

9. tracking the value of the flag qubit using at least one classical qubit registry; and causing execution of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

10. 10. The method of claim 1 , wherein updating the classical memory based on at least one of the syndrome or the at least one quantum error correction comprises tracking the syndrome of the logical qubit in the classical memory.

11. 10. The method of claim 1, wherein coherence of the respective data qubits of the logical qubits is maintained during execution of the at least one syndrome circuit segment.

12. causing execution of a state preparation circuit segment to prepare a state of the respective ancillary qubit before causing execution of the at least one syndrome circuit segment; and causing the respective ancillary qubit to be read out after the series of transport operations and the performing of the interaction of at least two physical qubits, wherein the syndrome of the logical qubit is generated based at least in part on a result of the reading of the respective ancillary qubit.

13. 1. A controller for a quantum computing system, the controller (a) configured to control operation of a quantum processor; and (b) comprising processing elements and a memory storing executable instructions, the executable instructions, when executed by the processing elements, causing the controller to perform at least: causing the performance of at least one syndrome circuit segment to generate a syndrome of a logical qubit, the at least one syndrome circuit segment being performed, at least in part, by causing the performance of a series of transport operations and interactions of at least two physical qubits, each transport operation and interaction of the at least two physical qubits in the series of transport operations causing physical transport of at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancillary qubit to a respective interaction zone defined by the quantum processor, such that at least one of (a) the respective data qubit of the logical qubit or (b) the respective ancillary qubit is disposed within the respective interaction zone, and a respective interaction of the at least two physical qubits is performed therein; causing at least one quantum error correction decision based at least in part on the syndrome of the logical qubit; a controller configured to cause a classical memory of at least one of the controller or the classical computation entity to be updated based on at least one of the syndrome or the at least one quantum error correction.

14. 14. The controller of claim 13, wherein the executable instructions, when executed by the processing element, are further configured to cause the controller to at least apply the at least one quantum error correction to the logical qubit.

15. causing the at least one quantum error correction to be applied to the logical qubit; updating a classical qubit registry corresponding to the logical qubit based on the at least one quantum error correction; causing a physical correction of the logical qubit to be implemented on one or more data qubits; or 14. The controller of claim 13, further comprising at least one of: causing a logical operation to be performed at least in part on one or more data qubits of the logical qubits to be modified based at least in part on the at least one quantum error correction.

16. 16. The controller of claim 15, wherein causing the physical correction of the logical qubit to be performed on the one or more data qubits comprises performing one or more transport operations on the one or more data qubits to cause the one or more data qubits to be transported into at least one of (a) into or (b) out of one or more interaction zones defined by the quantum processor.

17. causing execution of the at least one syndrome circuit segment; causing implementation of a first plurality of syndrome circuit segments, the first plurality of syndrome circuit segments selected from a defined set of syndrome circuit segments using a stochastic selection process; determining whether to cause execution of a second plurality of syndrome circuit segments based at least in part on the results of each of the first plurality of syndrome circuit segments, the second plurality of syndrome circuit segments being selected from the defined set of syndrome circuit segments; causing execution of the second plurality of syndrome circuit segments in response to determining to cause execution of the second plurality of syndrome circuit segments; and determining the at least one quantum error correction based at least in part on the respective results of the first plurality of syndrome circuit segments in response to determining not to cause execution of the second plurality of syndrome circuit segments.

18. 14. The controller of claim 13, wherein the logical qubit is one of a plurality of logical qubits, and the ancillary qubit is used to implement syndrome circuit segments for two or more logical qubits of the plurality of logical qubits.

19. the at least one syndrome circuit segment comprises a flagged syndrome circuit segment, a first ancillary qubit of two or more ancillary qubits used to implement the at least one syndrome circuit segment is used as a flag qubit, and the executable instructions, when executed by the processing element, further cause the controller to at least: using at least one classical qubit registry to track the value of the flag qubit; 14. The controller of claim 13, configured to cause execution of unflagged syndrome circuit segments in response to determining that the value of the flag qubit has changed.

20. The executable instructions further, when executed by the processing element, cause the controller to at least: causing execution of a state preparation circuit segment to prepare a state of each ancillary qubit before causing execution of the at least one syndrome circuit segment; 13. The controller of claim 12, configured to cause the respective ancillary qubit to be read out after the performing of the series of transport operations and the interaction of at least two physical qubits, and wherein the syndrome of the logical qubit is generated based at least in part on a result of the reading of the respective ancillary qubit.

21. 1. A method for implementing a logical multi-qubit gate, comprising: causing, by a controller configured to control operation of a quantum processor, the quantum processor to perform a first portion of the logical many-qubit gate by causing a first group of at least two-physical qubit interactions to be performed on at least a first subset of physical qubits of a set of physical qubits, the set of physical qubits comprising a first logical qubit data qubit, a second logical qubit data qubit, and one or more ancillary qubits, and the logical many-qubit gate being performed on at least the first logical qubit and the second logical qubit; causing, by the controller, the quantum processor to perform a multi-qubit quantum error correction cycle comprising implementing at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction; and causing, by the controller, the quantum processor to perform a second portion of the logical multi-qubit gate by causing a second group of at least two physical qubit interactions to be performed for at least a second subset of physical qubits of the set of physical qubits.

22. 22. The method of claim 21 , wherein at least one at least two-physical qubit interaction in the second group of at least two-physical qubit interactions is corrected based at least in part on the at least one quantum error correction.

23. 22. The method of claim 21 , further comprising at least one of: (a) causing a physical correction to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical many-qubit gate based on the at least one quantum error correction; or (b) causing an operation to be performed on at least one of the first logical qubit or the second logical qubit after completion of the logical many-qubit gate is corrected based at least in part on the at least one quantum error correction.

24. 22. The method of claim 21 , wherein a physical correction is performed on at least one of the first logical qubit or the second logical qubit prior to the performing of the second group of interactions of at least two physical qubits.

25. 22. The method of claim 21, further comprising causing tracking of at least one of the at least one syndrome or the at least one quantum error correction in a classical memory.

26. 22. The method of claim 21 , wherein performing at least one of the first group of interactions of at least two physical qubits, the at least one syndrome circuit segment, or the second group of interactions of at least two physical qubits comprises causing transport of one or more physical qubits of the set of physical qubits into or out of one or more interaction zones defined by the quantum processor.

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