Method and apparatus for reducing memory in NAND flash devices for storing page-related information

Abstract

Embedding a page type into a row address reduces the size of a page map memory in a NAND flash device for storing page-related information. The row address is received by the NAND flash device from a host on a data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during a row address cycle to obtain a word line in a NAND flash array and a block segment number for a block segment within the word line. The same block segment number is used for each page type within the block segment.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority under 35 U.S.C. 365(c) to U.S. Application No. 18 / 107,677, filed February 9, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to non-volatile memory devices, and more particularly to NAND flash memory devices. [Background technology]

[0003] Non-volatile memory refers to memory whose state is deterministic even when power to the device is interrupted. Storage devices that contain non-volatile memory include Secure Digital cards, multimedia cards, flash drives (e.g., Universal Serial Bus (USB) flash drives, also known as "USB thumb drives" or "USB memory sticks," which contain non-volatile memory with an integrated USB interface), and solid-state drives.

[0004] Non-volatile memory may include block addressable memory devices such as, for example, NAND, or more specifically, multi-threshold level NAND flash memory (e.g., single level cell ("SLC"), multi-level cell ("MLC"), tri-level cell ("TLC"), quad level cell ("QLC"), penta-level cell ("PLC") or other NAND).

[0005] NAND flash memory devices typically use one-transistor memory cells, which allows for high memory density, high reliability, and low power consumption. The memory cells are typically arranged in a memory array and are addressable in a row / column format. NAND flash cells use the threshold voltage of a floating-gate transistor to represent the data stored in the cell.

[0006] Three-dimensional (3D) NAND is a type of non-volatile flash memory that has multiple layers of memory cells stacked vertically, for example, 32, 48, 64 or more layers of cells can be stacked vertically.

[0007] In the course of the following detailed description, features of embodiments of the claimed subject matter will become apparent with reference to the drawings, in which like numerals represent like parts. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a 3D (three-dimensional) NAND flash device. [Figure 2] FIG. 2 is a block diagram of an array structure of a 3D (three-dimensional) NAND flash array in the 3D NAND flash device shown in FIG. 1. [Figure 3] FIG. 2 is a block diagram of a system including the 3D NAND flash device shown in FIG. 1. [Figure 4] 1 shows a six-cycle sequence used by a host to load an address of a 3D NAND flash array. [Figure 5] 10 is a table showing the mapping of page type bits transmitted on data pins DQ (DQ7:DQ5) to page types in a 3D NAND device during the fourth cycle. [Figure 6] 2 is an example of a word line / block segment table 152 shown in FIG. 1. [Figure 7] FIG. 10 is a timing diagram showing a six-cycle sequence used by a host to load addresses in a 3D NAND flash array. [Figure 8] FIG. 1 is a flow diagram of a method for loading addresses of a 3D NAND flash array. [Figure 9] FIG. 1 is a block diagram of a computer system including a 3D NAND device. DETAILED DESCRIPTION OF THE INVENTION

[0009] While the claimed subject matter will be described in detail below with reference to illustrative embodiments thereof, various alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be broadly construed and defined as set forth in the appended claims.

[0010] A 3D NAND device includes a 3D NAND flash array containing multiple NAND cells organized in rows and columns. The 3D NAND device does not have dedicated address pins. Addresses (row address and column address) are loaded by a host via data pins on the 3D NAND device in a six-cycle sequence. The column address is received by the 3D NAND flash on the data pins in the first and second cycles of the six-cycle sequence. The row address is received by the 3D NAND flash during the row address cycle on the data pins in the third, fourth, fifth, and sixth cycles of the six-cycle sequence. The row address includes a page address, a block address, and a logical unit (LUN) address.

[0011] The host sequentially follows the page number order defined in the page map. The row address is used by the 3D NAND device to decode the word lines, segments within a block (block segments), word line types, and word line groups stored in the page map in the static random access memory (SRAM) in the 3D NAND flash array. The word line type may be single-level cell ("SLC"), multi-level cell ("MLC"), tri-level cell ("TLC"), quad-level cell ("QLC"), or penta-level cell ("PLC"), and may differ depending on the native word line and edge word line. For example, in a 3D NAND device whose native word line type is QLC, the edge word line type may be SLC. Each block in the 3D NAND flash array contains pages. Groups of pages exist in subsegments, which may be called block segments. The block segments and word lines are used to access memory locations in the 3D NAND flash array. The word lines are grouped into word line groups so that they receive the same voltage during operation of the 3D NAND flash array.

[0012] Furthermore, the page type of the array operation is decoded by control circuitry within the 3D NAND device. As the number of layers (also called tiers or word lines) within a 3D NAND flash array increases, the size of the page map within the SRAM within the 3D NAND flash array for storing page-related information also increases, and the control circuitry within the 3D NAND flash array for decoding the page type also increases.

[0013] The size of a page map in an SRAM in a 3D NAND flash device for storing page-related information is reduced by embedding a page type in a row address, which is received by the 3D NAND flash device from a host on a data bus in a six-cycle sequence, and the received row address and column address are for accessing a 3D NAND flash array in the 3D NAND flash device.

[0014] Various embodiments and aspects of the present invention will now be discussed with detailed reference to the accompanying drawings, which illustrate the various embodiments. The following description and drawings are illustrative of the invention and should not be construed as limiting the invention. Numerous specific details are set forth in order to provide a thorough understanding of the various embodiments of the invention. However, in some instances, well-known or conventional details are not described in order to concisely discuss the embodiments of the invention.

[0015] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification do not necessarily all refer to the same embodiment.

[0016] 1 is a block diagram of a 3D (three-dimensional) NAND device 100. The 3D NAND device 10 includes an input / output control circuit 102 and a control circuit 104 coupled to a host memory controller (not shown) by a plurality of control and data signals. The 3D NAND device 100 also includes a 3D NAND flash array 106 including a plurality of NAND cells organized in rows and columns. The 3D NAND device 100, also referred to as a logical unit (LUN), may include one or more NAND flash dies. A NAND flash die is the smallest unit capable of independently executing commands and reporting status.

[0017] A row decoder 110 and a column decoder 108 are provided for decoding address signals to access the 3D NAND flash array 106. The 3D NAND device 100 further includes an input / output (I / O) control circuit 102 that manages the input of commands, addresses, and data to the 3D NAND device 100 and the output of data and status information from the 3D NAND device 100. An address register 116 communicates with the I / O control circuit 102, the row decoder 110, and the column decoder 108 to latch address signals before decoding. A command register 112 communicates with the I / O control circuit 102 and the control circuit 104 to latch input commands. A status register 114 communicates with the I / O control circuit 102 and the control circuit 104 to latch status.

[0018] The control circuitry 104 controls access to the 3D NAND flash array 106 in response to commands and generates state information. The control circuitry 104 communicates with the row decoder 110 and the column decoder 108 to control them in response to addresses. The control circuitry 104 includes a static random access memory (SRAM) 150 that stores page-related information for pages in the NAND flash array 106 in a word line / block segment table 152.

[0019] The Open NAND Flash Interface (ONFI) is a standard that defines the operation of the data bus and control signals 118. The ONFI standard supports an 8-bit or 16-bit data bus (two independent 8-bit data buses) and multiple packaged NAND flash dies (3D NAND devices 100).

[0020] The input / output control circuit 102 in the 3D NAND device 100 communicates with the host memory controller via a bidirectional data bus (DQ) and a bidirectional data strobe (DQS) signal. The DQS signal is for indicating a data valid window. The control circuit 104 in the 3D NAND device 100 receives control signals 118 from the host memory controller. The received control signals 118 include a chip enable (CE#) that selects the 3D NAND device 100 for data transfer with the host memory controller, an address latch enable (ALE) that indicates the type of bus cycle (command, address, or data), a command latch enable (CLE) that indicates the type of bus cycle (command, address, or data), a read enable (RE#), a write enable (WE#), and a write protect (WP#) that disables program and erase operations. The 3D NAND device 100 also includes control signals 118 output by the control circuit 104, including a ready / busy (R / B#) signal that indicates whether the 3D NAND device 100 is performing an operation (“busy”) or is ready for the next operation. In a NAND flash device 100 with multiple LUNs, there is a CE# for each LUN that controls the LUN.

[0021] The NAND flash device 100 does not have dedicated address pins. Addresses are loaded in a six-cycle sequence. The column address is received by the 3D NAND flash on the data pins in the first and second cycles of the six-cycle sequence. The row address is received by the 3D NAND flash on the data pins in the third, fourth, fifth, and sixth cycles.

[0022] It will be understood that the memory device of Figure 1 may include additional circuits and signals, and that the functional blocks of the memory device are not necessarily separated as shown in this example. For example, a single component or portion of a component of an integrated circuit device may be adapted to perform the functions of multiple block components of Figure 1. Alternatively, or additionally, the functionality of a single block component of Figure 1 may be distributed among multiple blocks. In addition, it should be noted that although specific I / O pins are described according to conventions for receiving and outputting various signals, other combinations or numbers of I / O pins may be used in various embodiments. Numerous variations are contemplated.

[0023] FIG. 2 is a block diagram of the array structure of the 3D (three-dimensional) NAND flash array 106 in the 3D NAND flash device 100 shown in FIG.

[0024] The 3D NAND flash array 106 is divided into multiple physical planes. In the example shown in FIG. 2, there are four physical planes: plane 0 (P0) 202-1, plane 1 (P1) 202-2, plane 2 (P2) 202-3, and plane 3 (P3) 202-4. Each physical plane 202-1, 202-2, 202-3, and 202-4 has its own cache register (not shown) and data register (not shown) independent of the other planes, enabling multi-plane operation in which simultaneous read, program, or erase operations are performed on multiple planes. Each physical plane 202-1, 202-2, 202-3, and 202-4 includes multiple blocks 204. Each block 204 is subdivided into multiple pages 206.

[0025] A block of planar NAND Flash contains a grid of cells connected by word lines (WL) and bit lines (BL). A word line is the set of all cells corresponding to a row across the block bit lines. A page is the set of bits corresponding to the same bit level within a word line. Data is programmed / read from NAND Flash by pages. The number of pages per WL within a block is based on the type of memory cell. Single-level cells ("SLC") store one bit of information per cell in one page (lower page). Multi-level cells ("MLC") store two bits of information per cell in two pages (lower page, upper page). Tri-level cells ("TLC") store three bits of information per cell in three pages (lower page, upper page, additional page). Quad-level cells ("QLC") store four bits of information per cell in four pages (lower page, upper page, additional page, top page). The Penta-Level Cell ("PLC") stores five bits of information per cell in five pages: Lower Page (LP), Upper Page (UP), Extra Page (XP), Top Page (TP), and European Page (EP).

[0026] 3 is a block diagram of a system 300 including the 3D NAND flash device 100 shown in FIG. 1. The system 300 includes a host circuit 310 and the 3D NAND flash device 100. The host circuit 310 includes a processor 302, a 3D NAND device controller 304, and a memory 306. The 3D NAND device controller 304 is configured by the processor 302 to send commands to the 3D NAND device 100. The memory 306 stores a page map lookup table 308 that is used by the processor 302 to send commands to the 3D NAND device 100.

[0027] 4 shows a six-cycle sequence used by the host circuit 310 to load an address for the 3D NAND flash array 106. The address includes a column address 402 and a row address 404. The six-cycle sequence will be described with reference to the 3D (three-dimensional) NAND flash device shown in FIG. 1. The column address 402 is received by the 3D NAND flash array 106 on data pins DQ (DQ7:DQ0) in the first and second cycles of the six-cycle sequence. Column address bits CA7:CA0 are received by the 3D NAND flash array 106 on data pins DQ (DQ7:DQ0) in the first cycle. Column address bits CA14:CA8 are received by the 3D NAND flash on data pins DQ (DQ6:DQ0) in the second cycle.

[0028] A row address 404 is received by the 3D NAND flash on the data pins (DQ7:DQ0) in the third, fourth, fifth, and sixth cycles. The row address includes a physical page address (PA), a page type, a block address (BA), and a LUN address (LA). The block address (BA) includes a plane address (e.g., BA[2:0]) and a block address per plane (e.g., BA[10:3]).

[0029] The eight physical page address bits (PA7:PA0) are received by the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0) in the third cycle as part of the row address cycle.

[0030] The five physical page address bits (PA12:PA8) and three page type bits (Page Type 2:Page Type 0) are received by the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0) in the fourth cycle. The word line number, block segment number, word line type, block type, and word line group number for each page type within a single row and block segment are the same.

[0031] Eight block address bits (BA7:BA0), including a 3-bit plane address (BA[2:0]) and five bits of an 8-bit block address per plane (BA[7:3]), are received by the 3D NAND flash array 106 on data pins DQ (DQ7:DQ0) in the fifth cycle.

[0032] Three bits of the 8-bit block address (BA[10:8]) per plane and the 3-bit LUN address (LA2-LA0) are received by the 3D NAND flash array 106 on the data pins DQ (DQ5:DQ0) in the sixth cycle.

[0033] 5 is a table showing the mapping of the page type bits transmitted on the data pins DQ (DQ7:DQ5) in the fourth cycle to page types within the 3D NAND device 100. In the embodiment shown in FIG. 5, the seven page types are encoded as coded page types in three bits.

[0034] Page type bits "001" (binary) are mapped to the lower page (LP). Page type bits "001" (binary) are mapped to the lower page (LP). Page type bits "010" (binary) are mapped to the upper page (UP). Page type bits "011" (binary) are mapped to the extra page (XP). Page type bits "100" (binary) are mapped to the top page (TP). Page type bits "101" (binary) are mapped to the European page (EP).

[0035] Page type bits "110" (binary) are mapped to static single level cell (sSLC) and page type bits "111" (binary) are mapped to dynamic single level cell (dSLC). A native mode block type or native mode word line type (e.g., QLC) can be converted to sSLC mode for the lifetime of the 3D NAND device 100 or to dSLC mode for a period of time, and then converted back to native mode after operation in dSLC mode is complete.

[0036] FIG. 6 is an example of the word line / block segment table 152 shown in FIG. 1 . The word line / block segment table 150 has one entry 602 per word line in a 3D NAND device. The same block segment number is used for each page type within a block segment. A single entry 602 per word line is used for the block segment within the page and word line. Each entry 602 includes a word line number field 604 and at least one block segment field 606. The number of block segment fields 606 per entry 602 depends on the number of block segments per word line in a block. The word line number field 604 stores the word line number (e.g., “1”), and the block segment field 606 stores the block segment number (e.g., “A”, “B”). Each block segment in the 3D NAND flash array 106 is assigned a unique block segment number.

[0037] FIG. 7 is a timing diagram illustrating a six-cycle sequence used by the host circuit 310 to load addresses within the 3D NAND flash array 106.

[0038] At time 702, a start command is sent by the host circuit 310 on the data pins DQ (DQ7:DQ0).

[0039] At time 704, column address bits CA7:CA0 are sent by the host circuit 310 to the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0).

[0040] At time 706, column address bits CA14:CA8 are sent by the host circuit 310 to the 3D NAND flash array 106 on data pins DQ (DQ7:DQ0).

[0041] At 708, the eight physical page address bits (PA7:PA0) are sent by the host circuitry 310 to the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0).

[0042] At time 710, five physical page address bits (PA12:PA8) and three page type bits (Page Type 2:Page Type 0) are sent by the host circuit 310 to the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0).

[0043] At time 712, eight block address bits (BA7:BA0), including a 3-bit plane address (BA[2:0]) and five bits of an 8-bit block address per plane (BA[7:3]), are sent by the host circuit 310 to the 3D NAND flash array 106 on data pins DQ (DQ7:DQ0).

[0044] At time 714, three bits of the 8-bit block address (BA[10:8]) and the 3-bit LUN address (LA2-LA0) per plane are sent by the host circuit 310 to the 3D NAND flash array 106 on the data pins DQ (DQ7:DQ0).

[0045] At time 716, a confirm command is sent by the host circuit 310 on the data pins DQ (DQ7:DQ0).

[0046] FIG. 8 is a flow diagram of a method for decoding a physical page address of a 3D NAND flash array 106.

[0047] In block 800, the word line numbers of the physical page addresses received in the six-cycle sequence are extracted from the physical page addresses. The eight physical page address bits (PA7:PA0) received on data pins DQ (DQ7:DQ0) by the 3D NAND flash array 106 in the third cycle and the five physical page address bits (PA12:PA8) received on data pins DQ (DQ7:DQ0) by the 3D NAND flash array 106 in the fourth cycle provide the word line numbers of the page.

[0048] In block 802, the extracted word line number is used to read the block segment field 606 in the entry 602 for the word line number in the word line / block segment table 152. The block segment field 606 stores the block segment number of the physical page address received in the six-cycle sequence. The block segment number is the remainder of the physical page address % the number of block segments.

[0049] 9 is a block diagram of a computer system 900 including a 3D NAND device 100. The computer system 900 may correspond to a computing device, including but not limited to, a server, a workstation computer, a desktop computer, a laptop computer, and / or a tablet computer.

[0050] The computer system 900 includes a system-on-chip (SOC or SoC) 904 that integrates a processor, graphics, memory, and input / output (I / O) control logic into a single SoC package. The SoC 904 includes at least one central processing unit (CPU) module 908, a volatile memory controller 914, and a graphics processing unit (GPU) 910. In other embodiments, the volatile memory controller 914 may be external to the SoC 904. Although not shown, each of the processor cores 902 may include one or more instruction / data caches, execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating-point units, retirement units, etc. According to one embodiment, the CPU module 908 may correspond to a single-core or multi-core general-purpose processor, such as those offered by Intel® Corporation.

[0051] The graphics processing unit (GPU) 910 may include one or more GPU cores and a GPU cache that can store graphics-related data for the GPU cores. The GPU cores may include one or more execution units and one or more instruction and data caches. In addition, the graphics processing unit (GPU) 910 may include other graphics logic units not shown in FIG. 9, such as one or more vertex processing units, rasterization units, media processing units, and codecs.

[0052] Within I / O subsystem 912 reside one or more I / O adapters 916 that convert the host communication protocol utilized within processor core 902 into a protocol compatible with a particular I / O device. Some protocols that can be converted using an adapter include Peripheral Component Interconnect (PCI)-Express (PCIe), Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), and Institute of Electrical and Electronics Engineers (IEEE) 1594 "Firewire."

[0053] The I / O adapter 916 can communicate with external I / O devices 924, which may include, for example, user interface devices including a display and / or touchscreen display 940, printers, keypads, keyboards, communication logic, wired and / or wireless, storage devices including hard disk drives (“HDDs”), solid state drives (“SSDs”) 918, removable storage media, digital video disk (DVD) drives, compact disk (CD) drives, redundant array of independent disks (RAID), tape drives, or other storage devices. The storage devices may be communicatively and / or physically coupled through one or more buses using one or more of a variety of protocols, including, but not limited to, Serial Attached SCSI (Small Computer System Interface) (SAS), Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe) over PCIe (Peripheral Component Interconnect Express), and Serial ATA (Advanced Technology Attachment) (SATA).

[0054] In addition, there may be one or more wireless protocol I / O adapters. Examples of wireless protocols include personal area networks such as IEEE 802.15 and Bluetooth 4.0, wireless local area networks such as IEEE 802.11-based wireless protocols, and cellular protocols.

[0055] The I / O adapter 916 can also communicate with a storage device, which can be a hard disk drive (HDD) or solid state drive (“SSD”) 918 including an SSD controller 920 , a host interface 928 , and a 3D NAND device 100 .

[0056] The computer system 900 may include a 3D NAND device 100 and a 3D NAND device controller 304 communicatively coupled to a CPU module 908 in an SoC 904. The 3D NAND device 100 may be included in a dual in-line memory module (DIMM), which may be referred to as a non-volatile dual in-line memory module (NVDIMM).

[0057] A non-volatile memory (NVM) device is memory whose state is deterministic even when power to the device is interrupted. In one embodiment, the NVM device may include NAND technology, or more specifically, a block-addressable memory device such as multi-threshold level NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), quad-level cell ("QLC"), tri-level cell ("TLC"), or other NAND).

[0058] The I / O adapter 916 may include a Peripheral Component Interconnect Express (PCIe) adapter communicatively coupled to a host interface 928 in the solid-state drive 918 via bus 944 using the NVM Express (NVMe) over PCIe (Peripheral Component Interconnect Express) protocol. The Non-Volatile Memory Express (NVMe) standard defines a register-level interface for host software that communicates with a non-volatile memory subsystem (e.g., a solid-state drive (SSD)) over Peripheral Component Interconnect Express (PCIe), a high-speed serial computer expansion bus. The NVM Express standard can be viewed at www.nvmexpress.org. The PCIe standard can be viewed at www.pcisig.com.

[0059] Applications 930 and an operating system (OS) 942 can be stored in volatile memory 926. Volatile memory is memory whose state (and therefore stored data) is indeterminate when power to the device is interrupted. Dynamic volatile memory requires refreshing of the data stored in the device to maintain its state. An example of dynamic volatile memory is DRAM (Dynamic Random Access Memory), or some variants such as Synchronous DRAM (SDRAM). The memory subsystems described herein may be DDR3 (Double Data Rate version 3, first released by JEDEC (Semiconductor Engineering Association) on June 27, 2007), DDR4 (DDR version 4, the first specification published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B, published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, first published by JEDEC in August 2014), WIO2 (Wide Input / Output version 2, JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory Module version 2, JESD229-3, first published by JEDEC in October 2013), or the like. The JEDEC standards may be compatible with numerous memory technologies, including but not limited to, DDR5 (DDR version 5 currently under consideration by JEDEC), LPDDR5 (LPDDR5 currently under consideration by JEDEC), HBM2 (HBM version 2 currently under consideration by JEDEC), or any other combination of memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards can be viewed at www.jedec.org.

[0060] Operating system 942 is software that manages computer hardware and software, including memory allocation and access to I / O devices. Examples of operating systems include Microsoft®, Windows®, Linux®, iOS®, and Android®.

[0061] Power source 946 provides power to the components of computer system 900. More specifically, power source 946 typically interfaces to one or more power supplies 948 within computer system 900 to power the components of system X00. In one example, power source 948 includes an AC-DC (alternating current-to-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) power source 946. In one example, power source 946 includes a DC power source such as an external AC-DC converter. In one example, power source 946 or power source 948 includes wireless charging hardware that charges via proximity to a charging field. In one example, power source 946 can include an internal battery or fuel cell power source.

[0062] The flow diagrams illustrated herein provide example sequences of various process actions. The flow diagrams may depict operations performed by software or firmware routines as well as physical operations. In one embodiment, the flow diagrams may depict the states of a finite state machine (FSM), which may be implemented in hardware and / or software. The order of actions, while shown in a particular sequence or order, may be changed unless otherwise specified. Thus, the illustrated embodiments should be understood as examples, and processes may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted in various embodiments, and therefore not all actions are required in every embodiment. Other process flows are possible.

[0063] Various operations or functions described herein, to the extent described, can be described or defined as software code, instructions, settings, and / or data. The content can be directly executable (in "object" or "executable" form) source code or differential code ("delta" or "patch" code). The software content of the embodiments described herein can be provided by a product storing the content or by a method of operating a communications interface and transmitting data through the communications interface. A machine-readable storage medium can cause a machine to perform the described functions or operations and includes any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as recordable and non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism for interfacing to a medium, such as a hardwired medium, a wireless medium, an optical medium, etc., to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or by sending signals that prepare the communications interface to provide data signals describing the software content. The communications interface may be accessed by one or more commands or signals sent to the communications interface.

[0064] The various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, hardwired circuitry, etc.

[0065] In addition to what is described herein, various modifications can be made to the disclosed embodiments and examples of the invention without departing from the scope thereof.

[0066] Therefore, the illustrations and examples herein should be considered illustrative rather than restrictive. The scope of the invention should be determined solely by reference to the claims that follow.

Claims

1. a NAND flash array including a plurality of NAND cells; a control circuit that decodes a physical page address received during a row address cycle to obtain a word line in the NAND flash array and a block segment number for a block segment within the word line, wherein the same block segment number is used for each page type within the block segment; 1. A non-volatile memory device comprising:

2. 2. The non-volatile memory device of claim 1, wherein the word line and block segment numbers are stored in a table in a static random access memory.

3. The non-volatile memory device of claim 2 , wherein each block segment has an entry in the table.

4. 4. A non-volatile memory device according to claim 1, wherein the physical page address is received as part of the row address cycle that includes an encoded page type.

5. 5. The non-volatile memory device of claim 4, wherein the coded page type is coded in 3 bits.

6. The non-volatile memory device of claim 4 , wherein the coded page type is a static single level cell.

7. The non-volatile memory device of claim 4 , wherein the coded page type is a dynamic single level cell.

8. 5. The non-volatile memory device of claim 4, wherein the NAND cells are quad-level cells and the coded page type is lower page, upper page, additional page or top page.

9. 5. The non-volatile memory device of claim 4, wherein the NAND cells are penta-level cells and the coded page type is lower page, upper page, additional page, top page or European page.

10. The non-volatile memory device of claim 1 , wherein the NAND cells are three-dimensional (3D) NAND cells.

11. A memory controller; a non-volatile memory device including a NAND flash array including a plurality of NAND cells; a control circuit that decodes a physical page address received during a row address cycle to obtain a word line in the NAND flash array and a block segment number for a block segment within the word line, wherein the same block segment number is used for each page type within the block segment; Including, the system.

12. 12. The system of claim 11, wherein the word line and block segment numbers are stored in a table in static random access memory.

13. The system of claim 12 , wherein each block segment has an entry in the table.

14. 14. The system of claim 11, wherein the physical page address was received as part of the row address cycle that includes an encoded page type.

15. 15. The system of claim 14, wherein the coded page type is coded on 3 bits.

16. 15. The system of claim 14, wherein the coded page type is a static single level cell.

17. 15. The system of claim 14, wherein the coded page type is a dynamic single level cell.

18. 15. The system of claim 14, wherein the NAND cells are penta-level cells and the coded page type is a lower page, an upper page, an additional page, a top page, or a European page.

19. 19. The system of claim 11, wherein the NAND cells are three-dimensional (3D) NAND cells.

20. a processor; Power supply and a display in combination with said non-volatile memory device; The system of claim 11 , further comprising one or more of:

21. decoding, by control circuitry within the non-volatile memory device, a physical page address received during a row address cycle to obtain a word line within a NAND flash array within the non-volatile memory device and a block segment number for a block segment within the word line; using, by said control circuitry, the same block segment number for each page type within said block segment; A method comprising:

22. 22. The method of claim 21, wherein the word line and block segment numbers are stored in a table in a static random access memory.

23. 23. The method of claim 22, wherein each block segment has an entry in the table.

24. 24. The method of any one of claims 21 to 23, wherein the physical page address was received as part of the row address cycle that includes an encoded page type.

25. Apparatus comprising means for carrying out the method of any one of claims 21 to 24.

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