SPI-based data transmission method, chip, controller, and storage medium

Abstract

SPI-based data transmission methods, chips, controllers, and storage media relating to the technology of communications. The method includes receiving a trigger signal from a first side transmitted by a second device in a communications system based on a second valid data block that needs to be exchanged, preparing a first side data block based on the trigger signal from the first side, wherein the first side data block includes a valid data block or an invalid data block, and in one data interaction process, transmitting the first side data block to a second device and receiving a second side data block corresponding to a second valid data block transmitted by the second device.

Description

Technical Field

[0001] Cross-reference to Related Applications This disclosure claims priority to Chinese Patent Application No. 202310224153.3, entitled "SPI-BASED DATA TRANSMISSION METHOD, CHIP, CONTROLLER, AND STORAGE MEDIUM", filed on February 28, 2023, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to the field of communication technologies, and more particularly, to an SPI-based data transmission method, chip, controller, and storage medium.

Background Art

[0003] In related technologies, in response to data being exchanged between an SPI slave device and an SPI master device based on the SPI (Serial Peripheral Interface) protocol, first, the master device receives a trigger signal from the slave device, and the master device prepares an invalid data block for exchanging with the valid data block of the slave device. Second, the slave device receives a trigger signal from the master device, and the slave device prepares an invalid data block for exchanging with the valid data block of the master device.

[0004] In related technologies, it can be seen that the process of exchanging valid data blocks and invalid data blocks between the master device and the slave device needs to be executed twice, and the data transmission efficiency needs to be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This disclosure is intended to solve, at least to some extent, one of the technical problems in the related technology. Accordingly, this disclosure provides an SPI-based data transmission method, chip, controller, and storage medium.

[0006] This disclosure provides an SPI-based data transmission method applicable to a first device in an SPI communication system, the method being: The trigger signal from the first side, transmitted by a second device in the communication system based on a second valid data block that needs to be exchanged, is received. Based on the trigger signal of the first side, the data block on the first side is prepared, and the data block on the first side includes either an active data block or an invalid data block. In a single data interaction process, a data block on the first side is sent to a second device, and a data block on the second side corresponding to a second valid data block sent by the second device is received. Includes. [Means for solving the problem]

[0007] In one embodiment, the data block on the first side is prepared based on the trigger signal on the first side. In response to a trigger signal on the first side, it is determined whether the first device has a first valid data block that needs to be replaced. If the first device has a first valid data block, the first valid data block is prepared as a data block on the first side, If the first device does not have a first valid data block, an invalid data block is prepared as the data block on the first side. Includes.

[0008] In one embodiment, the first device has a first transmit buffer and a second transmit buffer, and the first valid data block is prepared as the data block on the first side. This includes preparing the data block on the first side by writing the first valid data block from the first transmit buffer to the second transmit buffer.

[0009] In one embodiment, an invalid data block is prepared as a data block on the first side. This includes writing an invalid data block of a predetermined length to a second transmit buffer to prepare the data block on the first side.

[0010] In one embodiment, it is determined whether the first device has a first valid data block that needs to be replaced. It is determined whether the first transmit buffer has a first valid data block, If the first transmit buffer has a first valid data block, it is determined that the first device has a first valid data block that needs to be replaced. If the first transmit buffer does not have the first valid data block, it is determined that the first device does not have the first valid data block that needs to be replaced. Includes.

[0011] In one embodiment, before a first valid data block is written from a first transmit buffer to a second transmit buffer, the method further includes: receiving a message to be sent; encapsulating the message in a plurality of data frames; writing the plurality of data frames to a data block; and buffering the data block in the first transmit buffer.

[0012] In one embodiment, the first device further has a first receive buffer and a second receive buffer, and the reception of a second-side data block corresponding to a second valid data block transmitted by the second device includes the second-side data block being received into the first receive buffer and the second-side data block in the first receive buffer being written into the second receive buffer.

[0013] In one embodiment, the method further includes clearing the second transmit buffer and the first receive buffer in response to the completion of writing the second side data block to the second receive buffer.

[0014] In one embodiment, the first device is an SPI slave device, and the second device is an SPI master device.

[0015] After preparing a data block on the first side based on a trigger signal on the first side, the method further includes sending a trigger signal on the second side to a second device to cause the second device to prepare a second valid data block as a data block on the second side.

[0016] In one embodiment, in response to the determination that the reception of the data block on the second side is complete, the method further includes deducting 1 from the current reception count of the trigger signal on the first side; in response to the determination that the trigger signal on the first side has been received, the method further includes adding 1 to the current reception count of the trigger signal on the first side; and the preparation of the data block on the first side based on the trigger signal on the first side includes preparing the data block on the first side in response that the current reception count of the trigger signal on the first side is greater than 0.

[0017] In one embodiment, the SPI slave device is configured to have a first thread and a second thread, the first thread is configured to receive a trigger signal on the first side, prepare a data block on the first side, transmit a data block on the first side, and receive a data block on the second side, the second thread is configured to prepare a valid data block as a slave-side data block in response to the SPI slave device having a valid data block that needs to be replaced, and after the slave-side data block is prepared, to send a master-side trigger signal to the SPI master device to cause the SPI master device to prepare a master-side data block, and the first and second threads are controlled by a mutual exclusion lock.

[0018] In one embodiment, the first device is an SPI master device, and the second device is an SPI slave device, the second device having a third transmit buffer and a fourth transmit buffer, and in response to the second device having a second valid data block that needs to be replaced, the second device writes the second valid data block from the third transmit buffer to the fourth transmit buffer, and then transmits a trigger signal to the first side.

[0019] This disclosure provides an SPI-based data transmission method applicable to an SPI communication system including a first device and a second device, the method comprising: the second device transmitting a trigger signal to the first side based on a second valid data block that needs to be exchanged; the second device preparing the second valid data block as a data block to the second side; the first device receiving a trigger signal to the first side transmitted by the second device and preparing a data block to the first side based on the trigger signal to the first side, wherein the data block to the first side comprises a valid data block or an invalid data block; the first device transmitting the data block to the second device; and the second device transmitting the data block to the first device.

[0020] In one embodiment, the first device is an SPI master device, the second device is an SPI slave device, the second device has a third transmission buffer and a fourth transmission buffer, and the second device preparing the second valid data block as the second-side data block includes the second device writing the second valid data block from the third transmission buffer to the fourth transmission buffer to prepare the second-side data block. The second device transmitting the first-side trigger signal based on the second valid data block that needs to be exchanged includes the second device, in response to having the second valid data block that needs to be exchanged, transmitting the first-side trigger signal after writing the second valid data block to the fourth transmission buffer.

[0021] The present disclosure provides a chip including a memory, a processor, and a computer program stored in the memory and executable by the processor. The processor implements the method according to any one of the embodiments in response to the execution of the computer program.

[0022] The present disclosure provides a computer-readable storage medium storing computer instructions or programs for causing a computer to execute the method according to any one of the embodiments in response to being executed on the computer.

[0023] The present disclosure provides a controller including a first chip and a second chip, the first chip and the second chip being connected by an SPI bus. The second chip is configured to transmit a trigger signal on the first side based on a second valid data block that needs to be exchanged. The second chip is further configured to prepare the second valid data block as a data block on the second side. The first chip is configured to receive the trigger signal on the first side transmitted by the second chip and prepare a data block on the first side based on the trigger signal on the first side. The data block on the first side includes a valid data block or an invalid data block. The first chip is configured to transmit the data block on the first side to the second chip, and the second chip is further configured to transmit the data block on the second side to the first chip.

[0024] According to the SPI-based data transmission method provided by the present disclosure, a trigger signal on the first side transmitted by a second device in a communication system is received based on a second valid data block that needs to be exchanged. A data block on the first side is prepared based on the trigger signal on the first side. In one data interaction process, the data block on the first side is transmitted to the second device, and a data block on the second side corresponding to the second valid data block transmitted by the second device is received. The exchange of the valid data block can be completed through one data interaction between the first device and the second device, realizing the simultaneous transmission of master-side data and slave-side data, and improving the data transmission efficiency.

[0025] Additional aspects and advantages of the present disclosure are provided in part in the following description, some of which will be apparent from the following description or learned from the practice of the present disclosure.

[0026] The above and / or additional aspects and advantages of the present disclosure will become apparent and will be readily understood from the description of the embodiments in conjunction with the following drawings. [Brief explanation of the drawing]

[0027] [Figure 1a] This is a schematic diagram of a standard 4-wire SPI provided according to one embodiment of this description. [Figure 1b] This is a schematic diagram of a 5-wire SPI provided according to one embodiment of this description. [Figure 1c] This is a schematic diagram of a 6-wire SPI provided according to one embodiment of this description. [Figure 1d] This is a schematic diagram of the underlying hardwire connection provided according to one embodiment of this description. [Figure 1e] This is a schematic diagram of the SOC-side communication framework provided according to one embodiment of this description. [Figure 1f] This is a schematic diagram of the MCU-side communication framework provided according to one embodiment of this description. [Figure 1g] This is a schematic diagram of a slave device framework provided according to one embodiment of this description. [Figure 1h] This is a schematic diagram of the master device framework provided according to one embodiment of this description. [Figure 2a] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Figure 2b] This is a schematic diagram of the interaction between a master device and a slave device provided according to one embodiment of this description. [Figure 2c] This is a schematic diagram of the interaction between a master device and a slave device provided according to one embodiment of this description. [Figure 3a] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Figure 3b] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Figure 4a] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Figure 4b] This is a schematic flowchart of the TO_SLAVE pulse signal reception interrupt processing flow provided according to one embodiment of this description. [Figure 4c] This is a schematic flowchart of the processing flow of a scenario thread in which the master actively triggers data block exchange, as provided according to one embodiment of this description. [Figure 4d] This is a schematic flowchart of the processing flow of a scenario thread in which the slave actively triggers a data block exchange, as provided according to one embodiment of this description. [Figure 5] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Figure 6] This is a schematic flowchart of an SPI-based data transmission method provided according to one embodiment of this description. [Modes for carrying out the invention]

[0028] Embodiments of the present disclosure are described in detail below. Examples of embodiments are shown in the accompanying drawings, where the same or similar reference numerals in all of the accompanying drawings indicate the same or similar components or components having the same or similar function. The embodiments described below with reference to the accompanying drawings are illustrative and intended to illustrate the present disclosure and should not be construed as limiting the present disclosure.

[0029] In a multi-domain centralized automotive electronic architecture, the MCU (microcontroller unit) is configured to handle software functions requiring real-time performance and security, while the SOC (system-on-a-chip) is configured to handle software functions requiring computing performance. The MCU and SOC can be reasonably allocated with redundant backups, taking the above requirements into consideration. Ethernet is commonly used for communication between the MCU and SOC to meet high communication bandwidth requirements. On the other hand, other communication methods are used between the MCU and SOC for security reasons. Generally, the underlying hardware between the MCU and SOC may communicate directly through serial ports, SPI, and other methods.

[0030] In related technologies, some solutions implement active transmission on the SOC or MCU side based on the SPI bus, while others implement active transmission on both the SOC and MCU sides. However, these solutions suffer from insufficient real-time performance, failure to consider communication reliability at both ends of the communication, strict limitations on the length of the communication data, inability to accommodate scenarios where the SOC and MCU exchange valid data simultaneously, the need to occupy excessive hardware resources (such as pins) to control the data transmission process, or overly complex timing control of the underlying data transmission.

[0031] Referring to Figure 1a, which is a schematic diagram of a standard 4-wire SPI, two nodes (NODE1 and NODE2) are shown, with node NODE1 functioning as the master device and node NODE2 functioning as the slave device. 4-wire SPI cannot achieve real-time data exchange between master and slave. Generally, data exchange between the master and slave is performed by SPI master-side polling. This method consumes fewer hardware resources (number of pins) but has the disadvantage of insufficient real-time performance. MOSI is the master output slave input signal line, MISO is the master input slave output signal line, CLK is the signal line for transmitting the clock signal, and CS is the signal line for transmitting the chip selection signal.

[0032] Referring to Figure 1b, which is a schematic diagram of a 5-wire SPI, a 5-wire SPI generally adds a control line from the SLAVE device to the MASTER device. While transmission can be actively initiated through the standard four wires CS, CLK, MOSI, and MISO in response to the MASTER needing active transmission, it is impossible to quickly and accurately notify the SLAVE of the start of transmission. In response to the SLAVE needing active transmission, the MASTER can be notified through the S_CTRL control line, but at this point the MASTER may already be preparing to start data transmission. Therefore, in terms of bidirectional transmission efficiency, 5-wire SPI is superior to 4-wire SPI. Only one control line is added, which does not consume many resources (pins). However, complex logic is added to complete the control of bus contention that occurs with bidirectional transmission, and bus contention also affects transmission efficiency.

[0033] Referring to Figure 1c, which is a schematic diagram of a 6-wire SPI, a 6-wire SPI generally adds control lines from the SLAVE side to the MASTER side and control lines from the MASTER side to the SLAVE side. There are generally two methods for implementing bidirectional real-time transmission with 6-wire SPI.

[0034] The first method is for the MASTER to notify the SLAVE via M_CTL that it is ready in response to the need for the MASTER to transmit data. After the SLAVE has prepared the data, the SLAVE notifies the MASTER via S_CTL that it is ready, and then the MASTER begins data transmission. In order to ensure priority transmission on one side and prevent bus contention scenarios, priority control and state machine control are required on both the MASTER and SLAVE sides in response to the need for both sides to transmit data simultaneously.

[0035] The second method involves the MASTER notifying the SLAVE via M_CTL that it is ready when the MASTER needs to send data, and then the MASTER initiating data transmission. Conversely, the SLAVE notifying the MASTER via S_CTL that it is ready when the SLAVE needs to send data, and then the MASTER initiating data transmission. To ensure priority transmission on one side and prevent bus contention scenarios, priority control and state machine control are required on both the MASTER and SLAVE sides in response to the need for simultaneous data transmission from both sides.

[0036] The two methods described above offer higher real-time performance and transmission efficiency than 5-wire SPI. However, in bidirectional simultaneous transmission scenarios, additional logic control is required to prevent bus contention, and full-duplex real-time transmission cannot be fully achieved.

[0037] In addition, there are several solutions in related technologies for 7-wire and 8-wire SPI. On the one hand, more control states are added, increasing the complexity of the control logic and the probability of errors; on the other hand, the consumption of hardware resources (pins) increases.

[0038] Therefore, 6-wire SPI is a solution that takes resource consumption and real-time bidirectional transmission into consideration. However, in the case of bidirectional real-time transmission scenarios, the solutions of related technologies require the addition of complex bus contention control logic to ensure preferred transmission on one side. As stated in the background technology, the MASTER side and SLAVE side must perform the process of exchanging valid and invalid data blocks twice, and therefore, it is found that the related technologies cannot achieve bidirectional real-time transmission of valid and invalid data blocks.

[0039] Based on this, embodiments of the present disclosure optimize the communication timing of the underlying layer, so that the transmission of effective data blocks on the master and slave sides is completed in a single data interaction process, real-time data transmission on the master and slave sides is achieved, and data transmission efficiency is improved. Referring to Figure 1d, which is a schematic diagram of the underlying hardwire connection provided according to one embodiment of the present description. Note that a description of the hardwire connection pins in Figure 1d is shown in Table 1.

[0040] [Table 1]

[0041] Furthermore, one embodiment of this description also provides a set of SPI-based communication frameworks between the SOC and the MCU. Referring to Figure 1e, Figure 1e is a schematic diagram of the SOC-side communication framework provided according to one embodiment of this description. The SOC-side communication framework is divided into four layers, from bottom to top: the physical layer, the driver layer, the communication layer, and the application layer. The communication layer is divided into three modules, from bottom to top: the data link function module, the transmission function module, and the interface call module. The functions implemented by each layer on the SOC side are shown in Table 2.

[0042] [Table 2]

[0043] Referring to Figure 1f, which is a schematic diagram of the MCU-side communication framework provided according to one embodiment of this description, the MCU-side communication framework is divided into four layers from bottom to top: the physical layer, the driver layer, the communication layer, and the application layer. The communication layer is divided from bottom to top into a data link function module and a transmission function module. The functions implemented by each layer on the MCU side are shown in Table 3.

[0044] [Table 3]

[0045] The communication framework in the embodiment described herein enables a clearer architectural layering of the communication framework. Based on the communication timing of the underlying layer, the communication framework in the embodiment described herein satisfies the requirement of rapid portability. Note that in the embodiment described herein, the SOC side is the SPI slave side and the MCU side is the SPI master side. Various communication function requirements between the SOC side and the MCU side are met while achieving bidirectional communication between the SOC side and the MCU side.

[0046] The embodiments described here provide example scenarios for an SPI-based data transmission method. Referring to Figures 1g and 1h, Figure 1g is a schematic diagram of the slave device framework, and Figure 1h is a schematic diagram of the master device framework. In this example scenario, the slave side can use an SOC, and the master side can use an MCU. The communication layer mainly implements data link modules and transmission modules. Since the Linux operating system is employed on the SOC side, an interface call module is also required to complete data transmission between user space and kernel space.

[0047] In the example scenario, when the master actively triggers the exchange timing interaction process, the process of exchanging valid data blocks between the master and slave is illustrated as follows, including steps (1) to (6):

[0048] (1) On the master side, the application data message is sent to the data message transmission link list buffer of the transmission module in the communication layer via the application data transmission thread of the application layer. To obtain multiple valid data blocks, the application data message is encapsulated via the encapsulation thread of the transmission module, and valid data block A is written to the data block transmission FIFO buffer of the data link module. The transmission of the TO_SLAVE signal is triggered via the data transmission trigger thread, and the TO_SLAVE signal is sent to the slave side, which receives the TO_SLAVE signal and wakes up transmission thread 1.

[0049] (2) On the slave side, the valid data block B in the data block transmit FIFO buffer is written to the driver layer transmit buffer (DMA) via transmission thread 1. Once the slave side has finished preparing the valid data block B, the slave side sends the TO_MASTER signal to the master side via transmission thread 1.

[0050] (3) On the master side, the TO_MASTER signal is received through the data exchange thread, and valid data block A in the data block transmit FIFO buffer of the data link module is written to the driver layer transmit buffer (DMA) through the data exchange thread. Valid data block A is transmitted to the slave side through the master side drive interface.

[0051] (4) On the slave side, valid data block A is written to the slave side's receive buffer (DMA) through the slave side's drive interface. Through transmission thread 1, valid data block A is written from the slave side's driver layer receive buffer (DMA) to the slave side's data block receive FIFO buffer of the data link module. Valid data block A is parsed through the data link module's parsing thread, and the parsed data message is written to the slave side's transmission module's data message receive link list buffer, and then written to the application data buffer through the transmission module's receive thread, interface call module, and application data receive thread, and provided to the application data processing thread for processing.

[0052] (5) On the slave side, while the slave side is receiving valid data block A, valid data block B is transmitted to the master side through the slave side's drive interface.

[0053] (6) On the master side, valid data block B is written to the master side receive buffer (DMA) via the master side drive interface. Through the transmission complete interrupt thread, valid data block B is written from the master side driver layer receive buffer (DMA) to the master side data link module's data block receive FIFO buffer. Valid data block B is parsed through the data link module's parsing thread, and the parsed data message is written to the master side transmission module's data message receive link list buffer, and then written to the application data buffer via the transmission module's receive thread and application data receive thread, and provided to the application data processing thread for processing.

[0054] In the example scenario, when the slave actively triggers the exchange timing interaction process, the process of exchanging valid data blocks between the slave and master is illustrated as follows, including steps (1) to (5):

[0055] (1) On the slave side, the application data message is sent to the data message transmission link list buffer of the transmission module in the communication layer via the application data transmission thread of the application layer. To obtain multiple valid data blocks, the application data message is encapsulated via the encapsulation thread of the transmission module, and the valid data block X is written to the data block transmission FIFO buffer of the data link module. The valid data block X in the data block transmission FIFO buffer is written to the driver layer's transmit buffer (DMA) via transmission thread 2. Transmission thread 2 triggers the transmission of the TO_MASTER signal, which is sent to the master side, and the master side receives the TO_MASTER signal and invokes the data exchange thread.

[0056] (2) On the master side, the valid data block Y in the data link module's data block transmit FIFO buffer is written to the driver layer's transmit buffer (DMA) via the data exchange thread. The valid data block Y is then transmitted to the slave side via the master's drive interface.

[0057] (3) On the slave side, the valid data block Y is received by the receive buffer (DMA) of the slave's driver layer via the transmission thread 2, and the valid data block X in the transmit buffer (DMA) of the slave's driver layer is transmitted to the master side via the slave's drive interface.

[0058] (4) On the master side, the valid data block X is written to the master side receive buffer (DMA) via the master side drive interface. Through the transmission complete interrupt thread, the valid data block X is written from the master side driver layer receive buffer (DMA) to the master side data link module's data block receive FIFO buffer. The valid data block X is parsed through the data link module's parsing thread, and the parsed data message is written to the master side transmission module's data message receive link list buffer, and then written to the application data buffer through the transmission module's receive thread and application data receive thread, and provided to the application data processing thread for processing.

[0059] (5) On the slave side, the valid data block Y is written from the slave-side driver layer receive buffer (DMA) to the slave-side data link module's data block receive FIFO buffer via transmission thread 2. The valid data block Y is parsed via the data link module's parsing thread, and the parsed data message is written to the slave-side transmission module's data message receive link list buffer, and then written to the application data buffer via the transmission module's receive thread, interface call module, and application data receive thread, and provided to the application data processing thread for processing.

[0060] Note that SPI stands for Serial Peripheral Interface. This is a high-speed, full-duplex synchronous communication bus that can be configured for communication between chips. MCU stands for Microcontroller Unit. In automotive domain controllers, MCUs are generally configured to implement functions that require real-time performance and security. SOC stands for System on Chip. In automotive domain controllers, SOCs are generally configured to implement functions that require computing and communication performance.

[0061] In the example scenario, a data message refers to application layer data buffered in the transmission module. The data message buffered in the transmission module is encapsulated in a frame format as a data frame. Acknowledgment information is encapsulated in a frame format as an acknowledgment frame. Fixed data configured to pad the remaining space of a data block is encapsulated in a frame format as a padding frame. In the example scenario, driver layer data exchange is fixed-length, and data frames, acknowledgment frames, and padding frames can be written to a fixed-length memory space to form a data block. Note that data messages are a transmission module concept, while data frames, acknowledgment frames, padding frames, and data blocks are data link module concepts.

[0062] In the example scenario, the transmit and receive buffers of the data link module are configured to buffer 1280-byte data blocks transmitted and received. There are separate data block buffers for receiving and transmitting. The data block buffer is a first-in, first-out circular queue with a provisional queue depth of 12, which can simultaneously store 12 1280-byte data blocks. The transmit and receive buffers of the driver layer perform data interaction with the transmit and receive buffers (of the data link module).

[0063] In the example scenario, on the one hand, a new underlying SPI communication timing control method is implemented based on two newly added GPIO pins and driver layer code logic. This timing control method has simple logic and can avoid contention that could be caused by simultaneously triggering transmissions on the master and slave sides. On the other hand, a set of inter-chip communication frameworks between the SOC and MCU sides is implemented based on the underlying SPI communication, thereby providing fragmented transmission services for longer data. Furthermore, the framework is characterized by clear hierarchies, a simple interface, and excellent portability and extensibility.

[0064] One embodiment of this description provides an SPI-based data transmission method applicable to a first device of an SPI communication system. Referring to Figure 2a, the SPI-based data transmission method may include the following steps:

[0065] S210. The trigger signal from the first side, transmitted by the second device in the communication system, is received based on the second valid data block that needs to be replaced.

[0066] S220. Based on the trigger signal of the first side, the data block of the first side is prepared, and the data block of the first side includes an active data block or an invalid data block.

[0067] S230. In one data interaction process, a data block on the first side is sent to the second device, and a data block on the second side corresponding to a second valid data block sent by the second device is received.

[0068] The communication system includes a first device and a second device. The first device functions as a passive data receiver. Specifically, the second device has a second valid data block that needs to be exchanged, and the second device sends a trigger signal to the first device based on the second valid data block. The first device receives the trigger signal and prepares a data block on its side based on the trigger signal. After the first device has prepared the data block on its side, the first and second devices begin to jointly execute a data interaction process. In one data interaction process, the first device sends a data block on its side to the second device and, at the same time, receives a data block on its side corresponding to the second valid data block sent by the second device. It should be noted that in response to the first device having a valid data block that needs to be replaced, the valid data block to be replaced is prepared as a data block on the first side, and therefore, in a single data interaction process, data exchange between a valid data block on the first side and a valid data block on the second side is achieved between the first device and the second device. In response to the first device not having a valid data block that needs to be replaced, an invalid data block is prepared as a data block on the first side. In the embodiment, it can be seen that in a single data interaction process, data exchange between an invalid data block and a valid data block on the second side is performed between the first device and the second device only in response to the first device not having a valid data block that needs to be replaced.

[0069] In this embodiment, the SPI communication system includes a master device and a slave device. The SPI communication system corresponds to three scenarios: a scenario in which the master device (master side) actively triggers the data block exchange; a scenario in which the slave device (slave side) actively triggers the data block exchange; and a scenario in which both the master and slave sides simultaneously trigger the data block exchange. The following describes the SPI-based data transmission process for the different scenarios. In the embodiments described herein, the first device can be understood as the passive recipient of data. For example, in the scenario in which the master side actively triggers the data block exchange, and in the scenario in which both the master and slave sides simultaneously trigger the data block exchange, the first device may be considered a slave device. In the scenario in which the slave side actively triggers the data block exchange, the first device may be considered a master device.

[0070] Referring to Figure 2b, in a scenario where the master actively triggers data block exchange, the second device may be considered the master device and the first device may be considered the slave device. Specifically, in response to the master device having a second valid data block that needs to be exchanged, the master device sends a first-side trigger signal to the slave device, and the slave device receives the first-side trigger signal. Based on the first-side trigger signal, the slave device prepares a first-side data block for data interaction. Note that in response to the slave device having a valid data block that needs to be exchanged, the valid data block that needs to be exchanged is prepared as the first-side data block. In response to the slave device not having a valid data block that needs to be exchanged, an invalid data block is prepared as the first-side data block. It can be seen that the first-side data block contains either a valid data block or an invalid data block. After the completion of the data block on the first side, in a single data interaction process, the slave device sends the data block on the first side to the master device and receives the data block on the second side corresponding to the second valid data block sent by the master device. It can be seen that the exchange of valid data blocks between the master and slave devices is achieved in a single data interaction process, reducing the number of data exchanges between the master and slave devices and improving data transmission efficiency. Note that in scenarios where the master actively triggers the data block exchange, the trigger signal on the first side may be considered as the TO_SLAVE pulse signal.

[0071] Referring to Figure 2c, in a scenario where the slave actively triggers a data block exchange, the first device may be considered the master device and the second device may be considered the slave device. Specifically, the slave device prepares a second valid data block that needs to be exchanged, the slave device sends a trigger signal to the master device, and the master device receives the trigger signal. Based on the trigger signal, the master device prepares a first-side data block for data interaction. Note that in response to the master device having a valid data block that needs to be exchanged, the valid data block that needs to be exchanged is prepared as the first-side data block. In response to the master device not having a valid data block that needs to be exchanged, an invalid data block is prepared as the first-side data block. It can be seen that the first-side data block contains either a valid data block or an invalid data block. After the completion of the first side's data block, in a single data interaction process, the master device sends the first side's data block to the slave device and receives the second side's data block, corresponding to the second valid data block sent by the slave device. This allows for the exchange of valid data blocks between the master and slave devices in a single data interaction process, reducing the number of data exchanges and improving data transmission efficiency. Note that in scenarios where the slave actively triggers the data block exchange, the trigger signal on the first side may be considered a TO_MASTER pulse signal.

[0072] In a scenario where both the master and slave simultaneously trigger a data block exchange, the data interaction process and timing are the same as in a scenario where the master actively triggers the data block exchange, and this is not repeated.

[0073] According to the SPI-based data transmission method, data exchange between the first and second devices can be completed through a single data interaction, and simultaneous transmission of master and slave data is achieved. The timing control logic is simple, and there are no bus contention issues.

[0074] In some embodiments, the preparation of the data block on the first side based on a trigger signal on the first side may include determining in response to the trigger signal on the first side whether the first device has a first valid data block that needs to be replaced, if the first device has a first valid data block, preparing the first valid data block as the data block on the first side, and if the first device does not have a first valid data block, preparing an invalid data block as the data block on the first side.

[0075] Specifically, in response to the first device receiving a trigger signal on the first side transmitted by the second device, the first device determines whether the transmit buffer has data. If the transmit buffer has data, it indicates that the first device has a first valid data block that needs to be replaced. If the transmit buffer does not have data, it indicates that the first device does not have a first valid data block that needs to be replaced. If the first device has a first valid data block, it prepares the first valid data block as the first side data block. If the first device does not have a first valid data block, it prepares an invalid data block as the first side data block.

[0076] Referring to Figure 3a, in a scenario where the master actively triggers a data block exchange, the second device may be considered the master device and the first device may be considered the slave device. The trigger signal on the first side may be considered the TO_SLAVE pulse signal. Specifically, in a scenario where the master is idle with data blocks to be transmitted, the slave device receives the TO_SLAVE pulse signal transmitted by the master device. In response to the TO_SLAVE pulse signal, the slave device determines whether it has a first valid data block that needs to be exchanged. If the slave device has a first valid data block, it prepares the first valid data block as the data block on the first side. If the slave device does not have a first valid data block, it prepares an invalid data block as the data block on the first side.

[0077] Referring to Figure 3b, in a scenario where the slave actively triggers a data block exchange, the first device may be considered the master device, the second device may be considered the slave device, and the trigger signal on the first side may be considered the TO_MASTER pulse signal. Specifically, the master device receives the TO_MASTER pulse signal transmitted by the slave device. In response to the TO_MASTER pulse signal, the master device determines whether it has a first valid data block that needs to be exchanged. If the master device has a first valid data block, it prepares the first valid data block as the data block on the first side. If the master device does not have a first valid data block, it prepares an invalid data block as the data block on the first side.

[0078] In the embodiment, in response to the first device having a valid data block that needs to be replaced, the valid data block to be replaced is prepared as a data block on the first side, and thus, in a single data interaction process, data exchange between a valid data block on the first side and a valid data block on the second side is achieved between the first device and the second device. In response only to the first device not having a valid data block that needs to be replaced, data exchange between an invalid data block and a valid data block on the second side is performed between the first device and the second device. The data transmission process is simplified and data transmission efficiency is improved.

[0079] In some embodiments, the first device has a first transmit buffer and a second transmit buffer, and preparing the first valid data block as the first side data block includes preparing the first side data block by writing the first valid data block from the first transmit buffer to the second transmit buffer.

[0080] Specifically, the first device has a first transmit buffer and a second transmit buffer. The first valid data block is stored in the first transmit buffer of the first device, and in response to a trigger signal on the first side, the first device writes the first valid data block in the first transmit buffer to the second transmit buffer to prepare the data block on the first side for transmission to the second device.

[0081] In a scenario where the master actively triggers the data block exchange, the second device may be considered the master device and the first device may be considered the slave device. The trigger signal on the first side may be considered the TO_SLAVE pulse signal. The slave device has a driver layer and a data link module, the data link module has a first transmit buffer and the driver layer has a second transmit buffer. The first transmit buffer of the data link module has a first valid data block, and in response to the TO_SLAVE pulse signal, the slave device writes the first valid data block from the first transmit buffer of the data link module to the second transmit buffer of the driver layer to prepare the data block on the first side for transmission to the master device.

[0082] In a scenario where the slave actively triggers the data block exchange, the first device may be considered the master device and the second device may be considered the slave device. The trigger signal on the first side may be considered the TO_MASTER pulse signal. Specifically, the master device has a driver layer and a data link module, the data link module has a first transmit buffer and the driver layer has a second transmit buffer. The first transmit buffer of the data link module has a first valid data block, and in response to the TO_MASTER pulse signal, the master device writes the first valid data block from the first transmit buffer of the data link module to the second transmit buffer of the driver layer to prepare the data block on the first side for transmission to the slave device.

[0083] In this embodiment, in response to the first device having a valid data block that needs to be replaced, the valid data block that needs to be replaced is prepared as a data block on the first side, and thus, in a single data interaction process, data exchange between the valid data block on the first side and the valid data block on the second side is achieved between the first device and the second device.

[0084] In some embodiments, preparing an invalid data block as a data block on the first side includes preparing the data block on the first side by writing an invalid data block of a predetermined length to a second transmit buffer.

[0085] Specifically, the exchange of data blocks of a predetermined length is completed between the first device and the second device. Since the first transmit buffer of the first device has no data, custom invalid characters may be padded into the data blocks of the second transmit buffer according to a predetermined length, i.e., invalid data blocks of a predetermined length are written to the second transmit buffer. The first device prepares invalid data blocks of a predetermined length as data blocks on its side.

[0086] In a scenario where the master actively triggers the data block exchange, the second device may be considered the master device and the first device may be considered the slave device. The trigger signal on the first side may be considered the TO_SLAVE pulse signal. The slave device has a driver layer and a data link module, the data link module has a first transmit buffer and the driver layer has a second transmit buffer. The first transmit buffer of the data link module does not have a first active data block, and in response to the TO_SLAVE pulse signal, the slave device writes an invalid data block of a predetermined length to the second transmit buffer to prepare the data block on the first side for transmission to the master device.

[0087] In a scenario where the slave actively triggers the data block exchange, the first device may be considered the master device and the second device may be considered the slave device. The trigger signal on the first side may be considered the TO_MASTER pulse signal. Specifically, the master device has a driver layer and a data link module, the data link module has a first transmit buffer and the driver layer has a second transmit buffer. The first transmit buffer of the data link module does not have a first valid data block, and in response to the TO_MASTER pulse signal, the master device writes an invalid data block of a predetermined length to the second transmit buffer to prepare the data block on the first side for transmission to the slave device.

[0088] In this embodiment, data exchange between invalid data blocks and valid data blocks on the second side is performed between the first and second devices in response only to the first device not having any valid data blocks that need to be replaced. The data transmission process is simplified and data transmission efficiency is improved.

[0089] In some embodiments, determining whether a first device has a first valid data block that needs to be replaced includes determining whether a first transmit buffer has a first valid data block, determining if the first transmit buffer has a first valid data block, determining if the first device has a first valid data block that needs to be replaced, and determining if the first transmit buffer does not have a first valid data block that needs to be replaced.

[0090] Specifically, the first device has a first transmit buffer and a second transmit buffer. In response to the first device receiving a first-side trigger signal transmitted by the second device, the first device determines whether the first transmit buffer has data. If the first transmit buffer has data, it indicates that the first device has a first valid data block that needs to be replaced. If the first transmit buffer does not have data, it indicates that the first device does not have a first valid data block that needs to be replaced.

[0091] In a scenario where the master actively triggers a data block exchange, the second device may be considered the master device, and the first device may be considered the slave device. The trigger signal on the first side may be considered the TO_SLAVE pulse signal. The slave device has a data link module, and the data link module has a first transmit buffer. In response to the TO_SLAVE pulse signal, the slave device determines whether the first transmit buffer of the data link module has a first valid data block. If the first transmit buffer of the data link module has a first valid data block, it is determined that the slave device has a first valid data block that needs to be exchanged. If the first transmit buffer of the data link module does not have a first valid data block, it is determined that the slave device does not have a first valid data block that needs to be exchanged.

[0092] In a scenario where the slave actively triggers a data block exchange, the first device may be considered the master device and the second device may be considered the slave device. The trigger signal on the first side may be considered the TO_MASTER pulse signal. Specifically, the master device has a data link module, and the data link module has a first transmit buffer. In response to the TO_MASTER pulse signal, the master device determines whether the first transmit buffer of the data link module has a first valid data block. If the first transmit buffer of the data link module has a first valid data block, it is determined that the master device has a first valid data block that needs to be exchanged. If the first transmit buffer of the data link module does not have a first valid data block, it is determined that the master device does not have a first valid data block that needs to be exchanged.

[0093] In some embodiments, referring to Figure 4a, the method may further include the following steps before the first valid data block is written from the first transmit buffer to the second transmit buffer:

[0094] S410. The message to be sent is retrieved.

[0095] S420. The message is encapsulated in multiple data frames.

[0096] S430. Multiple data frames are written to a data block.

[0097] S440. The data block is buffered in the first transmit buffer.

[0098] The communication layer of the first device includes a data link module and a transmission module. The transmission module has a link list buffer for sending data messages, and the data link module has a first transmit buffer. Data messages from the application layer are sent to the data link layer. The link list buffer for sending data messages is configured to buffer the data messages being sent. The data link module encapsulates the data messages being sent into a data frame, writes the data frame into a data block, and writes the data block into the first transmit buffer of the data link module.

[0099] For example, the driver layer may complete the exchange of a 1280-byte data block in one go. The transmit and receive buffers of the driver layer may be 1280 bytes in size. The 1280-byte data block is initially filled with message frames (data frames or acknowledgment frames) until exactly 1280 bytes are filled. In response to the inability to completely fill 1280 bytes, invalid frames or invalid data are filled in according to the remaining space size. The transmit and receive data distribution scenarios of the driver layer are shown in the table below. [Table 4]

[0100] In a scenario where the master actively triggers data block exchange, the second device may be considered the master device and the first device may be considered the slave device. Specifically, the communication layer of the slave device includes a data link module and a transmission module, the transmission module of the slave device having a data message transmission link list buffer. The data link module of the slave device has a first transmit buffer, and the slave device encapsulates the data message to be transmitted in a data frame, writes the data frame to a data block, and writes the data block to the first transmit buffer of the data link module of the slave device.

[0101] In a scenario where the slave actively triggers data block exchange, the first device may be considered the master device and the second device may be considered the slave device. Specifically, the communication layer of the master device includes a data link module and a transmission module, the transmission module of the master device having a data message transmission link list buffer. The data link module of the master device has a first transmit buffer, and the master device encapsulates the data message to be transmitted in a data frame, writes the data frame to a data block, and writes the data block to the first transmit buffer of the data link module of the master device.

[0102] In some embodiments, the first device further comprises a first receive buffer and a second receive buffer, and the reception of a second-side data block corresponding to a second valid data block transmitted by the second device includes receiving the second-side data block into the first receive buffer and writing the second-side data block from the first receive buffer to the second receive buffer.

[0103] Specifically, the first device has a first receive buffer and a second receive buffer. The second device sends a second-side data block to the first device, the first device receives the second-side data block and writes the second-side data block to the first receive buffer of the first device, and the first device writes the second-side data block from the first receive buffer to the second receive buffer.

[0104] In a scenario where the master actively triggers the data block exchange, the second device may be considered the master device and the first device may be considered the slave device. The slave device has a driver layer and a data link module, the data link module has a second receive buffer and the driver layer has a first receive buffer. The master device sends the data block from the second side to the slave device, the slave device receives the data block from the second side into the first receive buffer of the driver layer and writes the data block from the second side from the first receive buffer of the driver layer to the second receive buffer of the data link module.

[0105] In a scenario where the slave actively triggers the data block exchange, the first device may be considered the master device and the second device may be considered the slave device. The master device has a driver layer and a data link module, the data link module has a second receive buffer and the driver layer has a first receive buffer. The slave device sends the data block from the second side to the master device, the master device receives the data block from the second side into the first receive buffer of the driver layer and writes the data block from the second side from the first receive buffer of the driver layer to the second receive buffer of the data link module.

[0106] In some embodiments, the method further includes clearing the second transmit buffer and the first receive buffer in response to the completion of writing the second side data block to the second receive buffer.

[0107] Specifically, the first device transmits a data block from the first side to the second device, and simultaneously, the first device receives a data block from the second side transmitted by the second device. The first device writes the data block from the second side to its second receive buffer. Once the writing of the data block from the second side to the second receive buffer is complete, it indicates that the first device has completed receiving the data block from the second side transmitted by the second device, i.e., the exchange of data blocks between the first and second devices is complete, and the first receive buffer and the second transmit buffer can be cleared.

[0108] In a scenario where the master actively triggers the data block exchange, the second device may be considered the master device and the first device may be considered the slave device. The slave device has a driver layer and a data link module, the data link module has a first transmit buffer and a second receive buffer, and the driver layer has a second transmit buffer and a first receive buffer. The first transmit buffer of the data link module has a first valid data block, and in response to the TO_SLAVE pulse signal, the slave device writes the first valid data block from the first transmit buffer of the data link module to the second transmit buffer of the driver layer, and the slave device sends the first side data block in the second transmit buffer to the master device. Simultaneously, the slave device receives the second-side data block transmitted by the master device, receives the second-side data block into the first receive buffer of the driver layer, and writes the second-side data block from the first receive buffer of the driver layer to the second receive buffer of the data link module. In response to the completion of writing the second-side data block to the second receive buffer, the first-side data block in the second transmit buffer and the second-side data block in the first receive buffer are cleared.

[0109] In a scenario where the slave actively triggers the data block exchange, the first device may be considered the master device and the second device may be considered the slave device. The master device has a driver layer and a data link module, the data link module has a first transmit buffer and a second receive buffer, and the driver layer has a second transmit buffer and a first receive buffer. The first transmit buffer of the data link module has a first valid data block, and in response to the TO_MASTER pulse signal, the master device writes the first valid data block from the first transmit buffer of the data link module to the second transmit buffer of the driver layer, and the master device transmits the first side data block in the second transmit buffer to the slave device. Simultaneously, the master device receives the second-side data block transmitted by the slave device, receives the second-side data block into the first receive buffer of the driver layer, and writes the second-side data block from the first receive buffer of the driver layer to the second receive buffer of the data link module. In response to the completion of writing the second-side data block to the second receive buffer, the first-side data block in the second transmit buffer and the second-side data block in the first receive buffer are cleared.

[0110] In some embodiments, the first device is an SPI slave device and the second device is an SPI master device. After the data block on the first side has been prepared based on a trigger signal on the first side, the method further includes sending a trigger signal on the second side to the second device to cause the second device to prepare a second valid data block as a data block on the second side.

[0111] Specifically, in response to the second device having a second valid data block that needs to be replaced, the second device sends a trigger signal to the first device, and the first device receives the trigger signal. Based on the trigger signal, the first device prepares the first-side data block for data interaction. After the preparation of the first-side data block is complete, the first device sends a trigger signal to the second device, and the second device prepares the second valid data block as the second-side data block based on the trigger signal.

[0112] For example, in response to an SPI master device having a second valid data block that needs to be replaced, the SPI master device sends a TO_SLAVE pulse signal to the SPI slave device, and the SPI slave device receives the TO_SLAVE pulse signal. Based on the TO_SLAVE pulse signal, the SPI slave device prepares the first-side data block for data interaction. After the preparation of the first-side data block is complete, the SPI slave device sends a TO_MASTER pulse signal to the SPI master device, and based on the TO_MASTER pulse signal, the SPI master device prepares the second valid data block as the second-side data block.

[0113] In some embodiments, in response to determining that the reception of the data block on the second side is complete, the method further includes subtracting 1 from the current number of receptions of the trigger signal on the first side.

[0114] In response to the determination that a trigger signal on the first side has been received, the method further includes adding 1 to the current number of times the trigger signal on the first side has been received. Similarly, preparing a data block on the first side based on a trigger signal on the first side includes preparing a data block on the first side in response that the current number of times the trigger signal on the first side has been received is greater than 0.

[0115] Specifically, the first device records the number of times the trigger signal on the first side has been received. In response to the first device completing the reception of the data block on the second side, the data exchange state of the first device may be released, and the first device may enter a data-ready state for receiving the data block, and therefore the current number of times the trigger signal on the first side has been received is deducted by 1.

[0116] In response to the first device determining that a trigger signal from the first side has been received, the current count of the trigger signal from the first side is incremented by 1 to reduce collisions on the bus, and the current count of the trigger signal from the first side indicates the data exchange state of the first device. If the current count of the trigger signal from the first side is greater than 0, it indicates that a trigger signal from the first side has been received, and a data block from the first side may be prepared.

[0117] For example, the slave side may execute an interrupt handling flow after the data block exchange is complete. Referring to Figure 4b, which shows the TO_SLAVE pulse signal reception interrupt handling flow. Specifically, the handling flow includes recording the number of data block exchanges triggered by the master side and received by the slave side, and calling a slave-side thread that is specially configured to handle scenarios in which the master side actively triggers a data block exchange.

[0118] For example, the slave side has a scenario thread in which the master side actively triggers a data block exchange. That is, in a scenario in which the master side actively triggers a data block exchange, the thread is responsible for exchanging data blocks with the master side. Referring to Figure 4c, Figure 4c shows the processing flow of the scenario thread in which the master side actively triggers a data block exchange. Specifically, the processing flow includes taking a fixed-length data block from the data link module of the communication layer in response to the slave side having data and writing the data block to the transmit buffer of the driver layer, writing a fixed-length invalid data block to the transmit buffer of the driver layer in response to the slave side not having data, waiting for the physical layer to complete the exchange of fixed-length data blocks, and processing and recording the number of data block exchanges triggered by the master side and received by the slave side (i.e., the count should be deducted by 1 each time an exchange is completed).

[0119] For example, the slave side has a scenario thread that actively triggers a data block exchange, i.e., in a scenario where the slave side actively triggers a data block exchange, the thread is responsible for exchanging data blocks with the master side. Referring to Figure 4d, Figure 4d shows the processing flow of the scenario thread where the slave side actively triggers a data block exchange. Specifically, the processing flow includes, in response to the slave side having data, retrieving a fixed-length data block from the data link module of the communication layer and writing the data block to the transmit buffer of the driver layer; in response to the slave side not having data, writing a fixed-length invalid data block to the transmit buffer of the driver layer; and waiting for the physical layer to complete the exchange of fixed-length data blocks.

[0120] In some embodiments, the SPI slave is configured to have a first thread and a second thread. The first thread is configured to receive a trigger signal on the first side, prepare a data block on the first side, transmit a data block on the first side, and receive a data block on the second side. The second thread is configured to prepare a valid data block as a slave-side data block in response to the SPI slave device having a valid data block that needs to be replaced, and to send a master-side trigger signal to the SPI master device after the slave-side data block is prepared, causing the SPI master device to prepare a master-side data block, and the first and second threads are controlled by a mutual exclusion lock.

[0121] An SPI slave device is configured to have a first thread for handling flows in which the master actively triggers a data block exchange, and a second thread for handling flows in which the slave actively triggers a data block exchange. In flows in which the master actively triggers a data block exchange, the SPI slave device receives a trigger signal from the first side, prepares a data block from the first side, transmits the data block from the first side, and receives a data block from the second side through the first thread. In flows in which the slave actively triggers a data block exchange, in response to the SPI slave device having a valid data block that needs to be exchanged, the SPI slave device prepares the valid data block as a slave-side data block through the second thread. After preparing the slave-side data block, a master-side trigger signal is sent to the SPI master device through the second thread to cause the SPI master device to prepare a master-side data block based on the master-side trigger signal. The first and second threads are controlled by adding mutual exclusion locks to ensure that only one thread can participate in data block exchange at a time.

[0122] In some embodiments, the first device is an SPI master device, and the second device is an SPI slave device, the second device having a third transmit buffer and a fourth transmit buffer. In response to the second device having a second valid data block that needs to be replaced, the second device writes the second valid data block from the third transmit buffer to the fourth transmit buffer, and then transmits a trigger signal to the first side.

[0123] In a scenario where the slave actively triggers the data block exchange, the second device is an SPI slave device and the first device is an SPI master device. In response to the SPI slave device completing data preparation, the SPI slave device sends a trigger signal to the SPI master device on the first side. Specifically, the second device has a third transmit buffer and a fourth transmit buffer. It is determined whether the third transmit buffer of the second device has a second valid data block, and if it does, it indicates that the second device has a second valid data block that needs to be exchanged. Furthermore, the second device writes the second valid data block from the third transmit buffer to the fourth transmit buffer, at which point the second device has completed data preparation and may send a trigger signal to the first device on the first side.

[0124] For example, in a scenario where the slave actively triggers a data block exchange, the first device may be considered a master device and the second device may be considered a slave device. The master device has a driver layer and a data link module, the data link module has a third transmit buffer and the driver layer has a fourth transmit buffer. The third transmit buffer of the data link module has a second valid data block, and in response to the TO_SLAVE pulse signal, the master device writes the second valid data block from the third transmit buffer of the data link module to the fourth transmit buffer of the driver layer, and the master device transmits the second-side data block in the fourth transmit buffer to the slave device. At the same time, the master device receives the first-side data block transmitted by the slave device, the master device receives the first-side data block in the third receive buffer of the driver layer, and writes the first-side data block from the third receive buffer of the driver layer to the fourth receive buffer of the data link module. In response to the completion of writing the second-side data block to the fourth receive buffer, the second-side data block in the fourth transmit buffer and the first-side data block in the third receive buffer are cleared.

[0125] One embodiment of this description provides an SPI-based data transmission method applicable to an SPI communication system including a first device and a second device. Referring to Figure 5, the method may include the following steps.

[0126] S510. The second device transmits a trigger signal to the first side based on the second valid data block that needs to be replaced.

[0127] S520. The second device prepares the second valid data block as the data block on the second side.

[0128] S530. The first device receives a trigger signal from the first side transmitted by the second device, and prepares a data block from the first side based on the trigger signal from the first side, the data block from the first side including an active data block or an invalid data block.

[0129] S540. The first device transmits the data block from the first side to the second device.

[0130] S550. The second device transmits the data block from the second side to the first device.

[0131] In some embodiments, the first device is an SPI master device, the second device is an SPI slave device, and the second device has a third transmit buffer and a fourth transmit buffer. Referring to Figure 6, the preparation of the second device as a second valid data block on the second side includes the following:

[0132] S610. The second device prepares the data block on the second side by writing the second valid data block from the third transmit buffer to the fourth transmit buffer.

[0133] The second device transmitting a trigger signal to the first side based on a second valid data block that needs to be replaced includes the following:

[0134] S620. In response that the second device has a second valid data block that needs to be replaced, the second device writes the second valid data block to the fourth transmit buffer and then transmits the trigger signal to the first side.

[0135] Embodiments of this description provide a chip including memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor performs the method according to any one of the embodiments in response to the execution of the computer program.

[0136] Embodiments of this description provide a computer-readable storage medium for storing computer instructions or programs that cause a computer to perform a method according to any one of the embodiments in response to being executed on the computer.

[0137] The embodiments described herein provide a controller including a first chip and a second chip, the first chip and the second chip being connected by an SPI bus.

[0138] The second chip is configured to transmit a trigger signal to the first side based on a second valid data block that needs to be replaced.

[0139] The second chip is further configured to prepare a second valid data block as a data block on the second side.

[0140] The first chip is configured to receive a trigger signal from the first side transmitted by the second chip and to prepare a data block from the first side based on the trigger signal from the first side, the data block from the first side including an active data block or an invalid data block.

[0141] The first chip is further configured to transmit data blocks from the first side to the second chip.

[0142] The second chip is further configured to transmit the data blocks from the second side to the first chip.

[0143] In some embodiments, referencing the Linux network communication framework makes the layering clearer and more specific. Depending on changes in the underlying hardware, only the relevant code in the physical and driver layers needs to be adapted; the higher communication layers do not need to be significantly modified. The higher-layer application can choose reliable or unreliable transmission depending on the actual situation. In reliable transmission scenarios, a message acknowledgment mechanism is introduced. Only messages that have been successfully acknowledged can be removed from the transmission module buffer; otherwise, a certain number of retransmission attempts are required. The higher-layer application can configure multiple transmission channels with priorities depending on the actual situation. The transmission module sequentially retrieves messages from the transmission channels and transmits them sequentially according to their priority levels.

[0144] For example, the communication layer primarily implements the data link module and the transmission module, and on the SOC side, since the Linux operating system is adopted, an interface call module is also required to complete data transmission between user space and kernel space. The data link module primarily provides data block buffering, data block and frame encapsulation and parsing, frame checksum calculation and verification, and acknowledgment frame reply. The transmit and receive buffers of the data link module are configured to buffer the transmitted and received 1280-byte data blocks. In the solution, there are separate data block buffers for receiving and transmitting. The data block buffer is a first-in, first-out circular queue with a provisional queue depth of 12, which can simultaneously store 12 1280-byte data blocks. The transmit and receive buffers of the driver layer perform data interaction with the transmit and receive buffers (of the data link module). The data link module encapsulates the data message in the transmission module and the acknowledgment information in the acknowledgment information buffer list into data frames and acknowledgment frames, respectively. It then writes the frames into data blocks, fills the remaining space, and then writes the entire data block into the data link module's transmit buffer.

[0145] For example, regarding the parsing of data blocks and frames, the data link module retrieves the data block from the receive buffer, parses the data frames and acknowledgment frames within the data block, discards the padding frames directly, and then writes the data within the data frame to the transmission module's buffer. The parsed acknowledgment frames are then processed by the transmission module (either by deleting successfully transmitted messages or retransmitting failed messages).

[0146] The frame format of the data link module is illustrated, and in this example, there are three types of frames: data frames, acknowledgment frames, and padding frames. The data frame adds 6 bytes of information to the data payload to identify which application layer service the data belongs to, and adds information about the data fragment.

[0147] Message validation for the data link module is illustrated. In response to encapsulating a frame message, it is necessary to calculate the corresponding CRC value of the frame message. The methods for calculating and filling the frame header and payload CRCs for data frames, acknowledgment frames, and padding frames are shown in the table below. [Table 5]

[0148] In response to parsing a frame message, it is necessary to check the CRC value of the corresponding frame message. The process for checking the frame header and payload CRC values ​​of data frames, acknowledgment frames, and padding frames is shown in the table below. [Table 6]

[0149] The data link module is shown in an illustrative example to respond with an acknowledgment frame. In response to the receipt of a data frame message, if the data frame is a frame that requires reliable transmission, it must send an acknowledgment frame back to the sender after parsing, regardless of whether the parsing process was successful or unsuccessful (unreliable transmission data frame messages do not require an acknowledgment frame).

[0150] It is illustrated that the transmission module provides a reliable, real-time data message transmission service to the application layer and the data link module. The transmission module sends data messages to the corresponding priority channel according to the message priority and adds a retransmission mechanism to data messages transmitted on the reliable channel.

[0151] The transmission modes are illustrated. In the solution, priority 0 channels are reserved for the transmission of acknowledgment frames and padding frames. Priority channels 1 through 31 can be used for service data for the transmission of data messages. Based on the reliability of data message transmission, two transmission modes are designed: reliable transmission and unreliable transmission. Priority channels 1 through 31 can be configured to use which transmission mode to use via the is_reliable field. In unreliable transmission mode, as long as the transmission module encapsulates the data message and writes it to the data link module's buffer, the data message is considered successfully transmitted and is removed from the transmission module's corresponding priority channel. In reliable transmission mode, after the transmission module writes the data message to the data link module's buffer, the data message is not removed from the transmission module's corresponding priority channel. Before further processing, it must wait for an acknowledgment frame (ACK / NACK frame) returned by the receiving end. If an ACK frame is received by the receiving end, the receiving end is considered to have successfully received the data packet, and the data message is then removed from the corresponding priority channel of the transmission module. If a NACK frame is received by the receiving end, the receiving end is considered to have encountered an error in response to receiving the data message, and at this point, the transmitting end must retransmit the data message. After a certain number of retransmissions, the data message is removed from the corresponding priority channel of the transmission module. If the transmitting end does not receive an acknowledgment frame from the receiving end, the transmitting end retransmits the data message at regular transmission intervals. After a certain number of retransmissions, the data message is removed from the corresponding priority channel of the transmission module. The corresponding data message in the corresponding priority channel can be acknowledged through the priority field and sequence number field of the acknowledgment frame.

[0152] Priority transmission is illustrated as an example, where the transmission module provides a total of 31 data message transmission channels with priorities ranging from 1 to 31, each channel having a corresponding priority. Priorities decrease sequentially from 1 to 31. The transmission module prioritizes buffered data messages within the higher-priority transmission channels. For data messages with high real-time requirements, the data messages can be transmitted through the higher-priority channels.

[0153] An interface call module is shown as an example. Since the SOC uses the Linux operating system, another interface call module is required to perform data transmission between user space and kernel space. The technical solution is to implement an interface for sending data from user space to kernel space and an interface for sending data from kernel space to user space via netlink communication mode, thereby satisfying the data transmission requirements.

[0154] The application layer is illustrated, and the SOC and MCU implement the fragmentation functionality at the application layer. Fragmentation and recombination of long data are implemented. In response to the transmission of long data, the data is divided according to the maximum transmission length, and fragment-related fields are populated. Four fields need to be populated: Fragment Flag (FRAG FLAG), Message ID (MSG ID), Fragment Count (FRAG CNT), and Fragment ID (FRAG ID). In response to the receipt of fragmented data, the fragmented data is buffered at the application layer, and these four fields are used to check whether the fragments corresponding to the complete message have been collected and whether the complete data can be transmitted to the higher-level service.

[0155] It should be noted that logic and / or steps shown in a flowchart or otherwise described herein, such as an ordered list that may be considered executable instructions used to implement a logical function, may be specifically implemented in any computer-readable medium used by an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or another system that can obtain instructions from an instruction execution system, apparatus, or device and execute those instructions), or in combination with such an instruction execution system, apparatus, or device. In the context of this description, “computer-readable medium” may be any device that can store, communicate, propagate, or transmit programs, including programs used by or in combination with an instruction execution system, apparatus, or device. More specific examples (a non-exclusive list) of computer-readable media include electrical connections with one or more wires (electronic devices), portable computer diskettes (magnetic devices), random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber devices, and portable compact disk read-only memory (CDROM). In addition, computer-readable media may also be paper or other suitable media on which programs can be printed, for the reason that programs can be acquired electronically, for example, by optically scanning paper or other media and then, as necessary, editing, interpreting, or otherwise processing them, and then stored in computer memory.

[0156] It should be understood that some parts of this disclosure may be implemented by using hardware, software, firmware, or a combination thereof. In embodiments, multiple steps or methods may be carried out by using software or firmware stored in memory and executed by an appropriate instruction execution system. For example, as in another embodiment, when hardware is used for implementation, the implementation may be carried out by any or a combination thereof of technologies known in the art, such as discrete logic circuits including logic gate circuits for implementing logic functions for data signals, dedicated integrated circuits including an appropriate combination of logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0157] In this description, reference terms such as “one embodiment,” “several embodiments,” “one example,” “a specific example,” and “several examples” mean that a particular feature, structure, material, or property described in conjunction with an embodiment or example is included in at least one embodiment or example of this disclosure. In this description, illustrative descriptions of the aforementioned terms do not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or properties described may be combined in an appropriate manner in one or more embodiments or examples.

[0158] In addition, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or the quantity of the technical features described. Accordingly, features limited by “first” or “second” may expressly or implicitly include at least one such feature. In the description of this disclosure, unless expressly specified, “plural” means at least two, for example, two or three.

[0159] In this disclosure, unless expressly specified and limited, the terms “attach,” “connect,” “connect,” and “fix” should be understood broadly. For example, unless expressly specified, a connection may be a fixed connection, a detachable connection, or an integrated connection; a connection may be a mechanical connection or an electrical connection; or a connection may be a direct connection, an indirect connection via an intermediary, or an internal communication or interaction relationship between two elements. A person skilled in the art will be able to understand the specific meaning of the terms in this disclosure based on the particular context.

[0160] Although embodiments of the Disclosure have been shown and described above, it should be understood that these embodiments are illustrative and should not be construed as limiting the Disclosure. Those skilled in the art can modify, alter, substitute, or change the embodiments described above within the scope of the Disclosure.

Claims

1. An SPI-based data transmission method applied to a first device of an SPI communication system, Receiving a trigger signal from the first side transmitted by a second device in the communication system based on a second valid data block that needs to be replaced, Preparing the data block on the first side based on the trigger signal on the first side, wherein the data block on the first side comprises an active data block or an invalid data block. In one data interaction process, the data block on the first side is transmitted to the second device, and the data block on the second side corresponding to the second valid data block transmitted by the second device is received. A method that includes [a certain feature].

2. Preparing the data block on the first side based on the trigger signal on the first side is In response to the trigger signal on the first side, it is determined whether the first device has a first valid data block that needs to be replaced, If the first device has the first valid data block, the first valid data block is prepared as the data block on the first side, If the first device does not have the first valid data block, the invalid data block is prepared as the data block on the first side. The method according to claim 1, comprising:

3. The first device has a first transmit buffer and a second transmit buffer, and the first valid data block is prepared as the data block on the first side. The method according to claim 2, comprising writing the first valid data block from the first transmit buffer to the second transmit buffer to prepare the data block on the first side.

4. The invalid data block is prepared as the data block on the first side. The method according to claim 3, comprising writing the invalid data block of a predetermined length to the second transmit buffer to prepare the data block on the first side.

5. Determining whether the first device has a first valid data block that needs to be replaced is: Determining whether the first transmit buffer has the first valid data block, If the first transmit buffer has the first valid data block, it is determined that the first device has the first valid data block that needs to be replaced. If the first transmit buffer does not have the first valid data block, it is determined that the first device does not have the first valid data block that needs to be replaced. The method according to claim 3, comprising:

6. Before writing the first valid data block from the first transmit buffer to the second transmit buffer, Retrieving the message being sent, Encapsulating the aforementioned message into multiple data frames, The process involves writing the aforementioned multiple data frames to a data block, The data block is buffered in the first transmit buffer. The method according to claim 3, further comprising:

7. The first device further has a first receive buffer and a second receive buffer, and receives a second-side data block corresponding to the second valid data block transmitted by the second device, The data block on the second side is received into the first receive buffer, Writing the data block on the second side within the first receive buffer to the second receive buffer The method according to claim 3, comprising:

8. The method according to claim 7, further comprising clearing the second transmit buffer and the first receive buffer in response to the completion of writing the second side data block to the second receive buffer.

9. The first device is an SPI slave device, and the second device is an SPI master device. After preparing the data block on the first side based on the trigger signal on the first side, the method, The method according to any one of claims 1 to 8, further comprising transmitting a trigger signal from the second side to the second device to cause the second device to prepare the second valid data block as a data block on the second side.

10. In response to the determination that the reception of the data block on the second side has been completed, the method, The method further comprises subtracting 1 from the current number of receptions of the trigger signal on the first side, In response to the determination that the trigger signal on the first side has been received, the method, The method further comprises adding 1 to the current number of receptions of the trigger signal on the first side, Preparing the data block on the first side based on the trigger signal on the first side is The method according to claim 9, further comprising preparing a data block on the first side in response to the current number of receptions of the trigger signal on the first side being greater than zero.

11. The SPI slave device is configured to have a first thread and a second thread, The first thread is configured to receive a trigger signal from the first side, prepare a data block from the first side, transmit the data block from the first side, and receive a data block from the second side. The second thread is configured to, in response to the SPI slave device having a valid data block that needs to be replaced, prepare the valid data block as a slave-side data block, and after the slave-side data block is prepared, send a master-side trigger signal to the SPI master device to cause the SPI master device to prepare a master-side data block. The method according to claim 9, wherein the first thread and the second thread are controlled by mutual exclusion locks.

12. The method according to any one of claims 1 to 8, wherein the first device is an SPI master device, the second device is an SPI slave device, the second device has a third transmit buffer and a fourth transmit buffer, and in response to the second device having a second valid data block that needs to be replaced, the second device writes the second valid data block from the third transmit buffer to the fourth transmit buffer, and then transmits a trigger signal to the first side by the second device.

13. An SPI-based data transmission method applicable to an SPI communication system comprising a first device and a second device, The second device transmits a trigger signal to the first side based on a second valid data block that needs to be replaced. The second device prepares the second valid data block as a data block on the second side, The first device receives a trigger signal from the first side transmitted by the second device, and prepares a data block from the first side based on the trigger signal from the first side, wherein the data block from the first side comprises an active data block or an invalid data block. The first device transmits the data block on the first side to the second device, The second device transmits the data block on the second side to the first device. A method that includes [a certain feature].

14. The first device is an SPI master device, the second device is an SPI slave device, and the second device has a third transmit buffer and a fourth transmit buffer. The second device prepares the second valid data block as a data block on the second side. The second device prepares the data block on the second side by writing the second valid data block from the third transmit buffer to the fourth transmit buffer, The second device transmits a trigger signal to the first side based on the second valid data block that needs to be replaced. The method according to claim 13, wherein, in response to the second device having a second valid data block that needs to be replaced, the second device writes the second valid data block to the fourth transmit buffer and then transmits a trigger signal to the first side.

15. A chip comprising memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor performs the method according to any one of claims 1 to 12 in response to the execution of the computer program.

16. A computer-readable storage medium for storing computer instructions or programs that cause a computer to perform the method according to any one of claims 1 to 12 in response to being executed on the computer.

17. A controller comprising a first chip and a second chip, wherein the first chip and the second chip are connected by an SPI bus. The second chip is configured to transmit a trigger signal to the first side based on a second valid data block that needs to be replaced. The second chip is further configured to prepare the second active data block as a data block on the second side, The first chip is configured to receive a trigger signal from the first side transmitted by the second chip and to prepare a data block from the first side based on the trigger signal from the first side, wherein the data block from the first side comprises an active data block or an inactive data block. The first chip is further configured to transmit the data blocks on the first side to the second chip. A controller, wherein the second chip is further configured to transmit data blocks from the second side to the first chip.

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