Video transmission within mobile devices

Abstract

Video samples from one or more cameras of a mobile device are sent as analog levels to the device's system-on-a-chip (SoC) or other processor. Analog levels are either analog video samples or an encoded form of video samples. The samples are converted to digital and interpolated within the SoC to produce digital RGB samples suitable for display. Alternatively, analog video samples are interpolated within the SoC using analog processing to produce analog RGB samples. Or, only G-sampling is sent to the SoC and processed using analog processing. After processing within the SoC, the samples are sent as analog levels or in an encoded form to the corresponding receiver of the display, which is integrated with the column driver. The digital functions of the display's DDIC are either built into the SoC or connected to separate circuitry via a MIPI DSI interface.

Description

[Technical Field]

[0001] Cross-reference of related documents This application claims priority to U.S. Provisional Patent Application No. 63 / 516,220 (Attorney Reference No. HYFYP0017P), filed on 28 July 2023, and U.S. Provisional Patent Application No. 63 / 611,274 (Attorney Reference No. HYFYP0017P2), filed on 18 December 2023, both of which are titled "Video Transmission in Mobile Devices."

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 447,241 (Attorney Reference No. HYFYP0015P), filed on 21 February 2023, and U.S. Provisional Patent Application No. 63 / 500,341 (Attorney Reference No. HYFYP0015P2), filed on 5 May 2023, titled "Analog Video Transmission to Display Panel" and "Analog Video Transmission to Display Panel and Integration of Source Driver and Display Panel," respectively.

[0003] This application incorporates, by reference, the following documents: U.S. Application No. 15 / 925,123 (Attorney Reference No. HYFYP001) filed on 19 March 2018, U.S. Patent No. 10,158,396 issued on 18 December 2018, U.S. Application No. 16 / 494,901 (Attorney Reference No. HYFYP002) filed on 17 September 2019, and the application filed on 2 August 2022. U.S. Patent Application No. 17 / 879,499 (Attorney Reference Number HYFYP003), U.S. Patent Application No. 17 / 686,790 filed on March 4, 2022 (Attorney Reference Number HYFYP004AX1), U.S. Patent Application No. 17 / 887,849 filed on August 15, 2022 (Attorney Reference Number HYFYP006), U.S. Patent Application No. 17 / 851,821 filed on June 28, 2022 (Attorney Reference Number HYFYP003) U.S. Patent Application No. 18 / 448,330 (Attorney Reference No. HYFYP008), filed on August 11, 2023 (Attorney Reference No. HYFYP007), U.S. Patent Application No. 17 / 900,570 (HYFYP009), filed on August 31, 2022, U.S. Patent Application No. 17 / 946,479 (Attorney Reference No. HYFYP010), filed on September 16, 2022, filed on January 11, 2023 U.S. Patent Application No. 18 / 095,801 (Attorney Reference Number HYFYP011), U.S. Patent Application No. 18 / 098,612 (HYFYP013) filed on 18 January 2023, U.S. Patent Application No. 18 / 117,288 (Attorney Reference Number HYFYP014) filed on 3 March 2023, and U.S. Patent Application No. 18 / 442,491 (Attorney Reference Number HYFYP015) filed on the same date.

[0004] This invention generally relates to video transmission. More specifically, it relates to the transmission of video from a camera to a processor and from the processor to a display within a mobile device. [Background technology]

[0005] Image sensors, displays, and video processors are constantly competing to achieve larger formats, greater color depth, higher frame rates, and higher resolutions. Video transmission within mobile devices faces performance scaling bottlenecks that reduce throughput and degrade performance, while simultaneously consuming more cost and power than ever before. Eliminating these bottlenecks offers significant benefits.

[0006] For example, instead of the traditional single rear camera on a mobile device, new mobile devices can feature one or two front cameras in addition to two or three rear cameras (for higher dynamic range, depth sensing, etc.), allowing multiple cameras to operate and transmit video simultaneously. Furthermore, the resolution of these cameras is as high as the resolution of the display on the mobile device, and all of this puts stress on the interfaces between the camera and the processor, and between the processor and the display, resulting in more difficult and costly transmission of video within the mobile device. For instance, the display driver integrated circuit (DDIC) chip in a mobile phone is a hybrid chip that combines the functions of a timing controller and a display controller, and is a half-digital-half-analog chip with a digital-to-analog converter, making it complex to manufacture.

[0007] Therefore, in order to reduce the size, complexity, and cost of the components of mobile devices, new devices and technologies are desired to further simplify video transmission within mobile devices. [Overview of the Initiative]

[0008] To achieve the above and in accordance with the objectives of the present invention, a video transmission technology is disclosed that addresses the aforementioned shortcomings of the prior art.

[0009] A video signal is a list of luminance values. Maintaining precise fixed-bit width (i.e., digital) luminance values ​​is inefficient for video transmission, and since bit-precision reproduction of these luminance values ​​is not required, analog voltage values ​​offer a much larger dynamic range. Therefore, in embodiments of the present invention, the video signal is transmitted as an analog signal rather than as a digital signal. Also, instead of transmitting the video signal using the Mobile Industry Processor Interface (MIPI) standard within a portable device, embodiments use a novel video transmission that transmits encoded or unencoded analog samples.

[0010] In one embodiment, video samples from a camera sensor are held in the analog domain, transmitted to a system-on-a-chip (SoC), converted to digital for processing, and then transmitted to a display in the analog domain. Since the analog samples are displayed in the analog domain, a digital / analog hybrid DDIC chip in the display is not required. A digital-to-analog converter for converting video samples is not needed within the new DDIC of the display.

[0011] In another embodiment, analog samples from the sensor are sent to the SoC, processed in the analog domain, and sent to the display in the analog domain. No digital processing of the sampling is required in the SoC. In another embodiment, only G samples are sent from the sensor to the SoC. In yet another embodiment, two rows are read from the sensor at a time.

[0012] In any embodiment, the DDIC's functions may be divided into a DDIC-SD for the display and a DDIC-TCON for the SoC, separating the DDIC's timing controller (TCON) function from the display. Alternatively, the DDIC-TCON can be integrated into the SoC to further simplify connectivity and eliminate the MIPI interface. Advantages include reduced wiring between the camera and SoC, reduced wiring between the SoC and the display, reduced EMI and power consumption, and reduced clock rate.

[0013] The present invention, along with its further advantages, will be best understood by referring to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 shows a conventional video transmission technology within a mobile phone. [Figure 2A] Figure 2A shows improved video transmission within a mobile phone. [Figure 2B] Figure 2B shows improved video transmission in a mobile phone with a segmented DDIC. [Figure 3A] Figure 3A shows a more detailed diagram illustrating the transmission of analog video samples from the video source to the SoC. [Figure 3B] Figure 3B illustrates the transmission of analog video samples from a video source to the SoC, where only analog processing is used within the SoC, and only the green channel is transmitted. [Figure 3C] Figure 3C illustrates the transmission of analog video samples from a video source to an SoC, where only analog processing is used within the SoC, and the image sensor is read out in a different way. [Figure 4A] Figure 4A is a diagram illustrating in more detail the video transmission from the system-on-chip to the novel DDIC of the display using SAVT. [Figure 4B]Figure 4B is a diagram showing in more detail the video transmission from the system-on-chip using SSVT to the new DDIC of the display. [Figure 5A] Figure 5A shows the architecture of the SAVT transmitter in the mobile device. [Figure 5B] Figure 5B shows the architecture of the SAVT receiver in the mobile device. [Figure 6] Figure 6 is a diagram showing the architecture of the SAVT receiver where each amplifier drives an adjacent column and all control signals are processed by a single amplifier. [Figure 7] Figure 7 is a diagram showing the input of the SAVT receiver for interleaving multiple input amplifiers, thereby enabling the satisfaction of speed requirement items. [Figure 8] Figure 8 is the pixel transmission order showing how pixels and control signals are transmitted from the SAVT transmitter to the SAVT receiver. [Figure 9] Figure 9 is a diagram showing the input vector of the SAVT transmitter having a predetermined permutation providing a sub-pixel transmission sequence. [Figure 10A] Figure 10A is a diagram showing another embodiment of one of the SAVT receiving components of the DDIC of Figure 4A. [Figure 10B] Figure 10B is an overview of the sub-pixel order collected by the input amplifier of Figure 10A. [Figure 11] Figure 11 is a diagram showing the video transmission system in the mobile device. [Figure 12] Figure 12 is a logic block diagram of a specific implementation of the SSVT transmitter in the camera. [Figure 13] Figure 13 shows the block diagram of the SSVT receiver arranged in the SoC. [Figure 14] Figure 14 is a diagram showing in more detail the video transmission in the telephone of Figure 2A or 2B between the SoC using SSVT and the telephone. [Figure 15] Figure 15 is a diagram showing in more detail the SSVT receiver of the new DDIC. [Figure 16]Figure 16 shows an image sensor with a modified readout. [Figure 17] Figure 17 shows the color interpretation performed on a series of analog values ​​in the analog domain to generate an analog RGB signal. [Figure 18] Figure 18 shows an example illustrating how a signal sample (in this case, an analog value) is encoded within an encoder and then transmitted via an electromagnetic path. [Figure 19] Figure 19 shows a novel encoding technique applicable to signal samples, which are digital values. [Figure 20] Figure 20 shows the decoding of the analog input level encoded using the analog encoder described above. [Figure 21A] Figure 21A shows the use of an analog encoder and its corresponding analog decoder. [Figure 21B] Figure 21B illustrates the use of a digital encoder and its corresponding analog decoder. [Figure 21C] Figure 21C illustrates the use of a digital decoder to decode an encoded analog signal arriving via an electromagnetic path. [Figure 22] Figure 22 shows a simulation of the SSVT waveform transmitted via the electromagnetic path. [Modes for carrying out the invention]

[0015] With the increasing number of cameras on mobile devices and the higher resolution of those cameras and displays, it is understood that the digital interfaces used for video transmission from one or more cameras to a display are approaching their limits. Typically, these digital interfaces are MIPI CSI (Mobile Industry Processor Interface Camera Serial Interface) which transmits video from each camera to the mobile device's system-on-a-chip (SoC), and MIPI DSI (Mobile Industry Processor Interface Display Serial Interface) which transmits video from the mobile device's SoC to the display. Therefore, this digital interface (whether MIPI or another interface) will be replaced with analog video transmission between the camera and the SoC, and between the SoC and the display. The analog video samples may or may not be encoded.

[0016] Furthermore, while each image sensor (i.e., each camera) currently senses analog values, these analog values ​​are converted to digital, transmitted to the SoC, processed, and then sent to the display, where they are converted back to analog values ​​and displayed on the mobile device screen. Performing analog-to-digital conversion within each camera module takes up space and increases the cost of that module, but this conversion can be done more efficiently within the SoC. Moreover, while the digital-to-analog conversion of video samples within the DDIC of existing mobile device technology may require thousands of digital-to-analog conversions, with our analog video transmission technology, these conversions can be performed much more efficiently within the SoC, requiring only a handful of DACs. Thus, our improved DDIC is closer to an analog device, does not require a DAC for video sampling conversion, and is simpler and cheaper.

[0017] Thus, analog video samples (which may or may not be encoded) are sent from one or more cameras to the SoC, converted to digital samples for processing within the SoC, converted back to analog samples after processing within the SoC, and then transmitted (which may or may not be encoded) from the SoC to an improved DDIC for display on the screen of a mobile device. Within the improved DDIC, digital-to-analog conversion of the video samples is not required. Alternatively, the analog samples are received by the SoC, processed in the analog domain, and transmitted to the improved DDIC for display. Digital processing of the analog samples is not required in the SoC.

[0018] <Previous video transmission technologies within mobile devices> Figure 1 illustrates conventional video transmission within a mobile phone 10. A typical mobile phone configuration is shown, comprising a rear camera module 12 with three lenses (or image sensors) and a front camera module 14 with two lenses (or image sensors). Each camera or image sensor requires thousands of analog-to-digital converters (ADCs) to convert analog video samples into digital video samples, and a dedicated MIPI CSI digital interface to transmit the digital video samples to the mobile phone's SoC 30. Therefore, the SoC requires a corresponding number of digital MIPI CSI interfaces (five in this example) to receive the digital video samples for processing. After processing, a digital MIPI DSI transmitter 36 transmits the digital video samples to the DDIC 40 on the display 50.

[0019] The DDIC 40 includes a corresponding digital MIPI DSI receiver 40 that receives digital video samples. Because the DDIC is an analog / digital hybrid chip, it includes numerous other components such as a power generator 61, oscillator 62, display RAM 63, timing controller 64, panel driver 65, and data driver output 66. When driving an LED display (such as an OLED display 50) as opposed to an LCD display, the DDIC 40 typically includes an image enhancement component 67. Notably, this DDIC includes the timing controller 64 and image enhancement component 67, thousands of DACs (not shown), and digital functions within the display RAM 63. This architecture for video transmission in mobile phones (including the MIPI interface, digital transmission between the camera and SoC and between the SoC and the display, ADC in the camera module, digital functions in the DDIC, and DAC in the DDIC) is disadvantageous for the reasons mentioned above. Typically, the DDIC is implemented in 28nm HV CMOS.

[0020] In short, considering the high refresh rates required by smartphone displays, implementing the DDIC40 inside a smartphone can be difficult due to the MIPI receiver, SRAM, digital image processing, and approximately 1,000 DACs.

[0021] <An architecture that improves video transmission within mobile devices> Figure 2A shows improved video transmission within the mobile phone 100. Selected components within the phone 100 are shown, including the display 150 along with the rear camera module 112, the front camera module 114, the SoC 130, and the associated improved DDIC 140. As is well known, a DDIC is essentially one large source driver IC that drives all the rows of a small display, such as in a mobile phone, and typically there is only one DDIC implemented on a single silicon chip per display. The mobile phone 100 may be any suitable portable device such as a mobile phone, cellular phone, portable tablet computer, or personal digital assistant. As an advantage, this architecture streamlines the mobile DDIC architecture. This architecture allows for an optimal division of TCON and DDIC by shifting the DDIC's SRAM and image processing to the SoC, and the simplified DDIC 140 is now entirely analog. Only a few DACs in the SoC are needed for the transmitter, and the number of wires from the SoC to the DDIC is also reduced. Compared to MIPI, this architecture offers lower clock rates, lower EMI, and lower power consumption. The processor 130 may be any suitable processor (e.g., a CPU) configured to implement the following embodiments, and does not necessarily have to be called a “SoC”.

[0022] The rear camera module 112 includes any number of cameras (or image sensors), typically one, two, or three. Similarly, the front camera module 114 includes any number of cameras (or image sensors), typically one or two. Furthermore, since analog samples are transmitted from each camera using a transmitter 120, neither the rear camera module nor the front camera module nor each camera requires a MIPI CSI digital interface. Each rear or front camera then uses the transmitter 120 to transmit a set of analog levels as one or more EM signals 125 to the corresponding receiver 132 on the SoC via a suitable electromagnetic path. The number of EM signals 125 emitted by each camera using the transmitter 120 depends on the type of transmitter used, bandwidth, frequency, and other implementation decisions. In an alternative embodiment, each rear or front camera module 112 or 114 aggregates analog samples from its multiple sensors (e.g., three sensors) and uses a single transmitter to transmit the aggregated analog samples to the receiver on the SoC. The receiver and the SoC then separate the streams.

[0023] Each transmitter 120 may be a sampling analog video transmission (SAVT) transmitter or a spread spectrum video transmission (SSVT) transmitter as disclosed below and incorporated by reference in the above-mentioned patent and patent application. Modules 112 or 114 may include or not include an ADC for converting analog video samples to digital samples, depending on the embodiment, as described later. Furthermore, since samples are transmitted using analog levels in each EM signal 125 from the transmitter to the corresponding receiver, neither the camera module, nor each camera, nor the SoC 130 requires a MIPI CSI digital interface.

[0024] The following provides a more detailed explanation of both SAVT and SSVT technologies for transmitting video samples. Essentially, SAVT transmits analog video samples directly, while SSVT encodes and transmits them. SAVT is typically used over short distances where electromagnetic interference (EMI) is not a concern, while SSVT is typically used over long distances where EMI can degrade video quality to an unacceptable level. SSVT may be used when the mobile device is operating in a noisy environment. Typically, all transmitters in the front and rear camera modules use either SAVT or SSVT, although it is also possible to mix both types of video transmission between different cameras. SAVT technology is sometimes referred to as "clocked analog video transmission" or CAVT.

[0025] The SoC130 includes receivers 132 corresponding to each transmitter 120 in either the rear or front camera module. Each SAVT transmitter 120 transmits to the corresponding SAVT receiver 132, and each SSVT transmitter 120 transmits to the corresponding SSVT receiver 132. Notably, a digital MIPI CSI receiver is not required within the SoC130. Each receiver 132 receives analog levels and outputs analog video samples. In some embodiments, an optional ADC per receiver can convert the output analog video samples into digital video samples for processing within the SoC. As shown, the timing controller 164, image enhancement component 167, and display RAM 163 have been moved to the improved SoC130 from the conventional DDIC in mobile phones. Implementing these digital functions within the SoC is more efficient than implementing them within the conventional DDIC.

[0026] The SoC also includes a transmitter 136 that sends one or more electromagnetic (EM) signals 135 to a corresponding receiver 142 in the new DDIC 140. In the case of a mobile phone as shown in the diagram, it is assumed that there is one transmitter 136 (more transmitters are possible) that sends two to a maximum of six EM signals 135. Typically, the electromagnetic path for each EM signal is twisted pair wire, but other paths such as wireless, cable, and optical are also possible. For example, in the case of SSVT Tx, 6 pairs of twisted wire can provide 550 Msps (megasamples / second), and 3 pairs can provide 1100 Msps, but even higher Msps are possible. In a typical portable device (such as a mobile phone), the analog DDIC 140 drives 2000 rows of display. That is, one transmitter and 6 pairs of twisted wire. Assuming 3 subpixels per row, the DDIC 140 would have 6,000 outputs. Although not shown in the illustration, in general, in small portable devices such as mobile phones, the DDIC140 includes a gate driver and directly drives the gates using techniques such as “in-panel” gate drivers.

[0027] Similar to transmitter 120, transmitter 136 may be a SAVT transmitter or an SSVT transmitter, depending on the implementation. In the case of a SAVT transmitter, the digital video samples processed by the SoC are distributed to the input vector and input to the DAC (as described later) before being transmitted as analog level 135, but it is also possible to convert the processed digital video samples to analog video samples before inputting them to the SAVT transmitter. In another embodiment, the analog video samples after analog processing by the SoC are distributed to the input vector of the SAVT transmitter and then transmitted as analog level 135. In the case of an SSVT transmitter, the digital video samples may be encoded in digital form and then input to the DAC (described later) before being transmitted as analog level 135, but it is also possible to convert the processed digital video samples to analog video samples, encode them in analog format, and then output them as analog level 135. In another embodiment, the analog video samples after analog processing by the SoC are input to the SSVT transmitter 136.

[0028] For SAVT between the camera and the SoC, the reference clock may be provided by the microprocessor of the camera or transmitter 120, or the clock may be provided by another signal. This reference clock is separate from the EM signal 125. In the case of SAVT from the SoC, the TCON 164 provides each of the SAVT receivers 142 with a separate reference clock 139 (separate from the EM signal 135 and not shown in this drawing for clarity). That is, the DDIC 140 has a clock input provided by the TCON. This reference clock may be at a relatively low frequency, for example, around 10.5 MHz. The reference clock 139 is also shown in Figures 4A and 6.

[0029] In the case of SSVT, each SSVT receiver 132 or 142 may include a clock recovery circuit, synchronization and capture circuit, or similar, to recover the reference clock and other timing signals in the receiver. There may be one such circuit in each receiver, or each decoder in the receiver may have such a circuit. The reference clock may be transmitted as a subband of sampling, or similarly, specifically to the EM signals 125, 135 (i.e., at the timing of the transmitted levels). Thus, since the reference clock is transmitted using the EM signals, there is no need to provide a separate line for the reference clock between the transmitter and the receiver.

[0030] The display 150 has an associated analog DDIC 140, which includes a receiver 142. As described above, if the transmitter is SAVT, the corresponding receiver is SAVT, and if the transmitter is SSVT, the corresponding receiver is SSVT. Similar to the prior art DDIC 40, the novel DDIC 140 is connected to and communicates with the display 150 using a well-known technique such as chip-on-glass (COG) or chip-on-film (COF) technology. Chip-on-plastic technology is also usable but is not preferred.

[0031] In particular, the analog DDIC 140 does not include either the digital functions of the timing controller 164 or the image enhancement component 167. Also, the display RAM 163 is within the SoC and not included in the DDIC 140. Implementing these three components within the digital SoC (process less than 5 nm) rather than within the DDIC is very cost-effective and allows the DDIC to be extended in a less expensive 65 nm process rather than in the expensive 28 nm process. As described above, the DDIC 140 does not include and does not require a DAC for the purpose of converting video samples. Advantageously, thousands of DACs (or equivalents) are not required within the DDIC 140, and only a handful of DACs are required within the SoC 130 for converting video samples from digital to analog or for converting levels from digital to analog (depending on the embodiment used).

[0032] FIG. 2B shows improved video transmission by a split DDIC within the mobile phone 100'. FIG. 2A above shows the digital functions of the DDIC integrated with the SoC. As an intermediate step, it is also possible to implement this digital function within a separate IC 136 together with a transmitter separate from the SoC 130'. The IC 136 includes the TCON function, SRAM, and image processing. The DDIC-SD 140 includes all the analog functions of the DDIC together with an integrated receiver. The MIPI DSI interface 137 only transmits digital samples over a short distance. Thus, the functions of the DDIC are split between the IC 136 and the IC 140. Similar to the above, in the case of SAVT, the TCON within the IC 136 supplies a separate reference clock 139 (not shown in this drawing) to each of the SAVT receivers 142.

[0033] <Video Transmission by Analog-Digital Conversion and Interpolation within the SoC> Figure 3A shows in more detail the transmission of analog video samples from a video source to an SoC using a SAVT or SSVT transmitter 120 and a SAVT or SSVT receiver 132 within system 820. Shown is a video source 822 that generates analog video samples 832. The video source 822 can be implemented in any device capable of acquiring imaging information, such as, but not limited to, a still camera, a video camera, an infrared imaging device, or other similar imaging device capable of generating video information. Typically, in a portable device, the video source 822 includes an image sensor semiconductor die containing an array and associated electronics. In this embodiment, the analog-to-digital conversion and interpolation of the video samples are performed within the SoC.

[0034] The image sensor 824 is any array capable of generating an electronic signal proportional to the amount of light measured. For example, the image sensor is a planar array of photodiodes. Each photodiode represents a pixel position in the planar array, and the number of photodiodes in the planar array can vary greatly and depend on the size of the image sensor. Typically, the video source 822 is implemented in each camera within the rear camera module 112 or the front camera module 114.

[0035] It should be noted that in this embodiment, since an analog-to-digital converter (ADC) is not required within the video source, the cost, required space, generated heat, and complexity of the video source are reduced. Transmission from the video source to the SoC is one or more (P) electromagnetic signals 125 with analog levels, i.e., P≧1. There is a trade-off between the analog bandwidth requirement and the number P of EM signals 125. A larger P reduces the bandwidth requirement, with the maximum bandwidth requirement being when P=1. Advantageously, in this embodiment, the analog-to-digital converter 837 or converter (ADC) is implemented within the SoC, which may be a different process from the image sensor and may be more power-efficient. While prior art 4K image sensors may require approximately 4,000 ADCs to convert digital video samples and output them to the SoC, the image sensor 824 does not require an ADC.

[0036] The output of array 824 is analog video samples 832. The image sensor 824 may be monochromatic or color. In the former case, the generated values ​​represent only one color. In the latter case, well-known filtering techniques using a color filter array (CFA), such as a Bayer filter, are commonly applied. Bayer filtering selectively covers individual photodiodes with a filter of a predetermined color (e.g., red, blue, or green), generating a color sample for each photodiode. Alternative embodiments may use CYGM (cyan, yellow, green, magenta), CYYM (cyan, yellow, yellow, magenta), RYYB, RGBW, RCCC, RCCB, and other types of filtering. Regardless of the type of filter used, the magnitude of the filtered light is measured at each sample position. The output is a continuous serial signal sequence of each analog video sample 832, representing a pixel in a row, frame by frame, from left to right, row-first, as far as the image sensor 824 is sensing. Of course, different orders can be used. When Bayer filtering is used, the output consists of lines of BGBG... followed by lines of RGRG..., and each 2x2 pattern contains one of each of RGGB, so it is often called the RGGB format.

[0037] The analog video sample 832 is input serially to the transmitter 120 and transmitted as an analog level. As previously mentioned and as will be described in more detail below, the transmitter 120 can use either SAVT or SSVT. Thus, the row of analog video sample 239d is input serially to the SAVT transmitter in Figure 5A, or sample 437d is input serially to the SSVT transmitter in Figure 12. In the case of SSVT, the analog level is the encoded representation of the analog video sample 832, and in the case of SAVT, the analog level is the analog video sample 832 itself. The transmitter 120 can be placed in any suitable location, such as within the die of the image sensor 824, within the camera or video source 822, or very close to the video source.

[0038] In either case, analog sample 832 from the SAVT transmitter is sent to the SAVT receiver 132 located within the SoC, or analog levels from the SSVT transmitter are sent to the SSVT receiver 132 located within the SoC. Thus, the row of analog video sample 239d is output 220 from the SAVT receiver in Figure 5B, or the row of sample 85d is serially output from the SSVT receiver in Figure 13.

[0039] Either the SAVT or SSVT receiver 132 may output analog video samples 836 corresponding to the input analog video samples 832. Any number of ADCs 837 convert these samples into digital video samples 838, which are then processed by the image signal processor (ISP) 160. This image signal processor 160 outputs digital video samples 162, processed for further manipulation by the SoC 130, before the video samples are transmitted to the display 150 of the mobile device via the SoC's transmitter 136 (described later). The samples may be converted serially by a single high-speed ADC, in parallel by multiple (e.g., 16) ADCs operating at a lower frequency after 16 samples are aggregated, or using other appropriate techniques. Once the video samples are received at the display 150, they are driven to the display using either the receiver in Figure 6 or the receiver in Figure 15, depending on whether SAVT or SSVT is used for transmission.

[0040] Since the sample is still raw data from the image sensor (i.e., the Bayer filter output from sensor 824), the ISP160 performs a "demosaic" process, also known as "demosaicing," using CFA interpolation to interpolate the "missing" color values ​​at each position to create an RGB sample for each pixel. In other words, given only single-color measurements for each pixel, the ISP algorithmically estimates the "missing" color values ​​to create, for example, an RGB or YCbCr representation of the pixel. A variety of advanced and established image processing algorithms are available to perform color interpolation, including nearest neighbor, linear, cubic, and cubic spline techniques. When using a color space different from RGB (i.e., a different color filter array), CFA interpolation is performed using a color interpolation table appropriate for that color space.

[0041] The ISP160 further applies gamma correction to each sample, performs tone curve mapping, level-shifts each gamma-corrected sample, maps a range from (0-255) to (-128-127) to remove the DC component from the signal, applies path-specific amplifier dispersion correction to each gamma-corrected and level-shifted sample, performs gain correction to each sample, performs offset adjustment to each sample, and performs demra correction to each sample. Additional corrections and adjustments may also be made depending on the sensor's dynamic range and target display. To prevent image processing of control signals within the line buffer, the timing and position of the control signals within the buffer are known, and the logic determines that image processing of the control signals should not be performed.

[0042] In an alternative embodiment, one or more ADCs may be integrated with or placed before either a SAVT receiver or an SSVT receiver, as described in more detail below, in which case the SSVT receiver uses digital decoding and ADC 837 is not required after receiver 132.

[0043] Advantageously, since the image processor 160 and associated digital logic are located within the SoC 130 rather than within the image sensor 824, the image sensor and its associated circuitry can be made smaller, less complex, and more power-efficient. Implementing the ADC and image processor within the SoC 130 is also cost-effective and yield-enhancing. Optionally, digital formatting may be performed after the ADC 837 and before the image processor.

[0044] <Analog-only video transmission from video source to display> This embodiment provides analog transmission of video samples from a video source to an SoC, where analog-only processing is then performed within the SoC, transmitted through the SoC, and finally sent to a display. Advantageously, once the video information is transmitted from the video source, a DAC, ADC, and digital processing are unnecessary.

[0045] The path for delivering the EM signal 125 from the video source to the display may be within the SoC 130' or externally via a separate path. The figure shows the path within the SoC. If the stream is required both within and outside the SoC, the stream may be split within the SoC to form a separate external path. In this case, the SSVT and SAVT transmitters 136 in Figures 4A and 4B are also located outside the SoC 130'.

[0046] Figure 3B illustrates the transmission of analog video samples from a video source to an SoC, using only analog processing within the SoC where only the green channel is transmitted. Similar to Figure 3A, system 820' has a video source 822 and an SoC 130'. As described above, the sensor 824 and transmitter 120 operate to transmit analog level 125 to the SoC 130'. However, within the SoC, the analog video samples are held in the analog domain and eventually transmitted to the display. No digital processing of the samples takes place within the SoC. Advantageously, this analog bypass circuit requires neither an ADC nor digital logic (and there is no need to convert the samples back to analog at any point), thus simplifying the circuit, preserving the quality of the original analog samples, and improving image latency. SoC130' may include this analog bypass exclusively for supplying analog samples to the display, or it may include the circuit of SoC130 shown in Figure 3A if it is desirable to use the SoC's digital logic for digitizing images, collecting statistics from images, analyzing images to control the camera (for example, returning exposure compensation to the camera), etc. If the digital circuit of SoC130 is also present in SoC130', the digital video sample 162 is not sent to the display (only the analog video sample 840 is sent) and is used only for statistics and analysis, etc.

[0047] In this embodiment, analog samples from sensor 824 are converted to digital by an ADC, and then “demosaic processing” is performed within the Image Signal Processor (ISP) to obtain digital RGB samples for each pixel. Only the green channel (i.e., one G sample per element of the array) is sent from the camera to the SoC 130' (using either SSVT or SAVT). Since the green channel corresponds to the luminance (or “luma”) channel, a monochrome image is displayed on the display, but there is no loss of perceived resolution. Furthermore, the image latency on the display is significantly reduced, providing immediate feedback to the viewer in applications using near-eye displays such as virtual reality and augmented reality.

[0048] Alternatively, since only the green channel is transmitted, interpolation is only required on the R and B elements of the sensor to obtain a G sample. If a G sample already exists and the R and B samples for that G element are not needed, interpolation on the G element is unnecessary. For example, Figure 16 shows an array of RGB filters, and path 915 contains four elements BGRG in the lower left corner. Since interpolation is only required on the R and B elements to obtain a G sample, the interpolation becomes simpler and faster.

[0049] Digital video samples (i.e., G samples only) are input to transmitter 120 and then transmitted as analog levels via one or more (P) electromagnetic signals 125. As previously mentioned and as will be described in more detail below, transmitter 120 can use SAVT or SSVT. Thus, digital video sample 239c is input to the SAVT transmitter in Figure 5A, or sample 437c is input to the SSVT transmitter in Figure 12. In the case of SSVT, the analog level is the encoded representation of the digital video sample, while in the case of SAVT, the analog level represents the digital video sample itself. Transmitter 120 can be placed in any suitable location, such as within the die of the image sensor 824, within the camera or video source 822, or very close to the video source.

[0050] In either case, the analog level from the SAVT transmitter is transmitted to the SAVT receiver 132' located within the SoC 130'. Alternatively, the analog level from the SSVT transmitter is transmitted to the SSVT receiver 132' located within the SoC. Thus, the row of G analog video sample 239c is output from the SAVT receiver in Figure 5B, or the row of G sample 85c is serially output from the SSVT receiver in Figure 13.

[0051] In this embodiment, the receiver 132' (and the path of these analog samples within the SoC) does not include an ADC and therefore outputs the original green analog video samples to the ASP839. Once these green analog video samples are received within the ASP839, tone curve mapping is used to maximize the use of the subpixel-specific dynamic range with respect to human brightness discrimination. The analog signal processor (ASP) 839 can also perform other analog signal processing, such as gamma correction, to prepare the G analog video samples for display on the display. Typically, SDR (Standard Dynamic Range) signals may be processed by the processor 839, and HDR (High Dynamic Range) signals may also be processed.

[0052] Advantageously, the ASP839 is located within the SoC130' rather than within the image sensor 824, thus making the image sensor and its associated circuitry smaller, less complex, and more power-efficient. Furthermore, implementing the ASP within the SoC130 results in greater cost-effectiveness and a better yield.

[0053] These green analog video samples are then (if desired) further manipulated within the SoC and finally transmitted to the display 150, as described below with reference to Figure 4A or Figure 4B. Once the green samples are received by the display 150, they are driven to the display using either the SAVT receiver in Figure 6 or the SSVT receiver in Figure 15, depending on whether SAVT or SSVT is used for transmission.

[0054] <Analog transmission only from image sensor to display> This embodiment provides analog transmission of video sampling from an image sensor to an SoC, where only analog processing is performed, and the data is transmitted via the SoC and finally sent to a display. Advantageously, once the video information is transmitted from the sensor, digital processing such as DAC, ADC, and sampling is not required.

[0055] The path for delivering the EM signal 125 from the video source to the display may be within the SoC 130'' or externally via a separate path. If the stream is required both within and outside the SoC, the stream may be split within the SoC to form a separate external path, in which case the SSVT and SAVT transmitters 136 in Figures 4A and 4B are also located outside the SoC 130''.

[0056] Figure 3C illustrates the transmission of analog video samples from a video source to an SoC, where the image sensor is read out in a different way and only analog processing is used within the SoC. Similar to Figure 3A, system 820'' has a video source 822 and an SoC 130''. However, in this embodiment, there is no ADC in the video source. In this second technique for processing the output from sensor 824, the image sensor is read out in a different way, resulting in raw information being dumped from the image sensor to the SoC. As will be explained in more detail in Figure 16, in this second technique, two rows of the array are read out at once to facilitate processing in the analog domain, for example, "demosaic processing" in the analog domain. Using this technique, the RGB samples of each G pixel are created by color interpolation that occurs in the analog signal processor 869 of the SoC. Furthermore, no DAC or ADC is required in the video source, transmitter, receiver, or within the SoC.

[0057] Figure 16 shows an image sensor with a modified readout. As shown, the image sensor includes a pixel array 902 consisting of any number of elements 904 arranged in rows and columns. A color filter, such as a Bayer color filter 906, is positioned above the pixel array 902 such that each element senses a specific color, for example, element 928 senses B or blue, as is known in the art. Prior art image sensors read each row once, resulting in a serial output such as BGBGBG.... This results in a continuous output such as RGRGRG (i.e., the bottom row is followed by the next row above it). Such an output results in a series of values ​​where R and B are never adjacent, making it difficult to perform color interpolation.

[0058] Therefore, we propose modifying the readout from the image sensor to read at least two rows simultaneously. Values ​​910 and 911 of the second row from the bottom are read simultaneously, and a serial stream of values ​​such as BGRGBGRG···916 or GBGRGBGR···918 is output. Path 915 indicates the readout order: first the blue value from the first row, then the green and red values ​​from the second row, followed by the green value from the first row, and so on, resulting in serial output 916. Path 917 indicates a different readout order: first the green value from the second row, then the blue and green values ​​from the first row, followed by the red value from the second row, and so on, resulting in serial output 918. Other readout orders may be used that mix color values ​​from two adjacent rows, and the order of pixel values ​​may vary depending on whether a particular row starts with a red, green, or blue value.

[0059] Since two rows are read at a time, a serial output is possible for each of the four values ​​in those two rows (for example, BG from the beginning of row 910 and GR from the beginning of row 911, i.e., two Gs, one R, and one B), resulting in a serial pattern such as BGRG... or GBGR... as shown in the diagram. After the first two rows are read, rows 912 and 913 are read, and so on. Each group of four values ​​can have other similar outputs containing two green values, one red value, and one blue value. The image sensor may be read starting from any particular corner, from top to bottom or bottom to top, by row or column, or in any other similar way. Thus, the output from the video source is a series of values ​​916, 918, or similar. "Demosaicing" is performed in the analog domain within the SoC using this series of values, without the need to convert these values ​​to digital or use digital processing.

[0060] This type of color value ordering facilitates interpolation in the analog domain. Other color spaces that read two or more rows at once and mix color values ​​from different rows in the serial output also facilitate color interpolation in the analog domain.

[0061] Returning to Figure 3C, the video source then outputs a pattern such as 916 or 918, which is indicated and referenced in the video source as "RGGB...". The RGGB video sample is input serially to the transmitter 120 and transmitted as an analog level. As previously mentioned, the transmitter 120 can use either SAVT or SSVT. Thus, analog video sample 239a is input to the SAVT transmitter in Figure 5A, or sample 437a is input to the SSVT transmitter in Figure 12. In the case of SSVT, the analog level is the encoded representation of the analog video sample, and in the case of SAVT, the analog level is the analog video sample itself. The transmitter 120 can be placed in any suitable location, such as within the die of the image sensor 824, within the camera or video source 822, or very close to the video source.

[0062] In either case, analog samples from the SAVT transmitter are transmitted to the SAVT receiver 132'' located within the SoC 130'', or analog levels from the SSVT transmitter are transmitted to the SSVT receiver 132'' located within the SoC via one or more (P) electromagnetic signals 125. Thus, analog video sample 239a is output from the SAVT receiver in Figure 5B, or sample 85a is serially output from the SSVT receiver in Figure 13.

[0063] In this embodiment, the receiver 132'' (and SoC) does not include an ADC for sample conversion, so it outputs the received analog video samples to the ASP869. Once these analog video samples are received within the ASP869, color interpretation is performed.

[0064] Figure 17 shows the color interpretation performed on a series of analog values ​​in the analog domain to generate an analog RGB signal. Shown is the output 916 from Figure 16, which is a series of analog values ​​for each of the four values, containing one R, two G, and one B. To generate the B and R values ​​corresponding to all G values, the B and R values ​​on either side of each G value are used, and B value 931 and R value 932 are generated at the location of the G value. For example, considering a sensor element 930 with a G filter and a corresponding G value, the B and R values ​​are taken from either side to generate a GBR value at the location of the sensor element 930. As shown, this interpolation is performed for all elements that have a G value, and thus an RGB signal is generated at each G value. This RGB signal is then sent to a display, which can produce full color, albeit at a low resolution.

[0065] The analog signal processor (ASP) 839 can also perform other analog signal processing, such as gamma correction, to prepare analog video samples for display on the display. Advantageously, since the ASP 869 is located within the SoC 130'' rather than within the video source 822, the image sensor and its associated circuitry can be made smaller, less complex, and more power-efficient. Furthermore, implementing the ASP within the SoC 130'' is more cost-effective and yields better results.

[0066] However, in an alternative embodiment, the interpolation may occur in a signal processor of the video source (not shown) rather than in the analog signal processor 869 of the SoC. In this embodiment, the image sensor 824 outputs a pattern such as 916 or 918, which is referred to as "RGGB..." above, to the analog signal processor of the video source. As described above with respect to FIG. 17, color interpolation in the analog domain is then performed on these RGGB video samples. Since the interpolation is performed for each element having a G value, an RGB signal is generated for each G value. This RGB signal is input to the SAVT or SSVT transmitter 120 for transmission to the SoC 130'' as the EM signal 125. In this embodiment, the ASP 869 may still be present for other processing of the RGB signal if desired.

[0067] The analog video samples 870 (regardless of whether they are interpolated within the video source 822 or within the ASP 869) are then further manipulated (if necessary) within the SoC and then ultimately transmitted to the display 150 as described later with reference to FIGS. 4A or 4B. When the samples are received at the display 150, they are driven to the display using either the receiver of FIG. 6 or the receiver of FIG. 15 depending on whether SAVT or SSVT is used for transmission.

[0068] For the B and R samples from each B and R element for which interpolation is not performed (e.g., the first and third columns of FIG. 17), they are simply discarded and not transmitted to the display, or are transmitted to the display and then ignored, displayed, or specific values (either specific to R or B or the same for each) that improve (or at least do not degrade) the display of the interpolated RGB signal are transmitted and displayed.

[0069] <SAVT Transmission from SoC to Display> Figure 4A shows in more detail the video transmission from the system-on-chip to a novel DDIC of the display using SAVT. After processing by SoC 130, 130', or 130'', the digital video sample 162 is input to the SAVT transmitter 136 (which includes any number of DACs to generate analog video samples for output). As previously mentioned, one or more DACs may precede the SAVT transmitter, in which case the DAC integrated into the SAVT transmitter is not required. In some embodiments, analog video samples 840 or 870 are input, in which case a DAC is not required. The SAVT transmitter outputs any number of electromagnetic signals 135 that transmit the analog video samples to the DDIC.

[0070] As shown, the DDIC 140 includes SAVT receivers 142 (shown in Figure 6 below as an array of any number of separate components 142a, b, c for ease of illustration), each receiving component 142 receiving one of the EM signals 135 and driving its corresponding column of the display. As previously mentioned, the SAVT receiver does not include a DAC for converting video samples. The reference clock 139 is generated at the TCON of the SoC (whether on the same IC or separate) and input to the DDIC 140, from which it is distributed to each receiver 142.

[0071] In the embodiment of Figure 3A, a digital video sample 162 (i.e., an interpolated digital RGB sample) is input to the SAVT transmitter 136 for transmission (shown as 239b in Figure 5A, where DACs 260-269 are used). In the embodiment of Figure 3B, an analog video sample 840 (i.e., only the green channel) is input to the transmitter for transmission (shown as 239c in Figure 5A, where DACs 260-269 are not used). In the embodiment of Figure 3C, an analog video sample 870 (i.e., an interpolated analog RGB sample) is input to the transmitter for transmission (shown as 239b in Figure 5A, where DACs 260-269 are not used).

[0072] <SSVT Transmission from SoC to Display> Figure 4B shows in more detail the video transmission from the system-on-chip to the new DDIC of the display using SSVT. After being processed by SoC 130, 130', or 130'', the digital video sample 162 is input to the SSVT transmitter 136 (including any number of DACs for generating the analog levels for output). As described above, one or more DACs may precede the SSVT transmitter, in which case the DAC built into the SSVT transmitter is not necessary. In some embodiments, the analog video sample 840 or 870 is input, in which case a DAC is not necessary. The SSVT transmitter outputs any number of electromagnetic signals 135 that transmit the analog levels (the encoded form of the analog samples). As described above, typically, six electromagnetic paths are used to transmit the analog levels from the SoC to the DDIC. As shown, the DDIC 143 includes the SSVT receiver 610 that receives any number of EM signals 135 and drives the corresponding columns of the display. As described above, the SSVT receiver does not include a DAC for converting the video samples.

[0073] In the embodiment of FIG. 3A, the digital video sample 162 (i.e., the interpolated digital RGB sample) is input to the SSVT transmitter 图解3Aの実施形態では、デジタルビデオサンプル162(すなわち、補間後のデジタルRGBサンプル)が、伝送のためにSSVT送信機136に入力される(図14の439aに示され、DAC462が使用される)。図3Bの実施形態では、アナログビデオサンプル840(すなわち、グリーンチャンネルのみ)が、伝送のために送信機に入力される(図14の439cで示され、DAC462は使用されない)。図3Cの実施形態では、アナログビデオサンプル870(すなわち、補間後のアナログRGBサンプル)が、伝送のために送信機に入力される(図5Aの439aで示され、DAC462は使用されない)。136 for transmission (shown as 439a in FIG. 14 and DAC 462 is used). In the embodiment of FIG. 3B, the analog video sample 840 (i.e., only the green channel) is input to the transmitter for transmission (shown as 439c in FIG. 14 and DAC 462 is not used). In the embodiment of FIG. 3C, the analog video sample 870 (i.e., the interpolated analog RGB sample) is input to the transmitter for transmission (shown as 439a in FIG. 5A and DAC 462 is not used).

[0074] <SAVT Transmitter of Camera or SoC> The SAVT transmitter can be used to send video samples obtained from an image sensor to an SoC, and the SAVT transmitter can be used to send video samples from the SoC to a mobile phone display.

[0075] Figure 5A shows the architecture of SAVT transmitter 140 implementing SAVT transmitter 120 of a video source. The diagram shows a distributor 240 containing two line buffers 241 and 242 with input vectors, a distributor controller 230, optional digital-to-analog converters 260-269, and analog EM signals 270-279 output from each input vector. While this example shows multiple EM paths, there may be a single EM path or multiple EM paths. Depending on the implementation and design decisions, multiple outputs may improve performance but require more paths. To minimize wiring from transmitter 140, only a single path carrying a single EM signal 270 may be used.

[0076] Generally, when a stream of video samples is received from the sensor by the transmitter 140 (using any appropriate order), the video samples are (1) repeatedly distributed to one of the EM paths according to a predetermined permutation (in this example, a row-major permutation, i.e., an identity permutation), and (2) one EM signal per EM path is transmitted as an analog EM signal through the transmission medium. As a result, the original stream of time-sequential video sampling containing color pixel-related information is transmitted from the video source to the video sink. The reverse permutation in the corresponding SAVT receiver effectively outputs the received samples in the same order in which they were received at the distributor. Samples may arrive serially, for example, R→G→B, or they may arrive in parallel as RGB as three separate signals. The distributor 240 can be used to change the sampling order as needed.

[0077] Depending on the embodiments described above, an analog RGGB video sample 239a may be input, an analog-digital RGB sample 239b may be input, an analog or digital G sample may be input, or an analog BGBG···RGRG sample may be input. If the sample is digital, DACs 260-269 are used. In general, the transmitter does not necessarily have to be RGB and can accept analog video samples from any color space used.

[0078] The distributor 240 is positioned to receive exposed pixel color information in the sampling input set. The distributor 240 receives the exposed color information and writes a number of input vectors 280-288 to the first line buffer 241 (one input vector per EM path) according to a predefined permutation, where the input vectors are the sample set of the line buffer corresponding to one of the EM signals 270-279. When the line buffer 241 is full, each input vector 280-288 is read out onto the corresponding path 270-279 via the corresponding output ports 281-289. When these input vectors are read out from the line buffer 241 (or when the line buffer 241 is full), the input samples for the next line are written to the input vectors 290-298 of the second line buffer 242. Thus, when the second line buffer 242 is full, samples from the second line buffer 242 are output via the output ports 291-299. This writing to and reading from the first and second line buffers continues in this "ping-pong" manner as long as input samples arrive at the transmitter.

[0079] The number of line buffers required depends on the relative time required to load and unload the buffers. There is a continuous stream of data input to inputs 239a, b, c, or d. If the time T to load all samples into the buffer is the same as the time T to unload them, then two buffers are used (so that one can be unloaded while the other is being loaded). If the unloading time becomes shorter or longer, the buffer length can always be adjusted (i.e., by adjusting the number of input vectors or N of each input vector) so that the required number of line buffers is always two. However, more than two buffers can be used if necessary.

[0080] The distributor controller 230 controls the operation and timing of the line buffer. In particular, the controller is responsible for defining the permutations and the number of samples N used when constructing the input vector. In this example, N = 1024. Of course, the number of input vectors per line buffer and the number of samples N per input vector can vary considerably depending on the implementation, the type of input signal, the desired bandwidth, whether the transmitter is implemented as a camera or as an SoC, etc.

[0081] The controller 230 may also include a permutation controller that controls the distribution of samples to positions in the input vector. The controller also plays a role in adjusting the crossover of the clock domain from a first clock frequency to a second clock frequency. In a particular embodiment, the samples are F PIXEL It is clocked in at the frequency, and the sample is F SAVT Each input vector is clocked out at the sampling analog video transmission (SAVT) frequency. It is also possible to clock in multiple samples at once, such as two or three samples at a time, rather than one sample at a time. The analog samples are transmitted to the SAVT receiver along the electromagnetic path of the transmission medium as analog EM signals 270-279.

[0082] For illustrative purposes, one possible permutation is one in which each input vector contains N samples of color information. In this example, the exposed samples of the set of samples are assigned to the input vector from left to right. For example, the "R", "G", "G", and "B" values ​​of the first set of samples, the "R", "G", "G", and "B" values ​​of the next set of samples, and so on, are assigned to input vector 280 in that order (i.e., RGGBRGGB, etc.). Once input vector 280 has been assigned its N samples, the above process is repeated sequentially for the other input vectors until each input vector has N values. The number of N values ​​per input vector can vary greatly. As shown in this example, this given permutation maintains row-preferential order of the input samples; that is, the first input vector 280 contains samples 0 through 1023 of the first row in that order, and subsequent input vectors continue that permutation. In this way, the distributor controller 230 performs the permutation by assigning the input samples to specific addresses in the line buffer. Furthermore, the distributor 230 may use any permutation scheme, and it should be understood that any permutation scheme used by the transmitter will be used in reverse by the corresponding SAVT receiver. In a situation where only one electromagnetic path is used and video samples are received by the SAVT transmitter, the distributor writes to one input vector in each line buffer.

[0083] The corresponding SAVT transmitter 136 is implemented on the SoC to transmit to the display, as shown in Figure 4A. This transmitter is implemented similarly to the SAVT transmitter 120 described above, but with the following additions. The SAVT transmitter 136 takes input video samples and distributes them among multiple input vectors to transmit analog video samples in parallel via multiple electromagnetic paths 135 to the SAVT receiver 142 (shown as an array of SAVT receivers 142a, b, c) in Figure 4A. There may be a single EM path or multiple EM paths, and typically there may be six paths for a mobile phone. If there are six paths 270-279 and N=1080, this means a total of 6480 samples per line of the display, which is suitable for a 4K display (4096 x 2160 pixels) with 2160 pixels horizontally or 6480 subpixels in one line. The values ​​of N=1080 and six paths in Figure 5A are suitable for a transmitter on the SoC transmitting to a display 150.

[0084] In each SAVT receiving component 142a, b, or c, the input analog EM signal is received at the input terminal, and each analog sample is distributed sequentially through the sampling circuit to the storage cells of a specific column driver using the reverse order of a predetermined permutation used by the transmitter. Once all samples have been collected by each receiver, they are driven to the display. As a result, the original stream of time-sequential video sampling, including color and pixel-related information, is transmitted from the video source to the video sink. The reverse order permutation effectively stores the received samples as rows in the storage array (for the display) in the same order in which the rows of samples were received by the distributor. It should be understood that any permutation scheme may be used by the distributor 230, and whatever permutation scheme is used by the transmitter, its reverse permutation is used by the control logic of each receiver to distribute the input samples to the column drivers.

[0085] In one embodiment, four control signals are inserted into the stream of samples in distributor 240 that are sent to each receiver every 60 video samples. As shown, each input vector 280 in the line buffer contains a total of 1024 values including four control signals every 60 video samples. The control signals may be inserted at various positions of the input vector. As an example, the "samples" 960 - 1023 of input vectors 280 - 288 may actually be control signals. Any number of control signals can be used within each input vector. Further, although arbitrary, a finite number of control signals is possible. The more control signals are sent, the higher the required data transmission rate. Ideally, the number of control signals is limited to fit within the blanking period and a correspondence can be established between the transmission rate and the display line (thus reducing the amount of storage required and additional resynchronization). Further, the control signals may be inserted into the sampling stream by the distributor or the control signals may be inserted elsewhere.

[0086] In a particular embodiment, each line buffer 241 or 242 has an input port for input samples, and the samples are clocked in at the frequency of F PIXEL and each line buffer also has six output ports, such as 281 or 291 (when there are six EM signals each sent to one of six receiving components), and the samples are clocked out from each input vector at the sampled analog video transmission (SAVT) frequency of F SAVT . Also, it is possible to clock in two R, two G, two B samples at a time instead of one each, or three samples at a time. In one embodiment, it is 24 channels at F SAVT = 663.552 MHz.

[0087] <SAVT Receiver in SoC> Figure 5B shows the SAVT receiver 132 in the SoC. The receiver receives any number of EM signals 270-279 and inputs them to a collector 200 having two line buffers 201 and 202. Similar to the distributor of the SAVT transmitter in Figure 5A, each line buffer has any number of output vectors 204, 206, 208 (or 214, 216, 218), each vector holding any number of video samples corresponding to an input vector (e.g., N=1024). During operation, each output vector 204-208 of the first line buffer 201 is filled with samples from the corresponding EM signals 270-279, and while buffer 201 outputs its samples to receiver output 220 (via outputs 205, 207, 209), the second line buffer 202 is filled with the corresponding EM signals 270-279. When the first line buffer becomes empty, the second line buffer starts refilling while it is outputting to receiver output 220.

[0088] Similar to the SAVT transmitter in Figure 5A, there are preferably two line buffers, but more may be used if necessary, and the buffer length may be adjusted as described above. In the case of collector 200, the output is serial or parallel, and the output from each buffer may be parallel (i.e., all N samples at once from each output vector), and the time per sample to output may be longer than the input sampling. Therefore, if 100 samples are output at once, the output can be transferred 100 times slower than the input sampling (assuming the input sampling was one at a time).

[0089] The collector controller 230 sequences the samples from inputs 270...279 and controls the timing controller that unloads the samples for further processing. Because the input stream is continuous, the collector controller loads the samples into one line buffer, while the samples from the other line buffers are transferred to the output for further processing.

[0090] The rows of the image sensor 822 are serially output and sent to the collector 200 via the SAVT transmitter shown in FIG. 5A (using input 239d, i.e., BG···RG···), and output from the collector 200 in the same format as the input, i.e., BG···RG···, showing an embodiment of a receiver suitable for use with the embodiment of FIG. 3A. When output, the sample is sent to the ADC837. As described above, if a parallel input to the ADC837 is desired, the output from the collector 200 may be parallel. In order to distribute the input samples to the line buffer, regardless of which permutation is used in the corresponding SAVT transmitter, the SAVT receiver uses an inverse permutation to output the samples in the order in which the receiver output 220 was received by the SAVT transmitter (i.e., as received in 239d). In the embodiments of FIGS. 3B and 3C, the collector inputs all G samples or RGGB samples (as appropriate) and outputs these analog samples as [G···] samples via the receiver output 220’ or as [RGGB···] samples via the receiver output 220’’ corresponding to the original inputs 239c or 239a for further processing by the analog signal processor 839 or 869.

[0091] <SAVT Receiver of DDIC> FIG. 6 shows one architecture of the SAVT receiving component 142c of FIG. 4A, and each of the other receiving components 142a, 142b, etc. is implemented in a similar manner to drive their respective columns. In this architecture, each amplifier drives an adjacent column, and all control signals are processed by a single amplifier, which has the advantage that the columns being collected are relatively local to the S / H amplifier. However, other permutations of amplifiers for the columns are possible. For example, a permutation that minimizes the transmission bandwidth to the inputs (Ainp, Ainn) may be used. There are many other possible permutations (maps) from the input sample number to the columns.

[0092] Input terminal 821 is shown, which distributes the pixel data and control signals input from the SAVT transmitter to the S / H amplifier 824 (which receives pixel data numbered from 0 to 14) and the control signal receiving amplifier 826. The pixel data from amplifier 824 is transferred to either storage array A828 or storage array B830 as described above, and the control signals are processed by component 836 and output at 838. The pixel data from either storage array is then input to column driver 832 and output to column 834 as described above. Not shown is the control logic for controlling the timing of the input amplifiers, storage arrays, and column drivers. The pixel data is received sequentially on a single channel per chip (or possibly multiple channels per chip) and stored sequentially (at 1Fsavt cycle intervals) in the A / B collector, although it is also possible to store 15 subpixels in parallel in the array from 15 SHA amplifiers. The S / H amplifier 824 performs demultiplexing (also known as deinterleaving), and the complete demultiplexing is not finished until the samples are distributed to each column. The A / B collector also performs part of this task, in that the collector samples sequentially into separate rows (demultiplexing function), and then the columns are processed further.

[0093] Thus, the 15 interleaved S / H amplifiers receive the incoming pixel data, each driving 64 adjacent columns, i.e., 64 video tracks, thereby minimizing the span of the columns driven by each amplifier. This architecture provides 15 blocks of 64 video samples and one 64-bit subband channel (control signal) per display line (per receiving component). For example, amplifier 0 drives columns 0-63, amplifier 2 drives columns 64-127, etc., amplifier 15 drives columns 896-959, and amplifier 826 drives the control signal. Having all control signals on one channel means there is no difference in amplitude or delay from one signal to the next (as they would be on different channels). It is also possible for the control signal to arrive on channel 0 (i.e., amplifier 0) instead of amplifier 15. This is advantageous in that the control information arrives earlier than the pixel data. Another advantage of this architecture is that the control signal extraction only needs to look at the output of one deinterleaved amplifier, rather than distributing it to all the amplifiers, thus simplifying synchronization. Of course, depending on the implementation, there may be fewer or more S / H amplifiers than 15.

[0094] In this diagram, there are 15 video amplifiers, each driving 64 subpixels = 960 subpixels / chip. There is one control channel, transmitting 64 symbols per line (per receiving component). If MFM is used for timing synchronization, the 64 symbols are transition encoded, and after considering the flag bits and command bits, 24 or 25 control bits remain per line.

[0095] As shown, the control channel receives the control signal at amplifier 826, and this control signal has a reference voltage of 0V and F SAVTThe 16th signal is input to comparator 836, which operates at approximately 41.5 MHz. Assuming the control signal is in the range of -0.5V to +0.5V, the comparator detects whether the control signal is greater than 0V (meaning a digital 1) or less than 0V (meaning a digital zero). This digital data is output by 838, providing one control bit every 16 samples. The control signal provides synchronization and phase adjustment. From an implementation standpoint, the comparator could simply be a zero-crossing detector, in which case a reference voltage is not required. The reference clock 139 is sent from TCON.

[0096] This particular embodiment is for a 4K120 OLED display, and examples of parameter values ​​are shown in Table 1 below. Those skilled in the art will see that it is easy to modify the architecture, permutations, etc., to accommodate other display sizes and speeds, such as the resolutions of various other mobile phones. Examples of source driver identification are shown in U.S. Provisional Patent Applications 63 / 447,241 (Attorney No. HYFYP0015P) and 63 / 500,341 (Attorney No. HYFYP0015P2), as well as U.S. Patent Application 18 / 442,491 (Attorney No. HYFYP0015) referenced above. [Table 1]

[0097] Figure 7 shows the inputs of the SAVT receiver 142c for interleaving multiple input amplifiers to enable meeting speed requirements. (It is also possible to use a single amplifier, but the transmission speed will be reduced). The input terminal 821, distribution amplifiers 0-14 (824), and amplifier 826, as well as an associated switch 842 that rotates to effectively connect one amplifier at a time to receive one of the received subpixels or control signals, if applicable, are shown. Although not shown, sampling capacitors inside the switch are important for achieving the required speed and thus reduce the bandwidth requirements of the amplifiers themselves. In this way, the inputs are interleaved in 16 ways, and the output of the switch is demultiplexed into 16 channels operating at 1 / 16 of the data rate. The 960 subpixels in the line are grouped into 15 groups, each consisting of 64 subpixels, with one channel dedicated to the detection and processing of control signals.

[0098] Figure 8 is an overview of the pixel transmission sequence 300, showing how pixels 0-959 and control signals 0-63 are transmitted from the SoC's SAVT transmitter 136 to the receiver 142c in Figure 6, and which amplifier each is assigned to. Shown is the natural order of subpixels delivered via CEDS (Clock Embedded Differential Signaling), for example, subpixels arriving so as to be read from left to right, then top to bottom. Due to the 16-way interleaving of input data at the receiver, the preferred way to transmit subpixels to the receiver is from top left to top to bottom, then left to right, i.e., the indices of the transmitted subpixels (and control signals) are 0, 64, 128, etc. An example of the index of the S / H amplifier 302, subpixel index 304, and control track 306 of the 16th amplifier are shown.

[0099] In this permutation, amplifiers 15 (0-14) each drive 64 adjacent columns with subpixel values, and amplifier 15 processes all 64 control signals. This modification minimizes receiver hardware and input amplifier wiring load. Furthermore, this modification does not require padding in the data sequence, allowing for the slowest possible SAVT transmission rate. To optimally display text and other abrupt intensity transitions, it is desirable that the sampling amplifier stabilizes to a new value every 1 / Fsavt, i.e., approximately every 1.5 ns per sample. To implement this architecture, the sequence of subpixel indices transmitted by the transmitter is 0, 64, 128, ..., 832, 896; 1, 65, ..., 897; ...; 63, 127, 191, ..., 895, 959.

[0100] Figure 9 is a block diagram of the input vector 320 of the SAVT transmitter, having a predetermined permutation that provides the sequence of subpixel transmissions required by Figure 8. As previously described, when subpixels arrive at the distributor from the timing controller, they are distributed to the input vector 320 in the shown order. When the input vector is full, the samples in the input vector are output via the output port 321, transformed as necessary, and then sent to the SAVT receiver, which has the architecture described in Figure 6. Other input vectors of the line buffer are not shown, but each input vector has a similar permutation, and the receiver corresponding to each input vector has the same architecture as shown in Figure 6.

[0101] The above architecture of receiver 142c, along with the above transmission sequence, provides the above advantages and also maintains the slowest possible SAVT clock rate. Accurate sampling of each subpixel within the available time can be provided by synchronization.

[0102] Figure 10A shows another embodiment of the SAVT receiving component 142c of the DDIC in Figure 4A, each of the other receiving components 142a, 142b, etc., is implemented in a similar manner and drives their respective columns.

[0103] Timing generator 880, input terminal 881, and sampling blocks 882 and 883 are shown. Comparator 884 is a comparator for extracting control signals. Amplifier 885 is an amplification stage including a preamplifier, level converter, and high-voltage driver. Sixteen interleaved sampling amplifiers with offset cancellation (SHA amplifiers and offset control), including amplifier 886, are shown. Preferably, in this embodiment, amplifier 0 (886) is used for control signals (rather than amplifier 15 as in Figure 6) so that the control information arrives with ample time before the end of the display line time. This provides a small amount of time to decode the control channel and set up the signals to be used in the next line time.

[0104] In this embodiment, synchronization is achieved by requiring only a single comparator 884 (zero-crossing detector) on a single SHA channel and not requiring a DAC to set the comparison threshold. The synchronization algorithm is performed in the digital domain (zero-crossing detector output) and can perform both clock-level synchronization (adjusting the SHA output so that the side channel is seen on one specific SHA channel output) and phase-level synchronization (selecting the optimal sampling phase within a clock cycle).

[0105] Input terminal 881 has one analog input differential with 50-ohm termination (100R differential) and ESD protection. This is driven with a source impedance of 50R per side via a 50R transmit line. Thus, the received voltage is reduced by 50% compared to the transmit voltage. The 880's PLL multiplies a relatively slow reference clock 139a (e.g., Fsavt / 64) from TCON up to a selectable 11-phase full-speed Fsavt clock 139b (e.g., approximately 675MHz) per clock cycle. There is also fast timing generation for generating sampling strobes, reset signals, and output transfer strobes for SHA amplifiers 0-15. As shown in Figure 7, a 16-way deinterleaver 840 is constructed using the SHA amplifiers. The ON / OFF switch of this is rotated so that substantially only one is ON at a time. Thus, 16 consecutive samples are sequentially deinterleaved into 16 amplifiers, giving each amplifier ample time to stabilize. As shown in the diagram, the 15 SHAs each drive 64 adjacent subpixel rows and consist of a preamplifier, level shifter (differential to single-terminated), and high-voltage driver to drive the display rows. One of the SHAs drives the control samples (note that each control sample is 16 samples apart). The control samples represent digital values ​​to make the system robust, using transition coding (MFM) to provide timing and control information. The bandgap voltage reference circuit 887 provides current and voltage references to the various input amplifiers.

[0106] Figure 10B is an overview of the subpixel sequence collected by the input amplifier in Figure 10A. This overview shows how pixels 0-959 and control signals 0-63 are transmitted to the SAVT receiver in Figure 10A, and to which amplifier each subpixel is assigned. In the source driver, there is 16-way interleaving, so the preferred way to transmit the subpixels to the source driver is from top left to top down, and from left to right, i.e., the indices of the transmitted subpixels (and control signals) are ctrl0, 0, 64, 128, etc., and are transmitted sequentially to the 16 amplifiers. An example of the index of S / H amplifier 890, subpixel index 891, and control signal 892 of amplifier 0 886 are shown.

[0107] This subpixel order minimizes the source driver hardware and the wiring load on the input amplifier. To optimally display text and other rapid intensity transitions, it is desirable that the sampling amplifier can stabilize to a new value every 1 / Fsavt, or approximately every 1.5ns per sample. As shown in the figure, SHA0 transmits control and timing, SHA1-15 transmit video data, and each SHA drives 64 adjacent columns of the display. Since the SHAs are sampled sequentially, the transmission order is CTL[0], V[0], V

[64] , ...V

[0896] , CTL[1], V[1], V

[65] , ...V

[0897] , ...CTL

[63] , V

[63] , V

[0127] , ...V

[0959] . This sequence transmits 64 control bits per line, 960 video samples per line, and a total of 1,024 samples per line (per SAVT receiver).

[0108] As mentioned above, other permutations are also possible. Another possible permutation (not shown) uses a permutation in which all subpixels of each color are transmitted as a group, with blank transition bands between groups to reduce the bandwidth between groups, in order to minimize the SAVT bandwidth requirement. For example, all red subpixels are first transmitted from the SAVT transmitter to receiver 142c, followed by the green subpixels, and then the blue subpixels.

[0109] <Video transmission system embodiment> Figure 11 shows a video transmission system 700 within a mobile device. This figure provides a high-level diagram of the transmission from the SAVT transmitter 136 of the SoC to the SAVT receiver array 142 of the DDIC 140. The SoC outputs a set of color samples, such as subpixel values ​​in digital-analog format representing luminance values ​​from an image / video displayed on the display 710. The samples are input to the SAVT transmitter 704, converted to analog (if necessary), and transmitted to the SAVT receiver array 708 for display on the display 710 via twisted-pair wires or traces, cables, or a suitable EM path 706 within the mobile phone.

[0110] The transmitter's distributor includes a line buffer 720, an arbitrary number of input vectors (or banks) 722-726, and a distributor controller 728. RGB samples (or grayscale, or other color spaces) are received sequentially by the distributor and distributed to the input vectors according to a predetermined permutation controlled by the distributor controller 728. In this example, a row-first permutation is used, with the first portion of each row of the received video frame (or image) stored in input vector 722 from left to right, and so on, with the last portion of each row stored in input vector 726. Thus, when the line buffer 720 is full, it contains all the pixel information from the first row of the video frame, which is transmitted to the display panel 710 in the first row of the video frame for display. Each input vector is read out to the corresponding DAC 732-736 (if necessary), and each sample is converted to an analog sample for transmission. As samples arrive sequentially from the SoC 702, they are distributed, converted, transmitted, and finally displayed as video on the display 710.

[0111] Connecting the transmitter 704 to the receiver array 708 is the EM path of the cell phone 706, consisting of differential wire pairs, metal traces, etc., 742-746, with each wire pair transmitting a continuous stream of analog samples (electromagnetic signals or EM signals) from one of the DACs 732-736. Each differential wire pair terminates at input terminal 760 of one of the receivers 752-756. Other transmission media (e.g., wireless, optical) are also possible.

[0112] Each receiver in a receiver array, such as receiver 752, includes an input terminal 760, a collector 762, and a number of column drivers 764 (corresponding to the number of samples in each input vector, 1024 in this example). Samples are received continuously at input terminal 760 and collected in collector 762. Collector 762 can be implemented as a one-dimensional storage array or an array with a length equal to the size of the input vector. Each collector can be implemented using the storage array shown above. When each collector is full, all collected samples are output in parallel to all column drivers 764 of all receivers, amplified to the appropriate voltage required by the display, and output to column 766 using a single-ended format. As samples arrive continuously along the path, each collector continues to collect samples and output them to the display, affecting the video display. In one embodiment, each collector 762 is implemented using the A / B storage cells shown above. In other words, each column of the collector will have a pair of input samplers. The SHA amplifier can be considered part of collector 762.

[0113] <SSVT transmitter for camera module> Figure 12 shows a logic block diagram of a specific implementation of the SSVT transmitter 428a in a camera. The transmitter may be implemented in the camera itself, in the video source, or in close proximity to the video source. The distributor 440 includes an assembly bank 450, a staging bank 452, a presentation bank 454, and a controller 456. The encoder block 460 includes a bank of optional digital-to-analog converters (DACs) 462 and three encoders 442, one for each EM path of the transmission medium. As described herein, a stream of samples from a single source (such as a camera, image sensor, or another sensor) arrives at the transmitter 428a for encoding. As shown, the stream of video samples may arrive in parallel, serially, in any appropriate grouping as shown in 437a-d, and may represent any desired color space. Each encoder 442 encodes one input vector and produces a set of output levels as the EM signal. Therefore, there may be one encoder for each EM path, or any number (P) of encoders.

[0114] The distributor 440 is configured to successively receive exposed color information (e.g., RGB) for a stream of sample sets. In response, the assembly bank 450 constructs three input vectors V0, V1, and V2 from the received exposed color information (e.g., RGB) of the sample stream. Once a sample set is received, it is stored in the assembly bank 450 according to a predetermined permutation. The distributor 440 can use any number of different permutations when constructing vectors, each containing N samples, and the samples can be rearranged as needed using the distributor 240.

[0115] The staging bank 452 facilitates crossing N samples of each of the three vectors V0, V1, and V2 from a first clock frequency (or first timing domain) to a second clock frequency (or second domain) used for encoding and transmitting the resulting EM signal over the transmission medium.

[0116] In various embodiments, the first clock frequency can be faster than, slower than, or the same as, the second clock frequency. The first clock frequency f_pix is ​​determined by the video format selected by the video source. The second clock frequency f_ssvt is a function of f_pix, the number of EM paths P in the transmission medium, the number of samples S in each set of input / output sampling, and the SSVT conversion parameters N (number of input / output vector positions) and L (length of each SSDS code), where f_ssvt = (f_pix * S * L) / (P * N). In this arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at another rate. These rates may be the same or different. The encoder performs encoding while the next input vector is prepared. Presentation bank 454 presents N samples each of three encoder input vectors V0, V1, and V2 to encoder block 460 (for example, vector V0 is Sample 0,0 ~Sample 0,N-1 (including).

[0117] Controller 456 controls the operations and timings of assembly bank 450, staging bank 452, and presentation bank 454. In particular, the controller is responsible for defining the permutations and the number of samples N used when constructing the three encoder input vectors. Controller 456 is also responsible for adjusting the clock domain crossing from the first clock frequency to the second clock frequency performed by staging bank 452. Controller 456 is further responsible for adjusting the timing at which presentation bank 454 presents N samples of each of the three encoder input vectors to encoder block 460.

[0118] Within encoder block 460, any number of optional digital-to-analog converters (DACs) 462 are provided, each configured to receive one of the P*N samples (Sample 0,0 ~Sample P-1,N-1 ) assigned to the three encoder input vectors in a batch. Each DAC 462 converts the received sample from the digital domain into a differential pair of voltage signals having magnitudes proportional to the received digital value. The output of DAC 462 can be in the range from the maximum voltage to the minimum voltage.

[0119] The three encoders 442 are provided respectively for the three encoder input vectors. Each encoder 442 receives differential pair signals for each of the N samples for its encoder input vector, modulates each of the N differential pair voltage signals using chips from the code corresponding to each sample, accumulates the modulated values, and then generates a differential EM signal output. In this example, since there are three encoders 442, there are three EM signals 125a, 125b, 125c (Signal0~Signal2) transmitted simultaneously on the transmission medium.

[0120] The sequencer circuit 465 adjusts the timing of the operations of the DAC 462 and the encoder 442. The sequencer circuit 465 is in charge of controlling the clocking of the DAC 462 and the encoder 442. Also, the sequencer circuit 465 is responsible for generating two clock phase signals, "clk1" and "clk2", which control the operation of the encoder 442.

[0121] The receiver corresponding to the transmitter 428a can receive, decode the output level, and use the samples (for example) to collect them into the input RGB signal, as will be understood by those skilled in the art upon reading this disclosure. Analog encoding or digital encoding (and decoding) may be used. The DAC or ADC may precede or follow the encoder (or decoder), depending on the case and as required by the implementation. For example, since each EM signal is a series of analog levels, when digital encoding is used, the DAC follows each encoder. The SSVT encoding and decoding can be performed as described in the applications and patents incorporated by reference.

[0122] <SSVT Receiver of SoC> FIG. 13 is a block diagram of an SSVT receiver 132 arranged in a SoC. On the receiving side, the SSVT receiver 132 is responsible for decoding a stream of differential EM signals received on each transmission medium into a stream of video samples originally presented to the corresponding SSVT transmitter. After processing within the SoC, the video content (for example, signal S) contained in the samples can be distributed to the video display 150 and presented frame by frame. As a result, the video captured by the video source is recreated by the video sink. Alternatively, the decoded video information can be saved for later display.

[0123] Receiver 132 performs the reverse of the encoding performed by the SSVT transmitter 428a on the transmitting side. Receiver 132 uses any number of decoders 80 and collectors 46. Decoder 80 reconstructs the differential EM level signal into three decoder output vectors (in this example). Collector 46 then assigns samples of the decoder output vectors to the original stream into a set of samples containing S reconstructed signals, each corresponding to the original S.

[0124] P decoders 80 (indicated as 0 to P-1) are used to process differential EM level signals Level0 to Level P-1 They are arranged to receive each of them. In response, each of the decoders 80 receives the reconstructed samples of N differential pairs (Sample0~Sample N-1 This generates the following: If there are three decoders 80 (P=3), three output vectors V0, V1, and V2 are constructed.

[0125] Reconstruction bank 82 performs N reconstruction samples (Sample0~Sample) for each of the three decoder output vectors at the end of each decoding interval. N-1 Each of the differential pairs of ) is sampled and held. An optional analog-to-digital converter (ADC) 84 takes N samples (Sample0~Sample) for each of the three vectors. N-1 Each of the three vectors is provided. Each ADC converts the received differential pair voltage signal into a corresponding digital value, and as a result, a digital sample is provided for each of the three vectors. N-1 ~Sample0) is obtained. The ADC operates at a clock rate of f_ssvt / L. Alternatively, each EM signal is input to the ADC before each decoder, and decoding is performed digitally. In this case, ADC84 is not required.

[0126] Collector 46 includes staging bank 86 and decomposition bank 88. Staging bank 86 contains all reconstructed samples (N) for each of the three decoder output vectors. n-1receives ~N0). The decomposition bank 88 uses (a) the same permutation scheme as used on the transmission side to decompose the samples (from Sample N-1 to Sample0) for each of the three decoder output vectors into the exposed color information (e.g., the S signal) for the stream of sets of samples (e.g., in this example, "S = 3 for RGB pixels"), and (b) cross-references the reconstructed samples so as to return from the second clock domain to the first clock domain. The output samples are shown at 85a~d and correspond to the samples 437a~d input to the transmitter by the camera. The receiver 132 also includes a channel aligner 87 and a collector controller 89 and receives framing information and aperture information from each decoder 80. The framing signal means the timing for constructing a video frame on the display panel. N-1 The collector controller 89 adjusts the timing of the staging bank 86 and the decomposition bank 88 so that all the samples presented to the decomposition bank come from the common time interval during which the level signal was transmitted by the SSVT transmitter 428a. As a result, (a) the decomposition by bank 88 can delay all the samples to the receiver, and (b) since the decomposition bank 88 compensates for any timing differences, the individual channels of the transmission medium do not necessarily all have to be the same length. The collector controller 89 is also responsible for tracking the permutation and applying the same permutation as used on the transmission side when the decomposition bank 88 constructs the input vector.

[0127]

[0128] <SSVT Transmitter from SoC to DDIC> FIG. 14 shows in more detail the video transmission of FIGS. 2A or 2B between the SoC 130 using SSVT and the telephone 100. As shown, the SSVT transmitter 428b can input either digital video samples or analog video samples (e.g., digital analog RGB samples 439a or analog G samples 439c depending on which implementation is used as described above) and, as shown in FIG. 4B, can transmit any number of EM signals 135 to the DDIC 143. The DDIC 143 is typically a single silicon chip.

[0129] As described above, the input video samples 439a or 439c can be either analog or digital. In the analog case, no DAC 462 is required, and the encoding within the encoder 442 is analog encoding, thus outputting an analog output level of the EM signal. Even if the video samples from the SoC are digital, one or more DACs may be placed before the SSVT transmitter, and in that case, analog encoding is performed as described above. If the video samples input to the SSVT transmitter are digital samples, the DAC 462 is used, and in that case, analog encoding is used. Alternatively, the DAC 462 may be removed, the encoding is digital, and a DAC follows each encoder 442 to provide an analog output level. In any case, each EM signal 135 from the encoder transmits an SSVT-encoded analog output level as described herein.

[0130] The SSVT transmitter 428b can be implemented as described above similar to the SSVT transmitter 428a of FIG. 12, but the input to the SSVT transmitter 428b may be different as shown.

[0131] <SSVT Receiver of DDIC> Figure 15 shows DDIC's SSVT receiver 610 in more detail. As shown, each EM signal 702-704 is input to decoder 780, where analog decoding is performed, and the recovered analog sample (i.e., voltage) is output directly to a level shifter and amplifier, and finally 634 is output to the mobile phone display. In effect, the SSVT receiver 610 consists of circuits for processing each input EM signal, each circuit having a decoder, reconstruction bank, staging bank, and its own level shifter, amplification stage, etc. Each decoder is responsible for decoding the differential analog level received through the transmission medium back into a format suitable for display. Once in the appropriate format, the video content contained in the sample can be displayed frame by frame on the video display. As a result, video captures from any video source can be recreated in Videolink. As shown, the integrated receiver 610 does not require a source driver or a DAC (for converting digital samples to analog samples for display) as required by prior art sources or DDIC.

[0132] Each decoder 780 outputs to its corresponding collector (reconstruction bank 782 and staging bank 786). P represents the number of input electromagnetic signal pairs, each transmitting an independent SSVT signal except that it is an isochronous signal known to be generated synchronously with one another by the transmitting encoder. In a particular embodiment, P=6, so there are 6 decoders. Each decoder 780 performs an inverse transform of its differential pair encoder at the transmitting side and reconstructs its input differential level signal into an output vector of N reconstructed samples (although single-ended inputs may be used instead of differential inputs). Collector 746 assigns the decoder output vector samples (or "reconstructed samples") to predetermined positions in analog samples 634. These samples 634 are driven relative to a row of displays.

[0133] The P decoders 780 (labeled 0 to P-1) each provide differential EM signals 0 to EM signals. P-1, are arranged to receive 702~704. In response, each of the decoders 780 receives N differential pairs of reconstructed samples (Sample0~Sample N-1 This generates the following: The number of samples N is equal to the number of orthogonal codes used in the previous encoding, i.e., N orthogonal codes were used, meaning N codes from the codebook.

[0134] Reconstruction bank 782, at the end of each decoding interval, generates N reconstructed samples (Sample0~Sample) for each of the decoder output vectors. N-1 Each of the differential pairs of ) is sampled and held. Then, these differential pairs of received voltage signals are used to sample each of the output vectors (Sample N-1 Each signal is output as Sample0). Each reconfiguration bank can also convert from differential pairs to single-ended voltages. Since differential pairs are used to maintain accuracy at low voltages (and are less susceptible to external influences than single-ended voltages), it may be desirable to convert them to single-ended voltages as far down the signal chain as possible (by establishing a reference ground level). Therefore, the conversion to single-ended voltages does not need to be done in the reconfiguration bank and can be done later, such as in a column driver, for example, in a level shifter. The conversion is usually done for all signals (samples, control signals, etc.) and may occur in different locations depending on the type of signal and implementation.

[0135] Each staging bank 786 is a sample reconstructed from each decoder output vector (sample n-1 It receives all of the samples (up to sample 0) and functions as an analog output buffer. When samples are moved to staging bank 786, they are triggered by latch signal 623 derived from the decoded EM signal. When samples are released from staging bank 786, they are sent to level shifter 620.

[0136] The system also includes a channel aligner 787 and a staging controller 789 that receive framing and aperture information from each decoder 780. The framing signal 721 indicates the timing for forming a video frame and is sent to the display panel. The staging controller 789 adjusts the timing of the staging bank 786 so that all samples come from a common time interval from which the level signals were transmitted by the SSVT transmitter. As a result, the individual channels of the transmission medium do not necessarily all need to be the same length, as the channel aligner 787 and the staging controller 789 compensate for timing differences. The staging controller 789 also tracks and provides the staging bank 286 with the appropriate permutation selection to be used.

[0137] The SSVT receiver decodes the SSVT signal and outputs a number of reconstructed analog voltage samples 632 in parallel from its collector 746. Since these analog outputs 632 may not be within the voltage range required by the display panel, they may be input to a level shifter 620 that uses analog conversion to shift the voltage to a range suitable for driving the display 150, and amplification may also be performed using an amplifier 621. A suitable level shifter can be one known in the art, such as a latch type or an inverter type, and the amplifier can also be one known in the art. Level shifting and amplification are typically performed by the display's column drivers.

[0138] For example, the voltage range of each sample output from collector 746 is 0 to 1V, and the voltage range output from level shifter 620 is -8 to +8V (the inversion signal 622 is used to instruct the level shifter to invert the voltage every other frame, i.e., the range is -8 to 0V in one frame and 0V to +8V in the next frame). Thus, the EM signal does not require voltage inversion every frame; the SSVT receiver provides a positive voltage range (for example), and the level shifter inverts the voltage every other frame as the display panel expects. The SSVT receiver can also implement line inversion and dot inversion. The inversion signal instructs the level shifter which voltage to switch. Some display panels, such as OLEDs, do not require voltage inversion every other frame, in which case the inversion signal is unnecessary, and the level shifter does not invert the voltage every other frame. Display panels such as LCDs require this voltage inversion. The inversion signal 622 is reconstructed from the EM signal.

[0139] The level shifter 620 can also accept input gain and gamma values. The gain determines the degree of amplification to apply, and the gamma curve relates the luminous flux to the perceived brightness, linearizing the optical perception of luminous flux by human eyes. Typically, in prior art source drivers and DDICs, both gain and gamma are set values ​​determined by the manufacturing characteristics of the display panel. In the analog level shifter 620, gain and gamma may be implemented as follows: Gamma may be implemented in the digital part of the system, and level shifting and gain may be implemented by setting the amplification of the output stage. In the case of gamma, it is also possible to implement it by implementing a nonlinear amplification characteristic in the output driver. (Other gamma corrections are also performed by timing controllers and system-on-chip, but these gamma corrections are not described here).

[0140] Once shifted, sample 633 is input to amplifier 621, which amplifies each sample to the correct voltage range required by a particular display. Once amplified, sample 634 is output and used to drive the source electrodes of the corresponding columns of the display panel, as is known in the art.

[0141] In order to properly encode the SSVT signal for final display on a particular display, various physical characteristics or properties of that display are required by the SoC (or other display controller) or entity performing the SSVT encoding.608 These physical characteristics include, in particular, resolution, tessellation, backlight layout, color profile, aspect ratio, and gamma curve. Resolution is a constant of a particular display; tessellation refers to the way the display's plane is divided into regions in a regular, predetermined manner, on a pixel-by-pixel basis; backlight layout refers to the resolution and diffusion characteristics of the backlight; color profile is the exact luminance response of all primary colors, providing accurate color to the image; and the aspect ratio of the display has a discrete, known value.

[0142] These physical properties of a particular display are delivered to, embedded in, or provided to a particular display controller in various ways. For example, signal 608 delivers the values ​​of these physical properties directly from the display (or from another location within the mobile device) to the SSVT transmitter. Alternatively, an SSVT transmitter embedded within a particular display has these values ​​hardcoded into the transmitter. Or, a particular display controller is intended for use with only a specific type of display, and its characteristic values ​​are hardcoded into that display controller.

[0143] The input to the display can also be a backlight signal 604 that instructs the LEDs of the backlight, i.e., it instructs when and at what level to turn on. In short, this is a low-resolution representation of the image, and the backlight LEDs are turned on in the parts where the display needs to be brightened and dimmed in the parts where it needs to be darkened. The backlight signal is a monochrome signal and can also be embedded in the EM signal. That is, it can be another parallel independent EM signal transmitted together with other parallel video signals (for example), and can be of low resolution or high resolution.

[0144] Also, what is output from the channel aligner 787 is a gate driver control signal 606 that shares timing control information with the gate driver at the left end of the display in order to synchronize the gate driver with the column driver. Usually, each SSVT receiver includes a timing acquisition circuit that acquires the same timing control information for the gate driver, and one or more (usually the left end and / or the right end column drivers) of the column driver flex foils transmit that timing control information to the gate driver. The timing control information for the gate driver may be embedded in one of the EM signals and is restored from that signal using established spectrum spreading techniques.

[0145] Generally, conventional source drivers of displays are directly connected to the glass using "COF" (Chip-on-Flex or Chip-on-Foil) integrated circuit packages. These drivers can be replaced with the novel integrated SSVT receivers described herein, thereby changing existing displays into SSVT-compatible displays. The inputs of these ICs are usually connected by PCBA and provide input signals from the video source and the timing controller. These ICs can be close to or far from the display controller and transfer video signals and control signals with inexpensive wires.

[0146] <SSVT Signals, Encoding and Decoding> As described above, various embodiments of the present invention disclose that SSVT is used for sample transmission. An electromagnetic signal (EM signal) is a variable represented as electromagnetic energy whose amplitude changes over time. EM signals propagate from a transmitter to a receiver through an EM path such as a wire pair (or cable), free space (or wireless), light, or a waveguide (fiber). EM signals can be characterized as continuous or discrete, independently in two dimensions: time and amplitude. A "pure analog" signal is a continuous-time, continuous-amplitude EM signal; a "digital" signal is a discrete-time, discrete-amplitude EM signal; and a "sampling analog" signal is a discrete-time, continuous-amplitude EM signal. SSVT is an encoded discrete-time continuous-amplitude EM signal, an improvement over existing SSDS-CDMA signals. SSVT refers to the transmission of an electromagnetic signal over an EM path using improved spread spectrum direct sequence (SSDS) based modulation.

[0147] Code Division Multiple Access (CDMA®) is a well-known channel access protocol commonly used in wireless communication technologies, including cellular telephones. CDMA® is an example of multiple access, allowing multiple different transmitters to transmit information simultaneously on a single communication channel. In telecommunications applications, CDMA® allows multiple users to share a given frequency band without interference from other users. CDMA® employs spread spectrum direct sequence (SSDS) encoding, relying on a unique code to encode each user's data. Using unique codes allows multiple user transmissions to be combined and transmitted without user interference. On the receiver side, the same unique code is used for each user to demodulate each user's transmission and reconstruct each user's data.

[0148] SSVT signals are different from CDMA® signals. When a stream of input video samples is received by an encoder, each of the multiple encoder input vectors is encoded by SSDS-based modulation to generate an SSVT signal. The SSVT signal is then transmitted through the transmission medium. At the receiver, the received SSVT signal is decoded by applying corresponding SSDS-based demodulation to reconstruct the encoded samples. As a result, unlike CDMA® which transmits data from multiple users to multiple receivers, the original stream of video samples arranged in chronological order, including color / pixel-related information, is transmitted from a single video source to a single video sink.

[0149] Figure 18 shows a simplified example illustrating how signal samples (in this case, analog values) are encoded within an encoder and then transmitted via an electromagnetic path. An input vector of N analog values ​​902–908, each representing the voltage of an individual pixel in a video frame, is shown. These voltage values ​​can represent the luminance of a grayscale image or a specific color value within a pixel, for example, the luminance of the R, G, or B color values ​​of a pixel; that is, each value represents the amount of light perceived or measured in a given color space. While pixel voltage values ​​are used in this example, this encoding technique may be used with voltages representing any of the various signals from sensors, such as LIDAR values, sound values, tactile values, or aerosol values, and the analog values ​​may represent other samples, such as current. Signal samples that are digital values ​​can also be encoded, and this digital encoding will be discussed below. Furthermore, while one encoder and one EM path are shown, embodiments of the present invention work well with multiple encoders, each transmitting via an EM path.

[0150] Preferably, the range of these voltages is 0-1V for efficiency, although different ranges are possible. These voltages are typically taken from pixels in a row of a frame in a specific order, but a different convention may be used to select and order these pixels. Whatever convention is used to select and order these pixels for encoding, the same convention is used by the decoder at the receiving end to decode these voltages in the same order and place them where they belong in the resulting frame. In the same sense, if the frame is in color and uses RGB, the convention in this encoder may be that all R pixel voltages are encoded first, then the G and B voltages, or the convention may be that voltages 902-906 are the RGB values ​​of the pixels in that row, and the next three voltages 908-912 represent the RGB values ​​of the next pixel, and so on. In this case as well, the same convention used by this encoder for ordering and encoding the voltages is used by the decoder at the receiving end. Any specific convention (by color value, by row, etc.) can be used to order the analog values ​​902-908, as long as the decoder uses the same convention. As shown in the diagram, using codebook 920, any number of N analog values ​​902-908 may be presented for encoding at once, limited only by the number of entries in the codebook.

[0151] As previously mentioned, the codebook 920 has any number of N codes 932–938. In this simple example, the codebook has four codes, meaning that four analog values ​​902–908 are encoded at once. More codes may be used, such as 127 codes, 255 codes, etc., but for practical considerations such as circuit complexity, it is preferable to use fewer codes. As is known in the art, the codebook 920 contains N mutually orthogonal codes of length L, where L=4 in this example. Typically, each code is an SSDS code, but it does not necessarily have to be a spread code, as will be described herein. As shown, each code is divided into L time intervals (also called "chips"), each time interval containing the binary value of that code. As shown in code representation 942, code 934 may be represented in the traditional binary format "1, 1, 0, 0", but the same code may also be represented as "1, 1, -1, -1", as shown in code representation 944, for ease of use when modulating values, as described below. Codes 932 and 936-938 can also be represented as 942 or 944. Note that each code of length L is not associated with different computing devices (such as telephones), different people, or different transmitters, as is done in CDMA.

[0152] Therefore, the following technique is used in the sequence in which the four analog values ​​902 to 908 are transmitted to a receiver (having a corresponding decoder) via the transmission medium 34. Each analog value is modulated by each chip in the representation 944 of the corresponding code. For example, the value 902, i.e., 0.3, is sequentially modulated in time by each chip in the representation 944 of code 932. Modulation 948 may be a multiplication operator. Thus, modulating 0.3 by code 932 results in the sequence "0.3, 0.3, 0.3, 0.3". Modulating 0.7 by code 934 results in "0.7, 0.7, -0.7, -0.7", the value "0" becomes "0, 0, 0, 0", and the value "1" becomes "1, -1, 1, -1". Typically, the first chip of each code modulates the corresponding analog value, then the next chip of each code modulates that analog value, but depending on the implementation, a particular analog value may be modulated by all chips of that code before moving on to the next analog value.

[0153] For each time interval, the modulated analog values ​​are then summed by 951 (perceived vertically in this diagram) to obtain analog output levels 952-958. For example, the sum of the modulated values ​​for these time intervals yields output levels of 2, 0, 0.6, and -1.4. These analog output levels 952-958 may be further normalized or amplified to match the voltage limit of the transmission line and then transmitted sequentially in time in that order as they are generated through the electromagnetic path (such as differential twisted pair) of the transmission medium 34. The receiver then receives their output levels 952-958 in that order and then decodes them using the same codebook 920 using the inverse of the encoding scheme shown here. The resulting pixel voltages 902-908 may then be displayed within a frame on the receiver's display, according to the convention used. In this way, the analog values ​​902-908 are encoded substantially synchronously and transmitted through a single electromagnetic path in a continuous sequence of L analog output levels 952-958. Multiple encoders and electromagnetic paths can also be used as shown and described herein. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0154] Advantageously, despite the significant bandwidth reduction necessitated by robust SSDS technologies (such as spreading codes), the use of mutually orthogonal codes, modulation of each sample by corresponding code chips, summing of these modulations, and parallel transmission of N samples using L output levels significantly improves bandwidth. In contrast to conventional CDMA® technology, which serially encodes binary digits and then sums them, this invention utilizes the amplitude of the resulting waveform by first modulating the entire sample (i.e., the entire analog or digital value, not a single bit) by corresponding code chips, and then summing those modulations at each time interval of the code to obtain the resulting analog voltage level for each particular time interval. What is transmitted over the transmission medium are these analog output levels, not binary representations. Furthermore, this invention facilitates the transmission of analog voltage from one video source to another, i.e., endpoint to endpoint, unlike CDMA® technology which enables multiple access by different people, different devices, or different sources and transmits to multiple sinks. Moreover, no compression is required for the transmission of sample values.

[0155] Figure 19 illustrates this novel encoding technique applicable to signal samples that are digital values. Here, the digital values ​​902'~908' are digital representations of voltages. Using different voltage examples, value 902' is "1101", value 904' is "0011", value 906' is "0001", and value 908' is "1000". Each digital value is modulated (digitally multiplied) by the representation 944 of each code, i.e., "1" or "-1", depending on the code chip corresponding to the modulated digital value. Considering only the first time interval 940 of each code and adding the most significant bit (MSB), which is the sign bit, modulating "1101" yields "01101" (where "0" in the MSB means a positive value), modulating "0011" yields "00011", modulating "0001" yields "00001", and modulating "1000" yields "01000". These modulation values ​​are annotated and shown in the first time interval. (Although not shown in the diagram, modulating with a -1 chip yields negative values, which can be represented in binary using the appropriate binary representation for negative values.)

[0156] When summed digitally, these modulation values ​​in the first time interval yield the digital value 952'"011001" (again, the MSB is the sign bit). The other digital values ​​954'~958', not shown in this example, are calculated similarly. Considering this sum in decimal, we can see that the sum of the modulation values ​​13, 3, 1, and 8 is 25. Although not shown in this example, additional MSBs are usually available for the resulting levels 952'~958', as the sum may require more than 5 bits. For example, if the values ​​902'~908' are represented using 4 bits, then levels 952'~958' may be represented using up to 10 bits (adding 64 bits log2) if there are 64 codes. Alternatively, if 32 modulation values ​​are summed, an additional 5 bits are added. The number of bits required for the output level depends on the number of codes.

[0157] The output level 950' may first be normalized to match the input requirements of the DAC, and then sequentially supplied to the DAC959 to convert each digital value to its corresponding analog value for transmission via the EM path. The DAC959 may be a MAX5857 RF DAC (including a clock multiplier PLL / VCO and a 14-bit RFDAC core, with the composite path bypassed to directly access the RFDAC core), followed by a bandpass filter and a variable gain amplifier (VGA) (not shown). In some situations, the number of bits used in level 950' may exceed the number of bits allowed by the DAC959. For example, level 952' may be represented by 10 bits, while the DAC959 is an 8-bit DAC. In such situations, a suitable number of LSBs are discarded, and the remaining MSBs are processed by the DAC, but the visual quality of the resulting image on the display is not compromised.

[0158] Advantageously, the entire digital value is modulated, and then these modulated digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA®, which modulates each binary digit of a digital value and sums these modulated bits to generate the output. For example, assuming each digital value has B bits, CDMA® would transmit a total of B*L output levels, whereas this new digital (or analog) encoding technique only transmits a total of L output levels, which is advantageous.

[0159] Figure 20 shows the decoding of analog input levels encoded using the analog encoder described above. As shown in the figure, L input levels 950 are received through a single electromagnetic path of the transmission medium 34. As described herein and mentioned earlier, the codebook 920 contains N orthogonal codes 932-938 used to decode the input levels 950 to produce output vectors of N analog values ​​902-908, i.e., the same analog values ​​902-908 encoded above. To perform the decoding, each input level 952-958 is modulated 961 by each chip of each code corresponding to a specific index of the output vector 902-908, as shown by the vertical arrows. Considering the modulation of levels 952-958 by the first code 932, such modulation produces a set of modulated values ​​"2, 0, 0.6, -1.4". Modulation of levels 952-958 by the second code 934 produces a set of modulated values ​​"2, 0, -0.6, 1.4". Modulation using the third code 936 generates "2, 0, -0.6, -1.4", and modulation using the fourth code 938 generates "2, 0, 0.6, 1.4".

[0160] Next, as indicated by the horizontal arrows, each sequence of modulated values ​​is summed to produce one of the analog values ​​902–908. For example, the first sequence is summed to produce the analog value "1.2" (which becomes "0.3" after being normalized using a scaling factor of "4"). Similarly, the other three sequences of modulated values ​​are summed to produce the analog values ​​"2.8", "0", and "4", and after being normalized, the output vector of analog values ​​902–908 is obtained. Each code may modulate the input level before its sequence is summed, or all may modulate the input level before each sequence is summed. In this way, the N output vectors of analog values ​​902–908 are transmitted in parallel using L output levels.

[0161] These examples do not demonstrate decoding of digital input levels, but those skilled in the art will see that such decoding is straightforward once they read the above description of encoding digital values.

[0162] Figures 21A, 21B, and 21C illustrate that encoders and decoders can operate with either analog or digital sampling. These various analog and digital encoders and decoders are described above. As described above, multiple EM paths exist, and accordingly, multiple encoder / decoder pairs exist, and in some cases, a corresponding number of DACs or ADCs may exist.

[0163] Figure 21A shows the use of an analog encoder and a corresponding analog decoder. The input to the analog encoder 900 is either an analog sample 970 or a digital sample 971 converted to analog by a DAC 972 located in the analog encoder. In this way, either the analog or digital sample arriving at the analog encoder can be encoded for transmission over the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 may be used as is or converted to a digital sample using an ADC (not shown).

[0164] Figure 21B illustrates the use of a digital encoder and a corresponding analog decoder. The input to the digital encoder 901 is either a digital sample 971 or an analog sample 970 that has been converted to digital by an ADC 973 located in the digital encoder. Because the encoder is digital, a DAC 959 located in the encoder converts the encoded sample to analog before transmission over the electromagnetic path. In this way, analog or digital samples arriving at the digital encoder can be encoded for transmission over the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 may be used as is or converted to a digital sample using an ADC (not shown).

[0165] Figure 21C illustrates the use of a digital decoder to decode an encoded analog signal arriving via an electromagnetic path on the transmission medium 34. The encoded analog signal can be transmitted using either an analog encoder or a digital encoder, as described above. The ADC 974, located in the digital decoder 976, receives the encoded analog samples transmitted via the electromagnetic path and converts the samples into a digital format. These encoded digital samples are then decoded by the digital decoder 976 into digital samples 978 (corresponding to the values ​​of the input vectors of the samples that were originally encoded before being transmitted via the electromagnetic path). The digital samples 978 may be used as is or converted into analog samples using a DAC.

[0166] Figure 22 shows a simulation (similar to an idealized oscilloscope trace) of the SSVT waveform 602 transmitted via the electromagnetic path after output from the analog encoder (or after digital encoding and conversion by the DAC). The vertical scale is voltage, and the horizontal scale is an oscilloscope measurement time interval of 100 ps. Note that the SSVT signal 602 is an analog waveform, not a digital signal (i.e., the signal does not represent a binary number), and in embodiments, it can transmit voltages ranging from approximately -15V to approximately +15V. The voltage values ​​of the analog waveform are entirely analog (or at least can be). Also, the voltage values ​​are not limited to a certain maximum value, although high values ​​are not practical.

[0167] As explained earlier, analog voltage levels are transmitted sequentially through the electromagnetic path, and each level is the sum of modulated samples per time interval, such as the analog output levels 952-958 above or the digital output levels 952'-958' above (after passing through the DAC). When transmitted, these output levels appear as waveforms, such as waveform 602. In particular, voltage level 980 represents a sample (i.e., an output level) at a specific time interval of modulated samples. Using a simplified example, consecutive voltage levels 980-986 represent the transmission of four output levels. In this example, 32 codes are used, meaning that 32 samples may be transmitted in parallel. Thus, voltage levels 980-986 (followed by a number of subsequent voltage levels depending on the number of chips L in the code) form a parallel transmission of 32 encoded samples (such as pixel voltages from a video source). Following that transmission, the next set of L voltage levels in waveform 602 represents the transmission of the next 32 samples. Generally, waveform 602 represents encoding analog or digital values ​​into analog output levels and transmitting those levels at discrete time intervals to form a composite analog waveform.

[0168] Because all electromagnetic paths degrade the electromagnetic signals propagating through them due to phenomena such as attenuation, reflection due to impedance mismatch, and collisional attack signals, the measured input level at the receiving terminal is always subject to error with respect to the corresponding output level available at the transmitting terminal. Therefore, as is known in the art, this can be corrected by scaling the input level at the receiver (or normalizing or amplifying the output level at the transmitter). Furthermore, due to process gain (i.e., increasing L also increases electrical resilience), the decoded input level at the decoder is normalized by a scale factor using the code length to recover the transmitted output level, as is known in the art. Furthermore, as described herein, it is preferable that L>=N>=2, but in some situations L may be less than N, i.e., N>L>=2.

[0169] <Additional Embodiments> The present invention includes these additional embodiments. L1. A method for transmitting video samples in a mobile device, The process involves receiving a color digital video sample generated by the image sensor of the mobile device after color interpolation, Of each set of received color samples, only the G video sample is distributed to at least one electromagnetic path of the transmitter. A method comprising transmitting the G video sample as an analog level to the processor of the portable device via the electromagnetic path. L2. The method according to claim L1, wherein the analog level is the G video sample. L3. Distributing the G video samples to the first line buffer and the second line buffer, The method according to claim L2, further comprising alternately outputting the G video samples from the first line buffer and the second line buffer to each of the at least one electromagnetic path. L4. The method according to claim L1, further comprising encoding each vector of N G video samples input to each of the at least one electromagnetic path using a set of N mutually orthogonal spreading codes to produce L analog levels, wherein L>=N>=2, and each of the codes is used to encode one of the G video samples.

[0170] M1. A method for transmitting video samples in a processor of a mobile device, The receiver of the processor receives, via at least one electromagnetic path, an input analog level representing a G video sample generated by the image sensor of the portable device, The aforementioned G analog video samples are collected into a stream of analog video samples, The aforementioned G analog video sample is subjected to analog processing, The processed G analog video sample is transmitted from the processor to the display of the mobile device as an output analog level. A method that includes this. M2. The method according to claim M1, further comprising transmitting the processed G analog video sample to the DDIC-TCON via a MIPI interface before the transmission. M3. In the method according to claim M1, the transmission is: The processed G analog video samples are distributed to a first line buffer and a second line buffer, A method further comprising alternately outputting the processed G analog video samples from the first line buffer and the second line buffer to each of at least one electromagnetic path. M4. The method according to claim M1, further comprising encoding each vector of N processed G analog video samples input to each of at least one electromagnetic path using a set of N mutually orthogonal spreading codes to produce L output analog levels, wherein L>=N>=2, and each of the codes is used to encode one of the processed G analog video samples.

[0171] N1. A method for displaying a color signal in a DDIC (Display Driver Integrated Circuit) of a mobile device, In the aforementioned DDIC, at least one electromagnetic path is used to receive an analog level representing a G analog video sample from the processor of the portable device, In the collector of the DDIC, the G analog video sample corresponding to the analog level is collected, A method comprising driving the G analog video samples to the display of the mobile device without including a digital-to-analog converter (DAC) used to convert the digital video samples to the G analog video samples. N2. The analog video sample G is at the analog level, The aforementioned G analog video samples are collected into a first line buffer and a second line buffer, The method according to claim N1, further comprising alternately outputting the G analog video samples from the first line buffer and the second line buffer to the display. N3. The method according to claim N1, further comprising, prior to the collection, using a set of N mutually orthogonal spreading codes to decode each set of L analog levels from each of the at least one electromagnetic path to generate N G analog video samples, wherein L>=N>=2, and each of the codes is used to generate one of the G analog video samples.

[0172] O1. A method for transmitting video samples in a mobile device, Of the set of color video samples generated by the image sensor of the mobile device, only the G analog video sample is transmitted as an analog level to the processor of the mobile device via at least one electromagnetic path. The analog processing is performed on the aforementioned G analog video sample, The processor transmits the G analog video samples as analog levels from the processor to the DDIC of the mobile device without including an analog-to-digital converter (ADC) used to convert the G analog video samples. A method comprising driving the G analog video samples corresponding to the analog levels to the display of the portable device, without including a digital-to-analog converter (DAC) used to convert the digital video samples to the G analog video samples. The method according to claim O1, further comprising distributing the G analog video samples to a first line buffer and a second line buffer, and transmitting the G analog video samples by alternately outputting the G analog video samples from the first line buffer and the second line buffer to each of the at least one electromagnetic path. O3. The method according to claim O1, further comprising transmitting the G analog video samples by encoding each vector of N G analog video samples input to each of at least one electromagnetic path using a set of N mutually orthogonal spreading codes to generate L input analog levels, wherein L>=N>=2, and each of the codes is used to encode one of the G analog video samples.

[0173] P1. A method for transmitting video samples in a mobile device, The process involves reading samples from the image sensor of the aforementioned mobile device, wherein two lines of samples are mixed during the reading process, generating a stream of mixed analog video samples. The transmitter receives the mixed stream of analog video samples, The analog video samples are distributed to at least one electromagnetic path, A method comprising transmitting the analog video samples as analog levels to the processor of the portable device via the electromagnetic path without using an analog-to-digital converter (ADC) to convert the analog video samples. P2. The method according to claim P1, wherein the analog level is the analog video sample. P3. The method according to claim P2, further comprising distributing the analog video samples to a first line buffer and a second line buffer, and alternately outputting the analog video samples from the first line buffer and the second line buffer to each of the at least one electromagnetic path. P4. The method according to claim P1, further comprising encoding each vector of N analog video samples input to each of the at least one electromagnetic path using a set of N mutually orthogonal spreading codes to produce L analog levels, wherein L>=N>=2, and each of the codes is used to encode one of the analog video samples.

[0174] Q1. A method for transmitting video samples in a mobile device processor, The receiver of the processor receives, via at least one electromagnetic path, an input analog level representing a stream of analog video samples generated by the image sensor of the portable device, wherein the stream includes a mixture of two rows of samples from the image sensor. The analog level is collected into the stream of the analog video samples, The process involves performing color interpolation on the aforementioned stream of analog video samples to generate analog color video samples, A method comprising transmitting the aforementioned analog color video sample from the processor to the display of the portable device as an output analog level. Q2. The method according to claim Q1, further comprising transmitting the analog color video sample to the DDIC-TCON via a MIPI interface before the transmission. Q3. The above transmission involves distributing the analog color sample to the first line buffer and the second line buffer, The method according to claim Q1, further comprising alternately outputting the analog color sample from the first line buffer and the second line buffer to each of at least one electromagnetic path. Q4. The method according to claim Q1, further comprising encoding each vector of N analog color samples input to each of at least one electromagnetic path using a set of N mutually orthogonal spreading codes to produce L output analog levels, wherein L>=N>=2, and each of the codes is used to encode one of the analog color samples.

[0175] R1. A method for displaying a color signal in a DDIC (Display Driver Integrated Circuit) of a mobile device, The DDIC receives an analog level representing an analog color video sample from the processor of the portable device via at least one electromagnetic path, In the collector of the DDIC, the analog color video sample corresponding to the analog level is collected, A method comprising the DDIC driving the analog color video samples to the display of the portable device without including a digital-to-analog converter (DAC) used to convert the digital video samples to the analog color video samples. R2. The analog color video sample is at the analog level, The analog color video samples are collected into a first line buffer and a second line buffer, The method according to claim R1, further comprising alternately outputting the analog color video samples from the first line buffer and the second line buffer to the display. R3. The method according to claim R1, further comprising: before the collection, a set of N mutually orthogonal spreading codes is used to decode each set of L analog levels from each of the at least one electromagnetic path to generate N analog color video samples, where L>=N>=2, and each of the codes is used to generate one of the analog color video samples.

[0176] S1. A method for transmitting video samples in a mobile device, The process involves reading samples from the image sensor of the aforementioned mobile device, wherein two lines of samples are mixed during the reading process, generating a stream of mixed analog video samples. The mixed stream of analog video samples is transmitted as an input analog level to the processor of the portable device via at least one electromagnetic path, wherein an analog-to-analog converter (ADC) is not used to convert the analog video samples. The process involves performing color interpolation on the aforementioned stream of analog video samples to generate analog color video samples, The process involves transmitting the analog color video sample from the processor to the DDIC of the portable device as an output analog level, A method comprising driving the analog color samples corresponding to the analog levels to the display of the portable device, without including a digital-to-analog converter (DAC) used to convert the digital video samples to the analog color video samples. The method according to claim S1, further comprising S2. Distributing the mixed analog video samples to a first line buffer and a second line buffer, and transmitting the mixed analog video samples by alternately outputting the mixed analog video samples from the first line buffer and the second line buffer to each of the at least one electromagnetic path. S3. The method according to claim S1, further comprising transmitting the mixed analog video samples to generate L input analog levels, wherein each vector of N mixed analog video samples input to each of at least one electromagnetic path is encoded using a set of N mutually orthogonal spreading codes, and each of the codes is used to encode one of the analog video samples.

[0177] A1. A distributor configured to receive multiple streams of digital video samples generated by a system-on-chip of a mobile device and to distribute the digital video samples to multiple input vectors according to a predetermined permutation, A transmitter comprising a plurality of digital-to-analog converters (DACs), each configured to receive the digital video sample from one of the input vectors, convert the digital video sample from one of the input vectors into a series of analog video samples, and output the series of analog video samples to the display of the mobile device via an electromagnetic path. A2. The aforementioned distributor is A first line buffer that stores the plurality of input vectors, The transmitter according to claim A1, further comprising a second line buffer for storing a plurality of second input vectors, wherein a distributor is further arranged to alternately distribute lines of the digital video samples between the input vectors of the first line buffer and the second input vectors of the second line buffer, and the DAC alternately reads from the first line buffer while the distributor writes to the second line buffer, and from the second line buffer while the distributor writes to the first line buffer. A3. The transmitter according to claim A1, wherein the digital video samples distributed to the input vector constitute lines of an image. A4. The transmitter according to claim A1, wherein the digital video samples are distributed to the input vector at a first frequency, and the digital video samples are output from each of the input vectors at a second frequency different from the first frequency. A5. The transmitter according to claim A1, wherein the predetermined permutation allows each sampling amplifier of the source driver receiving one of the series of analog video samples to output the analog video sample to a contiguous storage location. A7. The transmitter is integrated with the timing controller of the SoC, and the integrated transmitter / timing controller is The transmitter according to claim A1, further comprising a gate driver control signal output to the gate driver of the display panel. A8. The integrated transmitter timing controller according to claim A7, wherein the integrated transmitter timing controller is located within the system-on-chip. A10. The transmitter according to claim A5, wherein the predetermined permutation allows one of the sampling amplifiers to sample only control signals. A11. The transmitter according to claim A1, further comprising a plurality of image processors, each image processor configured to read the digital video sample of one input vector from one of the input vectors, perform at least gamma correction on the digital video sample of one input vector, and output the corrected digital video sample of one input vector to one of the corresponding DACs.

[0178] B1. Source driver for mobile devices, An input terminal that receives analog electromagnetic signals via an electromagnetic path including a series of analog video samples, A plurality of sampling amplifiers, each configured to sample only a portion of the analog video sample and write the portion of the analog video sample to a location on a storage array specified for each sampling amplifier, A source driver comprising: a plurality of column drivers, each configured to read one of the analog video samples from one of the locations in the storage array, amplify one of the analog video samples, and drive one of the amplified analog video samples to a column of the display of the mobile device. B2. Source driver according to claim B1, further comprising a second storage array having designated positions for each sampling amplifier, wherein the sampling amplifier is configured to alternately write the respective portions of the analog video samples to the storage array or to the second storage array, and the column driver alternately reads from the storage array while the sampling amplifier is writing to the second storage array, and reads from the second storage array while the sampling amplifier is writing to the storage array. B3. The source driver according to claim B2, further comprising a control logic circuit configured to enable each of the sampling amplifiers to sample the portion of the analog video sample, to enable the sampling amplifiers to write to the storage array or the second storage array, and to enable the column driver to read from the storage array or the second storage array. B3. The source driver according to claim B1, wherein the electromagnetic signal includes a control signal used for synchronization and not driven to the columns of the display panel, and the source driver further includes a sampling amplifier dedicated to sampling the control signal. B4. The source driver according to claim B1, wherein the source driver does not include a digital-to-analog converter (DAC) used to convert video samples. B5. The source driver according to claim B2, wherein the column driver is further configured to read in parallel from the storage array when the storage array is full, or to read in parallel from the second storage array when the second storage array is full. B6. The source driver according to claim B1, wherein the series of analog video samples arrive in a predetermined permutation that enables each sampling amplifier to output each portion of the analog video samples to a contiguous storage location in the storage array. B7. The source driver according to claim B6, wherein the predetermined permutation indicates that one of the sampling amplifiers samples only the control signal.

[0179] E1. A video transmission device for a mobile device, It is a transmitter, A distributor configured to receive a stream of digital video samples and distribute the digital video samples to a plurality of input vectors in a line buffer according to a predetermined permutation, A digital-to-analog converter (DAC) for each input vector, wherein each DAC is configured to receive the digital video sample from its corresponding input vector and convert the digital video sample into a series of analog video samples, A transmitter having, A plurality of electromagnetic paths, each configured to transmit one of the series of analog video samples to the display of the mobile device, A source driver array including a source driver corresponding to each of the aforementioned DACs, wherein each source driver is A collector configured to receive the series of analog video samples from each of the aforementioned DACs and store the analog video samples of the corresponding input vectors, Multiple column drivers are configured to receive the stored analog video samples in parallel from the collector and to amplify each of the stored analog video samples for the column of the display, A source driver array having, A video transmission device equipped with the following features. E2. The video transmission apparatus according to claim E1, wherein the predetermined permutation allows each collector to store its respective analog video sample in a contiguous storage location. E3. The video transmission apparatus according to claim E1, wherein the predetermined permutation allows the sampling amplifier of the collector to sample only control signals.

[0180] C1. A device that integrates a timing controller and a transmitter, A distributor configured to receive multiple streams of digital video samples generated by a system-on-a-chip of a mobile device and to distribute the digital video samples to multiple input vectors according to a predetermined permutation, A plurality of digital-to-analog converters (DACs), each configured to receive the digital video sample from the input vector, convert the digital video sample into a series of analog video samples, and output the series of analog video samples to the display of the mobile device via an electromagnetic path, The gate driver control signal output to the gate driver of the aforementioned display, A device equipped with the following features. C2. The aforementioned distributor is A first line buffer that stores the plurality of input vectors, The apparatus according to claim C1, further comprising: a second line buffer storing a plurality of second input vectors, wherein a distributor is further configured to alternately distribute the lines of the digital video sampling between the input vectors of the first line buffer and the second input vectors of the second line buffer, and the image processor alternately reads from the first line buffer while the distributor writes to the second line buffer, and reads from the second line buffer while the distributor writes to the first line buffer. C3. The apparatus according to claim C1, wherein the digital video samples distributed to the input vector constitute lines of an image. C4. The apparatus according to claim C1, wherein the digital video samples are distributed to the input vector at a first frequency, and the digital video samples are output from each of the input vectors at a second frequency different from the first frequency. C8. The apparatus according to claim C1, wherein the apparatus is located within the system-on-chip. C10. The apparatus according to claim C9, wherein the apparatus is integrated within the system-on-chip of the portable device. C11. The apparatus according to claim C1, further comprising a plurality of image processors, each image processor configured to read the digital video sample of one input vector from one of the input vectors and to perform at least gamma correction on the digital video sample of the one input vector. C12. The apparatus according to claim C1, further comprising display RAM configured to store video samples for the display of the portable device. C13. The apparatus according to claim C12, wherein the apparatus is integrated within the system-on-chip of the portable device. C14. The apparatus according to claim C13, further comprising an image enhancement component.

[0181] D1. Analog DDIC-SD (Display Driver Integrated Circuit - Source Driver) for mobile devices, An input terminal configured to receive an analog electromagnetic signal via an electromagnetic path containing a series of analog video samples, A plurality of sampling amplifiers, each configured to sample only a portion of the analog video sample and write the portion of the analog video sample to a location on a storage array specified for each sampling amplifier, An analog DDIC-SD comprising: a plurality of column drivers, each configured to read one of the analog video samples from one of the positions of the storage array, amplify one of the analog video samples, and drive one of the amplified analog video samples relative to a column of the display of the mobile device. D2. The analog DDIC-SD according to claim D1, further comprising a second storage array having designated positions for each sampling amplifier, wherein the sampling amplifier is further configured to alternately write the respective portions of the analog video samples to the storage array or to the second storage array, and the column driver alternately reads from the storage array while the sampling amplifier is writing to the second storage array, and reads from the second storage array while the sampling amplifier is writing to the second storage array. D3. The analog DDIC-SD according to claim D2, further comprising a control logic circuit configured to enable each of the sampling amplifiers to sample the portion of the analog video sample, to enable the sampling amplifiers to write to the storage array or the second storage array, and to enable the column driver to read from the storage array or the second storage array. D3. The analog DDIC-SD according to claim D1, wherein a portion of the analog video samples is used for synchronization and is not driven relative to the rows of the display. D4. The analog DDIC-SD according to claim D1, wherein the analog DDIC-SD does not include a digital-to-analog converter (DAC) used to convert video samples. D5. The analog DDIC-SD according to claim D2, wherein the column driver is further configured to read in parallel from the storage array when the storage array is full, or to read in parallel from the second storage array when the second storage array is full. D6. The analog DDIC-SD according to claim D1, wherein the series of analog video samples arrive in a predetermined permutation that stipulates that each sampling amplifier outputs each portion of the analog video sample to a contiguous storage location in the storage array. D7. The analog DDIC-SD according to claim D1, wherein the analog electromagnetic signal includes a control signal used for synchronization and not driven for the rows of the display panel, and the source driver further includes a sampling amplifier dedicated to sampling the control signal. D8. The analog DDIC-SD according to claim D1, wherein the analog DDIC-SD does not include a timing controller. D9. The analog DDIC-SD according to claim D8, wherein the analog DDIC-SD does not include an image enhancement component. D10. The analog DDIC-SD according to claim D8, wherein the analog DDIC-SD does not include display RAM.

[0182] F1. Video transmission device, It is a transmitter, A distributor configured to receive a stream of digital video samples from a system-on-a-chip of a mobile device and distribute the digital video samples to a plurality of input vectors in a line buffer according to a predetermined permutation, A digital-to-analog converter (DAC) for each input vector, wherein each DAC is configured to serially receive the digital video sample from the corresponding input vector and convert the digital video sample into a series of analog video samples, A transmitter having, A plurality of electromagnetic paths, each configured to transmit one of the series of analog video samples to the display of the mobile device, A source driver array including a source driver corresponding to each of the aforementioned DACs, wherein each source driver is A collector configured to receive the series of analog video samples from each of the aforementioned DACs and store the analog video samples of the corresponding input vectors, Multiple column drivers are configured to receive the stored analog video samples in parallel from the collector and to amplify each of the stored analog video samples for the column of the display, A video transmission device comprising a source driver array having a source driver array. F2. The apparatus according to claim F1, wherein the transmitter is integrated into a timing controller and further comprises a gate driver control signal that is output to the gate driver of the display. F3. The apparatus according to claim F2, wherein the transmitter is located within the system-on-chip of the portable device. F4. The apparatus according to claim F2, wherein the transmitter is integrated within a single integrated circuit of the portable device. F6. The apparatus according to claim F1, wherein each source driver is located within the analog DDIC-SD (display driver integrated circuit - source driver) of the mobile device. F7. The apparatus according to claim F6, wherein the analog DDIC-SD does not include a digital-to-analog converter (DAC) used to convert video samples.

[0183] G1. A video transmission device for a mobile device, A transmitter that receives a stream of analog video samples from the image sensor of the mobile device and transmits the stream to the system-on-a-chip (SoC) of the mobile device, An electromagnetic path that receives the stream from the transmitter and transmits the stream to the SoC of the mobile device, A receiver of the SoC that receives the stream and distributes the stream for processing on the SoC, A video transmission device equipped with the following features. G2. The apparatus according to claim G1, wherein the transmitter is integrated into the camera module of the portable device. G3. The apparatus according to claim G1, wherein the camera module does not include an ADC for converting video samples. G4. The apparatus according to claim G1, wherein the stream is not transmitted using MIPI. G5. The apparatus according to claim G1, wherein the camera module does not include a MIPI interface. G6. The apparatus according to claim G1, wherein the SoC does not include a MIPI interface. G7. The apparatus according to claim G1, further comprising an ADC located in the SoC, which is positioned after the receiver and converts the stream into a stream of digital video samples for processing in the SoC.

Claims

1. A method for transmitting video samples on a mobile device, The transmitter receives analog video samples read from the image sensor of the portable device, The analog video samples are distributed to at least one electromagnetic path, To convert the aforementioned analog video samples, without using an analog-to-digital converter (ADC), the analog video samples are transmitted as analog levels to the processor of the mobile device via the electromagnetic path. A method that includes this.

2. The method according to claim 1, wherein the analog level is the analog video sample.

3. Distributing the analog video samples to the first line buffer and the second line buffer, The analog video samples are alternately output from the first line buffer and the second line buffer to each of the at least one electromagnetic path, The method according to claim 2, further comprising:

4. The method further includes encoding each vector of N analog video samples input to each of the at least one electromagnetic path using a set of N mutually orthogonal spreading codes to generate L analog levels, The method according to claim 1, wherein L >= N >= 2, and each of the spreading codes is used to encode one of the analog video samples.

5. A method for transmitting video samples in a mobile device processor, The receiver of the processor receives a received analog level representing an analog video sample generated by the image sensor of the portable device via at least one electromagnetic path, The aforementioned analog video samples are collected into a stream of analog video samples, Converting the analog video samples to digital video samples using at least one analog-to-digital converter (ADC), The process involves performing color interpolation on the aforementioned digital video sample to generate a color sample, The aforementioned color sample is transmitted from the processor to the DDIC-SD of the mobile device's display as an output analog level, A method that includes this.

6. The method according to claim 5, further comprising transmitting the color sample to a DDIC-TCON via a MIPI interface before transmitting the color sample from the processor to the DDIC-SD of the display of the mobile device as an output analog level.

7. Transmitting the aforementioned color sample as an output analog level from the processor to the DDI-SD of the mobile device's display is: The color samples are distributed to the first line buffer and the second line buffer, The method according to claim 5, further comprising alternately outputting the color sample from the first line buffer and the second line buffer to each of at least one electromagnetic path.

8. Transmitting the aforementioned color sample as an output analog level from the processor to the DDI-SD of the mobile device's display is: The method further includes encoding each vector of N color samples input to each of at least one electromagnetic path using a set of N mutually orthogonal spreading codes to generate L output analog levels. The method according to claim 5, wherein L >= N >= 2, and each of the codes is used to encode one of the color samples.

9. A method for displaying a color signal in a display driver integrated circuit (DDIC) for a mobile device, The DDIC receives an analog level representing a digital video sample from the processor of the mobile device via at least one electromagnetic path, In the collector of the DDIC, analog video samples corresponding to the analog level are collected, The DDIC drives the analog video samples to the display of the mobile device without including a digital-to-analog converter (DAC) used to convert the digital video samples to the analog video samples, A method that includes this.

10. The analog video sample is at the analog level, The analog video samples are collected into a first line buffer and a second line buffer, The method according to claim 9, further comprising alternately outputting the analog video samples from the first line buffer and the second line buffer to the display.

11. Prior to the aforementioned collection, the method further includes using a set of N mutually orthogonal spreading codes to decode each set of L analog levels from each of the at least one electromagnetic path to generate N analog video samples. The method according to claim 9, wherein L >= N >= 2, and each of the codes is used to generate one of the analog video samples.

12. A method for transmitting video samples on a mobile device, Before transmission, the analog video samples read from the image sensor of the mobile device are transmitted as input analog levels to the processor of the mobile device via at least one electromagnetic path, without using an analog-to-digital converter (ADC) to convert the analog video samples. The processor includes, at least one analog-to-digital converter (ADC) used to convert the analog video samples into digital video samples, The process involves performing color interpolation on the aforementioned digital video sample to generate a digital color sample, The process involves transmitting the digital color sample from the processor to the DDIC of the mobile device as an output analog level, A method comprising the DDIC driving analog samples corresponding to the output analog level to the display of the portable device, without including a digital-to-analog converter (DAC) used to convert the digital color samples to the analog video samples.

13. The analog video samples are distributed to a first line buffer and a second line buffer, The analog video sample is transmitted by alternately outputting the analog video sample from the first line buffer and the second line buffer to each of the at least one electromagnetic path, The method according to claim 12, further comprising:

14. The method further includes transmitting the analog video samples to generate L of the input analog video samples by encoding each vector of N analog video samples input to each of at least one electromagnetic path using a set of N mutually orthogonal spreading codes, The method according to claim 12, further comprising L >= N >= 2, and each of the codes being used to encode one of the analog video samples.

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