Microelectronic devices including vertical planar memory cell structures, and related memory devices and electronic systems

Abstract

A method for forming a microelectronic device, comprising the steps of: forming a preliminary stack structure having layers of sacrificial material and insulating material on a substrate structure; forming a slot extending perpendicularly to the preliminary stack structure, the slot having a first region and a second region; forming a memory cell material, a mask material and a trim material within the slot; removing a portion of the trim material in the first region of the slot; removing a portion of the trim material, the mask material and the memory cell material in the second region of the slot to form a memory string structure; and replacing the sacrificial material in the layers of the preliminary stack structure with a conductive material. The first region extends horizontally in a first direction, the second region intersects the first region and extends horizontally in a second direction. The memory string structures are horizontally separated from each other in the second direction.

Description

[Technical Field]

[0001] Priority Claim This application claims priority based on the filing date of U.S. Patent Application No. 18 / 424,709, filed on 26 January 2024, and further claims priority under 35 U.S.C § 119(e) based on U.S. Provisional Patent Application No. 63 / 492,290, filed on 27 March 2023. The disclosures of both of these applications are incorporated herein by reference in their entirety.

[0002] This disclosure relates, in various embodiments, to the field of design and manufacture of microelectronic devices in general. More specifically, this disclosure relates to methods for forming microelectronic devices, as well as related microelectronic devices, memory devices, and electronic systems. [Background technology]

[0003] Designers of microelectronic devices often want to increase the integration density or feature density within the device by reducing the dimensions of individual features and decreasing the spacing between adjacent features. Furthermore, designers of microelectronic devices often strive to design an architecture that is not only compact but also offers performance advantages and simplifies the design.

[0004] One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers and other electronic devices. There are many types of memory devices, including (but not limited to) non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also called a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array includes memory cell strings that extend vertically through one or more stacked structures containing layers of conductive and insulating materials. Each memory cell string may include at least one select element connected to it. With such a configuration, compared to conventional planar (i.e., two-dimensional) transistor array structures, it is possible to place more switching devices (e.g., transistors) within a unit die area (i.e., the length and width of the active surface consumed) by forming the array upward (i.e., vertically) on the die.

[0005] A vertical memory array architecture generally involves electrical connections between conductive materials and control logic devices (e.g., string drivers) in layers of the memory device's stack structure. This allows for the individual selection of memory cells in the vertical memory array for writing, reading, or erasing operations.

[0006] However, as the density of features increases and the tolerance for formation errors decreases, undesirable defects may occur in conventional manufacturing methods and the resulting structural configurations, and such defects may reduce the desired performance, reliability, and durability of the memory device. [Overview of the project]

[0007] In some embodiments, a method for forming a microelectronic device includes the step of forming a pre-stack structure having a plurality of layers on a substrate structure, each layer of the pre-stack structure comprising a sacrificial material and an insulating material perpendicularly adjacent to the sacrificial material. Furthermore, a slot is formed extending vertically through the pre-stack structure, the slot comprising a first region and a second region. The first region extends horizontally in a first direction, and the second region extends horizontally in at least one second direction that intersects the first region and forms an angle with respect to the first direction. Next, a memory cell material is formed in the slot, further, a mask material is formed on the memory cell material in the slot, and further, a trim material is formed on the mask material in the slot. Next, a portion of the trim material in the first region of the slot is removed, and further, a portion of the trim material, mask material and memory cell material is removed in the second region of the slot to form a memory string structure. Subsequently, the sacrificial material in each layer of the pre-stack structure is replaced with a conductive material after the memory string structure has been formed. As a result, the memory string structure extends vertically through the preliminary stack structure and is horizontally separated from each other in at least one second direction.

[0008] In some other embodiments, the microelectronic device includes a stack structure and a substrate structure located vertically below the stack structure. The stack structure has a plurality of layers, each layer comprising a conductive material and an insulating material perpendicularly adjacent to the conductive material. The stack structure is divided into blocks extending horizontally parallel to a first direction, and these blocks are separated from each other in a second direction by an insulating slot structure. The second direction is perpendicular to the first direction. At least one block has a slot extending vertically through all the layers and a memory string structure. The slot includes a first region and a second region intersecting the first region. The first region extends horizontally in the first direction, and the second region extends horizontally in at least one third direction. The third direction is at an angle to the first and second directions. The memory string structure extends vertically through the stack structure and is located within the horizontal region of the second region of the slot. The memory string structure is separated from each other horizontally in at least one third direction. The substrate structure includes a plug structure and additional conductive material, the plug structure being positioned within a horizontal region of a second region of a slot in at least one block and in contact with the memory string structure of the at least one block. Furthermore, the additional conductive material is in contact with the side surface of the plug structure.

[0009] In several other embodiments, the memory device comprises a stack structure and a substrate structure located vertically below the stack structure. The stack structure includes blocks extending parallel to a first horizontal direction, each block comprising a plurality of layers. Each layer comprises a conductive material and an insulating material perpendicularly adjacent to the conductive material. Each block individually includes at least partially filled slots and vertically extending memory cell strings. The at least partially filled slots extend vertically through the layers and have a backbone region and a rib region. The backbone region extends substantially linearly to the first horizontal direction, and the rib region intersects the backbone region. Each of the rib regions extends substantially linearly to at least one second horizontal direction at an angle to the first horizontal direction. The vertically extending memory cell strings are located within the horizontal region of the rib region of the at least partially filled slots. The substrate structure includes a plug structure and a laterally extending conductive structure, the plug structure being electrically connected to the vertically extending memory cell strings. Furthermore, the laterally extending conductive structure contacts the side wall of the plug structure. [Brief explanation of the drawing]

[0010] [Figure 1] This is a simplified partial top view of a microelectronic device structure in a processing step of a method for forming a microelectronic device according to the present disclosure. [Figure 2A] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2B] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2C] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2D]Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2E] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2F] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2G] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2H] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2I] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2J] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2K] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2L] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2M] Figure 1 shows a simplified partial perspective cross-sectional view of a part of the microelectronic device structure at different processing stages in the microelectronic device formation method. [Figure 2N]It is a simplified partial perspective cross-sectional view in different processing stages of a method for forming a microelectronic device, for a part of the microelectronic device structure shown in FIG. 1. [Figure 2O] It is a simplified partial perspective cross-sectional view in different processing stages of a method for forming a microelectronic device, for a part of the microelectronic device structure shown in FIG. 1. [Figure 2P] It is a simplified partial perspective cross-sectional view in different processing stages of a method for forming a microelectronic device, for a part of the microelectronic device structure shown in FIG. 1. [Figure 2Q] It is a simplified partial perspective cross-sectional view in different processing stages of a method for forming a microelectronic device, for a part of the microelectronic device structure shown in FIG. 1. [Figure 2R] It is a simplified partial perspective cross-sectional view of an additional part of the microelectronic device structure in the processing stage shown in FIG. 2Q. [Figure 3] It is a simplified partial top view of the microelectronic device structure following the processing stages of FIGS. 2Q and 2R. [Figure 4] It is a simplified partial top view of a microelectronic device structure according to another embodiment of the present disclosure. [Figure 5] It is a simplified partial top view of a microelectronic device structure according to still another embodiment of the present disclosure. [Figure 6] It is a simplified partial top view of a microelectronic device structure according to yet another embodiment of the present disclosure. [Figure 7] It is a simplified partial top view of a microelectronic device structure according to yet another embodiment of the present disclosure. [Figure 8] It is a simplified partial top view of a microelectronic device structure according to yet another embodiment of the present disclosure. [Figure 9] It is a schematic block diagram showing an electronic system according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0011] The following description includes specific details such as material composition, shape, and dimensions, and is intended to provide a sufficient description of embodiments of the disclosure. However, those skilled in the art should understand that embodiments of the disclosure can be carried out without using these specific details. In fact, embodiments of the disclosure can be carried out in combination with conventional microelectronic device manufacturing techniques used in the industry. The description provided below does not constitute a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not constitute a complete microelectronic device. Only the process operations and structures necessary to understand embodiments of the disclosure are described in detail below. Additional operations to form a complete microelectronic device from these structures can be carried out by conventional manufacturing techniques.

[0012] The drawings shown herein are for illustrative purposes only and are not intended to illustrate the actual shapes of any particular material, part, structure, device, or system. For example, it is naturally expected that the shapes shown in the drawings may differ from those shown due to manufacturing techniques and / or tolerances. Accordingly, embodiments described herein are not limited to any particular shape or area shown, and include, for example, variations in shape resulting from manufacturing. For example, an area shown or depicted as a box shape may not be perfectly box-shaped and / or may have nonlinear features, and an area shown or depicted as a circle may not be perfectly circular and / or may include linear features. Furthermore, an acute angle shown may be rounded, and vice versa. Accordingly, the areas shown in the drawings are schematic, and their shapes are not intended to illustrate the exact shape of an area and do not limit the scope of the claims. Also, the drawings are not necessarily to scale. Furthermore, elements common to multiple drawings may retain the same reference numeral.

[0013] In this specification, “memory device” means, but is not limited to, a microelectronic device that exhibits memory functionality. In other words, and to give a non-limiting example, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory such as conventional dynamic random access memory (DRAM), and conventional non-volatile memory such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0014] In this specification, the term "configured" means the size, shape, material composition, orientation and arrangement of one or more of at least one structure and at least one device that enables one or more of the structure or device to operate in a predetermined manner.

[0015] In this specification, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are defined based on the principal plane of the structure and not necessarily based on the Earth’s gravitational field. “Horizontal” or “lateral” means a direction substantially parallel to the principal plane of the structure, while “vertical” or “longitudinal” means a direction substantially perpendicular to the principal plane of the structure. Here, the principal plane of the structure is defined by a surface having a relatively large area compared to other surfaces of the structure. In the drawings, “horizontal” or “lateral” is perpendicular to the indicated “Z” axis and parallel to the indicated “X” or “Y” axis, while “vertical” or “longitudinal” is parallel to the indicated “Z” axis and perpendicular to the “X” and “Y” axes.

[0016] In this specification, features described as “adjacent” (e.g., regions, structures, elements) mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other (e.g., in the nearest location). Additional features (e.g., additional regions, additional structures, additional elements) that do not match the same attributes (or sets of attributes) of the “adjacent” features may be located between these “adjacent” features. In other words, “adjacent” features may be located directly adjacent to each other without any other features intervening between them, or they may be located indirectly adjacent to each other by the placement of at least one feature having attributes different from those associated with at least one of the “adjacent” features. Thus, features described as “vertically adjacent” mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other in the vertical direction (e.g., in the nearest vertical location). Furthermore, features described as “horizontally adjacent” mean, and include, features that have the same disclosed attributes (or sets of attributes) and are located closest to each other in the horizontal direction (e.g., in the nearest horizontal location).

[0017] In this specification, terms describing positional relationships such as “beneath,” “below,” “lower,” “bottom,” “over / above,” “upper,” “top,” “top,” “front,” “rear,” “left,” and “right” are used for convenience in describing the relationship between elements or features shown in drawings and other elements or features. Unless otherwise specified, these terms describing positional relationships are intended to include different orientations of the material in addition to the orientation shown in the drawing. For example, if the material shown in the drawing is inverted, an element described as “below,” “beneath,” or “on bottom of” another element or feature will be positioned as “above” or “on top of” that other element or feature. Furthermore, when a material is formed to cover a surface (e.g., a substantially perpendicular side wall of a structure), it can be described as formed on that surface, i.e., "formed over," even if the material is not necessarily physically located above that surface. Similarly, the surface can be described as being "under" the material on which it is formed. Therefore, those skilled in the art should understand that the term "below" can encompass both "above" and "below" positions depending on the context in which it is used. Materials can be positioned in other orientations (e.g., rotated 90 degrees, inverted, or flipped), in which case the positional relationships used herein shall be interpreted accordingly.

[0018] In this specification, unless the context explicitly indicates that an element is singular, the term includes cases where such element is plural.

[0019] In this specification, items listed with "and / or" include any one or any combination of the listed items.

[0020] In this specification, the expression "coupled to" refers to structures that are operationally coupled and connected, including, for example, direct ohmic electrical connections or indirect connections via other structures (e.g., connections via other structures).

[0021] In this specification, the term “substantially” means, and includes, that a given parameter, characteristic, or condition is met to the extent that a person skilled in the art would understand that such parameter, characteristic, or condition is met within an acceptable range of variation. For example, depending on the specific parameter, characteristic, or condition that is substantially met, that parameter, characteristic, or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or 100.0%.

[0022] In this specification, the terms “about” or “approximately” refer to a numerical value relating to a particular parameter and include both the numerical value itself and the degree of variation that a person skilled in the art would understand to be acceptable with respect to that parameter. For example, “about” or “approximately” with respect to a numerical value may include a value in the range of 90.0% to 110.0%, a value in the range of 95.0% to 105.0%, a value in the range of 97.5% to 102.5%, a value in the range of 99.0% to 101.0%, a value in the range of 99.5% to 100.5%, or a value in the range of 99.9% to 100.1%.

[0023] In this specification, "insulative material" means, and includes, materials that are electrically insulating. Electrically insulating materials may include, for example, the following: at least one of the following dielectric oxide materials (e.g., silicon oxide (SiOx), silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), magnesium oxide (MgOx)); at least one of the following dielectric nitride materials (e.g., silicon nitride (SiNy)); at least one of the following dielectric oxynitride materials (e.g., silicon oxynitride (SiOxNy)); and at least one of the following dielectric carbonate nitride materials (e.g., silicon carbonate (SiOxCzNy)). In this specification, formulas containing "x", "y", and "z" (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent materials having an average ratio of "x" other elements, "y" other elements, and (if present) "z" additional elements for every one atom of an element. Because these formulas represent relative atomic ratios rather than exact chemical structures, insulating materials may contain one or more stoichiometric compounds and / or one or more non-stoichiometric compounds. The values ​​of "x", "y", and "z" (if present) may be integers or non-integers. In this specification, "non-stoichiometric compound" means, and includes, compounds whose elemental composition cannot be expressed by clear natural number ratios and which do not obey the law of constant proportions. Furthermore, "insulative structure" means, and includes, structures formed from and containing insulating materials.

[0024] In this specification, “sacrificial material” means, including, a single material that is selectively etchable with respect to one or more other materials (e.g., one or more insulating materials). The sacrificial material may be selectively etchable with respect to one or more other materials upon common exposure to a first etchant (e.g., collective or reciprocal exposure), and one or more other materials may be selectively etchable with respect to the sacrificial material upon common exposure to a second different etchant. In this specification, a material is “selectively etchable” with respect to another material if it exhibits an etching rate at least about 5x that of the other material, including, for example, about 10x, 20x, or 40x. As a non-limiting example, depending on the material composition of one or more other materials, the sacrificial material may be formed from and include at least one dielectric oxide material (e.g., SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric oxycarbide material (e.g., SiOxCy), at least one hydrogenated dielectric oxycarbide material (e.g., SiCxOyHz), at least one dielectric carbonate nitride material (e.g., SiOxCzNy), and at least one semiconductor material (e.g., polycrystalline silicon). The sacrificial material may be selectively etchable to one or more other materials upon common exposure to a wet etchant containing, for example, phosphoric acid (H3PO4). Furthermore, "sacrificial structure" refers to a structure formed from and containing sacrificial material.

[0025] In this specification, "conductive material" means and includes materials that are electrically conductive. Examples of electrically conductive materials include one or more metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., This includes Co-based alloys, Fe-based alloys, Ni-based alloys, Fe-Ni-based alloys, Co-Ni-based alloys, Fe-Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Furthermore, "conductive structure" means a structure formed from or containing conductive materials or materials containing conductive materials, and includes such structures.

[0026] In this specification, "semiconductor material" means a material that has electrical conductivity between that of an insulating material and a conductive material. For example, a semiconductor material has an electrical conductivity of about 10 at room temperature. -8 Siemens per centimeter (S / cm) to approximately 10 4 S / cm(10 6 It may have an electrical conductivity in the range of S / m). Examples of semiconductor materials include elements belonging to Group IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples include compound semiconductor materials, such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)) and ternary compound semiconductor materials (e.g., Al X Ga 1-X As), and quaternary compound semiconductor materials (e.g., GaX In 1-X As Y P 1-Y ) may be mentioned, but are not limited thereto. Compound semiconductor materials may include, but are not limited to, combinations of elements from Group III and Group V of the periodic table (III-V semiconductor materials), or combinations of elements from Group II and Group VI of the periodic table (II-VI semiconductor materials). Further, other examples of semiconductor materials include oxide semiconductor materials such as zinc tin oxide (ZnxSnyO, known as "ZTO"), indium zinc oxide (InxZnyO, known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, known as "IGZO"), indium gallium silicon oxide (InxGaySizO, known as "IGSO"), indium tungsten oxide (InxWyO, known as "IWO"), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), zinc oxynitride (ZnxONz), magnesium zinc oxide (MgxZnyO), zirconium indium zinc oxide (ZrxInyZnzO), hafnium indium zinc oxide (HfxInyZnzO), tin indium zinc oxide (SnxInyZnzO), aluminum tin indium zinc oxide (AlxSnyInzZnaO), silicon indium zinc oxide (SixInyZnzO), aluminum zinc tin oxide (AlxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), zirconium zinc tin oxide (ZrxZnySnzO), and materials similar thereto.

[0027] In this specification, "homogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) do not vary across different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, "heterogeneous" means that the relative amounts of elements contained in a feature vary across different parts of the feature. If a feature is heterogeneous, the amounts of one or more elements contained in the feature may vary discontinuously (e.g., abruptly) or continuously (e.g., gradually, linearly, parabolicly, etc.). For example, the feature may be formed from, or contain, a stack of at least two different materials.

[0028] Unless otherwise specified, the materials described herein may be formed by any suitable technique, including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a person skilled in the art may select the deposition or growth technique. Furthermore, unless otherwise specified, the materials described herein may be removed by any suitable technique, including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, polishing planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0029] Figures 1 and 2A-2R are various diagrams showing the microelectronic device structure 100 at different processing stages in a method for forming a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device) according to the embodiments of this disclosure (details are given below). From the following description, it will be readily apparent to those skilled in the art that the structures (e.g., microelectronic device structure 100) and devices (e.g., microelectronic devices) described herein can be used in a variety of relatively large devices and / or systems. For clarity and ease of understanding of the drawings and related descriptions, not all features (e.g., regions, structures, materials, devices) of the microelectronic device structure 100 shown in one or more of Figures 1 and 2A-2R are necessarily shown in one or more other of Figures 1 and 2A-2R.

[0030] Figure 1 shows a simplified partial top view of a microelectronic device structure 100 during a processing step of a method for forming a microelectronic device according to an embodiment of the present disclosure. The microelectronic device structure 100 may be formed on a substrate structure 104 to include a pre-stack structure 102. The microelectronic device structure 100 may include a profile slot 106 internally, which defines a void within the pre-stack structure 102. As shown in Figure 1, the profile slot 106 has a profile defined by a backbone region 108 (also referred to herein as the “first region”) and one or more rib regions 110 (also referred to herein as the “second region”) extending horizontally from the backbone region 108.

[0031] As shown in Figure 1, the backbone region 108 may have a substantially rectangular profile formed by a portion of the profile slots 106, and the backbone region 108 includes relatively long sides (e.g., sides along the X direction) and relatively short sides (e.g., sides along the Y direction substantially perpendicular to the X direction). The multiple rib regions 110 may be spaced horizontally apart from each other (e.g., in the X direction), with the spacing ranging from about 100 nanometers (100 nm) to about 150 nanometers (150 nm). Alternatively, the rib regions 110 may be spaced apart from each other at a pitch of about 125 nanometers (125 nm) to about 175 nanometers (175 nm) in the X direction. In one embodiment, the rib regions 110 are spaced apart from each other at a pitch of about 146 nanometers (146 nm) in the X direction.

[0032] The rib regions 110 may include multiple substantially linear portions of the profile slots 106 within the pre-stack structure 102. The rib regions 110 may extend from opposite sides of a relatively long side (e.g., a side extending along the X direction) of the backbone region 108. Each individual rib region 110 may include a relatively long side (e.g., a horizontal boundary) along the direction extending from the backbone region 108. Multiple rib regions 110 extending individually from each opposite side of the backbone region 108 (e.g., the side along the X direction) may each form a set of rib regions 110 (e.g., a first rib set 112, a second rib set 114). The first rib set 112 and the second rib set 114 may form a mirror image symmetrical with respect to the lateral centerline of the backbone region 108 (e.g., a line extending along the X direction and located in the center in the Y direction). Alternatively, some of the multiple rib regions 110 may extend relative to the backbone region 108 at different angles than the other rib regions 110. For example, in one embodiment, each rib region 110 of the first rib set 112 forms a first angle with respect to the backbone region 108, and each rib region 110 of the second rib set 114 forms a different angle with respect to the backbone region 108. In other embodiments, the rib regions 110 may extend relative to the backbone region 108 at various angles. In one embodiment, each rib region 110 extends from the backbone region 108 at an angle of about 80 degrees. In another embodiment, each rib region 110 extends from the backbone region 108 at an angle of about 85 degrees to about 75 degrees. In another embodiment, each rib region 110 extends from the backbone region 108 at an angle of about 80 degrees to about 90 degrees, for example, about 85 degrees to about 90 degrees. In other embodiments, the rib regions 110 extend from the backbone region 108 at angles of less than approximately 80 degrees, for example, less than approximately 75 degrees, less than approximately 70 degrees, less than approximately 65 degrees, or less than approximately 60 degrees. The rib regions 110 may be spatially positioned relative to the backbone region 108 such that the bit lines (e.g., data lines, digit lines) that are formed later are located above the preliminary stack structure 102 (e.g., in the Z direction) and directly above (e.g., in the Z direction) the corresponding vertical memory string structure formed within the profile of the rib regions 110.This point will be described and illustrated in more detail below.

[0033] Figure 2A is a simplified partial perspective cross-sectional view of a portion of the microelectronic device structure 100 near the dashed line AA during the processing stage shown in Figure 1. As shown in Figure 2A, the microelectronic device structure 100 may be formed to include a pre-stack structure 102, which includes a sequence of insulating material 202 and sacrificial material 204 arranged alternately in the vertical direction (e.g., the Z direction), and is stacked as layers 206. Each layer 206 of the pre-stack structure 102 may include sacrificial material 204 that is perpendicularly adjacent to the insulating material 202 (e.g., directly perpendicularly adjacent in the Z direction).

[0034] The insulating material 202 of each layer 206 of the pre-stack structure 102 may be formed from or include at least one dielectric material. Examples of the at least one dielectric material include one or more of the following: at least one dielectric oxide film material (e.g., SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carbonate nitride material (e.g., SiOxCzNy). In some embodiments, the insulating material 202 of each layer 206 of the pre-stack structure 102 may be formed from or include a dielectric oxide film material such as SiOx (e.g., SiO2). The insulating material 202 in each layer 206 may be substantially homogeneous, or the insulating material 202 in one or more layers 206 (for example, each layer) may be heterogeneous.

[0035] The sacrificial material 204 of each layer 206 of the pre-stack structure 102 may be formed from, or include, at least one material (e.g., at least one insulating material) that is selectively removable from the insulating material 202. The sacrificial material 204 may be selectively etchable from the insulating material 202 upon common (i.e., simultaneous) exposure to a first etchant, and the insulating material 202 may be selectively etchable from the sacrificial material 204 upon common exposure to a second different etchant. As a non-limiting example, depending on the material composition of the insulating material 202, the sacrificial material 204 may be formed from or include one or more of the following: at least one dielectric oxide film material (e.g., SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric oxycarbide material (e.g., SiOxCy), at least one hydrogenated dielectric oxycarbide material (e.g., SiCxOyHz), at least one dielectric carbonate nitride material (e.g., SiOxCzNy), and at least one semiconductor material (e.g., polycrystalline silicon). In some embodiments, the sacrificial material 204 of each layer 206 of the pre-stack structure 102 may be formed from, or include, a dielectric nitride material such as SiNy (e.g., Si3N4). The sacrificial material 204 may be selectively etchable with respect to the insulating material 202 upon common exposure to a wet etchant containing, for example, phosphoric acid (H3PO4).

[0036] The preliminary stack structure 102 may be formed to include a desired number of layers 206. As a non-limiting example, the preliminary stack structure 102 may be formed to include 16 or more layers 206, 32 or more layers 206, 64 or more layers 206, 128 or more layers 206, or 256 or more layers 206.

[0037] The profile slot 106 may be defined as a negative space within a vertical boundary defined at least partially by a pre-stack structure 102. The pre-stack structure 102 may include side walls 208 that define the horizontal boundary of the profile slot 106 (e.g., horizontal directions consisting of the X direction, the Y direction, or a combination of the X and Y directions). Each rib region 110 may be horizontally partitioned by two side walls 208 of the pre-stack structure 102 that are opposite each other. In other words, a pair of opposing side walls 208 may form two relatively long horizontal boundaries of the individual rib regions 110 of the profile slot 106.

[0038] The sidewalls 208 of the pre-stack structure 102 may be tapered as a result of a removal process (e.g., deep dry etching) applied to the pre-stack structure 102 to form the profile slots 106. Alternatively, the sidewalls 208 may be formed substantially vertically. In the following description, the sidewalls 208 may include substantially vertical surfaces of the pre-stack structure 102 and / or substantially vertical surfaces of other materials formed on the pre-stack structure 102. Furthermore, the sidewalls 208 may include substantially vertical surfaces of the later-formed stack structure 210 and / or substantially vertical surfaces of other materials formed on the later-formed stack structure 210.

[0039] The pre-stack structure 102 may be formed to include one or more decks, each deck containing multiple layers 206. As shown in Figure 2A, the pre-stack structure 102 may include a lower deck 212 and an upper deck 214 located above the lower deck 212 (e.g., in the Z direction). The decks of the pre-stack structure 102 (e.g., the lower deck 212, the upper deck 214) may each contain a desired number of layers 206. As an unrestricted example, the decks of the pre-stack structure 102 (e.g., the lower deck 212, the upper deck 214) may each contain 10 layers 206. Alternatively, the decks of the pre-stack structure 102 may each contain fewer than 10 layers 206. As an even more unrestricted example, the decks of the pre-stack structure 102 may each contain 8 or more layers 206, for example, 16 or more layers 206, 32 or more layers 206, 64 or more layers 206, or 128 or more layers 206.

[0040] As will be described in more detail below, the lower deck 212 and the upper deck 214 may be formed in different processing stages, respectively. As a result, the upper deck 214 may be partially offset horizontally (e.g., in the X and / or Y directions) relative to the lower deck 212 (e.g., partially horizontally misaligned), which may result in an upper deck overhang 216. The downward lower end of the upper deck 214 of the pre-stack structure 102 (e.g., the lower end in the Z direction) may be exposed by the partial horizontal misalignment between the upper deck 214 and the lower deck 212. Alternatively, the horizontal misalignment between the upper deck 214 and the lower deck 212 of the pre-stack structure 102 may form a shoulder between the lower deck 212 and the upper deck 214. In such embodiments, the upward upper end of the lower deck 212 of the pre-stack structure 102 (e.g., the upper end in the Z direction) is exposed by the partial horizontal misalignment between the upper deck 214 and the lower deck 212. In some cases, a horizontal misalignment (e.g., in the X and / or Y directions) between the upper deck 214 and the lower deck 212 of the pre-stack structure 102 may cause the side walls 208 of the pre-stack structure 102 to be tapered, and the tapered side walls 208 may have a positive or negative incline. In yet another embodiment, the pre-stack structure 102 has substantially no horizontal offset, misalignment, and / or taper between the lower deck 212 and the upper deck 214.

[0041] As shown in Figure 2A, the microelectronic device structure 100 includes a lower dielectric material 218 and an upper dielectric material 220 at the bottom and top of the pre-stack structure 102, respectively. In particular, the upper dielectric material 220 and the lower dielectric material 218 may be positioned above and below layer 206 (e.g., in the Z direction), respectively. The lower dielectric material 218 and the upper dielectric material 220 may be formed from, or include, an insulating material. The lower dielectric material 218 and the upper dielectric material 220 may have substantially the same material composition as each other, or they may have different material compositions as each other. The lower dielectric material 218 and the upper dielectric material 220 may each be formed thicker vertically (e.g., in the Z direction) than the insulating material 202 of the individual layers 206 of the pre-stack structure 102. In some embodiments, the upper dielectric material 220 is formed thicker vertically than the lower dielectric material 218.

[0042] The microelectronic device structure 100 further includes a substrate structure 104, on which the preliminary stack structure 102 may be formed. The substrate structure 104 may include multiple materials. For example, the substrate structure 104 may include an upper substrate material 222, an intermediate substrate material 224, a lower substrate material 226, and a substrate dielectric material 228. The substrate structure 104 may be formed on a substrate 230. The upper substrate material 222 and the lower substrate material 226 may be formed from and include semiconductor materials, such as doped semiconductor materials (e.g., n-type polycrystalline silicon). The substrate dielectric material 228 may be formed from and include dielectric materials. The intermediate substrate material 224 may be formed from and include additional semiconductor materials, such as substantially undoped semiconductor materials (e.g., undoped polycrystalline silicon). As shown in Figure 2A, the substrate 230 may include structures or materials on which the substrate structure 104 is formed. In some embodiments, the substrate 230 includes a semiconductor structure (e.g., a semiconductor wafer, such as a silicon wafer). In other embodiments, the substrate 230 includes at least one control logic region below the substrate structure 104 (e.g., in the Z direction), the control logic region includes a control logic device configured to control various operations of other features of the microelectronic device structure 100 (e.g., the vertical memory cell 284 shown in Figure 2Q). As a non-limiting example, the control logic area of ​​board 230 may further include charge pumps (e.g., VCCP charge pump, VNEGWL charge pump, DVC2 charge pump), delay-locked loop (DLL) circuits (e.g., ring oscillators), Vdd regulators, drivers (e.g., string drivers), page buffers, decoders (e.g., local deck decoder, column decoder, low decoder), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuits (e.g., column repair circuits, low repair circuits), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear leveling devices, and other chip / deck control circuits.The control logic region of the substrate 230 may be connected to a source structure, one or more access line routing structures, one or more select line routing structures, and / or one or more digit line structures. In some embodiments, the control logic region of the substrate 230 includes CMOS (complementary metal-oxide-semiconductor) circuits. In such embodiments, the control logic region of the substrate 230 is characterized as having a “CMOS under Array” (or “CuA”) configuration.

[0043] As previously mentioned in relation to Figure 1, the profile slot 106 may include a void space (e.g., a trench, opening, or slit) extending vertically through the pre-stack structure 102. The profile slot 106 may extend vertically (e.g., in the Z direction) through the upper dielectric material 220, the upper deck 214 and the lower deck 212 layers 206, and the lower dielectric material 218. The lower (e.g., Z direction) boundary of the profile slot 106 may be defined at least partially by the upper surface (e.g., upper surface) of the substrate structure 104.

[0044] The substrate structure 104 may include a plurality of bottom plug cavities 232 inside. The bottom plug cavities 232 may include voids (e.g., openings, trenches, vias) that partially penetrate the substrate structure 104 in a vertical direction (e.g., the Z direction). In some embodiments, the bottom plug cavities 232 extend vertically through the upper substrate material 222 and the intermediate substrate material 224, and partially through the lower substrate material 226. The bottom plug cavities 232 may be formed by removing material from the substrate structure 104. Each bottom plug cavity 232 may have a desired horizontal cross-sectional shape, for example, an elliptical horizontal cross-sectional shape.

[0045] The formation of the microelectronic device structure 100 shown in Figure 2A may include the step of forming a base structure 104 on a substrate 230. The step of forming the base structure 104 on the substrate 230 may include the steps of forming a base structure dielectric material 228 on the substrate 230, forming a lower base structure material 226 on the base structure dielectric material 228, forming an intermediate base structure material 224 on the lower base structure material 226, and forming an upper base structure material 222 on the intermediate base structure material 224.

[0046] After forming the substrate structure 104 on the substrate 230, the bottom plug cavity 232 may be formed by removing material from the upper substrate structure material 222, the intermediate substrate structure material 224, and the lower substrate structure material 226. The horizontal position of the bottom plug cavity 232 may be selected to coincide with a desired position of a vertical memory string structure that is subsequently formed, which may be formed above the bottom plug subsequently formed within the bottom plug cavity 232 (for example, in the Z direction).

[0047] After the bottom plug cavity 232 is formed, sacrificial material may be formed on the substrate structure 104 and filled into the bottom plug cavity 232. Subsequently, a portion of the sacrificial material located above the uppermost surface of the substrate structure 104 (e.g., in the Z direction) may be removed (e.g., by a polishing and planarization process such as a CMP process), thereby exposing the substrate structure 104 and filling the bottom plug cavity 232 with sacrificial material to a vertical level (e.g., in the Z direction) that is substantially coplanar with the upper surface of the upper substrate structure material 222.

[0048] After filling the bottom plug cavity 232 with sacrificial material, the lower deck 212 of the preliminary stack structure 102 may be formed on the base structure 104. The lower deck 212 of the preliminary stack structure 102 may be formed by forming a lower dielectric material 218 on the base structure 104, and then sequentially forming a series of layers in which the sacrificial material 204 and insulating material 202 are stacked alternately in the vertical direction.

[0049] After forming the lower deck 212 of the preliminary stack structure 102, the lower part of the profile slot 106 (for example, the vertical (Z-direction) range of the lower deck 212) may be formed by selectively removing material from the lower deck 212 of the preliminary stack structure 102. This creates a gap with horizontal profiles of the backbone region 108 and the rib region 110 in a top view.

[0050] After forming the lower part of the profile slot 106, the lower part of the profile slot 106 may be filled with sacrificial material. Subsequently, a portion of the sacrificial material formed on the uppermost surface of the lower deck 212 (e.g., the upper surface in the Z direction) may be removed (e.g., by a polishing and planarization process such as a CMP process), thereby exposing the upper surface of the lower deck 212.

[0051] After filling the lower part of the profile slot 106 with sacrificial material, the upper deck 214 of the preliminary stack structure 102 may be formed on the lower deck 212 of the preliminary stack structure 102 and on the sacrificial material at the bottom of the profile slot 106. The upper deck 214 of the preliminary stack structure 102 may be formed by forming a sequence of alternating vertical stacks of insulating material 202 and sacrificial material 204 on the lower deck 212 and on the sacrificial material at the bottom of the profile slot 106. Subsequently, the upper dielectric material 220 may be formed on the layers 206 of insulating material 202 and sacrificial material 204.

[0052] After forming the upper deck 214 of the pre-stack structure 102, the upper part of the profile slot 106 (for example, within the upper deck 214) may be formed by selectively removing material from the upper deck 214 of the pre-stack structure 102. This creates a void with horizontal profiles of the backbone region 108 and the rib region 110 in a top view.

[0053] After the upper part of the profile slot 106 is formed, sacrificial material may be removed from the lower part of the profile slot 106 and the bottom plug cavity 232. This results in the profile slot 106 (including the backbone region 108 and its rib region 110) and the bottom plug cavity 232.

[0054] Referring to Figure 2B, after the profile slot 106 is formed as shown in Figure 2A, the barrier oxide material 236 may be formed on the exposed surface of the microelectronic device structure 100. The barrier oxide material 236 may extend continuously on the surface of the microelectronic device structure 100 defining the profile slot 106 and the bottom plug cavity 232. As shown in Figure 2B, the barrier oxide material 236 may extend substantially continuously over and cover the entire exposed surface (e.g., sidewall 208) of the pre-stack structure 102 and the substrate structure 104. The barrier oxide material 236 may be formed from, or contain, a dielectric oxide material (e.g., silicon oxide).

[0055] After the barrier oxide material 236 is formed, the storage nitride material 238 may be formed on the barrier oxide material 236. The storage nitride material 238 may substantially cover the barrier oxide material 236 and extend continuously thereon. The storage nitride material 238 may be formed to conform to the surface shape of the upper surface of the barrier oxide material 236. The storage nitride material 238 may be provided inside and outside the profile slot 106 and the bottom plug cavity 232. The storage nitride material 238 may be formed from, or include, a dielectric nitride material (e.g., silicon nitride).

[0056] After the storage nitride material 238 is formed, a band-engineered tunnel oxide material (hereinafter referred to as band-engineered tunnel oxide material) 240 may be formed on the storage nitride material 238. The band-engineered tunnel oxide material 240 may substantially cover the storage nitride material 238 and extend continuously thereon. The band-engineered tunnel oxide material 240 may be formed to conform to the surface shape of the upper surface of the storage nitride material 238. The band-engineered tunnel oxide material 240 may be provided inside and outside the profile slot 106 and the bottom plug cavity 232. The band-engineered tunnel oxide material 240 may be formed from, or include, a dielectric oxide material (e.g., silicon oxide).

[0057] After forming the band-engineered tunnel oxide material 240, the semiconductor material 242 may be formed on the band-engineered tunnel oxide material 240. The semiconductor material 242 may substantially cover the band-engineered tunnel oxide material 240 and extend continuously thereon. The semiconductor material 242 may be provided inside and outside the profile slot 106 and the bottom plug cavity 232. The portion of the bottom plug cavity 232 that is not yet filled with the barrier oxide material 236, storage nitride material 238, and band-engineered tunnel oxide material 240 may be substantially filled with the semiconductor material 242. The semiconductor material 242 may be doped or substantially undoped. In some embodiments, the semiconductor material 242 may be formed from N-type polycrystalline silicon that is doped (e.g., lightly doped) with a species that enhances the conductivity of polycrystalline silicon (e.g., one or more species that enhance N-type conductivity, such as arsenic, phosphorus, and antimony).

[0058] The formation of the semiconductor material 242 may include a step of forming the semiconductor material 242 substantially thicker than its ultimately desired thickness. After forming the semiconductor material 242, a portion of the semiconductor material 242 is removed, thereby obtaining a relatively thin remainder of the semiconductor material 242 extending over the sidewall 208 of the preliminary stack structure 102. As an example, the semiconductor material 242 is formed to have an initial thickness of about 15 nanometers (nm). Subsequently, by partially removing the semiconductor material 242, the semiconductor material 242 remaining within the vertical boundary of the preliminary stack structure 102 has a thickness in the range of about 3 nm to about 7 nm, for example, about 5 nm.

[0059] In this disclosure, the barrier oxide material 236, the storage nitride material 238, the band-engineered tunnel oxide material 240, and the semiconductor material 242 may be collectively referred to as the memory cell material 244.

[0060] As shown in Figure 2B, when forming the barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, and semiconductor material 242, the bottom plug cavity 232 is coated in order with the barrier oxide material 236, storage nitride material 238, and band-engineered tunnel oxide material 240, and then the semiconductor material 242 may be filled (for example, by conformal deposition of the semiconductor material). By filling the bottom plug cavity 232 with the semiconductor material 242, the bottom plug 246 is formed within the bottom plug cavity 232.

[0061] Referring to Figure 2C, after the semiconductor material 242 is formed, the liner nitride material 248 may be formed on the semiconductor material 242. The liner nitride material 248 may substantially cover the semiconductor material 242 and extend continuously thereon. The liner nitride material 248 may be formed to conform to the surface shape of the upper surface of the semiconductor material 242. The liner nitride material 248 may be provided inside and outside the profile slot 106 and may cover the bottom plug 246. The liner nitride material 248 may be formed from and include a dielectric nitride material (e.g., silicon nitride). The liner nitride material 248 may be formed to have a thickness of about 10 nm or less, for example, in the range of about 10 nm to about 1 nm, about 5 nm or less, or about 3 nm or less. The liner nitride material 248 can suppress oxidation of the semiconductor material 242.

[0062] After the liner nitride material 248 is formed, a liner oxide material 250 may be formed on the liner nitride material 248. The liner oxide material 250 may substantially cover the liner nitride material 248 and extend continuously thereon. The liner oxide material 250 may be formed to conform to the surface shape of the upper surface of the liner nitride material 248. The liner oxide material 250 may be provided inside and outside the profile slot 106. The liner oxide material 250 may be formed from and include a dielectric oxide material (e.g., silicon oxide). The liner oxide material 250 may be formed to have a thickness of about 10 nm or less, for example, in the range of about 10 nm to about 1 nm, about 5 nm or less, or about 3 nm or less.

[0063] In this disclosure, the liner nitride material 248 and the liner oxide film material 250 may be collectively referred to as the liner material 252.

[0064] Referring next to Figure 2D, after the liner oxide material 250 is formed, the mask material 254 may be formed on the liner oxide material 250. The mask material 254 may substantially cover the liner oxide material 250 and extend continuously thereon. The mask material 254 may be formed to conform to the surface shape of the upper surface of the liner oxide material 250. The mask material 254 may be provided inside and outside the profile slot 106. In some embodiments, the mask material 254 may be formed from a semiconductor material, such as polycrystalline silicon, and may include this. The mask material 254 may be doped or undoped. As a non-limiting example, the mask material 254 may be formed from N-type doped polycrystalline silicon, and may include this. The mask material 254 may be formed to have a thickness in the range of about 5 nm to about 15 nm, for example, about 10 nm.

[0065] Referring to Figure 2E, after the mask material 254 is formed, the trim material 256 may be formed on the mask material 254. The trim material 256 may substantially cover the mask material 254 and extend continuously thereon. The trim material 256 may be formed to conform to the surface shape of the upper surface of the mask material 254. The trim material 256 may be provided inside and outside the profile slot 106. The trim material 256 may at least partially (e.g., substantially) fill the unfilled portions of the rib region 110 of the profile slot 106. In some embodiments, the trim material 256 substantially fills the remaining (e.g., unfilled) portions of the rib region 110 located between horizontally opposing portions of the pre-stack structure 102. The trim material 256 may at least partially (e.g., substantially) fill the rib region 110 of the profile slot 106 up to at least the vertical height (e.g., Z direction) of the pre-stack structure 102. As shown in Figure 2E, a portion of the backbone region 108 may remain substantially unfilled even after the formation of the trim material 256. The trim material 256 may only partially fill the portion of the backbone region 108 that remains after the formation of the mask material 254.

[0066] The trim material 256 may be formed from, and may include, at least one material having different etching selectivity from the materials subsequently formed (e.g., sacrificial filler material, cover material, mask oxide film material). In some embodiments, the trim material 256 may be formed from, and may include, a dielectric nitride material (e.g., silicon nitride). In yet other embodiments, the trim material 256 may be formed from a dielectric nitride material and may include an additional material (also referred to herein as a “core material”) having a different material composition from the dielectric nitride material on or above the dielectric nitride material.

[0067] Referring to Figure 2F, after the trim material 256 is formed, a portion of the trim material 256 may be removed (for example, by a nitride trimming treatment) to form a trim edge 264 at or near the intersection of the backbone region 108 and the rib region 110 of the profile slot 106. The trim material 256 may be substantially removed from the backbone region 108 while remaining within the rib region 110. As shown in Figure 2F, in some embodiments, a portion of the trim material 256 near the backbone region 108 within the rib region 110 is removed, resulting in the trim edge 264 of the trim material 256 being located within the horizontal boundary of the rib region 110. The trim edge 264 of the trim material 256 may be horizontally offset from the backbone region 108. In yet another embodiment, the trim edge 264 of the trim material 256 is located on or relatively close to the horizontal boundary of the backbone region 108. Material removal processes (e.g., wet etching) can disrupt the continuity of the trim material 256 within the profile slots 106, resulting in the portions of trim material 256 within individual rib regions 110 becoming separated and discontinuous. Furthermore, portions of trim material 256 outside the boundaries of the profile slots 106 (e.g., upper vertical boundaries) may also be removed. Material removal processes may expose the surface of the mask material 254 within the backbone region 108 and outside the boundaries of the profile slots 106.

[0068] Referring next to Figure 2G, after removing a portion of the trim material 256 to form the trim edge 264 (Figure 2F), the sacrificial filler material 258 may be formed in the remaining (e.g., unfilled) portion of the profile slot 106 (e.g., by non-conformal deposition). The sacrificial filler material 258 may substantially fill the backbone region 108 of the profile slot 106. The sacrificial filler material 258 may also partially extend into the rib region 110 of the profile slot 106. The sacrificial filler material 258 may be formed from and include at least one material having etching selectivity with respect to the trim material 256 and the mask material 254. In some embodiments, the sacrificial filler material 258 is formed from and includes a carbon-containing material.

[0069] The sacrificial filler material 258 may initially be formed non-conformally inside and outside the profile slot 106 (e.g., by non-conformal deposition). Subsequently, portions of the sacrificial filler material 258 located outside the profile slot 106 may be removed (e.g., by CMP), and the remaining sacrificial filler material 258 may be substantially confined within the profile slot 106. In the material removal process (e.g., CMP process), portions (e.g., portions in the Z direction) of the barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trim nitride material 256 located on the upper vertical boundary of the profile slot 106 may also be removed. In some embodiments, the material removal process may also partially remove the upper dielectric material 220 (e.g., by vertically indenting it). The material removal process may expose the upper dielectric material 220 and form a substantially flat upper horizontal plane including the coplanar upper horizontal plane of the sacrificial packing material 258, upper dielectric material 220, barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trim material 256.

[0070] Next, referring to Figure 2H, after removing the top of the sacrificial filler material 258 located outside the profile slot 106 (Figure 2G), the cover material 260 may be formed (for example, in the Z direction) on the sacrificial filler material 258, upper dielectric material 220, barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trim material 256. The cover material 260 may be formed on a substantially flat upper horizontal plane defined by and including the coplanar upper horizontal planes of the sacrificial filler material 258, upper dielectric material 220, barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trim material 256. The cover material 260 may have a substantially flat upper horizontal surface. The cover material 260 may be formed from, or contain, a dielectric oxide film material (e.g., silicon oxide). In some embodiments, the cover material 260 includes silicon oxide (e.g., SiO2) formed by deposition using tetraethyl orthosilicate ("TEOS") as the silicon source.

[0071] After forming the cover material 260, a portion of the cover material 260 within the horizontal boundary of the backbone region 108 may be removed (for example, by etching). As shown in Figure 2H, by removing a portion of the cover material 260, a cover material gap 266 (e.g., a trench, an opening) may be formed within the horizontal region of the backbone region 108 of the profile slot 106. The cover material gap 266 has an elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) and may at least partially expose the sacrificial filler material 258 within the backbone region 108.

[0072] The cover material gap 266 may have a horizontal span. In this case, the span is defined as the distance between opposing long sides (for example, in the Y direction), and the span is such that at least a portion of the upper surface of the sacrificial filler material 258 is exposed without exposing the trim material 256. Furthermore, the cover material gap 266 may be configured not to expose any of the upper dielectric material 220, barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, and mask material 254. In some embodiments, the cover material gap 266 only partially (for example, not completely) exposes the upper surface of the sacrificial filler material 258.

[0073] Referring to Figure 2I, after forming the cover material 260 and the cover material gap 266, the sacrificial fill material 258 may be removed from the profile slot 106 (for example, by excavation). By removing the sacrificial fill material 258 from the profile slot 106, a portion of the mask material 254 in the horizontal region of the backbone region 108 may be exposed. The removal of the sacrificial fill material 258 may also expose a further portion of the mask material 254 in the portion of the rib region 110 adjacent to the backbone region 108.

[0074] After the sacrificial filler material 258 is removed, the trim material 256 may be further moved back horizontally (e.g., trimmed) and repositioned so that the trim edge 264 is relatively far from the backbone region 108. The exposed portion of the trim material 256 may be removed (e.g., by thermal phosphoric acid etching), and as a result, the new horizontal position of the trim edge 264 is located horizontally outward (e.g., relative to the backbone region 108) than the horizontal position of the trim edge 264 in the processing step described above in relation to Figure 2F.

[0075] Figures 2J to 2R include simplified partial perspective views of the processing steps in the method for forming the microelectronic device structure 100, following the processing steps described above in relation to Figure 2I. For this reason, the cover material 260 is not shown in each of Figures 2J to 2R in order to clarify the drawings and related explanations and to facilitate understanding. However, it should be understood that in the processing steps of Figures 2J to 2R, the cover material 260 and the cover material gap 266 formed within it and defined therein still exist.

[0076] After the sacrificial filler material 258 is removed, a series of trim etch cycles may be performed to sequentially form one or more preliminary vertical memory string structures 268 on the side walls 208 of the preliminary stack structure 102. An example of such a sequential trim etch cycle process is shown in Figures 2J to 2M. The preliminary vertical memory string structures 268 may be formed within the rib regions 110 of the profile slot 106. Upon completion of each trim etch cycle, individual vertical memory string structures 268 are formed on the side walls 208 of the individual rib regions 110 of the profile slot 106. After the first trim etch cycle forms a first group of preliminary vertical memory string structures 268 within the rib regions 110, the second trim etch cycle forms a second group of preliminary vertical memory string structures 268 within the rib regions 110, the third trim etch cycle forms a third group of preliminary vertical memory string structures 268 within the rib regions 110, and so on, until this series of trim etch cycles is completed. Within each rib region 110, each subsequent trim etch cycle may form a separate vertical memory string structure 268 at a position relatively far horizontally from the backbone region 108 than another separate vertical memory string structure 268 formed by a previous trim etch cycle.

[0077] In the processing stage shown in Figure 2J, two preliminary vertical memory string structures 268 are formed on individual side walls 208 that partially define individual rib regions 110 of the preliminary stack structure 102. These two preliminary vertical memory string structures 268 and two other preliminary vertical memory string structures 268 opposite them may have been formed by two trim etch cycles performed before the start of the trim etch cycle described in relation to Figures 2J to 2M. Horizontally adjacent preliminary vertical memory string structures 268 (for example, horizontally along the long side of the corresponding rib region 110) may be separated from each other by a preliminary vertical memory string structure space 270. The width of each preliminary vertical memory string structure 268 and the width of each adjacent preliminary vertical memory string structure space 270 may be partially determined by the width of the trim material 256 removed in each trim etch cycle, as will be described later.

[0078] Referring to Figure 2J, each trim etch cycle may include the step of removing a portion of the trim material 256 within the rib region 110 of the profile slot 106 to expose a portion of the mask material 254 within the rib region 110. The portion of the removed trim material 256 may be referred to herein as a “memory string portion” because a later-formed preliminary vertical memory string structure 268 is formed corresponding to the location of the removed portion of the trim material 256. Similarly, a portion of the exposed mask material 254 may be referred to herein as a “memory string portion” because it is located at the location of the later-formed preliminary vertical memory string structure 268.

[0079] The material removal process shown in Figure 2J may reposition the trim edge 264 of the trim material 256 further horizontally away from the backbone region 108 of the profile slot 106. This material removal process may remove the memory string portion of the trim material 256. The material removal process may include a step of exposing the trim edge 264 formed in the previous trim etch cycle to at least one type of etchant (e.g., thermal phosphoric acid etchant). The etchant may be introduced to the trim edge 264 in the rib region 110 of the profile slot 106 through the cover material gap 266 (Figure 2I) in the cover material 260 (Figure 2I) and the backbone region 108 of the profile slot 106. The cover material 260 may suppress (e.g., minimize, prevent) the etchant from entering the rib region 110 of the profile slot 106 from above (e.g., in the Z direction). In this way, the material removal process may be carried out to remove portions of the trim material 256 (e.g., memory string portions) in stages. The extent of removal (horizontal retraction) of individual trim material 256 within the rib region 110 may be controlled, as desired, by selecting an etchant composition according to a predetermined etching rate, selecting the processing time of the material removal process, and / or selecting other parameters of the material removal process.

[0080] By removing the memory string portion of the trim material 256, the trim edge 264 retracts to a selected new horizontal position, thereby granting the individual pre-vertical memory string structures 268 formed through the trim etch cycle a desired horizontal width (e.g., horizontally along the long side of the corresponding rib region 110). The horizontal width of the individual pre-vertical memory string structures 268 (e.g., horizontally along the long side of the corresponding rib region 110) may be in the range of about 20 nm to about 150 nm, for example, about 50 nm to about 120 nm, about 80 nm to about 100 nm, or about 90 nm to about 100 nm.

[0081] As shown in Figure 2J, individual rib regions 110 may be bounded by two opposing sidewall portions 208 of the pre-stack structure 102. Thus, within each individual rib region 110, each trim etch cycle may form a pair of pre-vertical memory string structures 268 on the opposing sidewalls 208 within the rib region 110, facing each other horizontally (for example, in a horizontal direction perpendicular to the long side of the corresponding rib region 110). In a pre-stack structure 102 having a profile slot 106 containing multiple rib regions 110, each trim etch cycle may form two pre-vertical memory string structures 268 within each rib region 110 of the profile slot 106, facing each other horizontally (for example, in a horizontal direction perpendicular to the long side of the corresponding rib region 110).

[0082] Referring to Figure 2K, after removing the memory string portion of the trim material 256 within the rib region 110, the exposed portion of the mask material 254 (Figure 2J) within the rib region 110 may be converted into a mask oxide material 262. In some embodiments, the mask oxide material 262 may be formed from and include a dielectric oxide material, such as silicon oxide (SiO2). The mask oxide material 262 may be formed by converting the exposed portion of the mask material 254 into an oxide (e.g., thermal oxidation or plasma oxidation). The mask oxide material 262 may be formed over a horizontal width (e.g., horizontally along the long side of the corresponding rib region 110) between the adjacent pre-vertical memory string structure space 270 and the trim edge 264. Furthermore, the mask oxide material 262 may be formed continuously over a substantially entire vertical range (e.g., Z direction) of the side wall 208 of the pre-stack structure 102. The mask oxide film material 262 may be formed to have a thickness in the range of approximately 5 nm to approximately 15 nm, for example, approximately 8 nm to approximately 12 nm, or approximately 10 nm. The mask oxide film material 262 may also be used as an inhibition material to inhibit (e.g., delay, limit) the removal of the mask material 254 in a later process (e.g., removal by wet etching), as will be discussed later in relation to Figure 2P. Alternatively, instead of the mask oxide film material 262, another type of inhibition material may be formed from the exposed portion of the mask material 254. For example, the inhibition material may include one or more materials formed by gas phase doping or silicide of the mask material 254.

[0083] Referring to Figure 2L, after the formation of the mask oxide film material 262, the additional portion of the trim material 256 may be removed (e.g., by a wet etchant) so that the trim edge 264 is further horizontally separated from the backbone region 108 of the profile slot 106. The additional material removal process may include bringing the trim edge 264 of the trim material 256 formed in the processing step of Figure 2J into contact with at least one type of etchant (e.g., a thermal phosphoric acid etchant). The etchant may be introduced to the trim edge 264 in the rib region 110 of the profile slot 106 through the cover material gap 266 (Figure 2I) provided in the cover material 260 (Figure 2I) and the backbone region 108 of the profile slot 106. The cover material 260 may suppress or prevent the etchant from entering the rib region 110 of the profile slot 106 from above (e.g., in the Z direction).

[0084] The additional trim material 256 may be removed over a horizontal range (e.g., horizontally along the long side of the corresponding rib region 110), which may correspond to a desired width of individual post-formed pre-vertical memory string structure spaces 270 horizontally interposed between horizontally adjacent pre-vertical memory string structures 268. The width of each pre-vertical memory string structure space 270 (e.g., horizontally along the long side of the corresponding rib region 110) may be greater than 0 nm and less than or equal to about 25 nm, for example, in the range of about 5 nm to about 20 nm, about 10 nm to about 20 nm, or about 15 nm. The additional trim material 256 may be removed over a substantially entire vertical range (e.g., Z direction) of the side wall 208 of the pre-stack structure 102.

[0085] As shown in Figure 2L, by removing the additional portion of the trim material 256, each portion of the mask material 254 located beneath the removed additional portion may be exposed.

[0086] Next, referring to Figure 2M, after removing the additional portion of the trim material 256, the exposed portion of the mask material 254 may be selectively removed (for example, by wet etching with tetramethylammonium hydroxide ("TMAH")), thereby exposing each portion of the liner oxide material 250. By removing the portion of the mask material 254, a preliminary vertical memory string structure space 270 may be formed between the trim edge 264 formed in the processing stage of Figure 2K and the preliminary vertical memory string structure 268 that is closest to it in the horizontal direction (for example, in the horizontal direction along the long side of the corresponding rib region 110).

[0087] As shown in Figure 2M, the trim etch cycle described in relation to Figures 2J to 2M may result in the formation of pre-vertical memory string structures 268 within individual rib regions 110 of the profile slot 106. Each pre-vertical memory string structure 268 may be horizontally bounded by adjacent pre-vertical memory string structure spaces 270 in the horizontal direction (e.g., horizontally along the long side of the corresponding rib region 110). The pre-vertical memory string structure spaces 270 may extend horizontally from and between adjacent pre-vertical memory string structures 268. The pre-vertical memory string structures 268 may extend vertically (e.g., in the Z direction) over substantially the entire height of the pre-stack structure 102 and may encompass the vertical ranges (e.g., in the Z direction) of both the lower deck 212 and the upper deck 214 of the pre-stack structure 102.

[0088] After completing individual trim etch cycles, one or more additional trim etch cycles may be performed to form additional preliminary vertical memory string structures 268 and additional preliminary vertical memory string structure spaces 270 within the rib region 110 of the profile slot 106. As shown in Figure 2N, a portion of trim material 256 adjacent to the already removed portion of trim material 256 shown in Figure 2J may be removed by a material removal process similar to that described above in relation to Figure 2J. Subsequently, additional processing steps similar to those described above in relation to Figures 2K to 2M may be performed for additional trim etch cycles.

[0089] Figure 2O shows the result of multiple trim etch cycles, which have formed multiple preliminary vertical memory string structures 268 within the rib region 110 of the profile slot 106. As shown in Figure 2O, substantially all of the horizontal width of the trim material 256 within the rib region 110 (e.g., horizontally along the long side of the corresponding rib region 110) has been removed, and the preliminary vertical memory string structures 268 and the preliminary vertical memory string structure space 270 extend horizontally across the entire horizontal width previously occupied by the trim material 256 within the rib region 110.

[0090] The number of groups of pre-vertical memory string structures 268 within each rib region 110 may be equal to twice the number of trim etch cycles performed. The number of pre-vertical memory string structures 268 within each rib region 110 of the profile slot 106 may be determined in part by the horizontal width of the rib region 110 (e.g., horizontally along the long side of the corresponding rib region 110), the horizontal width of the pre-vertical memory string structures 268 (e.g., horizontally along the long side of the corresponding rib region 110), and the horizontal width of the pre-vertical memory string structure space 270 (e.g., horizontally along the long side of the corresponding rib region 110). Each pre-vertical memory string structure 268 may have substantially the same horizontal width as the others, or one or more pre-vertical memory string structures 268 may have a different horizontal width from one or more other pre-vertical memory string structures 268. Furthermore, each of the auxiliary vertical memory string structure spaces 270 may have substantially the same horizontal width as the others, or one or more auxiliary vertical memory string structure spaces 270 may have a different horizontal width from the other one or more auxiliary vertical memory string structure spaces 270. In some embodiments, an individual rib region 110 may have a group of eight auxiliary vertical memory string structures 268 on each of the two opposing side walls 208 of the auxiliary stack structure 102 that partially defines the rib region 110. In other embodiments, an individual rib region 110 may have seven or fewer auxiliary vertical memory string structures 268 on each of the two opposing side walls 208 of the auxiliary stack structure 102 that partially defines the rib region 110. In yet another embodiment, an individual rib region 110 may have nine or more auxiliary vertical memory string structures 268 on each of the two opposing side walls 208 of the auxiliary stack structure 102 that partially defines the rib region 110.

[0091] During the processing stage of each trim etch cycle, multiple rib regions 110 of the profile slot 106 may be processed synchronously (e.g., simultaneously). As a non-limiting example, if multiple rib regions 110 each form 16 vertical memory string structures (e.g., 8 vertical memory string structures for each side wall 208 defining each rib region 110), then within each rib region 110, two preliminary vertical memory string structures 268 may be formed horizontally opposite to each other (e.g., in a horizontal direction perpendicular to the long side of the corresponding rib region 110). In this way, 8 trim etch cycles may be performed and 16 preliminary vertical memory string structures 268 may be formed within each rib region 110.

[0092] Referring comprehensively to Figures 2O and 2P, after completing a series of trim etch cycles, portions of the liner oxide material 250, liner nitride material 248, semiconductor material 242, band-engineered tunnel oxide material 240, and storage nitride material 238 overlapping the preliminary vertical memory string structure space 270 may be removed by one or more additional material removal processes, resulting in the formation of the vertical memory string structure 272 (Figure 2P) and the vertical memory string structure space 274 (Figure 2P). The process by which such material removal processes lead to the configuration of the microelectronic device structure 100 shown in Figure 2P will be described in more detail below.

[0093] After completing a series of trim etch cycles, portions of the liner oxide material 250 exposed by the trim etch cycles (e.g., as described in relation to Figure 2M) may be removed (e.g., by wet etching), which may change the depth of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long side of the corresponding rib region 110). The removal process may expose portions of the underlying liner nitride material 248.

[0094] After removing the portion of the liner oxide material 250, the exposed portion of the liner nitride material 248 may be removed by an additional material removal process (e.g., an additional wet etching process). Alternatively, the portion of the liner nitride material 248 may be removed simultaneously with the removal of the portion of the liner oxide material 250 (e.g., by a single process). The removal of the exposed portion of the liner nitride material 248 may be performed via a preliminary vertical memory string structure space 270, thereby further changing the depth of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long side of the corresponding rib region 110). The removal process may expose a portion of the underlying semiconductor material 242.

[0095] After removing the portion of the liner nitride material 248 that overlaps with the preliminary vertical memory string structure space 270, the exposed portion of the semiconductor material 242 may be removed by an additional material removal process (e.g., an additional wet etching process). Alternatively, the portion of the semiconductor material 242 may be removed simultaneously with the removal of one or more liner nitride materials 248 and liner oxide materials 250 (e.g., by a single process). The removal of the semiconductor material 242 may be carried out through the preliminary vertical memory string structure space 270, which may further change the depth of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long side of the corresponding rib region 110).

[0096] After removing the portion of the semiconductor material 242 that overlaps with the preliminary vertical memory string structure space 270, the portion of the band-engineered tunnel oxide material 240 may be removed by an additional material removal process (e.g., an additional wet etching process). Alternatively, the portion of the band-engineered tunnel oxide material 240 may be removed simultaneously with (e.g., by a single process) the removal of one or more of the doped polysilicon material 242, the liner nitride material 248, and the liner oxide material 250. The removal of the band-engineered tunnel oxide material 240 may be carried out via the preliminary vertical memory string structure space 270, thereby further changing the depth of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long side of the corresponding rib region 110).

[0097] After removing the portion of the band-engineered tunnel oxide material 240 that overlaps with the preliminary vertical memory string structure space 270, the portion of the storage nitride material 238 may be removed by an additional material removal process (e.g., an additional wet etching process). Alternatively, the portion of the storage nitride material 238 may be removed simultaneously with (e.g., by a single process) the removal of one or more of the band-engineered tunnel oxide material 240, semiconductor material 242, liner nitride material 248, and liner oxide material 250. The removal of the storage nitride material 238 may be carried out via the preliminary vertical memory string structure space 270, which may further change the depth of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long side of the corresponding rib region 110).

[0098] After removing the portion of the storage nitride material 238 that overlaps with the preliminary vertical memory string structure space 270, the portion of the barrier oxide material 236 may be exposed through the preliminary vertical memory string structure space 270. The depth of the preliminary vertical memory string structure space 270 may reach at least the band-engineered tunnel oxide material 240 (for example, in a horizontal direction perpendicular to the long side of the corresponding rib region 110), and may also reach, for example, at least the storage nitride material 238 or at least the barrier oxide material 236.

[0099] The portions of the liner oxide material 250, liner nitride material 248, semiconductor material 242, band-engineered tunnel oxide material 240, and / or storage nitride material 238 that overlap with the preliminary vertical memory string structure space 270 are removed, and at the same time, portions of the mask oxide material 262 (Figure 2O), mask material 254 (Figure 2J), liner oxide material 250 (Figure 2C), and liner nitride material 248 (Figure 2C) are removed from the preliminary vertical memory string structure 268, which may result in the exposure of the semiconductor material 242. During this removal process, the mask oxide material 262 may suppress (e.g., delay, slow down, or limit) the removal of the mask oxide material 262 and the materials located beneath it (e.g., mask material 254, liner oxide material 250, liner nitride material 248). Therefore, the removal of the mask oxide material 262 overlapping the preliminary vertical memory string structure 268 and the material located beneath it may be performed at a slower removal rate than the removal of the liner oxide material 250, liner nitride material 248, semiconductor material 242, band-engineered tunnel oxide material 240, and / or storage nitride material 238 overlapping the preliminary vertical memory string structure space 270.

[0100] As shown in Figure 2P, as a result of the material removal process described with reference to Figures 2O and 2P, a vertical memory string structure 272 may be formed from the preliminary vertical memory string structure 268 (Figure 2O), and a vertical memory string structure space 274 may be formed from the preliminary vertical memory string structure space 270 (Figure 2O).

[0101] The horizontal pitch between the horizontal centers of each adjacent vertical memory string structure 272 may be in the range of approximately 20 nm to approximately 175 nm, for example, in the range of approximately 50 nm to approximately 130 nm, in the range of approximately 70 nm to approximately 115 nm, or in the range of approximately 90 nm.

[0102] As a result of the material removal treatment (e.g., wet etching) used to form the vertical memory string structures 272 and vertical memory string structure spaces 274, the vertical memory string structure spaces 274 may be relatively wider (e.g., in the horizontal direction along the long side of the corresponding rib region 110) than their respective preliminary vertical memory string structure spaces 270 (Figure 2O). For example, the width of each vertical memory string structure space 274 (e.g., in the horizontal direction along the long side of the corresponding rib region 110) may be in the range of about 30 nm to about 80 nm, for example, about 55 nm. Furthermore, the vertical memory string structures 272 may be relatively narrower (e.g., in the horizontal direction along the long side of the corresponding rib region 110) than their respective preliminary vertical memory string structures 268 (Figure 2O). For example, the width of each vertical memory string structure 272 (e.g., in the horizontal direction along the long side of the corresponding rib region 110) may be in the range of about 20 nm to about 50 nm, for example, about 35 nm.

[0103] Figures 2Q and 2R are simplified perspective views showing a portion of the microelectronic device structure 100 in a processing stage after the processing stage described above, in relation to Figure 2P. Figure 2R is a simplified partial perspective cross-sectional view of the microelectronic device structure 100 in portion B, indicated by the dashed line in Figure 2Q, and corresponds to the processing stage shown in Figure 2Q.

[0104] Referring to Figure 2Q, after the vertical memory string structure 272 and vertical memory string structure space 274 are formed, the cover material 260 (Figure 2I) may be removed (e.g., by etching). The cover material 260 may be substantially removed from above (e.g., in the Z direction) the upper dielectric material 220, barrier oxide material 236, storage nitride material 238, band-engineered tunnel oxide material 240, and semiconductor material 242.

[0105] Continuing to refer to Figure 2Q, the top plug 286 may be formed to contact the top of the vertical memory string structure 272. The top plug 286 may be formed before forming the semiconductor material 285 in the recess in the substrate structure 104, as described below. The top plug 286 may be formed by patterning a cavity corresponding to the top plug 286 using conventional photolithography techniques, and then forming the semiconductor material within the top plug cavity. In some embodiments, the top plug 286 may be composed of polysilicon doped with one or more conductivity-enhancing elements (e.g., lightly doped), such as N-type polysilicon (e.g., polysilicon doped with one or more of arsenic, phosphorus, and antimony). As shown in Figure 2Q, individual top plugs 286 may be in contact (e.g., physical contact, electrical contact) with a plurality (e.g., multiple) horizontally adjacent vertical memory string structures 272. In some embodiments, individual top plugs 286 may contact four vertical memory string structures 272 within individual rib regions 110 of the profile slot 106. The top plugs 286 may also be used as drain-side contact structures for the vertical memory string structures 272.

[0106] After the top plug 286 is formed, at least one trench 276 (e.g., a slot, slit, or opening) may be formed, which may extend vertically through the entire pre-stack structure 102. The trench 276 may be formed by removing a portion of the pre-stack structure 102 (including a layer 206 consisting of its insulating material 202 and sacrificial material 204). The trench 276 may be horizontally offset from the profile slot 106 (e.g., in the Y direction) and extend horizontally substantially parallel to the backbone region 108 of the profile slot 106. The trench 276 may have an elongated horizontal cross-sectional shape (e.g., a shape in which the dimension in the X direction is greater than the dimension in the Y direction). Furthermore, the trench 276 may extend vertically (e.g., in the Z direction) through at least a portion of the upper substrate structural material 222 and the intermediate substrate structural material 224 of the substrate structure 104. In some embodiments, the trench 276 may extend vertically (e.g., in the Z direction) downward through the lower substrate structural material 226. In some embodiments, the trench 276 may individually reach or extend vertically beyond the substrate structural dielectric material 228.

[0107] After forming the trench 276, at least a portion of the intermediate substrate structure material 224 (Figure 2P) of the substrate structure 104 may be removed (e.g., excavated) to form a recess extending horizontally (e.g., in the Y direction) from the trench 276 to the bottom plug 246 (Figure 2P). Subsequently, portions of the barrier oxide material 236, storage nitride material 238, and band-engineered tunnel oxide material 240 in the vertical position of the recess may be removed in the region horizontally surrounding the semiconductor material 242 of the bottom plug 246, exposing the semiconductor material 242. As shown in Figure 2Q, individual bottom plugs 246 may be in contact (e.g., physical contact, electrical contact) with a plurality (e.g., multiple) of horizontally adjacent vertical memory string structures 272. In some embodiments, individual bottom plugs 246 may be in contact with four vertical memory string structures 272 within individual rib regions 110 of the profile slot 106. The bottom plug 246 may be used as the source-side contact structure of the vertical memory string structure 272.

[0108] After the bottom plug 246 is exposed, the recess in the substrate structure 104 may be backfilled with semiconductor material 285 through the trench 276. The semiconductor material 285 may be in contact with the semiconductor material 242 of the bottom plug 246. The semiconductor material 285 may have substantially the same material composition as the semiconductor material 242, or it may have a different material composition from the semiconductor material 242. In some embodiments, the semiconductor material 285 may be formed from doped polysilicon, for example, N-type polysilicon (e.g., polysilicon doped with one or more conductivity-enhancing elements such as arsenic, phosphorus, and antimony).

[0109] After forming the semiconductor material 285, a portion of the semiconductor material 285 in the trench 276 may be removed (for example, by isotropic etching) to form a trench oxide film material 288 at the bottom of the trench 276. The trench oxide film material 288 may cover the surface of the substrate structure 104 exposed at the bottom of the trench 276. For example, the trench oxide film material 288 may be formed on or on the surfaces of the upper substrate structure material 222, the semiconductor material 285, and the lower substrate structure material 226.

[0110] After the top plug 286, trench oxide material 288, and bottom plug 246 have formed contact with the semiconductor material 285, the microelectronic device structure 100 may be subjected to a replacement gate process. During the replacement gate process, the sacrificial material 204 of layer 206 of the preliminary stack structure 102 may be replaced at least partially (e.g., substantially) with the conductive material 280. This allows the replacement gate process to convert the preliminary stack structure 102 into a stack structure 210. The stack structure 210 may include an alternating vertical (e.g., Z-direction) sequence of insulating material 202 and conductive material 280 arranged as layers 278. During the replacement gate process, the trench oxide material 288 may protect portions of the substrate structure 104 located within the horizontal region of the trench 276 from removal.

[0111] The conductive material 280 of layer 278 of the stack structure 210 may be formed from one or more of the following: at least one metal, at least one alloy, at least one conductive metal-containing material (e.g., at least one conductive metal nitride, at least one conductive metal silicide, at least one conductive metal carbide, at least one conductive metal oxide), and at least one conductive doped semiconductor material (e.g., conductive doped polysilicon). In some embodiments, the conductive material 280 may be formed from W. Optionally, at least one liner material (e.g., at least one insulating liner material, at least one conductive liner material) may be formed around the conductive material 280. The liner material may be formed from, for example, one or more metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the liner material may include at least one conductive material used as a seed material for forming the conductive material 280. In some embodiments, the liner material may include titanium nitride (TiNx, e.g., TiN). In yet another embodiment, the replacement gate process may further include the formation of a dielectric liner, for example, the deposition of aluminum oxide (AlOx, e.g., Al2O3). As a non-limiting example, in each layer 278 of the stack structure 210, AlOx (e.g., Al2O3) may be formed directly adjacent to the insulating material 202, TiNx (e.g., TiN) may be formed directly adjacent to the AlOx, and W may be formed directly adjacent to the TiNx. For ease of understanding and clarity of explanation, the liner material is not shown in Figures 2Q and 2R, but it should be understood that the liner material may be placed around the conductive material 280.

[0112] Referring together to Figures 2P and 2Q, the replacement gate process used to form the stack structure 210 may include treating the microelectronic device structure 100 with at least one wet etchant prepared to selectively remove a portion of the sacrificial material 204 of layer 206 of the preliminary stack structure 102 through a trench 276. The wet etchant may be selected to remove a portion of the sacrificial material 204 without substantially removing a portion of the insulating material 202 of layer 206 of the preliminary stack structure 102, and without substantially removing portions of the barrier oxide material 236, liner oxide material 250, cover material 260 (Figure 2I), and trench oxide material 288. In some embodiments, if the sacrificial material 204 comprises a dielectric nitride material (e.g., SiNy, Si3N4, etc.) and the insulating material 202 comprises a dielectric oxide film material (e.g., SiOx, SiO2, etc.), the sacrificial material 204 of layer 206 of the preliminary stack structure 102 may be selectively removed using a wet etchant containing H3PO4. After selectively removing the portion of the sacrificial material 204, the resulting recess may be filled with a conductive material 280 to form a stack structure 210 (including its layer 278). The conductive material 280 may then be recessed isotropically to provide electrical isolation between layers 278. After forming the stack structure 210, the trench 276 may be filled with a dielectric material to form a filled trench structure (as described later with reference to Figure 3).

[0113] In another embodiment, the preliminary stack structure 102 may initially be formed to have an alternating vertical (e.g., Z-direction) sequence of insulating material 202 and conductive material 280 arranged as layers 278, rather than a sequence of insulating material 202 and sacrificial material 204 arranged as layers 206 as described above. Each layer 278 of the preliminary stack structure 102 may contain conductive material 280 perpendicularly adjacent to insulating material 202 (e.g., directly perpendicularly adjacent in the Z-direction). In such an embodiment, no subsequent replacement gate processing is performed.

[0114] Referring to Figure 2Q, layers 278, in which insulating material 202 and conductive material 280 are alternately stacked, are stacked vertically above the bottom plug 246. The stack structure 210 includes a vertical memory string region 282 and may also include vertical memory cells 284 located at the intersection of the vertical memory string structure 272 and the conductive material 280 of layer 278. A portion of the conductive material 280 may be used as an access line structure (e.g., a word line structure) for the vertically connected memory cells 284. Furthermore, one or more layers 278 adjacent to the bottom plug 246 (e.g., in the Z direction) may be used as a selected gate source (SGS) structure, and one or more layers 278 adjacent to the top plug 286 (e.g., in the Z direction) may be used as a selected gate drain (SGD) structure.

[0115] Accordingly, according to embodiments of the present disclosure, a method for forming a microelectronic device includes the step of forming a pre-stack structure having layers on a substrate structure. Each layer of the pre-stack structure includes a sacrificial material and an insulating material perpendicular to the sacrificial material. The method further includes the steps of forming a slot having a first region and a second region extending vertically through the pre-stack structure, forming a memory cell material in the slot, forming a mask material in the slot and on the memory cell material, and forming a trim material in the slot and on the mask material. Subsequently, the method includes the steps of removing a portion of the trim material in the first region of the slot, and removing a portion of the trim material, mask material and memory cell material in the second region of the slot to form a memory string structure. Furthermore, after forming the memory string structure, the method includes replacing the sacrificial material in the layers of the pre-stack structure with a conductive material. The first region extends horizontally in a first direction. The second region intersects the first region and extends horizontally in at least one second direction at an angle to the first direction. The memory string structure extends vertically through the preliminary stack structure and is horizontally separated from each other in at least its second direction.

[0116] According to other embodiments of the present disclosure, a microelectronic device includes a stack structure and a substrate structure positioned perpendicularly below the stack structure. The stack structure has layers, each layer comprising a conductive material and an insulating material perpendicularly adjacent to the conductive material. The stack structure is divided into blocks extending horizontally parallel to a first direction. The blocks are separated from each other by insulating slot structures in a second direction, which is orthogonal to the first direction. At least one block has slots and a memory string structure that penetrates the entire layer perpendicularly. The slots include a first region and a second region intersecting the first region. The first region extends horizontally in the first direction. The second region extends horizontally in at least one third direction, which is at an angle to the first and second directions. The memory string structure extends perpendicularly through the stack structure within the horizontal region of the second region of the slot. The memory string structures are separated from each other horizontally in at least their third direction. The substrate structure includes a plug structure and additional conductive material. The plug structure is located within the horizontal region of the second region of the slot of at least one block. The plug structure is in contact with the memory string structure of the at least one block. The additional conductive material is in contact with the sides of the plug structure.

[0117] According to yet another embodiment of the present disclosure, the memory device has a stack structure and a substrate structure positioned vertically below the stack structure. The stack structure includes blocks extending parallel to a first horizontal direction. Each block includes a layer. Each layer has a conductive material and an insulating material adjacent to the conductive material perpendicularly. Each block includes at least partially filled slots and vertically extending memory cell strings. The at least partially filled slots extend perpendicularly through the layers. The slots have a backbone region and a rib region. The backbone region extends substantially linearly in the first horizontal direction. The rib region intersects the backbone region, and each rib region extends substantially linearly in at least one second horizontal direction at an angle to the first horizontal direction. The vertically extending memory cell strings are located within the horizontal region of the rib region of at least partially filled slots. The substrate structure includes a plug structure and a laterally extending conductive structure. The plug structure is electrically connected to the vertically extending memory cell strings. The conductive structure extending laterally contacts the side wall of the plug structure.

[0118] Figure 3 is a simplified partial plan view of the microelectronic device structure 100 following the processing steps described with reference to Figures 2R and 2Q. As shown in Figure 2R, the microelectronic device structure 100 includes a vertical memory string structure 272 located within the rib region 110 of the profile slot 106, which is horizontally adjacent to the side wall of a stack structure 210 that partially defines the rib region 110. Figure 3 also shows a top plug 286 and a bottom plug 246, which are vertically offset from the vertical memory string structure 272 (for example, positioned above and below it, respectively) and are electrically connected to the vertical memory string structure 272.

[0119] Furthermore, as shown in Figure 3, the microelectronic device structure 100 may also include a filled trench structure 302 formed by filling a trench 276 (Figure 2Q) in the stack structure 210 (Figure 2Q) with a dielectric material (e.g., dielectric oxide film material, silicon oxide, etc.). The filled trench structure 302 may extend substantially parallel to the backbone region 108 of the profile slot 106 in the horizontal direction (e.g., the X direction). Moreover, the length of the filled trench structure 302 in the horizontal direction (e.g., the X direction) may be substantially equal to the length of the backbone region 108 of the profile slot 106 in the horizontal direction (e.g., the X direction).

[0120] As shown in Figure 3, each rib region 110 of the profile slot 106 is interposed between two horizontally adjacent portions of the stack structure 210 (horizontally, e.g., in the X direction). The horizontal dimensions of the individual rib regions 110 of the profile slot 106 may be selected to ensure sufficient structural stability of the stack structure 210 and to substantially maintain its shape and configuration in the processing steps described above with reference to Figures 1 and 2A to 2R. The configuration of the preliminary stack structure 102 (Figure 2P) and the portion of the stack structure 210 (Figure 2R) located between the individual rib regions 110 may prevent (e.g., substantially prevent) the collapse of the preliminary stack structure 102 (Figure 2P) and the portion of the stack structure 210 (Figure 2R).

[0121] As described in relation to Figures 2J to 2O above, the trim etch cycle may begin at the end of the individual rib region 110 closest to the backbone region 108 of the profile slot 106 and proceed away from the backbone region 108 of the profile slot 106. Figure 3 shows a typical horizontal direction 304 (e.g., extending from the opposite side of the backbone region 108) that the subsequent trim etch cycle may follow.

[0122] The stack structure 210 of the microelectronic device structure 100 may be divided into blocks 306 separated from each other by the filled trench structure 302 (e.g., segmented, partitioned) (e.g., in the Y direction). Alternatively, the stack structure 210 of the microelectronic device structure 100 may be divided into blocks electrically separated from each other by the filled trench structure 302 and the backbone region 108 (e.g., the size of the blocks is approximately half the size of the block 306 shown in Figure 3), and the filled trench structure 302 may individually extend vertically, completely penetrating the stack structure 210 (e.g., in the Z direction).

[0123] At least some of the blocks 306 of the stack structure 210 may extend substantially parallel to each other in the horizontal direction (e.g., the X direction). Each block 306 of the stack structure 210 may have substantially the same geometric configuration (e.g., substantially the same dimensions and substantially the same shape) as each other block 306, or one or more blocks 306 may have a different geometric configuration (e.g., different dimensions and / or different shape) than one or more other blocks 306. Furthermore, each pair of adjacent blocks 306 of the stack structure 210 may be separated from each other horizontally by the same distance as each other pair of adjacent blocks 306 of the stack structure 210 (e.g., a distance corresponding to the width of the individual filling trench structure 302 in the Y direction), or at least one pair of adjacent blocks 306 of the stack structure 210 may be separated from each other horizontally by a distance different from the distance separating the other at least one pair of adjacent blocks 306. In some embodiments, the blocks 306 of the pre-stack structure 102 have substantially uniform size, shape and spacing with respect to each other (e.g., substantially without variation, substantially equal, substantially constant).

[0124] Block 306 may be further subdivided into subblocks 308. Each subblock 308 is defined by the horizontal profile of the corresponding rib region 110. Thus, a subblock 308 may include a vertical memory string structure 272 on a pair of opposing side walls 208 of the stack structure 210, which are partially defined by the individual rib regions 110 within the stack structure 210.

[0125] Figures 1, 2A to 2R, and 3 show the configuration of the profile slot 106 according to the embodiments of this disclosure, but in other embodiments, the microelectronic device structure 100 may be formed to have a different profile slot configuration. Non-limiting examples of such different profile slot configurations will be described in further detail below with reference to Figures 4 to 7. As shown in Figures 4 to 8, the microelectronic device structures 400, 500, 600, 700, and 800 may be formed to have profile slots 406, 506, 606, 706, and 806, respectively, each having a different horizontal profile (e.g., when viewed as a top view) than the profile slot 106 of the microelectronic device structure 100. The microelectronic device structures 400, 500, 600, 700, and 800 may each have different profile slots 406, 506, 606, 706, and 806, and may also be formed by processing steps similar to those described above with reference to Figures 2A to 2R to form the desired microelectronic devices of this disclosure.

[0126] Referring to Figure 4, the preliminary stack structure 402 (for example, corresponding to the preliminary stack structure 102 shown in Figures 1 and 2A to 2P) may be formed to have a profile slot 406. The profile slot 406 may include a first region 408 extending in a first horizontal direction (e.g., the X direction) and a second region 410 extending parallel to a second horizontal direction that intersects the first region 408 and forms an angle with respect to the first horizontal direction. The first region 408 may have a similar function to the backbone region 108 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may have a single elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape). The second region 410 may have a similar function to the rib region 110 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may have a single elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) and may partially overlap the first region 408 in the horizontal direction.

[0127] To form the profile slot 406, the second region 410 may be formed within the pre-stack structure 402 (for example, by a material removal process such as an etching process), and then the first region 408 may be formed within the pre-stack structure 402 (for example, by an additional material removal process such as an additional etching process). The first region 408 may be formed after the formation of the second region 410 (for example, following the formation of the second region 410). After the formation of the profile slot 406, the microelectronic device structure 400 may be subjected to additional processing substantially similar to that described above with reference to Figures 2A to 2R for the microelectronic device structure 100. Subsequent trim etch cycles used during the additional processing (for example, trim etch cycles similar to those described above with reference to Figures 2J to 2O) may proceed in a general horizontal direction 412 away from the first region 408.

[0128] Referring to Figure 5, the preliminary stack structure 502 (corresponding to, for example, the preliminary stack structure 102 shown in Figures 1 and 2A to 2P) may be formed to have a plurality of profile slots 506. Each profile slot 506 may individually include a first region 508 and a second region 510 intersecting the first region 508. The first regions 508 of the plurality of profile slots 506 are spaced apart from each other, forming a row of first regions 508 extending in a first horizontal direction (e.g., the X direction), and may be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. The second regions 510 of the plurality of profile slots 506 are spaced apart from each other and may extend parallel to a third horizontal direction that is at an angle to the first and second horizontal directions. The first region 508 of each profile slot 506 has a function similar to the backbone region 108 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a desired horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape, square horizontal cross-sectional shape, circular horizontal cross-sectional shape). The second region 510 of each profile slot 506 has a function similar to the rib region 110 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a single elongated horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape) that partially overlaps horizontally with the first region 508.

[0129] To form the profile slot 506, the second region 510 may be formed within the pre-stack structure 502 (for example, by a material removal process such as an etching process), and thereafter, the first region 508 may be formed within the pre-stack structure 502 (for example, by an additional material removal process such as an additional etching process). The first region 508 may be formed after the formation of the second region 510 (for example, following the formation of the second region 510). After the formation of the profile slot 506, the microelectronic device structure 500 may be subjected to additional processing substantially similar to that described above with reference to Figures 2A to 2R for the microelectronic device structure 100. The first region 508 may be formed after the formation of the second region 510 (for example, following the formation of the second region 510). After the formation of the profile slot 506, the microelectronic device structure 500 may be subjected to additional processing substantially similar to that described above with reference to Figures 2A to 2R for the microelectronic device structure 100. Subsequent trim etch cycles used during the additional processing (for example, trim etch cycles similar to those described above with reference to Figures 2J to 2O) may proceed according to a general horizontal direction 512 away from each first region 508.

[0130] Referring to Figure 6, the preliminary stack structure 602 (corresponding to, for example, the preliminary stack structure 102 shown in Figures 1 and 2A to 2P) may be formed to have a plurality of profile slots 606. Each profile slot 606 may individually include a first region 608 and a second region 610 intersecting the first region 608. The first regions 608 of the plurality of profile slots 606 may be spaced apart from each other and form a plurality of columns that extend individually in a first horizontal direction (e.g., the X direction). The first regions 608 within each column may be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. The first regions 608 in different columns may be horizontally offset from each other in the second horizontal direction. The second regions 610 of the plurality of profile slots 606 may be spaced apart from each other and extend parallel to a third horizontal direction that forms an angle with respect to the first and second horizontal directions. Profile slots 606 adjacent to each other in the first horizontal direction may be partially offset in the third horizontal direction. For example, the second regions 610 of two adjacent profile slots 606 in the first horizontal direction may partially overlap in the third horizontal direction, and the first regions 608 of two profile slots 606 may be completely offset in the third horizontal direction. As shown in Figure 6, some profile slots 606 may be substantially aligned with each other in the third horizontal direction, and such profile slots 606 may extend in series in the third horizontal direction. Parts of the pre-stack structure 602 may be interposed between profile slots 606 that are substantially aligned with each other in the third horizontal direction.

[0131] The first region 608 of each profile slot 606 may have a function similar to the backbone region 108 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a desired horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape, square horizontal cross-sectional shape, circular horizontal cross-sectional shape). The second region 610 of each profile slot 606 may have a function similar to the rib region 110 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a single elongated horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape) that partially overlaps horizontally with the first region 608.

[0132] To form the profile slot 606, the second region 610 may be formed within the pre-stack structure 602 (for example, by a material removal process such as an etching process), and then the first region 608 may be formed within the pre-stack structure 602 (for example, by an additional material removal process such as an additional etching process). The first region 608 may be formed after the formation of the second region 610 (for example, following the formation of the second region 610). After the formation of the profile slot 606, the microelectronic device structure 600 may be subjected to additional processing substantially similar to that described above with reference to Figures 2A to 2R for the microelectronic device structure 100. Subsequent trim etch cycles used during the additional processing (for example, trim etch cycles similar to those described above with reference to Figures 2J to 2O) may proceed according to a general horizontal direction 612 away from each first region 608.

[0133] Referring to Figure 7, the preliminary stack structure 702 (corresponding to the preliminary stack structure 102 described above, for example, with reference to Figures 1 and 2A to 2P) may be formed to have a plurality of profile slots 706. Each profile slot 706 may include a first region 708 and a second region 710 intersecting the first region 708. The first regions 708 of the plurality of profile slots 706 may be spaced apart from each other and form a plurality of columns, each of which may extend in a first horizontal direction (e.g., the X direction). The first regions 708 within each column may be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction. The first regions 708 belonging to different columns may be horizontally offset from each other in the second horizontal direction. The second regions 710 of the plurality of profile slots 706 may be spaced apart from each other and extend parallel to a third horizontal direction that forms an angle with respect to the first and second horizontal directions. Adjacent profile slots 706 in the first horizontal direction may be partially offset in the third horizontal direction. For example, the second regions 710 of two adjacent profile slots 706 in the first horizontal direction may partially overlap each other in the third horizontal direction, and the first regions 708 of these two profile slots 706 may be completely offset in the third horizontal direction. As shown in Figure 7, some of the profile slots 706 are substantially aligned with each other in the third horizontal direction, so that these profile slots 706 may extend in series along the third horizontal direction. Part of the pre-stack structure 702 may be interposed between such substantially aligned profile slots 706 in the third horizontal direction.

[0134] The first region 708 of each profile slot 706 may have a similar function to the backbone region 108 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a desired horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape, square horizontal cross-sectional shape, circular horizontal cross-sectional shape). The second region 710 of each profile slot 706 may have a similar function to the rib region 110 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may exhibit a single elongated horizontal cross-sectional shape (e.g., rectangular horizontal cross-sectional shape) and may partially overlap the first region 708 in the horizontal direction.

[0135] To form the profile slot 706, the first region 708 and its second region 710 may be formed substantially simultaneously within the pre-stack structure 702 (e.g., substantially simultaneously). After the formation of the profile slot 706, the microelectronic device structure 700 may be subjected to additional processing substantially similar to that described above with reference to Figures 2A to 2R for the microelectronic device structure 100. Subsequent trim etch cycles used during the additional processing (e.g., trim etch cycles similar to those described above with reference to Figures 2J to 2O) may proceed according to a general horizontal direction 712 away from each of the first regions 708.

[0136] Referring to Figure 8, the preliminary stack structure 802 (for example, corresponding to the preliminary stack structure 102 shown in Figures 1 and 2A to 2P) may be formed to have a profile slot 806. The profile slot 806 may include a plurality of first regions 808 extending parallel to each other along a first horizontal direction (e.g., the X direction) and offset from each other in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction, and a plurality of second regions 810 intersecting the first regions 808 and extending parallel to each other along a third horizontal direction that forms an angle with respect to the first and second horizontal directions. The first regions 808 may be individually offset from the midpoint of the profile slot 806 in the third horizontal direction. For example, two (2) first regions 808 may be positioned approximately 1 / 4 length and approximately 3 / 4 length along the third horizontal direction of the profile slot 806, respectively. Each of the first regions 808 of the profile slot 806 may have a function similar to the backbone region 108 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may each exhibit an elongated horizontal cross-sectional shape (for example, a rectangular horizontal cross-sectional shape). Each of the second regions 810 of the profile slot 806 may have a function similar to the rib region 110 of the profile slot 106 described above with reference to Figures 1, 2A to 2R and 3, and may each exhibit an elongated horizontal cross-sectional shape (for example, a rectangular horizontal cross-sectional shape) and may overlap horizontally with each of the first regions 808.

[0137] To form the profile slot 806, a second region 810 may be formed within the pre-stack structure 802 (e.g., via a material removal process such as an etching process), and then a first region 808 may be formed within the pre-stack structure 802 (e.g., via an additional material removal process such as an additional etching process). The first region 808 may be formed after the formation of the second region 810 (e.g., following the formation of the second region 810). In yet another embodiment, the first region 808 and the second region 810 may be formed almost simultaneously with each other to form the profile slot 806. After the formation of the profile slot 806, the microelectronic device structure 800 may be subjected to additional processing substantially similar to the processing described above for the microelectronic device structure 100 with reference to Figures 2A to 2R. Subsequent trim etch cycles employed during the additional processing (e.g., trim etch cycles similar to those described above with reference to Figures 2J to 2O) may proceed along a general horizontal direction 812 away from each first region 808.

[0138] Microelectronic device structures according to embodiments of this disclosure (for example, the microelectronic device structures 100, 400, 500, 600, 700, and 800 described above with reference to one or more of Figures 1 to 8) may be used in electronic systems according to embodiments of this disclosure. For example, Figure 9 is a block diagram of electronic system 900 according to embodiments of this disclosure. Electronic system 900 may include, for example, a computer or computer hardware component, a server or other network hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet with Wi-Fi or cellular communication capabilities such as an iPad® tablet or a SURFACE® tablet, an e-reader, and a navigation device.

[0139] The electronic system 900 may include at least one memory device 902. The memory device 902 may include, for example, the microelectronic device structures described herein (e.g., microelectronic device structures 100, 400, 500, 600, 700, 800 described herein with reference to one or more of Figures 1 to 8). The electronic system 900 may further include at least one electronic signal processor device 904 (often referred to as a “microprocessor”). The electronic signal processor device 904 may optionally include the microelectronic device structures described herein (e.g., microelectronic device structures 100, 400, 500, 600, 700, 800 described herein with reference to one or more of Figures 1 to 8). In Figure 9, the memory device 902 and the electronic signal processor device 904 are shown as two separate devices, but in other embodiments, the electronic system 900 may include a single (e.g., only) memory / processor device having the functions of both the memory device 902 and the electronic signal processor device 904. In such embodiments, the memory / processor device may include the microelectronic device structures described herein (for example, the microelectronic device structures 100, 400, 500, 600, 700, 800 described herein with reference to one or more of Figures 1 to 8). The electronic system 900 may further include one or more input devices 906 for a user to input information into the electronic system 900. Examples of input devices 906 include a mouse or other pointing device, a keyboard, a touchpad, buttons, an operation panel, etc. The electronic system 900 may further include one or more output devices 908 for outputting information (for example, visual information or audio information) to the user. Examples of output devices 908 include a monitor, a display, a printer, an audio output jack, a speaker, etc. In one embodiment, the input devices 906 and output devices 908 may constitute a single touchscreen device that can input information into the electronic system 900 and output visual information to the user.The input device 906 and the output device 908 may communicate electrically with one or more of the memory device 902 and the electronic signal processor device 904.

[0140] The structures, devices, and methods disclosed herein can favorably promote one or more of the following compared to conventional structures, conventional devices, and conventional methods: improved performance of microelectronic devices, reduced costs (e.g., manufacturing costs, material costs), advancement of component miniaturization, and improved package density. Furthermore, the structures, devices, and methods disclosed herein can improve scalability, efficiency, and simplicity compared to conventional structures, conventional devices, and conventional methods.

[0141] The following are additional, non-limiting embodiments of this disclosure.

[0142] Embodiment 1: A method for forming a microelectronic device includes the step of forming a pre-stack structure on a substrate structure, wherein the pre-stack structure has a plurality of layers, each comprising a first material and an insulating material perpendicular to the first material. The method further includes the step of forming a slot that penetrates the pre-stack structure vertically, wherein the slot comprises a first region extending horizontally in a first direction and a second region intersecting the first region and extending horizontally in at least one second direction at an angle to the first direction. The method further includes the steps of forming a memory cell material in the slot, forming a mask material on the memory cell material and in the slot, forming a trim material on the mask material and in the slot, removing a portion of the trim material in the first region of the slot, and removing a portion of the trim material, the mask material and the memory cell material in the second region of the slot to form a memory string structure that penetrates the pre-stack structure vertically and is horizontally separated from each other in at least one second direction.

[0143] Embodiment 2: In the method of Embodiment 1, the step of removing a portion of the trim material, the mask material, and the memory cell material within the second region of the slot includes performing a trim etching cycle, each trim etching cycle including the steps of: removing a portion of the trim material within the second region of the slot to expose a portion of the mask material within the second region; forming a blocking material from a portion of the mask material within the second region; removing an additional portion of the trim material adjacent to the blocking material to expose an additional portion of the mask material within the second region; and removing the additional portion of the mask material.

[0144] Embodiment 3: The method of Embodiment 2 further includes a step of partially removing a portion of the memory cell material that horizontally overlaps with the recess formed by removing the additional portion of the mask material after the trim etching cycle has been completed.

[0145] Embodiment 4: In the method of Embodiment 3, the step of partially removing a portion of the memory cell material includes the steps of: selectively etching a portion of the semiconductor material of the memory cell material to expose a portion of the oxide film material of the memory cell material; selectively etching a portion of the exposed oxide film material of the memory cell material to expose a portion of the nitride material of the memory cell material; and selectively etching a portion of the exposed nitride material of the memory cell material to expose an additional portion of the oxide film material of the memory cell material.

[0146] Embodiment 5: The method of Embodiment 4 further includes the steps of forming a dielectric liner material in the slot and on the memory cell material before forming the mask material, and removing a portion of the dielectric liner material exposed by removing an additional portion of the mask material before selectively etching a portion of the semiconductor material of the memory cell material.

[0147] Embodiment 6: In any of Embodiments 1 to 5, the first material of the plurality of layers of the pre-stack structure includes a sacrificial material, and further includes the step of replacing the sacrificial material of the plurality of layers with a conductive material after forming the memory string structure.

[0148] Embodiment 7: The method of any of Embodiments 1 to 5 further comprises the steps of forming a plug opening in the horizontal region of the second region of the slot and extending the plug opening vertically within the base structure, and filling the plug opening with the memory cell material before forming a mask material in the slot, wherein a portion of the memory cell material in the slot is continuous with the additional portion of the memory cell material in the plug opening.

[0149] Embodiment 8: The method of Embodiment 7 further includes the steps of forming the substrate structure to include a sacrificial material interposed perpendicularly between the semiconductor material and an additional semiconductor material, and forming the additional portion of the memory cell material in contact with the sacrificial material of the substrate structure.

[0150] Embodiment 9: The method of Embodiment 8 further includes the steps of: forming an additional slot that penetrates the pre-stack structure vertically and reaches the substrate structure, thereby exposing the side surface of the sacrificial material of the substrate structure; after forming the additional slot, removing at least a portion of the sacrificial material of the substrate structure to form a recess that partially exposes the additional portion of the memory cell material that fills the plug opening; after forming the recess, extending the recess horizontally into the additional portion of the memory cell material to expose the semiconductor material of the additional portion of the memory cell material; and filling the horizontally extended recess with a conductively doped semiconductor material.

[0151] Embodiment 10: The method of any of Embodiments 1 to 5 further includes the following steps before removing a portion of the trim material in the first region of the slot: that is, after forming the trim material in the slot, filling the remainder of the first region of the slot with sacrificial filler material; forming additional masking material that extends substantially continuously horizontally and covers the pre-stack structure and the horizontal region of the slot; forming an opening that completely penetrates the additional masking material vertically and is confined to the horizontal boundary of the first region of the slot; and selectively removing the sacrificial filler material through the opening in the additional masking material.

[0152] Embodiment 11: The method of any of Embodiments 1 to 10 further includes the step of selecting the memory cell material to include the following: a first dielectric oxide material substantially covering the sidewall of the pre-stack structure; a dielectric nitride material substantially covering the first dielectric oxide material; a second dielectric oxide material substantially covering the dielectric nitride material; and a semiconductor material substantially covering the second dielectric oxide material.

[0153] Embodiment 12: The method of any of Embodiments 1 to 11 further comprises the steps of selecting the mask material to include polysilicon and selecting the trim material to include silicon nitride.

[0154] Embodiment 13: A microelectronic device comprising a stack structure having a plurality of layers, each containing a conductive material and an insulating material perpendicular to the conductive material, wherein the stack structure is divided into blocks extending horizontally parallel to a first direction and separated from each other by an insulating slot structure in a second direction perpendicular to the first direction, and at least one of the blocks is a slot extending vertically through all the layers, comprising a first region extending horizontally in the first direction and a second region intersecting the first region and extending horizontally in at least one third direction at an angle to the first and second directions, and a memory string structure extending vertically through the stack structure and disposed within the horizontal region of the second region of the slot, separated from each other horizontally in at least one third direction.

[0155] Embodiment 14: A microelectronic device of Embodiment 13, wherein each of the memory string structures comprises a layer of a first dielectric oxide material on the sidewall of the stack structure partially defining the slots, a layer of dielectric nitride material on the layer of the first dielectric oxide material, a layer of a second dielectric oxide material on the layer of dielectric nitride material, and a layer of semiconductor material on the layer of the second dielectric oxide material.

[0156] Embodiment 15: A microelectronic device according to Embodiment 14, further comprising a substrate structure located vertically below the stack structure, wherein the substrate structure includes: a source contact structure located within a horizontal region of a second region of the slot of at least one block and in contact with the memory string structure of at least one block; and an additional conductive material in contact with the side surface of the source contact structure.

[0157] Embodiment 16: A microelectronic device according to Embodiment 15, wherein the source contact structure each includes: an additional layer of the first dielectric oxide material; an additional layer of dielectric nitride material on the additional layer of the first dielectric oxide material; an additional layer of the second dielectric oxide material on the additional layer of dielectric nitride material; and an additional layer of semiconductor material on the additional layer of the second dielectric oxide material, wherein the additional layer of semiconductor material is continuous with the layer of semiconductor material of each memory string structure.

[0158] Embodiment 17: A microelectronic device according to Embodiment 16, wherein the additional conductive material of the substrate structure is in direct physical contact with the additional layer of semiconductor material of each source contact structure.

[0159] Embodiment 18: A microelectronic device according to Embodiment 17, wherein each source contact structure is in contact with a plurality of memory string structures in a horizontally overlapping manner.

[0160] Embodiment 19: A microelectronic device according to any of Embodiments 13 to 18, further comprising a drain contact structure disposed within a horizontal region of a second region of a slot and in contact with the memory string structure, wherein the drain contact structure is located vertically above the source contact structure and overlaps the source contact structure horizontally.

[0161] Embodiment 20: A memory device comprising a stack structure, the stack structure comprising a block extending parallel to a first horizontal direction, each block comprising a plurality of layers comprising a conductive material and an insulating material perpendicularly adjacent to the conductive material, each block comprising at least partially filled slots extending vertically through the layers, the slots comprising a backbone region extending substantially linearly in the first horizontal direction and at least one rib region extending substantially linearly in a second horizontal direction intersecting the backbone region and at an angle to the first horizontal direction, the stack structure comprising a string of vertically extending memory cells formed within the horizontal region of the rib region of the at least partially filled slots, and a substrate structure located vertically below the stack structure, the substrate structure comprising a source contact structure electrically connected to the string of vertically extending memory cells and a horizontally extending conductive structure in contact with the side wall of the source contact structure.

[0162] While various modifications and alternative forms are possible with respect to this disclosure, specific embodiments are illustrated in the drawings and described in detail herein. However, this disclosure is not limited to any specific form disclosed. Rather, this disclosure encompasses all modifications, equivalents, and alternative forms that fall within the scope of the claims and their legal equivalents appended below. For example, elements and features disclosed in relation to one embodiment of this disclosure can be combined with elements and features disclosed in relation to other embodiments of this disclosure.

Claims

1. A method for forming a microelectronic device, A step of forming a preliminary stack structure on a substrate structure, wherein the preliminary stack structure has a plurality of layers, each containing a first material and an insulating material adjacent to the first material in a direction perpendicular to it, A step of forming a slot in the aforementioned pre-stack structure so as to extend vertically, wherein the slot is A first region extending horizontally in the first direction, A second region intersects the first region and extends horizontally in at least one second direction at an angle to the first direction, Processes including, The steps include forming a memory cell material in the aforementioned slot, A step of forming a mask material in the slot and on the memory cell material, A step of forming trim material in the slot and on the mask material, A step of removing a portion of the trim material within the first region of the slot, A step of removing a portion of the trim material, mask material, and memory cell material within the second region of the slot to form a memory string structure in which the preliminary stack structure extends vertically and is horizontally separated from each other in at least one second direction, A method that includes this.

2. A method according to claim 1, wherein the step of removing a portion of the trim material, the mask material and the memory cell material in the second region of the slot includes performing a trim etching cycle, each trim etching cycle being A step of removing a portion of the trim material in the second region of the slot to expose a portion of the mask material in the second region of the slot, A step of forming a blocking material from a portion of the mask material within the second region of the slot, A step of removing the additional portion of the trim material adjacent to the blocking material to expose the additional portion of the mask material in the second region of the slot, A step of removing the additional portion of the mask material, A method that includes this.

3. A method according to claim 2, further comprising the step of partially removing, after the completion of the trim etching cycle, a portion of the memory cell material that overlaps horizontally with a recess formed by removing the additional portion of the mask material.

4. The method according to claim 3, wherein the step of partially removing a portion of the memory cell material is: A step of selectively etching a portion of the semiconductor material of the memory cell material to expose a portion of the oxide film material of the memory cell material, A step of selectively etching a portion of the exposed oxide film material of the memory cell material to expose a portion of the nitride material of the memory cell material, A step of selectively etching a portion of the exposed nitride material of the memory cell material to expose a portion of an additional oxide film material of the memory cell material, A method that includes this.

5. The method according to claim 4, Before forming the mask material, a step of forming a dielectric liner material in the slot and on the memory cell material, A step of removing a portion of the dielectric liner material that has been exposed by removing an additional portion of the mask material before selectively etching a portion of the semiconductor material of the memory cell material, A method that further includes this.

6. A method according to any one of claims 1 to 5, wherein the first material of the plurality of layers of the pre-stack structure includes a sacrificial material, and further comprises the step of replacing the sacrificial material of the plurality of layers with a conductive material after forming the memory string structure.

7. A method according to any one of claims 1 to 5, The steps include forming a plug opening within the horizontal region of the second region of the slot, and extending the plug opening vertically within the base structure, Before forming the mask material in the slot, the plug opening is filled with the memory cell material. A method further comprising the wherein a portion of the memory cell material in the slot is continuous with an additional portion of the memory cell material in the plug opening.

8. The method according to claim 7, The process of forming the substrate structure including a sacrificial material interposed perpendicularly between the semiconductor material and an additional semiconductor material, A step of forming the additional portion of the memory cell material by bringing it into contact with the sacrificial material of the substrate structure, A method that further includes this.

9. The method according to claim 8, The process involves forming an additional slot that penetrates the aforementioned pre-stack structure vertically and reaches the base structure, thereby exposing the side surface of the sacrificial material of the base structure through the additional slot, After forming the additional slot, the steps include removing at least a portion of the sacrificial material of the substrate structure to form a recess that partially exposes the additional portion of the memory cell material that fills the plug opening, After forming the recess, the recess is extended horizontally within the additional portion of the memory cell material, thereby exposing the semiconductor material of the additional portion of the memory cell material. A step of filling the horizontally extending recess with a conductively doped semiconductor material, A method that further includes this.

10. A method according to any one of claims 1 to 5, wherein before removing a portion of the trim material in the first region of the slot, The steps include: forming the trim material in the slot, and then filling the remaining portion of the first region of the slot with sacrificial filler material; A step of forming an additional mask material that extends horizontally substantially continuously over the horizontal region of the pre-stack structure and the slot and covers them, The steps include: forming an opening that completely penetrates the additional mask material vertically and is limited to the horizontal boundary of the first region of the slot; A step of selectively removing the sacrificial filler material through the opening in the additional mask material, A method that further includes this.

11. A method according to any one of claims 1 to 5, A first dielectric oxide film material substantially covering the side wall of the aforementioned pre-stack structure, A dielectric nitride material substantially covering the first dielectric oxide film material, A second dielectric oxide film material substantially covering the dielectric nitride material, A semiconductor material substantially covering the second dielectric oxide film material, A method further comprising the step of selecting the memory cell material to include the following:

12. A method according to any one of claims 1 to 5, A step of selecting the mask material so as to contain polysilicon, A step of selecting the trim material to contain silicon nitride, A method that further includes this.

13. A microelectronic device, Each has a stack structure having a plurality of layers, each containing a conductive material and an insulating material adjacent to the conductive material perpendicularly, and the stack structure is divided into blocks that extend horizontally parallel to a first direction and are separated from each other in a second direction perpendicular to the first direction, and at least one of the blocks is A slot extending vertically through all of the aforementioned layers, A first region extending horizontally in the first direction, A second region that intersects the first region and extends horizontally in at least one third direction that forms an angle with respect to the first and second directions, Slots that include, The stack structure extends vertically and is arranged within the horizontal region of the second region of the slot, and the memory string structure is separated from each other horizontally in at least one third direction, Microelectronic devices including

14. A microelectronic device according to claim 13, Each of the above memory string structures is A layer of first dielectric oxide film material on the side wall of the stack structure that partially defines the slot, A layer of dielectric nitride material on the layer of the first dielectric oxide material, A layer of a second dielectric oxide film material on the layer of the dielectric nitride material, A layer of semiconductor material on the layer of the second dielectric oxide film material, Microelectronic devices including

15. A microelectronic device according to claim 14, The stack structure further includes a base structure located vertically below the aforementioned stack structure, the base structure being A source contact structure is disposed within the horizontal region of the second region of at least one of the slots of the block and in contact with the memory string structure of the at least one block, An additional conductive material that contacts the side surface of the source contact structure, Microelectronic devices including

16. A microelectronic device according to claim 15, wherein the source contact structure is individually The additional layer of the first dielectric oxide film material, The additional layer of dielectric nitride material on the additional layer of the first dielectric oxide film material, The additional layer of the second dielectric oxide film material on the additional layer of the dielectric nitride material, The additional layer of semiconductor material on the additional layer of the second dielectric oxide film material, A microelectronic device comprising the above, wherein the additional layer of the semiconductor material is continuous with the layer of the semiconductor material of each memory string structure.

17. A microelectronic device according to claim 16, wherein the additional conductive material of the substrate structure is in direct physical contact with the additional layer of the semiconductor material of each source contact structure.

18. A microelectronic device according to claim 17, wherein each source contact structure overlaps horizontally with and is in contact with a plurality of memory string structures.

19. A microelectronic device according to any one of claims 13 to 18, further comprising a drain contact structure disposed within a horizontal region of the second region of the slot and in contact with the memory string structure, wherein the drain contact structure is located vertically above the source contact structure and horizontally overlaps the source contact structure.

20. A memory device, It includes a stack structure, and the stack structure is It has a first horizontally extending block, each block comprising a plurality of layers, each comprising a conductive material and an insulating material perpendicular to the conductive material, and each block individually comprises a slot that is at least partially filled and extends perpendicularly to the layers, the slot is The first backbone region extending substantially linearly in the horizontal direction, Rib regions that intersect the backbone region and extend substantially linearly in at least one second horizontal direction at an angle to the first horizontal direction, Includes, The memory cell string has a horizontal region within the rib region of the at least partially filled slot, The stack structure includes a base structure located vertically below it, and the base structure is A source contact structure electrically connected to the vertically extending memory cell string, A conductive structure extending horizontally that contacts the side wall of the source contact structure, A memory device that includes this.

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