Loop bandwidth control for fractional-N frequency synthesizers

Abstract

In one example, the system includes a phase-locked loop (100) comprising a charge pump (104) coupled to a phase frequency detector (102), a low-pass filter (106) coupled to the charge pump, and a VCO (108) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current (126) to the low-pass filter. The system also includes a current source (114) configured to provide a bias current (130) to the charge pump. The system includes a first bias compensation circuit (116) configured to increase the bias current (130) in response to a control voltage (128) supplied to the VCO being within a first range. The system also includes a second bias compensation circuit (116) configured to decrease the bias current (130) in response to a control voltage (128) supplied to the VCO being within a second range.

Description

[Technical Field]

[0001] A phase-locked loop (PLL) is a system that compares the frequency of a local oscillator to the frequency of a received input signal and uses a feedback loop to lock the local oscillator frequency to the frequency of the received input signal. The output frequency of the local oscillator can be a multiple of the input frequency. A PLL may include a phase-frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). Frequency synthesizers in frequency-modulated continuous-wave (FMCW) radar systems, such as those used in automotive and industrial applications, can use a PLL to transmit a signal with a frequency that rises over time, known as a chirp signal. [Overview of the project]

[0002] According to at least one example described herein, the system includes a phase-locked loop comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a VCO coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter. The system also includes a current source configured to provide a bias current to the charge pump. The system includes a first bias compensation circuit configured to increase the bias current in response to a control voltage supplied to the VCO being within a first range. The system also includes a second bias compensation circuit configured to decrease the bias current in response to a control voltage supplied to the VCO being within a second range.

[0003] According to at least one example described herein, a method includes providing a bias current to a charge pump in a phase-locked loop using a current source. This method also includes providing a control voltage to a VCO in a phase-locked loop, the control voltage being provided in response to a charge pump current from the charge pump. This method includes increasing the bias current provided to the charge pump using a first bias compensation circuit in response to the control voltage being within a first range. This method also includes decreasing the bias current provided to the charge pump using a second bias compensation circuit in response to the control voltage being within a second range.

[0004] According to at least one example described herein, the system includes a phase-locked loop comprising a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a VCO coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current to the low-pass filter, the low-pass filter is configured to provide a control voltage to the VCO, and the gain of the VCO varies with the control voltage. The system also includes a current source configured to provide a bias current to the charge pump, the charge pump current varying with the bias current. The system includes a voltage threshold generator configured to provide a first voltage range and a second voltage range. The system also includes a first bias compensation circuit configured to increase the bias current in response to the control voltage provided to the VCO being within the first voltage range. The system includes a second bias compensation circuit configured to decrease the bias current in response to the control voltage provided to the VCO being within the second voltage range. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of a PLL following various examples.

[0006] [Figure 2] This is a graph of VCO gain versus VCO control voltage according to various examples.

[0007] [Figure 3] This is a block diagram of a PLL following various examples.

[0008] [Figure 4] This is a block diagram of a circuit for varying the charge pump current according to various examples.

[0009] [Figure 5] This is a block diagram of a circuit for varying the charge pump current according to various examples.

[0010] [Figure 6] This is a block diagram of an FMCW radar system, including an FMCW radar system-on-chip (SOC), following various examples.

[0011] [Figure 7] This is a flowchart illustrating methods for adjusting the charge pump current within a PLL according to various examples.

[0012] In drawings, the same reference number or other reference numerals are used to indicate identical or similar features (functionally and / or structurally). [Modes for carrying out the invention]

[0013] A PLL uses an input reference signal F, which has a relatively stable frequency at the input. IN It receives and outputs a frequency that is a multiple of the reference signal, F OUT It generates an output signal called a PFD. The PLL also locks the phase of the output signal with the input signal. The PLL may include a PFD and a subsequent charge pump. The PFD uses a reference signal F at its two inputs. IN and the feedback signal F FBKReceives and determines whether one of the two inputs has a lower frequency or a delayed phase. The PFD provides one or more phase error output signals (e.g., an up signal and a down signal). The charge pump receives the phase error output signals from the output of the PFD and converts them into a push or pull of current to or from a loop filter. The charge pump generates a control voltage V CTRL for the VCO that controls the frequency of the VCO. There may be a loop filter between the charge pump and the VCO.

[0014] In automotive and industrial radar systems, a PLL can be used to generate a radar frequency signal for transmission that has a constant amplitude and a frequency that changes substantially linearly (e.g., increases) over time from a frequency lower limit to a frequency upper limit. The chirp signal generated by the PLL can have a wide bandwidth. Therefore, it is useful for the VCO to have a wide continuous tuning range to generate a chirp signal with a wide bandwidth. The VCO may include a varactor, which is a voltage-controlled capacitor used to control the frequency of the radar frequency output signal. The capacitance of the varactor changes by changing the control voltage V CTRL , thereby causing a frequency change in the chirp signal. The relationship between V CTRL and the frequency is referred to as the VCO gain (e.g., K VCO ) and is expressed in Hertz per Volt (Hz / V). K VCO can change non-linearly with the change in V CTRL . When K CTRL changes with the change in V VCO , the loop bandwidth can also change with the change in V CTRL . If the loop bandwidth is not consistent over the chirp, phase noise fluctuations can be generated and some frequencies can be noisier than other frequencies. Also, the loop bandwidth may have to be constrained for the worst-case scenario (e.g., the highest K VCO ), which can overshoot the reference clock noise.

[0015] In the examples provided herein, the charge pump current I CP V CTRL K produced by the change VCO To compensate for the change in V, CTRL It can be changed along with the loop bandwidth, as explained below. VCO and charge pump current I CP It is proportional to both. Therefore, K VCO ga V CTRL If the value is lower than the first range, CP V in its first range CTRL It can be increased to provide consistent bandwidth for the value. VCO ga V CTRL If the value is high for the second range, I CP V CTRL It can be reduced to provide consistent bandwidth for its second range of values. CP V is used to generate chirps. CTRL K over the entire range of values VCO It can be changed inversely proportional to the fluctuations of I. CP V CTRL This can be changed using a circuit element that increases or decreases the bias current supplied to the charge pump in response to the value of I. In one example, one or more current-steering digital-to-analog converters (DACs) can be used. CP It is used to change the current steering DAC. Current steering DACs can have various configurations. In this example, the current steering DAC has a binary input and generates an analog output in the form of a current based on the voltage value provided in the binary input. The current steering DAC is used to change the K of a given VCO. VCO To compensate for fluctuations in the current, it may be adjusted or trimmed to provide an appropriate current. Using the examples herein, the entire bandwidth of the chirp may be generated by a single VCO, thereby reducing the area and power consumption for the radar system.

[0016] Figure 1 is a block diagram of a PLL circuit 100 according to various examples herein. In one example, PLL 100 is a fractional-N PLL. A fractional-N PLL can generate output frequencies that are not limited to integer multiples of the input frequency. A fractional-N PLL includes additional circuitry that enables precise interpolation between integer multiples of a reference frequency. PLL 100 includes a PFD 102, a charge pump (CP) 104, a low-pass filter (LPF) 106, and a VCO 108. PLL 100 also includes a frequency divider 110, a sigma-delta modulator 112, and a bias current source 114. DAC 116 is coupled to the bias current source 114.

[0017] PFD102 uses the reference signal F IN The first input 118 receives the signal F, and the feedback signal F FBK It includes a second input 120 that receives the reference signal F. PFD102 is a reference signal F. IN and the feedback signal F FBK Based on the difference between the two, the PFD 102 provides an up or down signal (e.g., UP signal 122 or DN signal 124) to the charge pump 104. When the PFD 102 sends an UP signal to the charge pump 104, the charge pump 104 delivers a pull-up current to the LPF 106. The charge pump current is then passed through the PLL 100. CP It is shown as 126. The pull-up current is the voltage V CTRL The current is increased to 128, which is then supplied to the VCO108 by the LPF106. When the PFD102 sends the DN signal to the charge pump 104, the charge pump 104 pulls down the current from the LPF106, thereby V CTRL 128 decreases. The base current provided by the charge pump 104 is supplied by the bias current source 114. BIAS It is proportional to 130. BIAS If you increase or decrease 130, I CP 126 increases or decreases. CP When 126 changes, V is supplied to VCO108. CTRL 128 changes. VCO108 is V CTRL Received 128, F OUTA signal 132 is generated, where F OUT The frequency is V CTRL Based on a value of 128. In the PLL 100, the frequency divider 110 provides feedback, and the sigma-delta modulator 112 enables non-integer-based feedback. The frequency divider 110 can provide integer values, and the sigma-delta modulator 112 enables values ​​between integers by rapidly transmitting alternating integer values. The chirp profile provides the frequency range of the chirp in one example.

[0018] PLL100 controls the signal F, which changes over time in a carefully controlled manner. OUT Since it is used to generate 132, the PLL100 is useful for having a consistent linear and predictable response to various control signals. As mentioned above, V CTRL 128 and F OUT The relationship with 132 does not have to be linear; in some examples, I CP V such as 126 CTRL Compensation is applied by adjusting the controls that affect 128.

[0019] In one example, K VCO V CTRL 128 is determined through testing for PLL100. Ideally, K VCO It is flat, V CTRL It does not change as 128 changes. However, the test is as shown in Figure 2, K VCO However, V CTRL High for several ranges of 128, V CTRL This may indicate that it is lower than the other range of 128. Referring again to Figure 1, DAC116 is V CTRL Based on the value of 128, I BIAS The value of 130 is configured to increase or decrease. The DAC116 pushes current to the bias current source 114 or pulls current from the bias current source 114. BIAS The value of 130 can be changed, thereby V CTRL It can be adjusted to 128. V CTRL When 128 changes, K VCOK VCO To counteract the change, via DAC116 I BIAS 130 has been changed, V CTRL A consistent bandwidth is generated over a range of 128. Each DAC116 is an example of a bias compensation circuit, and other embodiments are V CTRL In response to 128, bias current I BIAS Other types of bias compensation circuits may be included to control 130. A further explanation of this process is provided with reference to Figures 2 to 6 below.

[0020] Figure 2 shows K following various examples. VCO V CTRL Graph 200 is 128. In Graph 200, the x-axis is V CTRL 128 is represented in volts. The y-axis is K VCO The values ​​are expressed in Hz / V. Graph 200 has two curves 202 and 204. Curve 202 represents a first exemplary VCO, labeled VCO1, which may be typical of a 77 GHz automotive radar system. Curve 204 represents a second exemplary VCO, labeled VCO2, which may be typical of a 60 GHz automotive or industrial radar system. In one example, VCO1 has a bandwidth of 1.25 GHz and VCO2 has a bandwidth of 2.33 GHz, and these bandwidths may be multiplied to provide higher frequencies using circuit elements not shown herein.

[0021] As shown in Graph 200, K VCO V CTRL It changes as 128 changes. For example, V at 0.4V CTRL At 128 values, the K of VCO2 (curve 204) VCO It is approximately 1.2 × 10 9 It is Hz / V. 0.9V V CTRL In the 128-value system, the K of VCO2 VCO It is approximately 3.2 × 10 9 It is Hz / V. Finally, 1.3V V CTRL In the 128-value system, the K of VCO2 VCO It is approximately 2.1 × 10 9It is Hz / V. The curve 202 for VCO1 shows a similar pattern. The cubic waveforms shown for curves 202 and 204 indicate that an exemplary VCO with a wide tuning range varies non-linearly. The examples in this specification show the K shown in graph 200 VCO To counter the non-linearity of the curve and as a result, to provide a uniform loop bandwidth, a system and method for varying the charge pump current I CP 126 are provided.

[0022] FIG. 3 is a block diagram of PLL100 according to various examples of this specification. The components of PLL100 and their operations have been described above with respect to FIG. 1. FIG. 3 is a block diagram of the phase domain showing the phase transfer function of PLL100. In this example, LPF106 includes a resistor R Z 302 and a capacitor C304. Various phases of the signal are labeled in FIG. 3. For example, Φ IN (s)306 is the phase of the input reference signal F IN , and Φ FBK (s)308 is the phase of the feedback signal F<e000096>. Φ E (s)310 is the phase error signal, and Φ OUT (s)312 is the phase of the F OUT signal 132. The phase transfer function for PLL100 is shown in Equation (1). TIFF2026511223000002.tif19165<00,00440>

[0023] In Equation (1), Φ E (s) is the phase error signal, M is the feedback division ratio of the divider 110, I CP is the charge pump current I CP 126, and K VCO is the VCO gain in Hz / V. In Equation (1), R Z is the zero resistance of LPF106, and C is the capacitor 304. The bandwidth (BW) of this exemplary PLL100 can be estimated by Equation (2). <e000443>TIFF2026511223000003.tif13121

[0024] Therefore, the bandwidth is the charge pump current I CP 126, K VCO , and R Z It is proportional to K. As shown in equation (2), VCO If V changes significantly, the bandwidth also changes accordingly. Figure 2 shows the V for several VCOs. CTRL As 128 changes, K VCO This indicates that V changes. CTRL When 128 changes and generates a chirp, the loop bandwidth also changes. As mentioned above, if the loop bandwidth is not consistent across the chirp, phase noise fluctuations can occur. Also, the loop bandwidth is affected in the worst-case scenario (e.g., at the highest K). VCO This may be a constraint, which reduces the bandwidth of the chirp signal.

[0025] Equation (2) shows that the bandwidth is K VCO This indicates that it changes along with [something]. However, the bandwidth is I CP It also changes with 126. The other values ​​in equation (2) are constant. Therefore, V CTRL To generate a consistent bandwidth across 128 values, CP 126 is V CTRL K caused by 128 changes VCO It can be changed in inverse proportion to the fluctuation of V. As an example, given V CTRL K about 128 VCO If the value is low, CP It is possible to increase V by 126. CTRL K about 128 VCO If the value is high, CP It can be reduced by 126. K VCO V CTRL Based on 128 measured variations, I CP By adjusting 126, a more consistent bandwidth can be achieved in the PLL100. In the example herein, the current steering DAC116 is V CTRL Based on the value of 128, I BIASThe value of 130 is configured to increase or decrease. The DAC116 pushes current to or pulls current from the bias current source 114, I BIAS The value of 130 can be changed. CP 126 is I BIAS It changes with 130, and therefore this process is I CP 126, V CTRL Change along with 128 changes, V CTRL K in the range of 128 VCO To compensate for the change.

[0026] Figure 4 shows I according to various examples in this specification. CP This is a block diagram of circuit 400 for changing 126. Circuit 400 is I CP I change 126 BIAS The DAC116 includes one or more DACs 116 that push current to or pull current from a bias current source 114 in order to change the value of 130. CTRL It is configured to push or pull the current based on a value of 128. As described above, each DAC116 is an example of a bias compensation circuit, and other embodiments are V CTRL In response to 128, bias current I BIAS Other types of bias compensation circuits may be included to control 130.

[0027] Circuit 400 includes a bias current source 114, a charge pump 104, DACs 116A, 116B, and 116C (collectively DAC116), and a threshold generator 402. Any number of DACs 116 may exist in other examples. Three DACs are useful in this example. The threshold generator 402 determines when each DAC 116 is active and V CTRLIt may include a memory configured to store voltage thresholds for each DAC116, which manage how much current to source or sink for a given value of 128. In some examples, the threshold generator 402 may be a voltage threshold generator circuit and include any suitable circuit elements for generating threshold voltages, such as a resistor network. In another example, the threshold generator 402 may be a circuit element configured to provide a voltage threshold. The threshold generator 402 provides a voltage threshold for DAC116A. THRESH1 V for 404A, DAC116B THRESH2 V for 404B and DAC116C THRESH3 Generates 404C. Each DAC116 also V CTRL Receiving 128, therefore DAC116, V CTRL 128 can be compared to the DAC's voltage threshold, and based on the comparison, it can be turned on or off. By turning DAC116 on or off, I CP To adjust 126, it operates to push current to or pull current from the bias current source 114.

[0028] The bias current source 114 is I CP Generate a baseline current for 126. This baseline current is I in this example. CONST It is 406. V CTRL Based on the value of, the current supplied by DAC116 is the regulated current I ADJUST It is 408. ADJUST 408 may be positive or negative in the examples provided herein. CONST 406 is I ADJUST Combined with 408, I BIAS This becomes 130, which is supplied to the charge pump 104. The charge pump 104 is I BIAS Based on the value of 130, I CP Provide 126 to LPF106. BIAS When 130 increases, I CP 126 increases. BIAS When 130 decreases, I CP 126 decreases.

[0029] As shown in equation (2) above, the loop bandwidth is I CP 126 and K VCO It is proportional to K. VCO If the value is low, CP 126 can be increased to equalize the loop bandwidth. VCO If the value is high, CP 126 can be reduced to equalize the loop bandwidth. VCO is V CTRL Since it changes along with 128, V CTRL The value of 128 is I CP This may be useful in determining whether to increase or decrease 126. Each of the DAC116 is V CTRL Received 128, V CTRL V received 128 from threshold generator 402. THRESH It is then compared. Each DAC116 is then turned on or off in response to the comparison. In this example, DAC116A and DAC116C are boost DACs. When a boost DAC is turned on, it ADJUST Provides a positive current to 408. DAC116B is an attenuated DAC in this example. When an attenuated DAC is turned on, I ADJUST We pull current from 408. Therefore, V CTRL By selectively turning DAC116 on or off based on the value of 128, ADJUST 408 is I BIAS The value of 130 can be changed, and this will result in I CP 126 changes, and K fluctuates. VCO Adjust.

[0030] In one example, the K of PLL100 VCO The curve is curve 204 in Figure 2. As shown in Figure 2, V CTRL If 128 is low (for example, less than 600mV), K VCO It is low. Therefore, if no compensation is provided, the V in this voltage range is low. CTRL The loop bandwidth will be lower for 128. In this example, V CTRL If 128 is less than 600mV, the DAC116A turns on. THRESH1404A is set to approximately 600mV. DAC116A is V CTRL 128 to V THRESH1 Compare with 404A. V CTRL If 128 is lower, V CTRL The transistor in the DAC116A coupled to the 128 input turns on, increasing the current I1 410A supplied by the DAC116A, thereby increasing the current I ADJUST 408 increases. The DAC116 may push or pull current as described herein using current mirrors and other internal circuit elements. In this example, V CTRL If 128 is less than 600mV, DAC116B and 116C are off. Therefore, V CTRL If 128 is less than 600mV, the current I2 from DAC116B (410B) and the current I3 from DAC116C (410C) are approximately zero. CTRL If 128 is less than 600mV, ADJUST An increase of 408 is I CP Increasing 126 results in this V (as shown in Figure 2). CTRL Low K for the 128 range VCO To compensate for that.

[0031] V CTRL When 128 rises above 600mV, the DAC116A turns off and stops supplying current I1 410A. CTRL If the range of 128 is 600mV to 1100mV, DAC116B will turn on. DAC116B is V CTRL It can be configured to turn on within any suitable voltage range for 128. CTRL DAC116B turns on when 128 is within the voltage range of 600-1100mV in this example. DAC116B is an attenuated DAC, and I BIAS The current is pulled from 130. Current I2 410B is the current sinking from charge pump 104, and therefore, I ADJUST 408 is negative during this phase when the DAC116B is on. When the DAC116B pulls or sinks current, I CP 126 is V CTRLIt decreases when 128 is within the above range. As shown in Figure 2, V CTRL If 128 is approximately 600-1100mV, then K VCO It is high, therefore, I CP 126 should be lowered to compensate within this voltage range. Attenuation DACs like the DAC116B, K VCO When I CP Lower 126, therefore this V CTRL It provides more consistent bandwidth across a range of 128.

[0032] In this example, V CTRL When 128 rises above 1100mV, DAC116B turns off, and current I2 410B drops to zero. DAC116C is V CTRL The 128 is configured to turn on when it reaches approximately 1100mV. CTRL At a value of 128, the DAC116C has a current of I3 410C. ADJUST Provided to 408. DAC116C is a boost DAC and provides positive current I3 410C. V CTRL Within this voltage range of 128, ADJUST 408 increases, I CP Increase 126. K VCO The higher V in this voltage range CTRL Since it is lower than 128 (as shown in Figure 2), for this voltage range I CP Raising 126 results in a lower K VCO Compensate for V CTRL It provides a flatter bandwidth across the entire 128-voltage range.

[0033] Referring again to Figure 2, the example K such as curve 204. VCO The curve is low V CTRL Lower K at 128 VCO V in the intermediate range CTRL Higher K at 128 VCO , and high V CTRL Lower K at 128 VCO This indicates that the DAC116 has a low V CTRL 128 is ICP Increase 126, and the intermediate range V CTRL 128 is I CP Reduce 126 and increase V CTRL 128 is I CP By increasing 126 again, this fluctuating K VCO This compensates for the following. As shown in equation (2), the loop bandwidth is I CP 126 and K VCO It is proportional to the product of K. VCO When I CP Increase 126, K VCO When I CP By lowering 126, V CTRL A more consistent bandwidth is achieved across a range of 128.

[0034] In other examples, different numbers of DAC116 may be useful. The third-order K shown in Figure 2. VCO Curves 202 and 204 (or similar curves) can be compensated with three DAC116s shown in Figure 4, using two boost DAC116s and one attenuating DAC116. In other examples, K VCO The curves may have different shapes, and different configurations of the DAC116 may be useful. In other examples, only one or two DAC116s may be used to provide compensation. VCO In another example involving a curve, three or more DAC116s may be useful. DAC116 also has a range of V CTRL It can be constructed for 128 values. In some examples, low or high V CTRL For 128 values, the attenuated DAC116 may be useful, while for the intermediate range V CTRL For 128 values, boosting the DAC116 may be useful. In other examples, the DAC116 and threshold V THRESH Any preferred configuration of 404 may be useful.

[0035] Turn the DAC116 on and off. CTRLThe value 128 is an example, and other voltage values ​​can be used in other examples. Also, in some examples, the range for turning on the DAC116 may overlap. For example, the V in a small window. CTRL In the case of 128, both DAC116A and DAC116B are V THRESH1 404A and V THRESH2 Based on the value of 404B, it may be on. V CTRL As 128 increases or decreases, either DAC116A or 116B changes V THRESH It can be turned off as determined by [the relevant factor].

[0036] The bias current source 114 is I ADJUST Combined with 408, I BIAS Current I generates 130 CONST 406 may include any suitable circuit elements for providing the threshold. The threshold generator 402 provides a voltage threshold V THRESH 404 may include any suitable circuit that provides a voltage to the DAC116 and determines when the DAC116 is turned on or off. In one example, the threshold generator 402 includes a resistor network having several taps, where a specific tap is selected for each DAC116 and a suitable voltage is applied to that DAC116. THRESH Provides a 404 error.

[0037] In one example, K (as shown in Figure 2) VCO The curve is determined through testing of a given PLL100. Then, circuit elements as shown in Figure 4 (e.g., DAC116 and threshold generator 402) are used to determine a given V CTRL Based on 128, the desired I CP It may be implemented to provide 126. The circuit elements may be trimmed or adjusted to provide appropriate voltage thresholds for turning the DAC116 on or off and for providing appropriate amounts of current from the DAC116 (e.g., currents 410A, 410B, and 410C). Any suitable circuit elements may be useful in other examples. The use of bias current source 114, DAC116, and threshold generator 402 is one example of implementing the system described herein.

[0038] Figure 5 shows I according to various examples in this specification. CP This is a block diagram of circuit 500 for varying 126. Circuit 500 includes the components of the PLL 100 described above with respect to Figure 1. Circuit 500 also includes several attenuating DACs 116 (represented by "A") and several boosting DACs 116 (represented by "B"). A and B may be any number in the examples herein. Circuit 500 is such that the DACs 116 vary V CTRL Current I in response to a value of 128 BIAS This shows how it is configured to boost or dampen 130.

[0039] In circuit 500, <0> from <b-1>The B-boost DAC116s are shown, numbered up to . Each boost DAC116 includes a typical current source 502 and a voltage comparator 504. DAC116 <b-1>The current source 502 for this purpose is current I BOOST,B-1 This generates a current of 410 in one example (as described above with respect to Figure 4). Current I BOOST,B-1 Based on the voltage comparator 504, I ADJUST Provided to 408. Voltage comparator 504 is V at the first input. CTRL Receive 128, and V as the second input. BOOST,B-1 Receives V BOOST,B-1 Regarding Figure 4, the threshold voltage V described above is as follows: THRESH It is 404. Control voltage V CTRL 128 and V BOOST,B-1 Based on the comparison with, DAC116 <b-1>It can be turned on or off. DAC116 <b-1>When it is turned on, current I BOOST,B-1 I ADJUST Provided to 408, I BIAS When combined with 130, I CP Increase 126. DAC116 <b-1>When it is turned off, no current is supplied by the boost DAC116. Any number of boost DAC116 may be present in the examples herein, V BOOST The value (for example, V THRESH ) is a fluctuating K VCO To compensate for this, appropriate V CTRL The boost DAC116 may be configured to turn on at a value of 128.

[0040] Similarly, <0> from <a-1>The numbered "A" attenuation DAC116s are shown. Each attenuation DAC116 includes a typical current source 508 and a voltage comparator 506. DAC116 <a-1>The current source 508 for current I ATTEN,A-1 This generates a current of 410 in one example (as described above with respect to Figure 4). Current I ATTEN,A-1 Based on the voltage comparator 506, I ADJUST It is pulled from 408. Voltage comparator 506 is V at the first input. CTRL Receive 128, and V as the second input. ATTEN,A-1 Receives V ATTEN,A-1 Regarding Figure 4, the threshold voltage V described above is as follows: THRESH It is 404. V CTRL 128 and V ATTEN,A-1 Based on the comparison with, DAC116 <a-1>It can be turned on or off. DAC116 <a-1>When it is turned on, current I ATTEN,A-1 is, I ADJUST Pulled from 408, I BIAS Reduced by 130 to I CP Decrease by 126. DAC116 <a-1>When it is turned off, no current is pulled by the attenuated DAC116. Any number of attenuated DAC116 may be present in the examples herein, V ATTEN The value (for example, V THRESH ) is a fluctuating K VCO To compensate for this, appropriate V CTRL The attenuating DAC116 may be configured to turn on with a value of 128.

[0041] The PLL shown in Figure 5 operates similarly to the PLL 100 described above. The charge pump 104 is I CP 126 is supplied to LPF106. LPF106 is V CTRL 128 is provided to VCO108, and VCO108 is V CTRL Output signal F based on the value 128 OUT Provides 132. V CTRL To provide stable bandwidth over a range of 128 values, CP 126 is a fluctuating K VCO To compensate for this, the DAC116 is used and modified as described herein.

[0042] Figure 6 is a block diagram of an FMCW radar system including an FMCW radar SOC according to various examples of this specification. The radar system includes a processing unit 650 and an FMCW radar SOC 600. In some examples, the processing unit 650 is integrated into the FMCW radar SOC 600. The radar SOC 600 may include a plurality of transmit channels 604 for transmitting FMCW signals and a plurality of receive channels 602 for receiving reflected transmit signals. The number of receive channels may also be greater than the number of transmit channels. For example, the radar SOC 600 may have two transmit channels and four receive channels. The transmit channels include appropriate transmitters and antennas. The receive channels include appropriate receivers and antennas. Each of the receiving channels 602 is identical and includes mixers 606, 608 for combining the transmitted signal with the received signal to generate a beat signal (alternatively referred to as a decharp signal, intermediate frequency (IF) signal, or raw radar signal), baseband bandpass filters 610, 612 for filtering the beat signal, variable gain amplifiers (VGAs) 614, 616 for amplifying the filtered beat signal, and analog-to-digital converters (ADCs) 618, 620 for converting the analog beat signal to a digital beat signal.

[0043] The receiving channel 602 is coupled to a digital front-end (DFE) 622, which performs decimation filtering on the digital beat signal to reduce the sampling rate and return the signal to baseband. The DFE 622 can also perform other operations on the digital beat signal, such as DC offset rejection. The DFE 622 is coupled to a high-speed interface component 624, which forwards the output of the DFE 622 to a processing unit 650.

[0044] The processing unit 650 may perform all or part of the method for operating the radar system in response to the received digital beat signal. The processing unit 650 may include any suitable processor or combination of processors 651. For example, the processing unit 650 may be a digital signal processor, a microcontroller unit (MCU), an FFT engine, a DSP+MCU processor, a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In some examples, the processing unit 650 and / or memory components 652 are integrated into the FMCW radar SOC 600.

[0045] The memory component 652 provides storage, for example, a non-temporary computer-readable medium, which may be used to store software instructions executed by the processing unit 650, such as any software instructions for implementing the operations described herein. The memory component 652 may include any suitable combination of read-only memory (ROM) and / or random-access memory (RAM), such as static RAM.

[0046] The control component 626 includes functionality for controlling the operation of the radar SOC 600. The control component 626 may include, for example, an MCU that runs software for controlling the operation of the radar SOC 600 between detection mode and operation mode.

[0047] The Serial Peripheral Interface (SPI) 628 provides an interface for communication with the processing unit 650. For example, the processing unit 650 can use the SPI 628 to send control information to the radar SOC 600, such as chirp timing and frequency, transmit antenna activation and timing between transmit antennas, output power level, and triggers for monitoring functions.

[0048] The programmable timing engine 642 receives chirp parameter values ​​from the control component 626 for a sequence of chirps in a radar frame, and includes functionality for generating chirp control signals that control the transmission and reception of chirps in a frame based on the parameter values, including timing between chirps generated by different transmitting antennas in classification mode and between chirps generated by the same transmitting antenna in detection mode.

[0049] The radio frequency synthesizer (RFSYNTH) 630 includes functionality for generating an FMCW signal for transmission based on a chirp control signal from the timing engine 642. In some examples, the RFSYNTH 630 includes a PLL with a VCO. In one example, the PLL is PLL 100 as described herein.

[0050] The clock multiplier 640 increases the frequency of the transmission signal from RFSYNTH630 to the frequencies of mixers 606 and 608. The cleanup PLL 634 increases the frequency of the signal of an external low-frequency reference clock (not shown) to the frequency of RFSYNTH630 and operates to filter out reference clock phase noise from the clock signal.

[0051] Figure 7 shows the fluctuating K according to various examples described herein. VCO This is a flowchart of Method 700 for adjusting the charge pump current in a PLL to compensate for [something]. The steps of Method 700 can be performed in any suitable order. The hardware components described above with respect to Figures 1, 3, 4, 5, and / or 6 can implement Method 700 in some examples. In some examples, any suitable hardware, software, or digital logic can implement Method 700.

[0052] Method 700 begins with 710, in which a current source provides a bias current to a charge pump in a phase-locked loop circuit. In one example, the bias current source 114 provides the bias current I as described above. BIAS Provides 130. Bias current I BIAS 130 is the charge pump current I provided by the charge pump. CP This can affect the magnitude of 126 and can be used to compensate for the nonlinear behavior of other parts of the phase-locked loop circuit.

[0053] Method 700 is when LPF106 controls the voltage V CTRL Continue with 720, providing 128 to VCO108 in the PLL. Control voltage V CTRL 128 is the charge pump current I from the charge pump. CP Provided in response to 126. As mentioned above, I CP 126 is modified via PFD102, bias current I BIAS Adjusted using 130, V CTRL Change 128. V CTRL 128 is the output signal F provided by VCO108. OUT Control 132.

[0054] Method 700 involves a control voltage V CTRL In response to the fact that is within the first range, a bias current I is supplied to the charge pump 104 using the first bias compensation circuit. BIAS Continue increasing 130 to 730. The first bias compensation circuit can be a boost DAC in this example. As mentioned above, K VCO When the value is low, the bias current I BIAS Increasing the value by 130 helps provide a more consistent loop bandwidth.

[0055] Method 700 involves a control voltage V CTRL In response to 128 being within the second range, a bias current I is supplied to the charge pump 104 using the second bias compensation circuit. BIAS The value continues at 740, which is reduced from 130. The second bias compensation circuit can be an attenuated DAC in this example. As mentioned above, K VCO When the value is high, the bias current I BIAS Reducing 130 helps to provide a more consistent bandwidth. In other examples, two or more DACs or bias compensation circuits control the voltage V CTRL The fluctuating K at both ends of 128 VCO It may be useful in compensating for that.

[0056] In the examples of this specification, the charge pump current I CP 126 is V CTRL Changed along with 128, V CTRL K caused by 128 changes VCO The fluctuations can be compensated for. The loop bandwidth of the PLL is K VCO and charge pump current I CP It is proportional to both 126. Therefore, V CTRL For the first range of 128 values, K VCO If the value is low, CP 126 is V CTRL It can be increased to provide consistent bandwidth over its first range of 128 values. CTRL For the second range of 128 values, K VCO If the value is high, CP 126 is V CTRL It may be reduced to provide a consistent bandwidth over its second range of 128 values. One or more current steering DACs 116, for example, I CP Used to change 126. Current steering DAC116 is used to change the K of a given VCO. VCO To compensate for fluctuations, it can be configured to provide an appropriate current. Using the examples herein, the entire bandwidth of the chirp can be generated by a single VCO, thereby reducing the area and power consumption for the radar system.

[0057] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, device A is connected to device B via intermediary component C, such that device B is controlled by device A via a control signal generated by device A, provided that intermediary component C does not alter the functional relationship between device A and device B.

[0058] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by the manufacturer to perform that function, and / or may be configurable (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the configuration and / or layout of hardware components, via the interconnection of the devices, or a combination thereof.

[0059] Circuits or devices described herein as including specific components may instead be coupled to those components to form the circuit element or device described. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be coupled to at least some of the passive elements and / or power sources during or after manufacturing, for example, by an end user and / or a third party, to form the structure described.

[0060] The circuits described herein are reconfigurable to include replaced components in order to provide functionality that is at least partially similar to the functionality available before the component replacement.

[0061] In this specification, unless otherwise stated, “about,” “approximately,” or “substantially” preceding a parameter means that the parameter is within + / - 10% of that parameter. Modifications may be made to the examples described, and other embodiments are possible within the scope of the claims of the present invention.

Claims

1. It is a system, A charge pump coupled to a phase frequency detector, A low-pass filter coupled to the charge pump, A voltage-controlled oscillator (VCO) coupled to the low-pass filter, A phase-locked loop comprising the charge pump configured to supply charge pump current to the low-pass filter, A current source configured to provide a bias current to the charge pump, A first bias compensation circuit configured to increase the bias current in response to the control voltage supplied to the VCO being within a first range, A second bias compensation circuit configured to reduce the bias current in response to the control voltage supplied to the VCO being within a second range, A system that includes this.

2. The system according to claim 1, The system further includes a third bias compensation circuit configured to increase the bias current in response to the control voltage supplied to the VCO being within a third range.

3. The system according to claim 1, wherein the first bias compensation circuit is a current-steering digital-to-analog converter (DAC).

4. The system according to claim 1, further comprising a voltage threshold generator circuit configured to provide the first range and the second range.

5. The system according to claim 1, wherein the phase-locked loop is configured to generate a chirp signal, and the frequency of the chirp signal changes in response to the control voltage.

6. The system according to claim 1, wherein the gain of the VCO changes with the control voltage.

7. The system according to claim 6, wherein the first bias compensation circuit increases the bias current to compensate for the gain of the VCO.

8. The system according to claim 6, wherein the second bias compensation circuit reduces the bias current in order to compensate the gain of the VCO.

9. A system according to claim 1, wherein increasing the bias current increases the charge pump current, and decreasing the bias current decreases the charge pump current.

10. A system according to claim 1, wherein increasing the bias current increases the bandwidth of the phase-locked loop, and decreasing the bias current decreases the bandwidth of the phase-locked loop.

11. It is a method, Using a current source, a bias current is supplied to the charge pump in the phase-locked loop, To provide a control voltage to the voltage-controlled oscillator (VCO) in the phase-locked loop that responds to the charge pump current from the charge pump, In response to the control voltage being within a first range, the bias current supplied to the charge pump is increased using a first bias compensation circuit. In response to the control voltage being within a second range, the bias current supplied to the charge pump is reduced using a second bias compensation circuit, Methods that include...

12. The method according to claim 11, A method further comprising increasing the bias current supplied to the charge pump using a third bias compensation circuit in response to the control voltage being within a third range.

13. The method according to claim 11, wherein the first bias compensation circuit is a current-steering digital-to-analog converter (DAC).

14. The method according to claim 11, A method further comprising generating a chirp signal using the phase-locked loop, wherein the frequency of the chirp signal changes in response to the control voltage.

15. A method according to claim 11, wherein increasing the bias current increases the bandwidth of the phase-locked loop.

16. A method according to claim 11, wherein reducing the bias current reduces the bandwidth of the phase-locked loop.

17. It is a system, A charge pump coupled to a phase frequency detector, A low-pass filter coupled to the charge pump, A voltage-controlled oscillator (VCO) coupled to the low-pass filter, A phase-locked loop comprising a charge pump configured to supply a charge pump current to a low-pass filter, the low-pass filter configured to supply a control voltage to a VCO, and the gain of the VCO changing with the control voltage, A current source configured to provide a bias current to the charge pump, wherein the charge pump current changes together with the bias current. A voltage threshold generator configured to provide a first voltage range and a second voltage range, A first bias compensation circuit configured to increase the bias current in response to the control voltage supplied to the VCO being within the first voltage range, A second bias compensation circuit configured to reduce the bias current in response to the control voltage supplied to the VCO being within the second voltage range, A system that includes this.

18. The system according to claim 17, wherein increasing the bias current increases the bandwidth of the phase-locked loop.

19. The system according to claim 17, wherein reducing the bias current reduces the bandwidth of the phase-locked loop.

20. The system according to claim 17, The system further includes a third bias compensation circuit configured to increase the bias current in response to the control voltage supplied to the VCO being within a third voltage range.

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