Selective source bias in memory peripherals

Abstract

Techniques and implementations for selective source biasing for memory peripherals. Selective source biasing can be configured to minimize leakage, which can lead to savings. Selective source biasing can be configured to bias off-transistors.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 493,304, entitled "SELECTIVE SOURCE BIAS IN MEMORY PERIPHERAL", filed on March 30, 2023, which is hereby incorporated by reference in its entirety for all purposes. Information

[0002] Unless otherwise specified herein, the techniques described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section.

[0003] Memory arrays can have applicability in many digital technologies. In digital technologies, various types of memory can be utilized. Some memory types may suffer from leakage (leakage current). For example, but not limited to, in some memories such as static random - access memory (SRAM), there may be some leakage around the SRAM memory. For example, in the standby state, the memory is not in operation and / or performs relatively minimal operations, and the memory is ready for the next access but may not be accessed for a period of time. The external management of the memory can be performed by such external management techniques, such as an external controller and / or some other form of external environment from the memory, but is not limited thereto.

[0004] Approaches that utilize external management to facilitate leakage current reduction require external management of the memory mode at each point in time, which can lead to complexity. For example, if external management is used to transition to or exit a hold state (i.e., completely shut down peripherals), signals may be sent and received to facilitate some kind of communication handshake acknowledgment indicating that power-on / re-on is complete, which can complicate the process. Furthermore, returning from a hold state may require a large number of clock cycles, potentially incurring significant costs for the system.

[0005] All subjects discussed in this section of this book are not necessarily prior art, nor should they be presumed to be prior art simply because they are described in this section. Furthermore, references to prior art in this description should not be interpreted as an acknowledgment or any suggestion that such prior art constitutes common general knowledge in any country or in any art. In this regard, any recognition of a problem in the prior art discussed in this section, or related to such subject, should not be treated as prior art unless explicitly stated to be prior art. Rather, any discussion of a subject in this section should be treated as part of an approach adopted by the inventor to a particular problem. This approach itself may also be inventive. Therefore, the above summary is for illustrative purposes only and is not limiting in any way. In addition to the above exemplary aspects, embodiments, and features, further aspects, embodiments, and features will become apparent by referring to the drawings and the detailed description below. [Overview of the Initiative]

[0006] This specification describes various exemplary devices, systems, and methods for selective source biasing for memory peripherals. Some exemplary systems may include one or more inverter circuits. An exemplary system may include biasing one or more transistors included in one or more inverter circuits. Systems and methods may include knowing the logic state of substantially most of the nets in an inverter circuit.

[0007] As a result, according to various embodiments, it becomes easier to minimize leaks, which leads to savings.

[0008] The above-mentioned overview is illustrative and not intended to be limiting. Further embodiments, features, and characteristics beyond those described above will become apparent by reference to the drawings and the following detailed description. [Brief explanation of the drawing]

[0009] The subject matter is specifically pointed out and explicitly claimed in the conclusion section of this specification. The aforementioned and other features of this disclosure will be more fully apparent from the following description and the appended claims, together with the accompanying drawings. With understanding that these drawings illustrate only some embodiments of this disclosure and should therefore not be considered limiting its scope, this disclosure is described with additional specificities and details through the use of the accompanying drawings.

[0010] [Figure 1] This section outlines the bit-cell array source bias.

[0011] [Figure 2A] This specification demonstrates several principles of SSBs, as described herein, and their applicability to memory peripherals, through various embodiments. [Figure 2B] This specification demonstrates several principles of SSBs, as described herein, and their applicability to memory peripherals, through various embodiments.

[0012] [Figure 3] Shows a schematic diagram of a circuit diagram according to one or more embodiments.

[0013] [Figure 4] Shows the types of power supply and / or ground switch circuits that can be utilized according to various embodiments.

[0014] [Figure 5] Shows the types of power supply and / or ground switch circuits.

[0015] [Figure 6] Shows an exemplary computer device.

[0016] [Figure 7A] Shows the top levels of LDP and LCTL, including an example of SSB implementation in LCTL segment control according to various embodiments. [Figure 7B] Shows the top levels of LDP and LCTL, including an example of SSB implementation in LCTL segment control according to various embodiments.

[0017] [Figure 8A] Shows the top levels of LDP and LCTL, including an example of SSB implementation in an LDP cell according to various embodiments. [Figure 8B] Shows the top levels of LDP and LCTL, including an example of SSB implementation in an LDP cell according to various embodiments.

[0018] [Figure 9A] Shows the SSB implementation in an LDP cell-bit line circuit according to various embodiments. [Figure 9B] Shows the SSB implementation in an LDP cell-bit line circuit according to various embodiments. [Figure 9C] Shows the SSB implementation in an LDP cell-bit line circuit according to various embodiments.

[0019] [Figure 10A] Illustrates SSB implementations in an LDP cell-sense amplifier according to various embodiments. [Figure 10B] Illustrates SSB implementations in an LDP cell-sense amplifier according to various embodiments.

[0020] [Figure 11A] Illustrates an exception handling (3)-type B switch that is activated according to a logical state according to various embodiments. [Figure 11B] Illustrates an exception handling (3)-type B switch that is activated according to a logical state according to various embodiments.

[0021] [Figure 12] Illustrates some waveform signals received during the utilization of an SSB implementation according to various embodiments.

[0022] [Figure 13] Illustrates some examples of logical conditions for entering a selective SB according to various embodiments.

[0023] [Figure 14] Illustrates some examples of benchmark results.

MODE FOR CARRYING OUT THE INVENTION

[0024] The following description sets forth various examples along with specific details in order to provide a complete understanding of the claimed subject matter. However, after a review and understanding of the present disclosure, it will be understood by those skilled in the art that the claimed subject matter may be practiced without some or more of the specific details disclosed herein. Further, in some instances, well-known methods, procedures, systems, components, and / or circuits have not been described in detail so as to avoid unnecessarily obscuring the claimed subject matter.

[0025] The following detailed description refers to the accompanying drawings which form part of this specification. In the drawings, unless the context should be interpreted otherwise, similar symbols typically identify similar components. The exemplary embodiments described in the detailed description, drawings, and claims are not intended to limit. Other embodiments may be used and other modifications may be made without departing from the spirit or scope of the subject matter presented herein. It will be readily apparent that the aspects of this disclosure generally described herein and shown in the drawings can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are expressly intended and form part of this disclosure.

[0026] This disclosure covers, in particular, but not limited to, methods, apparatus, and circuit systems for enabling selective source bias (SSB) design / techniques (hereinafter, SSB) to enable leakage reduction around SRAM during various states, such as standby states. In some embodiments, the SSB may be automatically activated by a chip selection input (CS_N), which may include normal setup and hold. The CS_N may be used to avoid the need to activate and wait for more than one cycle, then sample the input, or detect memory shortage indicating that power is at nominal value. In systems with multiple SRAM chips, or systems in which SRAM may be integrated with other devices on the bus, the chip selection (CS) line may determine when a particular SRAM chip is active and may interact with the rest of the system and / or some alternative methods. In some embodiments, the SSB may be activated with array source bias to facilitate leakage reduction. In some embodiments, selected transistors may be biased. In some embodiments, power levels and ground levels may be biased, but signals may not. In some embodiments, the gates of one or more biased transistors may be kept "completely off," which may further improve leakage reduction.

[0027] It should be understood that standby can include a state in which memory is inactive and / or substantially inactive (i.e., ready for subsequent access but not accessed for a period of time).

[0028] Prior to referring to the drawings, a brief introduction to some of the components included in the drawings may be provided. For example, Figures 2B, 6B, 7B, 8C, 9B, and 10B may include floorplan descriptions of memory, which may be used to help facilitate the implementation of at least some of the various embodiments disclosed herein. These figures, including the floorplan, may include, but are not limited to, various components that may be associated with / included in the SRAM, such as sense amplifiers and / or word line drivers. Examples of components / units include, but are not limited to, the following: • GCTL - A global control unit that may include control for clock control, address latching, and / or data input / output cells. • I / O - These may be data input / output drivers. • LDP - Local Data Path, which may be a component that includes a sense amplifier, a write driver, and / or a read and write multiplexer (also known as a mux). • WL - A word line driver that may include some address decoding logic. A local control unit that can be configured to manage word line selection and control for components / units within LCTL-LDP. • Array - may also be a bit cell array.

[0029] Referring to Figure 1, which shows an overview of the bit cell array source bias, in Figure 1, the SRAM bit cell (hereinafter referred to as bit cell) 100 may include a pair of complementary bit lines, namely a first bit line 102A and a second bit line 102B. The bit cell 100 may include a first inverter 104A, a second inverter 104B, a first data node 106A, and a second data node 106B. In Figure 1, the first inverter 104A may include a first PMOS transistor 108A, the first PMOS transistor 108A may have its source and drain terminals coupled between VDD and the first data node 106A, and its gate is coupled to the second data node 106B. The data nodes 106A and 106B may operate as two complementary storage nodes within the bit cell 100. The first inverter 104A may include a first NMOS transistor 110A, which may have a drain coupled to a first data node 106A and a source coupled to a bit cell ground 112. As shown in Figure 1, the gate of the first NMOS transistor 110A may be coupled to a second data node 106B. The second inverter 104B may include a second PMOS transistor 108B, which may have a source terminal and a drain terminal coupled between VDD and the second data node 106B, and its gate is coupled to the first data node 106A. Furthermore, the second inverter 104B may include a second NMOS transistor 110B, whose drain may be coupled to the second data node 106B, and whose source may be coupled to a bit cell ground 112. As shown in the figure, the second NMOS transistor 110B may have its gate coupled to the first data node 106A. Furthermore, the bit cell 100 may include a first NMOS access device 114A which may be disposed between the first bit line 102A and the first data node 106A, and a second NMOS access device 114B which may be disposed between the second bit line 102B and the second data node 106B.

[0030] It should be understood that Figure 1 may be shown to facilitate understanding of the claimed subject matter. Bit cell 100 may help to provide some context regarding how the claimed subject matter may be utilized to reduce leakage according to one or more embodiments. In Figure 1, according to one or more embodiments, the power level and ground level may be biased. Furthermore, as will be described later, in Figure 1, according to one or more embodiments, all transistors may be in a “completely off” state, and the gates of biased transistors may remain “completely off.”

[0031] In Figure 1, the 6-transistor bit cell 100 may include a bit cell ground 112, and the bit cell ground 102 may be coupled to the bit cell 100 in a conventional manner to facilitate source biasing. As shown in the figure, the bit cell ground 112 may consist of two devices, where one of the transistors of the ground 112 may be configured as a switch and the other as a diode.

[0032] As shown in Figure 1, bit cell 100 may include an internal net state that is 1 at the first data node 106A, which may correspond to 0 on the other side. Thus, three of the transistors may be in an off state (i.e., the first NMOS transistor 110A, the second PMOS transistor 108A, and the second NMOS access device 114B). Focusing on the second PMOS transistor 108B, the second PMOS transistor 108B (i.e., pull-up PMOS) may be receiving a reduced VDS from the source bias. As shown in Graph 120, the reason for the reduced VDS of the second PMOS transistor 108B may be that the bias can raise the bit cell ground by about 200 mV, which can be lower or higher depending on VDD, transistor type, etc. Thus, the second PMOS transistor 108B may only receive a reduced VDS. As a result, leakage reduction may be facilitated according to one or more embodiments.

[0033] On the other side of bit cell 100, the VDS of the first NMOS transistor 110A (i.e., pull-down NMOS) may decrease. However, in addition to the decreased VDS, the first NMOS transistor 110A may be affected by the bulk / body effect. The bulk / body effect can occur when the source voltage and the body (i.e., bulk) are different (for example, the source voltage is higher than the body), which can increase VD. Here again, according to one or more embodiments, leakage reduction can be facilitated.

[0034] In bit cell 100 in Figure 1, the second NMOS access device 114B (i.e., the pass gate) may be in an off state, which may be substantially the same state as the first access device 114A. As shown in Figure 1, the second NMOS access device 114B may experience bulk / body effects, reduced VDS, and negative VGS. The negative VGS may be a result of the word line coupled to the second NMOS access device 114B being pulled down to zero, and the source may be slightly higher (e.g., about 200 mV). Thus, of the three off transistors, namely the first NMOS transistor 110A, the second PMOS transistor 108A, and the second NMOS access device 114B, any one of them may experience all three effects.

[0035] As described above, the bit cell shown and described in Figure 1 may facilitate a further understanding of this disclosure by providing context and comparison. Around the SRAM, according to one or more embodiments, most and / or substantially all transistors may experience all of the aforementioned effects. As a result, leakage around the SRAM can be reduced.

[0036] In short, SSB designs such as those disclosed herein, which can be implemented around memory, may, according to one or more embodiments, have no power-on or power-off processes involved, thus facilitating a fast approach to significantly reduce standby current. In one example, substantially no extra cycles are required, and dedicated inputs and / or chip selection may be included, as described above, to enter or exit the mode. In another example, the associated control inputs may have a reasonable setup time. In yet another example, substantially no inrush glitch (i.e., the phenomenon experienced when powering up peripherals and / or the entire SRAM) may occur. In yet another example, the energy cost of entering or exiting the SSB may be less than the energy cost of access. In yet another example, logic signals may maintain their voltages (i.e., bias levels are not propagated to logic signals). Furthermore, as described above, the current of “off” transistors (PMOS and NMOS) may decrease, such as |VT| increasing and |VDS| decreasing due to bulk / body effects, resulting in negative VGS for NMOS and positive VGS for PMOS.

[0037] Figures 2A and 2B illustrate several principles of SSB as described herein and their applicability to memory peripherals in various embodiments, such as static random access memory (SRAM) peripheral functions and SSB implementations.

[0038] Figure 2A shows a simplified diagram of a miniature SRAM floorplan (hereinafter referred to as floorplan 200), which may be the highest level of memory. Floorplan 200 may include pairs of local data paths (LDPs), pairs of word line drivers (WLs), local control (LCTLs), global control (GCTLs), pairs of input / output (I / O) and multiple bit cell arrays (arrays).

[0039] Figure 2B shows a simplified schematic diagram of a gate clock. In Figure 2B, the gate clock schematic diagram 202 may include control logic communicatively coupled to a logic gate, direct signals (e.g., a clock input) communicatively coupled to the logic gate, and a gate clock output from the logic gate. A reference to the logic state of the gate clock may be shown in Figure 2B.

[0040] In Figure 2A, the LDP may include, but is not limited to, various components such as a sense amplifier, a write driver, and a multiplexer (mux). The inputs to the LDP may be sense-enabled and write-enabled, and a considerable number of nets, including bit lines, may be pre-charged to facilitate known states. Some of the other components may be controlled by gate clocks (see, e.g., Figure 2B), such as sense-enabled and write-enabled. Thus, the logic within the LDP may be controlled by gate clock inputs, such as sense-enabled and / or write-enabled, which may assist the inputs, and inactive gate clocks may help to check the state of nets in subsequent logic (i.e., driven by gate clock inputs).

[0041] The LCTL may include control for the word line driver and may be configured to be the starting point for sense enable and write enable. The LCTL may include decoding logic, which may be modified to bring substantially all of its outputs to known states when SSB mode may be active. Furthermore, the LCTL may include a gate clock circuit, in standby mode (i.e., SSB mode), where the gate clock is inactive and can result in known logic states.

[0042] Next, referring to GCTL, a GCTL can include addresses and various input latches, and the addresses and input latches (i.e., nets) can be forced into known states by reasonable resource consumption. For example, a net can be forced into a known logical state by propagating a normal logical state in response to a received signal when a signal is received. The received signal can be, but is not limited to, a dedicated input (e.g., CLK) or a chip select (e.g., CS_N), depending on the various embodiments. However, since the forced situation does not occur frequently, forcing the logical state of a net is only one approach, at least partially based on design requirements. Furthermore, a GCTL can include partial address decoding, and if the logical state of the address latches is known, the logical state of the decoding logic can also be known. As mentioned above, a GCTL can include clock generation circuits, and their logical states can be known when the main inputs (e.g., dedicated input / CLK and chip select / CS_N) are in the off state. It will be understood that knowledge of the logical state of a net helps to facilitate the subject matter being claimed.

[0043] The gate clock WL can operate like a gate clock (i.e., when the input is known, the logical state of the net is known). For example, when SSB mode is active, WL may be inactive.

[0044] In I / O, due to its nature, input and / or output data may be unknown, and therefore exceptions that need to be managed may exist. Since modifying input and / or output is undesirable, the logical state of I / O is not enforced. For example, it is undesirable to change a recently read value from memory. Exception management will be discussed later.

[0045] Figure 3 shows schematic diagrams of circuits according to one or more embodiments. In Figure 3, circuit 300 may include a first inverter circuit 302 that is communicatively coupled to a second inverter circuit 304. As shown, the first inverter circuit 302 may be communicatively coupled to a source bias (SB) VDD 306, and the second inverter circuit 302 may be communicatively coupled to an SB ground (SB GND) 308.

[0046] In Figure 3, the first inverter circuit 302 may include a first PMOS transistor 310 and a first NMOS transistor 312. The second inverter circuit 304 may include a second PMOS transistor 314 and a second NMOS transistor 316. SB VDD 306 may include two PMOS transistors, namely a first PMOS transistor configured as a voltage source switch 318 and a second PMOS transistor configured as a voltage source diode 320. Furthermore, SB GND 308 may include two NMOS transistors, namely a first NMOS transistor configured as a ground switch 322 and a second NMOS transistor configured as a ground diode 324. As described, the voltage source diode 320 and the ground diode 324 may or may not be required, as indicated by "X", depending on the various embodiments. As shown in the figure, the source of the first PMOS transistor 310 may be communicatively coupled to SB VDD 306, and the drain of the second NMOS transistor 316 may be communicatively coupled to SB GND 308.

[0047] As shown in Figure 3, the logic state of virtually all nets can be determined. In the example shown, in standby mode (SSB mode), the input to the first inverter circuit 302 may be in a logic state of 1, which may result in a logic state of 0 at the input to the second inverter 304. The first PMOS transistor 310 may be in an off state, communicatively coupled to the switch, and may deactivate the switch, receiving virtually all of the available effects from the bias. The logic state may be 1, which may be higher than the power supply, which may be analogous to a negative VGS.

[0048] In Figure 3, BS GND 308 can be biased up (e.g., to about 200 mV), and the output of the first inverter circuit 302 can be true 0 (i.e., the SB voltage cannot be propagated). The second NMOS transistor 316 can be in the off state and can be communicatively coupled to SB GND 308. Thus, the biased power supply and ground can be communicatively coupled to transistors that can be in the off state (e.g., the first PMOS transistor 310 and the second NMOS transistor 316), which can have the following results: the biased level cannot be propagated to the logic signal, the signal in the logic state of 0 can remain at 0 V and cannot be raised to about 200 mV, the signal in the logic state of 1 can remain at the VDD level and cannot drop to (VDD-200 mV), and the unbiased transistor can remain at its normal voltage and, since it is not biased, can easily recover quickly without significant energy cost. As a result, the current in the off-state transistors (e.g., the first PMOS transistor 310 and the second NMOS transistor 316) can be reduced in at least three ways: by the bulk / body effect that promotes an increase in |VT|, by a reduced |VDS|, and by a negative VGS for the NMOS transistor and a positive VGS for the PMOS transistors (e.g., the first PMOS transistor 310 and the second NMOS transistor 316). Thus, the three modes (i.e., conditions) that can occur in each of the biased transistors can help facilitate minimizing leakage according to various embodiments, which can lead to savings.

[0049] To facilitate exiting SB mode, it may be necessary to restore the voltage. However, restoring the voltage may not involve a full rise of the power supply or a pull-down or full swing to ground, but rather involve returning the circuit from the bias level to 0 or the full VDD level, and the process may not be very slow. Thus, one solution approach may involve utilizing setup time before the clock without requiring a handshake, which can be used to indicate that power-up is complete, etc.

[0050] Before moving on to the next figure, in Figure 3, graph 326 may show the bias level as illustrated.

[0051] Figure 4 shows types of power supply and / or ground switch circuits that may be used according to various embodiments. As shown in Figure 4, some types of switches may include a main VDD switch (Type A) 402 and a main GND switch (Type A) 404. The main VDD switch 402 and the main GND switch 404 may each have global control, as described above.

[0052] Some alternative types may include a local VDD switch (Type B) 406 and a local GND switch (Type B) 408, which may be used to address exceptions, where the exception may include a part of the logic whose logic state is unknown when SSB mode is active. In some examples, one signal may facilitate the determination of substantially all of the logic states of other signals in the given part of the logic. In such cases, it may be possible to utilize local signals for control, which may include determining which of the switches may be active and which may not be active. It should be noted that the local enable signal may be substantially the same for both local switches 406 and 408, and therefore only one may be disconnected. Further details may be described and shown later (e.g., Figures 7A and 7B).

[0053] Figure 5 shows the types of power and / or ground switch circuits. As shown in Figure 5, the use of type B switches (406 and 408 shown in Figure 4) can be shown. In Figure 5, the circuit 500 may include a first inverter 502, a second inverter 504, a third inverter 506, and a fourth inverter 508, which are communicatively coupled as shown. Furthermore, the first inverter 502 and the second inverter 504 may be communicatively coupled to a first type B VDD 510 and a first type B GND 512. The third inverter 506 and the fourth inverter 508 may be communicatively coupled to a third type B VDD 514 and a fourth type B GND 516.

[0054] In Figure 5, when the logic states of the inputs are unknown, one net state may cause one or more other logic states to be determined in a one-to-one manner. Therefore, local VDD switches (Type B) and local GND switches (Type B) may be used to reduce leakage in such cases. For example, in some embodiments, four inverters 502, 504, 506, and 508 arranged in a row may be communicatively coupled as shown. During normal operation, substantially all power supplies may be communicatively coupled by global control signals EN_VDD_N and EN_VDD (not shown). However, in SSB mode, the global control signal may disconnect a Type B switch, as shown in the replication circuit 518 which has an input logic state of 0. Parallel switches may also be controlled by local control inputs, which generally open one of VDD or GND and close the other.

[0055] In some embodiments, the claimed subject matter may be described using a simulation model. For example, a memory model may be used for development and to determine benchmark results. This simulation model can be developed in a manner similar to that used for the development of general-purpose SPRAM in the relevant technology.

[0056] As a result, according to various embodiments, it becomes easier to minimize leaks, which leads to savings.

[0057] Figure 6 shows an exemplary computer device. Figure 6 is a block diagram of an exemplary computing device 600 that can be embodied by those skilled in the art, configured according to at least some embodiments of the present disclosure. In one exemplary configuration, the computing device 600 may include one or more processors 610 and system memory 620. A memory bus 630 may be used for communication between the processors 610 and the system memory 620.

[0058] Depending on the desired configuration, the processor 610 may include, but is not limited to, any type of microprocessor (μP), microcontroller (μC), digital signal processor (DSP), or any combination thereof. The processor 610 may include one or more levels of caching, such as a level 1 cache 611 and a level 2 cache 612, a processor core 613, and registers 614. The processor core 613 may include an arithmetic logic unit (ALU), a floating-point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. 615 may also be used with the processor 610, or in some implementations, the memory controller 615 may be an internal part of the processor 610.

[0059] Depending on the desired configuration, the system memory 620 may be of any type, including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory), or any combination thereof. The system memory 620 may include an operating system 621, one or more applications 622, and program data 624. The application 622 may include a selective source bias management algorithm 623 configured to perform the functions described herein, including the functional blocks and / or actions described. The program data 624 may include wake-up bias data 625 for use with the process selective source bias management algorithm 623, among other information described herein. In some exemplary embodiments, the application 622 may be configured to operate with the program data 624 on the operating system 621 so that an implementation of wake-up circuit management as part of an integrated circuit can be provided as described herein. For example, the apparatus described herein may comprise all or part of a computing device 600 and be capable of executing all or part of the application 622 to facilitate process corner management in an integrated circuit as described herein. This described basic configuration is shown in Figure 6 by its components within the dashed line 601.

[0060] The computing device 600 may have additional features or functionalities and additional interfaces to facilitate communication between the basic configuration 601 and any necessary devices and interfaces. For example, a bus / interface controller 640 may be used to facilitate communication between the basic configuration 601 and one or more data storage devices 650 via a storage interface bus 641. The data storage device 650 may be a removable storage device 651, a non-removable storage device 652, or a combination thereof. Examples of removable and non-removable storage devices include, to name a few, magnetic disk devices such as flexible disk drives and hard disk drives (HDDs), optical disk drives such as compact disk (CD) drives or digital multipurpose disk (DVD) drives, solid-state drives (SSDs), and tape drives. Exemplary computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any way or technique for storing information such as computer-readable instructions, data structures, program modules, or other data.

[0061] System memory 620, removable storage device 651, and non-removable storage device 652 are all examples of computer storage media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or any other media that may be used to store desired information and may be accessed by computing device 600. Any such computer storage media may be part of device 600.

[0062] The computing device 600 may also include an interface bus 642 for facilitating communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to the basic configuration 701 via a bus / interface controller 640. An exemplary output interface 660 may include a graphics processing unit 661 and an audio processing unit 662, which may be configured to communicate with various external devices such as displays or speakers via one or more A / V ports 663. An exemplary peripheral interface 660 may include a serial interface controller 671 or a parallel interface controller 672, which may be configured to communicate with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices, etc.) or other peripheral devices (e.g., printers, scanners, etc.) via one or more I / O ports 673. An exemplary communication interface 680 may include a network controller 681, which may be configured to facilitate communication with one or more other computing devices 690 via network communication via one or more communication ports 682. A communication connection is an example of a communication medium. A communication medium may typically be embodied by computer-readable instructions, data structures, program modules, or other data within a modulated data signal such as a carrier wave or other transport mechanism, and may include any information distribution medium. A “modulated data signal” can be a signal having one or more of its characteristics set or modified in a manner that encodes the information within the signal. Examples, but not limited to, communication mediums may include wired mediums such as wired networks or direct wired connections, as well as wireless mediums such as acoustic, radio frequency (RF), infrared (IR), and other wireless media. As used herein, the term computer-readable medium may include both storage mediums and communication mediums.

[0063] The computing device 600 may be implemented as part of a small-form-factor portable (or mobile) electronic device, such as a mobile phone, personal digital assistant (PDA), personal media player device, wireless web viewing device, personal headset device, application-specific device, or hybrid device including any of the above functions. The computing device 600 may also be implemented as a personal computer, including both laptop and non-laptop computer configurations. Furthermore, the computing device 600 may be implemented as part of a wireless base station or other wireless system or device.

[0064] After reviewing this disclosure, it should be understood that the claimed subject matter may include a wide variety of integrated circuit devices, as intended within the scope and intent of this disclosure. Therefore, the claimed subject matter is not limited in these respects.

[0065] Some parts of the detailed description above are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored in computing system memory, such as computer memory. These descriptions or representations of algorithms are examples of techniques used by those skilled in the data processing technique to communicate the nature of their work to others skilled in the technique. Here, an algorithm is also generally considered to be a self-consistent set of operations or similar processes that produce a desired result. In this context, operations or processes involve the physical manipulation of physical quantities. Typically, but not always, such quantities may take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, or otherwise manipulated. For reasons of common use, it is sometimes convenient to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, digits, etc. However, it should be understood that all of these terms and similar terms should be associated with the appropriate physical quantities and are merely convenient labels. Unless otherwise specified, as will be apparent from the following description, throughout this specification, any use of terms such as “process,” “calculate,” “calculate,” and “determine” is understood to refer to an action or process of a computing device that manipulates or transforms data that is represented as a physical electronic or magnetic quantity in the memory, registers, or other information storage devices, transmitting devices, or display devices of a computing device.

[0066] The claimed subject matter is not limited to any specific implementation described herein. For example, some implementations may be in hardware, such as those employed to operate on a device or combination of devices, while others may be in software and / or firmware. Similarly, the claimed subject matter is not limited in this respect, but some implementations may include one or more articles such as signal-carrying media, storage media, and / or memory media. For example, such storage media, such as CD-ROMs, computer disks, and flash memory, may have instructions stored thereon that, when executed by a computing device, such as a computing system, computing platform, or other system, result in the execution of a processor according to the claimed subject matter, such as one of the aforementioned implementations. One possibility is that a computing device includes one or more processing units or processors, one or more input / output devices such as a display, keyboard, and / or mouse, and one or more memories such as static random access memory, dynamic random access memory (DRAM), flash memory, and / or hard drives.

[0067] There is little distinction between hardware and software implementations of a system configuration, and the use of hardware or software is generally (but not always) a design choice representing a cost-effectiveness trade-off, in that in certain contexts the choice between hardware and software can be important. There are various means (e.g., hardware, software, and / or firmware) to which the processes and / or systems and / or other technologies described herein may be affected, and the preferred means will vary depending on the context in which the processes and / or systems and / or other technologies are deployed. For example, if the implementer determines that speed and accuracy are paramount, the implementer may choose primarily hardware and / or firmware means; if flexibility is paramount, the implementer may choose primarily software implementation; or, even more alternatively, the implementer may choose several combinations of hardware, software, and / or firmware.

[0068] The detailed description above illustrates various embodiments of devices and / or processes through the use of block diagrams, flowcharts, and / or examples. Those skilled in the art will understand that, insofar as such block diagrams, flowcharts, and / or examples include one or more functions and / or operations, each function and / or operation within such block diagrams, flowcharts, or examples can be implemented individually and / or collectively by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, some parts of the subject matter described herein may be implemented via application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein can be equivalently implemented in an integrated circuit, in whole or in part, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or substantially any combination thereof, and that designing circuits and / or writing code for software and / or firmware is well within the scope of the art of those skilled in the art in light of this disclosure. Furthermore, those skilled in the art will understand that mechanisms of the subject matter described herein can be distributed as products in various forms, and that exemplary embodiments of the subject matter described herein are applicable regardless of the particular type of signal-carrying medium used to actually carry out the distribution. Examples of signal-carrying media include, but are not limited to, recordable media such as flexible disks, hard disk drives (HDDs), compact discs (CDs), digital multipurpose discs (DVDs), digital tapes, and computer memory, as well as transmission media such as digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0069] Those skilled in the art will recognize that it is common in the art to describe devices and / or processes in the manner described herein and then, using engineering practices, to integrate such described devices and / or processes into data processing systems. That is, at least some of the devices and / or processes described herein can be integrated into semiconductor integrated circuit systems through a reasonable amount of experimentation. Those skilled in the art will recognize that a typical semiconductor integrated circuit system may generally include one or more of the following: a system unit housing, video display devices, memory such as volatile and non-volatile memory, processors such as microprocessors and digital signal processors, computing entities such as operating systems, drivers, graphical user interfaces, and application programs, one or more interaction devices such as touchpads or screens, and / or control systems including feedback loops and control motors (e.g., feedback for sensing position and / or velocity, control motors for moving and / or adjusting components and / or quantities). A typical semiconductor integrated circuit system may be implemented using any suitable commercially available components, such as those typically found in computing / communication and / or network computing / communication systems.

[0070] The subjects described herein may include different components contained within or connected to other components. It should be understood that such illustrated architectures are merely illustrative and that many other architectures can be implemented to achieve the same function. Conceptually, any arrangement of components to achieve the same function is effectively “associated” in such a way that the desired function is achieved. Thus, any two components in this specification combined to achieve a particular function, whether in architecture or as intermediate components, can be considered “associated” with each other in such a way that the desired function is achieved. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” with each other to achieve the desired function, and any two components that can be associated in such a way can also be considered “operably coupled” with each other to achieve the desired function. Specific examples of operably coupled components include, but are not limited to, physically matable and / or physically interacting components, and / or wirelessly interactable and / or wirelessly interacting components, and / or logically interacting and / or logically interactable components.

[0071] With regard to the use of substantially any plural and / or singular terms herein, those skilled in the art can convert from plural to singular and / or singular to plural as appropriate to the context and / or use. Various singular / plural substitutions may be explicitly stated herein for clarity.

[0072] In general, it will be understood by those skilled in the art that the terms used herein, particularly in the appended claims (e.g., the body of the appended claims), are generally intended as “open” terms (for example, the term “includes” should be interpreted as “includes but not limited to,” the term “has” should be interpreted as “has at least,” and the term “includes” should be interpreted as “includes but not limited to,” etc.). It will further be understood by those skilled in the art that if a particular number of claims to be introduced is intended, such intent is explicitly stated in the claims, and if such statement is not present, such intent does not exist. For example, to aid understanding, the following appended claims may include the use of the introductory phrases “at least one” and “one or more” to introduce the claims. However, the use of such phrases should not be interpreted as implying that the introduction of a claim description by the indefinite article "a" or "an" limits any particular claim containing such introduced claim description to an invention containing only one such description (for example, "a" and / or "an" should typically be interpreted as meaning "at least one" or "one or more"), even if the same claim contains the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an"), and the same applies to the use of definite articles used to introduce claim descriptions. Furthermore, even if a specific number of descriptions in an introduced claim is explicitly stated, a person skilled in the art will recognize that such a description should typically be interpreted as meaning at least the number described (for example, the mere description of "two descriptions" without other modifiers typically means at least two descriptions or two or more descriptions). Furthermore, when conventions similar to "at least one of A, B, and C, etc." are used, such configurations are generally intended to be understood by those skilled in the art (for example, "a system having at least one of A, B, and C" includes, but is not limited to, systems having only A, only B, only C, A and B together, A and C together, B and C together, and / or systems having A, B and C together, etc.).Where conventions similar to “at least one of A, B, or C” are used, such configurations are generally intended in a sense that a person skilled in the art would understand the convention to mean (for example, “a system having at least one of A, B, or C” includes, but is not limited to, a system having only A, only B, only C, A and B together, A and C together, B and C together, and / or a system having A, B, and C together). Furthermore, a person skilled in the art would understand that substantially any disjunct word and / or disjunct phrase presenting two or more alternative terms should be understood to intend the possibility of including one of the terms, either of the terms, or both of the terms in the description, claims, or drawings. For example, the phrase “A or B” would be understood to include the possibilities of “A” or “B” or “A and B”.

[0073] In this specification, references to “one implementation,” “several implementations,” or “other implementations” may mean that a particular feature, structure, or characteristic described in relation to one or more implementations may be present in at least some implementations, but not necessarily in all of them. Various occurrences of “one embodiment,” “one embodiment,” or “several embodiments” in the foregoing description do not necessarily refer to the same embodiment.

[0074] While specific exemplary techniques are described and illustrated herein using various methods and systems, it should be understood by those skilled in the art that various other modifications may be made and equivalents may be substituted without departing from the claimed subject matter. Furthermore, many modifications may be made to adapt specific situations to the teachings of the claimed subject matter without departing from the central concepts described herein. Thus, the claimed subject matter is not limited to the specific examples disclosed, and such claimed subject matter may also include all implementations that fall within the scope of the appended claims, and their equivalents.

[0075] Using a simulation model, and after the model is fully functional, virtually all SSB-related circuits can be implemented / integrated as follows: The technology could be GF 22 n FDX. • Relatively little optimization for low speed / low dynamic power consumption Without a layout, the simulation can be performed using a method that includes estimating capacitance and resistance. • Mux-4, 2SEG was typically tested with the maximum configuration of 2kx128, but 2kx32 was also tested for some results.

[0076] Figures 7A and 7B show SSB implementations (segment control) in the LCTL 708 shown in Figure 7B, according to various embodiments. Figures 6A and 6B may show the following: Top-level view Regarding the switch power supply, please see below. • The AREADY 702 signal is in SSB mode. • Global power supply VDD_CNTR 704 shown in Figure 7A • Global ground GND_CNTR 706 shown in Figure 7A These power supplies may be coupled to most of the cells shown schematically. This is possible for at least some of the following reasons: The gate clock can be disabled. The address decoder can be set to a known state when AREADY=0. As a result, the logic state of virtually all signals within an LCTL can be fixed (i.e., the basic condition for SSB).

[0077] Figures 8A and 8B show SSB implementations in the LDP cell 810 shown in Figure 8B according to various embodiments. The following may be shown in Figures 8A and 8B. Switch cell 802 may have GND_LDP 804 and VDD_LDP 806 as outputs, as shown in Figure 8A. To bring virtually all inputs to a known logical state, virtually all pins of the mux control bus YSEL_N[3:0] can be driven to "1". The inverter at the highest level of the cell may be coupled as shown in some of the previous figures (e.g., Figure 5). The RDATA 808 may also be a read data bus line, and its tristate driver may include both NMOS and PMOS connected to a switching power supply. The RDATA 808 can maintain its logic state, but its level may be shifted to 200 mV or (VDD-200 mV). • In the GDP cell, you can see how RDATA exceptions can be managed.

[0078] Figures 9A, 9B, and 9C show SSB implementations in the LDP 904 cell shown in the bit line circuit of Figure 9C according to various embodiments. Figures 8A, 8B, and 8C show write and read multiplexers. The bit line power supply may be VDD_LDP 902 and a switchable power supply as shown in Figures 9A and 9B.

[0079] Figures 10A and 10B show SSB implementations in the LDP cell 1002 shown in the sense amplifier of Figure 10B according to various embodiments. Figures 10A and 10B may include the following: • The upper Nor2 gate can be joined according to the guidelines. • The sense power supply may be switchable to facilitate avoiding leakage paths to the bit lines. The lower enable NMOS, which can be coupled to GND_LDP according to the guidelines, can be configured to function as an actual leakage reduction device.

[0080] Figures 11A and 11B illustrate various embodiments of an exception handling (3) type B switch that is activated according to a logical state. Figures 10A and 10B may include the following: Type B switching may be possible when a small number of signals are logically dependent on each other in a one-to-one manner. • Since costs are based on area, leak savings can be improved or even significantly increased. The schematic diagram shown may be a GDP showing the I / O cells of memory 1116 as shown in Figure 11B, with the output driver visible. The function may be a function of RDATA 1102, and here the yellow light may be a tristate bus. Therefore, in this schematic diagram, it will be as follows: ·keeper • Multiplexer stage Output inverter The fragmented rectangles 1104 may enclose the type B switches, each having separate controls that are substantially all logically associated with each other. Each control may be for both a power switch and a ground switch. (For example, displaying signal 1106) • The second control in each Type B switch is the "global" EN_GND or EN_VDD_N signal. • 1108, 1110, 1112, and 1114 can supply output from Type B switches, and these can be "safely" used as power supplies for the indicated circuits.

[0081] Figure 12 shows several waveform signals received during the use of an SSB implementation according to various embodiments. As shown in Figure 11, the first signal 1202 may be the waveform output of the switchable power supply and ground operation in GDP. The second signal 1204 may be the waveform output of the switchable power supply and ground operation in LDP. The third signal 1206 may be the waveform output of the conditionally switchable power supply and ground operation. Due to logic dependencies, switching may occur alternately between power supply and ground.

[0082] As a result, the various embodiments disclosed may include at least some of the following: Various control signals that behave as gate clocks have known logical states in standby mode and can therefore be managed by a Type A switch (e.g., WL). The address and WR_N inputs may be latched first to facilitate the ability to force the state within the latch to a known state when SSB mode is active. Type A may use these latches. • The multiplexer control signal within a data path cell (LDP) may have one of four active signals. Logical modifications may be made so that virtually all are inactive in SSB mode, which means that virtually all LDP inputs may be in a known state. • The address decoder for WL selection may be modified in SSB mode so that, in effect, none of the WLs are selected. Since the output status is not known in advance, the data output driver can be managed with a Type B switch. SSB control logic does not necessarily need to have switches for its function. (Array bit cells may have a "normal" array source bias.)

[0083] Figure 13 shows at least some examples of logical conditions for entering a selective SB according to various embodiments. In Figure 13, some examples of logical conditions for entering an SSB may include: When CS_N changes to "1", the memory may be automatically placed into the SSB. • It may not be efficient enough when the entire domain can run at very low frequencies. • Automatic activation of SSB, which can be turned off on the rising edge of the clock and turned on at the end of the access. This may require some delay at the start of access due to the recovery of the switchable power supply, which may not be a problem if the speed requirements are relatively low / medium. · Dedicated input When the entire domain can be run at very low frequencies, it may exhibit characteristics similar to those of something that is not sufficiently efficient.

[0084] Figure 14 shows some examples of benchmark results. In Figure 14, the following may be shown: • SSB leaks can occur when array source bias is also active. The minimum time required for savings may include the minimum period for actual energy savings, which may occur when the energy costs of the transition can be taken into account. As illustrated, in the case of an SSG, 0.72 V, -40C corner, gate leakage can be substantially large, which can result in a relatively smaller gain compared to other PVTs.

[0085] Figure 14 shows the exception handling propagation path from the shifted level to the "true 0 / 1" level according to various embodiments. In Figure 14, the following may be shown: RDATA may be an exception because it is a signal whose level can be shifted to the level of the SB power supply. • The DO, memory data output port may remain driven to a "true 0" or "true 1" level with normal driver strength. The solution may involve adding two transistors enclosed by the dashed green rectangle. • DO signal feedback may ensure an open path to a non-switchable power supply. Leaks can be effectively prevented. • DO can be driven with normal strength.

Claims

1. A peripheral device for an instance of a memory circuit, A first inverter circuit having first and second transistors, wherein one of the first or second transistors is in the off state, A second inverter circuit having third and fourth transistors, wherein one of the third or fourth transistors is in the off state, and the first and second inverter circuits are coupled to each other in a communicative manner. A power supply that is communicatively coupled to one of the first or second transistors which is in the off state, A ground that is communicatively coupled to one of the third or fourth transistors which is in the off state, Means for applying a bias potential from the power supply to one of the first or second transistors which is in the off state, The peripheral device includes means for providing a bias ground to one of the third or fourth transistors which is in the off state.

2. The peripheral device according to claim 1, further comprising means for deactivating the bias potential.

3. The peripheral device according to claim 2, wherein the means for deactivating the bias potential includes using a setup time prior to the clock to return the voltage to the power supply.

4. The peripheral device according to claim 1, wherein the memory includes static random access memory (SRAM).

5. The peripheral device according to claim 1, wherein the memory includes dynamic random access memory (DRAM).

6. The peripheral device according to claim 1, wherein the means for applying the bias potential includes means for applying the bias potential to one or more pull-down devices.

7. A method for selective source bias in a memory peripheral device, Determining that the first transistor of the first inverter circuit is in the off state, The first and second inverters are coupled to each other in a communicative manner, including determining that the second transistor of the second inverter circuit is in the off state. The first transistor is coupled to the power supply in a communication manner, The second transistor is connected to ground in a communicative manner, Applying a bias potential from the power supply to the first transistor, The method comprising providing a second transistor with bias grounding.

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