TDC including a multiplexer for reconstructing input signals and FPGA including the same

Abstract

Disclosed is an FPGA programmed to include a plurality of TDCs, each TDC configured to determine the time difference between two signals and having a pair of input nodes to which the two signals are input, and a multiplexer configured to selectively connect the plurality of input signals to the input node pair of each TDC.

Description

Technical Field

[0001] [1] The present invention relates to technologies for FPGAs, and particularly to FPGA technologies including a TDC that includes a multiplexer for reconstructing an input signal.

Background Art

[0002] [2] A TDC (Time-to-Digital Converter) is a device or circuit that converts the time interval between two events into a digital output. TDCs play an important role in many scientific and industrial application fields where precise timing measurements are required. It is widely used in application fields that require high-precision timing measurements, such as time-of-flight (TOF) measurements in particle physics, medical imaging, radar systems, and laser range finding. A TDC operates by measuring the time difference between two events, exemplified by signal arrival or signal transmission and reflection at two points within a circuit. Generally, a counter is used to count the number of clock cycles between two events. Then, the count is converted into a digital output indicating the time interval. There are various types of TDCs, such as leading-edge TDCs, trailing-edge TDCs, and interpolating TDCs. A leading-edge TDC measures the time between the leading edge of a start signal and the leading edge of a stop signal, and a trailing-edge TDC measures the time between the trailing edge of a start signal and the trailing edge of a stop signal. An interpolating TDC uses interpolation techniques to estimate the time interval between two clock cycles and increase the resolution of the TDC.

[0003] [3] TDC can be implemented using ASICs (Application-Specific Integrated Circuits), MCUs (Microcontrollers), PSoCs (Programmable System-on-Chip), DSPs (Digital Signal Processors), FPAAs (Field Programmable Analog Arrays), TACs (Time-to-Amplitude Converters), TFCs (Time-to-Frequency Converters), and FPGAs (Field Programmable Gate Arrays).

[0004] [4] When implementing TDC using FPGA, the following problems may arise: Firstly, the resources provided to the FPGA, including logic cells, lookup tables (LUTs), and routing channels, are limited, which can limit the resolution and accuracy of the TDC implemented in the FPGA. Secondly, at high clock frequencies, jitter can introduce errors in TDC measurements. Here, jitter refers to fluctuations in the timing of the clock signal due to factors such as noise and temperature. Thirdly, factors such as voltage drop, temperature changes, and differences in the manufacturing process can cause the TDC to behave non-linearly, which can induce errors in TDC measurements at high resolution. Fourthly, FPGAs experience delays through signal processing and routing, and such delays can introduce errors in TDC measurements at small time intervals.

[0005] [5] Routing in FPGAs refers to the process of connecting programmable logic elements (e.g., lookup tables, flip-flops, and multiplexers) to a chip to form a desired logic circuit. Routing determines how signals propagate through the chip and can have a significant impact on the overall performance of the design. One of the main causes of delay in FPGA routing is the capacitance of the interconnect wires that connect the logic elements. As the number of logic elements and the distance between them increases, the capacitance of the interconnect wires also increases. This capacitance can delay signal propagation through the wires, increasing the overall design delay. Another factor that induces delay in FPGA routing is routing congestion. Routing congestion occurs when the FPGA's routing resources are limited and there are many logic elements to connect. Routing congestion can induce delay because it increases the distance between logic elements and increases the capacitance of the interconnect wires.

[0006] [6] A tapped delay line is a digital signal processing technique used to implement a thermometer code. In a thermometer code, each bit of a binary number is represented by a separate signal line, and the line corresponding to the "on" bit represents what the binary value indicates. To implement a thermometer code using a tapped delay line, a series of delay elements are used to represent each bit. The input binary number is converted into a series of pulses, each pulse representing one bit of the binary number. These pulses are delayed by a different amount depending on the position of each bit before being fed into the tapped delay line. At the output of the tapped delay line, each output signal line represents a bit of the binary number, and the "on" line represents the binary value. This technique is commonly used in digital-to-analog converters (DACs) to convert digital signals to analog signals.

[0007] [7] In FPGAs, a carry chain block is a hardware block used to perform high-speed arithmetic operations, particularly addition and subtraction. Addition and subtraction of multi-bit numbers in digital circuits require the calculation of carry bits, which can become a bottleneck in high-speed operations. Carry chain blocks efficiently handle such carry bit calculations, enabling faster and more efficient arithmetic operations. A carry chain block generally consists of a sequence of full adder circuits interconnected in a specific way to form a carry chain. Each full adder circuit calculates one bit of its output and the carry bit to be propagated to the next stage in the chain. By connecting these full adder circuits in a chain, the carry bits are propagated through the chain during a single clock cycle, enabling high-speed addition and subtraction of multi-bit numbers. In addition to providing high-speed arithmetic operations, carry chain blocks can also be used to implement counters and other sequential circuits that require the calculation of carry bits.

[0008] [8] The timing report tool is a software tool used to analyze the timing performance of a design implemented in an FPGA. The tool generates a report that provides information about the timing characteristics of the design. This report includes information about the timing characteristics of the design, including data path delay, critical path, setup time and hold time, clock skew and maximum operating frequency. The data path delay mentioned above is the time it takes for a data signal to propagate through the logic elements of the FPGA.

[0009] [9] A multiplexer, abbreviated as "MUX," is an electronic circuit that selects one of several input signals and transmits the selected input to an output line. The input-output structure of a multiplexer generally consists of several input lines, a selection line, and one or more output lines. The number of input lines corresponds to the number of input signals that the multiplexer can select, and the selection line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a selection line that determines which of the four input signals to send to the output. The selection line can be controlled by a binary code that indicates the selected input line. Multiplexers are often used in digital systems to reduce the number of wires required to transmit data and control signals. They can be used to embody functions such as data selectors, memory address decoders, and bus assignment circuits. [Overview of the project] [Problems that the invention aims to solve]

[0010]

[10] The present invention aims to provide an FPGA configuration that allows multiple TDCs to be combined and used for various purposes. [Means for solving the problem]

[0011]

[11] According to one aspect of the present invention, a provided FPGA may be programmed to include: a plurality of Time to Digital Converters (TDCs), each of which has a pair of input nodes into which the two signals are input; and a multiplexer configured to selectively connect the plurality of input signals to the input node pair of each of the TDCs.

[0012]

[12] In this case, the plurality of input signals include a first start signal and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to the plurality of TDCs in common, and the multiplexer may be programmed to further include a correction calculation unit that determines the average of a plurality of occurrence time differences output by the plurality of TDCs to the first start signal and the first end signal as a calibrated occurrence time difference between the first start signal and the first end signal.

[0013]

[13] In this case, the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a first delay line section to which an input pulse having the time difference between the occurrence of the first start signal and the first end signal as its width is input; a code conversion section that converts the order of the elements of the thermometer code output by the first delay line section and outputs it; and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference determined by each TDC, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

[0014]

[14] Alternatively, the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a plurality of delay line sections to which input pulses having the time difference between the occurrence of the first start signal and the first end signal as a width are input; a code conversion section that merges a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that uses the conversion code to determine the occurrence time difference determined by each TDC; wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, and the predetermined criterion may be the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

[0015]

[15] Alternatively, the plurality of input signals may include a first start signal, a first end signal, and a second end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs, and to provide a circuit connected to the first TDC with a first time difference which is the time difference between the first start signal and the first end signal determined by the first TDC, and to provide a circuit connected to the second TDC with a second time difference which is the time difference between the first start signal and the second end signal determined by the second TDC.

[0016]

[16] Alternatively, the plurality of input signals may include a first start signal, a second start signal, and a first end signal, and the multiplexer may be configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, and to provide a circuit connected to the first TDC with a first time difference which is the time difference between the first start signal and the first end signal determined by the first TDC, and to provide a circuit connected to the second TDC with a second time difference which is the time difference between the second start signal and the first end signal determined by the second TDC.

[0017]

[17] According to one aspect of the present invention, a non-volatile recording medium readable by an electronic device provided may record a binary file containing configuration data which is configured to program the FPGA to implement a digital circuit comprising: a plurality of Time to Digital Converters (TDCs), each TDC having a pair of input nodes into which the two signals are input; and a multiplexer configured to selectively connect the plurality of input signals to the input node pair of each TDC.

[0018]

[18] The plurality of input signals include a first start signal and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to the plurality of TDCs in common, and the digital circuit further includes a correction calculation unit that determines the average of a plurality of occurrence time differences output by the plurality of TDCs with respect to the first start signal and the first end signal as a calibrated occurrence time difference between the first start signal and the first end signal.

[0019]

[19] In this case, the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a first delay line section to which an input pulse having the time difference between the occurrence of the first start signal and the first end signal as its width is input; a code conversion section that converts the order of the elements of the thermometer code output by the first delay line section and outputs it; and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference determined by each TDC, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

[0020]

[20] Alternatively, the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a plurality of delay line sections to which input pulses having the time difference between the occurrence of the first start signal and the first end signal as a width are input; a code conversion section that merges a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that uses the conversion code to determine the occurrence time difference determined by each TDC, wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, and the predetermined criterion is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

[0021]

[21] Alternatively, the plurality of input signals may include a first start signal, a first end signal, and a second end signal, and the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs, and is configured to provide a first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and to provide a second time difference, which is the time difference between the first start signal and the second end signal determined by the second TDC, to a circuit connected to the second TDC.

[0022]

[22] Alternatively, the plurality of input signals include a first start signal, a second start signal, and a first end signal, and the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, and provide a first time difference, which is a generated time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and provide a second time difference, which is a generated time difference between the second start signal and the first end signal determined by the second TDC, to a circuit connected to the second TDC.

[0023]

[23] According to one aspect of the present invention, a provided TDC system can include a PCB board (600) including the aforementioned FPGA (1); and a computing device (700) that acquires the generated time difference from the PCB board.

[0024]

[24] According to the present invention, it is possible to provide a configuration of an FPGA that enables a plurality of TDCs to be combined and used for multiple purposes.

Brief Description of the Drawings

[0025] [Figure 1]

[25] FIG. 1 shows a configuration diagram of an FPGA according to an embodiment of the present invention.

[0026] [Figure 2]

[26] FIG. 2 is a diagram for explaining an input pulse input to a first delay line unit according to an embodiment of the present invention.

[0027] [Figure 3]

[27] FIG. 3 shows a configuration of a first delay line unit according to an embodiment of the present invention.

[0028] [Figure 4]

[28] FIG. 4 is a diagram for explaining the index of the buffer in FIG. 3.

[0029] [Figure 5]

[29] Figure 5 shows a table illustrating data path delay according to one embodiment of the present invention.

[0030] [Figures 6a-6b]

[30] Figures 6a and 6b show a configuration in which multiple delay line sections are arranged in parallel according to one embodiment of the present invention.

[0031] [Figures 7a-7b]

[31] Figure 7a shows the configuration of the first delay line section and the second delay line section of Figure 6b, and Figure 7b is for explaining the operation of the code conversion section when two delay line sections are used according to one embodiment of the present invention.

[0032] [Figure 8]

[32] Figure 8 shows a graph of delays with and without the application of the code conversion unit according to one embodiment of the present invention.

[0033] [Figure 9]

[33] Figure 9 is a diagram illustrating the array criteria for flip-flop output values ​​and the increase in the number of taps in Figure 8 depending on whether or not the code conversion unit is applied, according to one embodiment of the present invention.

[0034] [Figure 10]

[34] Figure 10 illustrates a method for providing input pulses for multiple TDCs using multiple input signals according to one embodiment of the present invention.

[0035] [Figure 11]

[35] Figure 11 shows the input signals and TDC input pulses in Figure 10.

[0036] [Figure 12]

[36] Figure 12 shows a graph for checking jitter using TDC according to one embodiment of the present invention.

[0037] [Figure 13]

[37] Figure 13 is a diagram illustrating the operation of a multiplexer according to another embodiment of the present invention.

[0038] [Figure 14]

[38] Figure 14 shows the input pulses of the TDCs due to the signals input to each TDC in Figure 13.

[0039] [Figure 15]

[39] Figure 15 is a diagram illustrating the operation of a multiplexer according to another embodiment of the present invention.

[0040] [Figure 16]

[40] Figure 16 shows the input pulses of the TDCs due to the signals input to each TDC in Figure 15.

[0041] [Figure 17]

[41] Figure 17 is a block diagram of a TDC system provided according to one embodiment of the present invention. [Modes for carrying out the invention]

[0042]

[42] Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and can be embodied in various other forms. The terms used herein are for the purpose of understanding the embodiments and are not intended to limit the scope of the present invention. Also, the singular form used herein includes the plural form unless the context clearly indicates the opposite.

[0043]

[43] Figure 1 shows a diagram of the FPGA configuration according to one embodiment of the present invention.

[0044]

[44] Figure 2 is a diagram illustrating the input pulse input to the first delay line section according to one embodiment of the present invention.

[0045]

[45] The following explanation will be given with reference to both Figure 1 and Figure 2.

[0046]

[46] The FPGA(1) may include an input signal generation unit (10), a first delay line unit (20), a code conversion unit (30), a clock pulse count unit (40), a priority encoder unit (50), and an arithmetic unit (60).

[0047]

[47] Specifically, the FPGA(1) configuration described above may be a TDC (Time to Digital converter) configuration.

[0048]

[48] ​​As shown in Figure 2, the input signal generation unit (10) can generate an input pulse (P1) whose width is the time difference (T) between the rising edge (E1) of a predetermined given start signal (S1) and the rising edge (E2) of a predetermined given end signal (S2). The input signal generation unit (10) can be composed of logic gates necessary for the above generation.

[0049]

[49] The first delay line section (20) can receive an input pulse (P1) having a width equal to the time difference (T) between the start signal (S1) and the end signal (S2). The first delay line section (20) can output a thermometer code (O1). In this case, the thermometer code is composed of the output values ​​of the flip-flops included in the first delay line section (20), and for example, an 8-bit value, where the output values ​​of each flip-flop can be referred to as elements of the thermometer code.

[0050]

[50] Figure 3 shows the configuration of the first delay line section according to one embodiment of the present invention.

[0051]

[51] Figure 4 is a diagram illustrating the buffer index in Figure 3.

[0052]

[52] The first delay line section (20) may include a delay line (D_L) containing a plurality of buffers (delay elements) (B), and D-flip-flops (FF) tapped to the output terminals of each buffer (B) of the delay line.

[0053]

[53] Multiple buffers can be connected in a cascade delay manner, that is, multiple buffers can be arranged in the order in which the input pulses (P1) flow.

[0054]

[54] The waveform (Signal) of the input pulse (P1) in Figure 3 can be output at the output terminals of each buffer (B) with a predetermined delay. That is, the output value of the first buffer (B1) is output at the output terminal of the first buffer (B1) with a predetermined delay, and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value of the first buffer (B1) (for example, '1') can also be input to the first flip-flop (FF1).

[0055]

[55] At this time, data path delays may occur between each buffer (B) and when passing through flip-flops (FF). For example, a delay of d1 may occur before the input value ('1') of the first buffer (B1) is transmitted to the second buffer (B2), and a delay of d11 may occur before the output value ('1') of the first buffer (B1) is transmitted to the first flip-flop (FF1). Similarly, a delay may occur each time data is transmitted from the previous buffer to the next buffer, and each time data is transmitted from any buffer to a flip-flop connected to that buffer.

[0056]

[56] Figure 4 is a diagram illustrating the buffer index according to one embodiment of the present invention.

[0057]

[57] Each field in the table in Figure 4 indicates the buffer name, index, and output value of the buffer.

[0058]

[58] Each buffer can be assigned an index that defines the order of the buffers. For example, the first buffer (B1) can be assigned index '1', the second buffer (B2) can be assigned index '2', and similarly the eighth buffer (B8) can be assigned index '8'. In this way, if each buffer (B) is arranged in the order in which the input pulses (P1) flow, and the indices are arranged according to that order, then for example, 1000 buffers can each be assigned indices from 1 to 1000.

[0059]

[59] Figure 5 shows a table illustrating data path delay according to one embodiment of the present invention.

[0060]

[60] Referring to Figures 1 and 5, the code conversion unit (30) can convert and output the order of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line unit (20). At this time, the code output by the code conversion unit (30) (e.g., 11010000) (the order of the indices in the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) can be called the 'converted code (CO1)'.

[0061]

[61] The converted code (CO1) output by the code conversion unit (30) may be an arrangement of the elements of the thermometer code (O1) according to a predetermined criterion. In this case, the predetermined criterion may be the data path delay from the output node (N1) of the input pulse (P1) to the output node (N2) of each of the multiple flip-flops (FF) included in the first delay line unit (20). This will be explained in detail with reference to Figure 5.

[0062]

[62] Each field in the table shown in Figure 5 can represent the buffer index number, the value of the first delay, the value of the second delay, and the total value (rank). In this case, the rank can represent the rank relative to the overall total value. In this case, the buffer with the smallest total value can have rank 1, and the buffer with the highest total value can have the last rank. Or, in other embodiments, the reverse is also possible.

[0063]

[63] As shown above in Figure 3, the above total value can represent the time it takes for data to be transmitted from the node (N1) where the input pulse (P1) is output to any flip-flop (e.g., FF4).

[0064]

[64] A first delay may occur, which is the time it takes for the input value of any buffer to be transmitted to other buffers adjacent to that buffer, and a second delay may occur, which is the time it takes for the output value of any buffer to be transmitted to the input of the flip-flop connected to that buffer.

[0065]

[65] In this case, the sum of the first delay value and the second delay value for each buffer can be called the data path delay.

[0066]

[66] Referring to both Figure 3 and Figure 5, when the indices of each buffer are arranged in order, the rank of the sum of the values ​​of the first delay and the second delay may differ from the rank of the index number of each buffer. For example, in the case of the third buffer, the buffer array rank is 3, so the index number is '3', but the rank of the sum may be '5'. Looking at it in detail, in order for data to be transmitted to the third flip-flop (FF3), it must pass through the first buffer (B1), the second buffer, and the third buffer. At this time, predetermined delays (d1, d2, d3) occur each time the data passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur until the data output from the third buffer (B3) is output as the output value of the third flip-flop (FF3). In other words, the delay from the output node (N1) of the input pulse (P1) to the output nodes (N2, N23) of the third flip-flop (FF3) can be the sum of d1, d2, d3, and d13.

[0067]

[67] In this way, the delay (i.e., the sum) until data is transmitted to the output node of each flip-flop (FF3) can be calculated.

[0068]

[68] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3 and the buffer index for the fourth flip-flop (FF4) is 4. That is, the total delay to the output node of the third flip-flop, which has a buffer index of 3, may be greater than the total delay to the output node of the third flip-flop, even though the fourth flip-flop has to pass through one more buffer than the third flip-flop.

[0069]

[69] The code conversion unit (30) can convert the order of the elements of the thermometer code (O1) based on the calculated delay (total value) (for example, in ascending order of total value).

[0070]

[70] The converted code (CO1) output by the code conversion unit (30) may be provided to the priority encoder unit (50).

[0071]

[71] The priority encoder unit (50) can digitize long thermometer codes. For example, the priority encoder unit (50) can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if there are 5200 buffers (delay elements) (B) and 5200 flip-flops (FFs) connected to the buffer as described above in Figure 3, a sequence of 5200 consecutive binary numbers will be output, which can be represented as a 13-bit binary number.

[0072]

[72] In other words, the priority encoder unit (50) can represent a 5200-bit first thermometer code (TC1) and a second thermometer code (TC2) as 13-bit binary numbers as output values ​​(CO1) corresponding to the time of the code conversion unit (30).

[0073]

[73] Referring to Figure 2, the first thermometer code (TC1) may be a code output by the code conversion unit (30) in relation to the rising edge of the input pulse (P1) at the rising edge (E4) of the first clock pulse (CK2) that occurred after the rising edge (E1) of the input pulse (P1) among the generated clock pulses (CK). The first thermometer code (TC1), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0074]

[74] The second thermometer code (TC2) may be a code output by the code conversion unit (30) in relation to the falling edge (E2) of the input pulse (P1) at the rising edge (E6) of the first clock pulse (CK4) that occurred after the falling edge (E2) of the input pulse (P1) among the generated clock pulses (CK). The second thermometer code (TC2), represented in 13 bits, may be provided as input to the arithmetic unit (60).

[0075]

[75] In this case, the time interval of the first thermometer code (TC1) and the time interval of the second thermometer code (TC2) may be smaller than the period of the clock pulse (CK).

[0076]

[76] Referring again to Figures 1 and 2, the clock pulse counting unit (40) can receive an input pulse (P1) from the input signal generation unit (10).

[0077]

[77] The clock pulse counting unit (40) can count the number of clock pulses (CK) that occur during the duration (T) of the input pulse (P1). For example, in Figure 2, there are two rising edges of the clock pulses that occur during the period when the input pulse (P1) is ON, as shown by edges (E4, E5), so the counted value may be 2.

[0078]

[78] The output value (coarse count) of the clock pulse counting unit (40), that is, the counted value, can be provided to the calculation unit (60).

[0079]

[79] Referring to Figures 1 and 2, the calculation unit (60) can determine the value of the occurrence time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses. For example, the occurrence time difference may be 2*Period+TC1-TC2.

[0080]

[80] Figures 6a and 6b show a configuration in which multiple delay line sections are arranged in parallel according to one embodiment of the present invention.

[0081]

[81] As shown in Figure 6a, two or more delay line sections (20) may be connected in parallel. In this case, the input pulse (P1) output from the input signal generation unit (10) can be input to the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24), respectively. The first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line section (21), the second delay line section (22), the third delay line section (23), and the fourth delay line section (24) can then be input to the code conversion unit (30).

[0082]

[82] As shown in Figure 6b, we can consider the possibility that in another embodiment, two delay line sections (20) are connected in parallel.

[0083]

[83] For example, an input pulse (P1) output from the input signal generation unit (10) may be provided along a first path (path1) through which the output terminal of the input signal generation unit (10) and the input terminal of the first delay line unit (21) are connected to each other, and a second path (path2) through which the output terminal of the input signal generation unit (10) and the input terminal of the second delay line unit (22) are connected to each other.

[0084]

[84] At this time, the time it takes for the input pulse (P1) output from the input signal generation unit (10) to reach the input terminal of the first delay line unit (21) and the input terminal of the second delay line unit (22) may be different. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path2). In the embodiment of Figure 6b, the length of the first path (path1) is shorter than the length of the second path (path2), so it can be seen that the input time interval of the input pulse (path1) through the first path (path1) is shorter than the input time interval of the input pulse (path2) through the second path (path2).

[0085]

[85] Figure 7a shows the configuration of the first delay line section and the second delay line section of Figure 6b, and Figure 7b is for explaining the operation of the code conversion section when two delay line sections are used according to one embodiment of the present invention.

[0086]

[86] For the sake of explanation, Figure 7a shows that each delay line contains four buffers and four flip-flops.

[0087]

[87] In Figure 7b, each field in the table can represent the delay line section number, buffer index number, first delay value, second delay value, first total value (first rank), and first total value (overall rank). In this case, the first rank can represent the rank of each total value relative to the buffer index of the buffer in each delay line section. The overall rank can represent the rank of each total value relative to the buffer index of all buffers in the first and second delay line sections.

[0088]

[88] The code conversion unit (30) can be configured to generate a single conversion code by sorting and merging the elements of a first set (for example, {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) which is the sum of the elements of the thermometer code output by the first delay line unit (21) and the buffer index pairs sorted in ascending order of sum, and the elements of a second set (for example, {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) which is the sum of the elements of the thermometer code output by the second delay line unit (22) and the index pairs sorted in ascending order of sum.

[0089]

[89] In other words, each element of the first set and each element of the second set can be sorted in ascending order of their sum.

[0090]

[90] For example, the output values ​​based on the buffer index in the first delay line section (21) may be {1, 2, 3, 4}, and the output values ​​based on the buffer index in the second delay line section (22) may be {5, 6, 7, 8}. Also, in the embodiments of Figures 6b and 7a, delay (d1) may be less than delay (d5). Therefore, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output values ​​of the flip-flops for each buffer index can be sorted in the above sorted order. For example, the sorted values ​​(buffer indices) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0091]

[91] As described above, when multiple delay line sections (20) are used, they may have slightly different input delays depending on their arrangement. Figure 8, described below, shows the delays due to the arrangement when multiple delay line sections are used.

[0092]

[92] Figure 8 shows a graph of delays with and without the application of the code conversion unit according to one embodiment of the present invention.

[0093]

[93] Figure 9 is a diagram illustrating the array criteria for flip-flop output values ​​and the increase in the number of taps in Figure 8 depending on whether or not the code conversion unit is applied, according to one embodiment of the present invention.

[0094]

[94] Figure 8(a) shows a delay graph based on the number of taps when the code conversion unit (30) is not applied, and Figure 8(b) shows a delay graph based on the number of taps when the code conversion unit (30) is applied.

[0095]

[95] The fields in the table in Figure 9 include the sorting order, the sorting criteria for the flip-flop output values, and the sorting order for the total delay values.

[0096]

[96] The following explanation will be given with reference to both Figures 8 and 9.

[0097]

[97] The horizontal axis of the graph (g1, g2) represents the number of taps. Referring to Figure 7b, one tap can represent a pair of buffers (delay elements) (e.g., B1) and a flip-flop (FF1) connected to it. For example, if the total number of pairs of buffers and connected flip-flops is 1000, then the total number of taps may be 1000.

[0098]

[98] The vertical axis of the graph (g1, g2) represents the delay time (ns). The above delay time can be said to represent the total delay required for data to be transmitted to the output node of the flip-flop tapped to each buffer described above in Figure 5.

[0099]

[99] Referring to both Figures 7a and 9, an increase in the number of taps in graph (g1) can mean, for example, an increase in the buffer index. For example, if the number of taps on the horizontal axis of graph (g1) is 4, it can mean a buffer index of 4. In this case, the delay value on the vertical axis of graph (g1) may be D4 (=d1+d2+d3+d4+d14) as shown in Figure 7b. For example, if the number of taps is 5, it can mean a buffer index of 5. In this case, the delay value on the vertical axis of graph (g1) may be D5 (=d5+d15) as shown in Figure 7b. Referring to Figure 9, D4 > D5 can be seen here. Here, it can be seen that the delay observed in the flip-flop of each tap does not increase as the tap index (e.g., index 4 -> index 5) increases, but may even locally decrease as the tap index increases.

[0100]

[0100] On the one hand, an increase in the number of taps in the graph (g2) does not mean an increase in the buffer index, but can mean an increase in position according to the alignment order in the state where the output values of each flip-flop are aligned by the code conversion unit (30). For example, when the number of taps on the horizontal axis of the graph (g2) is 4, the position order of the aligned buffer indices can be 1, 2, 5, 3, meaning buffer index 3. And the delay value which is the vertical axis of the graph (g2) in this case can be D3 (= d1 + d2 + d3 + d13). For example, when the number of taps is 5, the position order of the aligned buffer indices can be 1, 2, 5, 3, 6, meaning buffer index 6. And the delay value in this case can be D6 (= d5 + d6 + d16). At this time, referring to FIG. 9, D3 < D6 can be true.

[0101]

[0101] That is, as shown in (a) of FIG. 8, when the code conversion unit (30) of the present invention is not applied, it can be seen that the graph (g1) for the delay due to an increase in the number of taps does not have the property of monotonically increasing. On the other hand, as shown in (b) of FIG. 8, when the code conversion unit (30) of the present invention is applied, it can be seen that the graph (g2) for the delay due to an increase in the number of taps exhibits an increasing phenomenon without decreasing.

[0102]

[0102] For example, different from an ASIC which is a custom semiconductor, an FPGA that can be directly designed through programming can change the functions of the chip by programming. Therefore, different from an ASIC, the functions of each component included in the FPGA can change, and (or depending on the arrangement of the components), the delay may not always increase but may decrease each time the number of taps increases, and there may be no increasing phenomenon without decreasing.

[0103]

[0103] However, as described above, it can be confirmed that the code conversion unit (30) can correct the output of the first delay line unit (20) through the graph (g2).

[0104]

[0104] As described above, when multiple delay line sections (20) are used, delay alignment can be provided through the code conversion section. As a result, errors due to jitter can be corrected and a TDC with high time resolution can be provided. For example, when four delay line sections are configured in parallel and have a total of 9600 taps, a TDC with a resolution of 0.8 ps per tap can be provided.

[0105]

[0105] Figure 10 is a diagram illustrating a method for providing input pulses for multiple TDCs using multiple input signals according to one embodiment of the present invention.

[0106]

[0106] In order to provide input pulses to multiple TDCs using multiple input signals, the FPGA(2) may include multiple TDCs(100), a multiplexer(200), and a correction calculation unit(300).

[0107]

[0107] In this case, multiple TDCs (100) can be configured to determine the time difference between the occurrence of two signals. For example, the two signals may be the same as the start signal (S1) and end signal (S2) in Figure 2, and the time difference between the occurrences may represent, for example, T in Figure 2.

[0108]

[0108] In this case, each of the multiple TDC(100) may include the configuration described above in Figures 1 to 9.

[0109]

[0109] In this case, each of the multiple TDC(100) can have a pair of input nodes that receive the two signals mentioned above.

[0110]

[0110] For example, multiple TDCs (100) can include a first TDC (110), a second TDC (120), and a third TDC (130). The first TDC (110) can include an input node pair consisting of nodes (NN1) and (NN2). The second TDC (120) can include an input node pair consisting of nodes (NN3) and (NN4). The third TDC (130) can include an input node pair consisting of nodes (NN5) and (NN6).

[0111]

[0111] The multiplexer (200) can selectively connect multiple input signals (I1, I2, ..., IN) to their respective pairs of input nodes in the TDC (100).

[0112]

[0112] For example, as shown in Figure 10, the input signals of the multiplexer (200) may include a first input signal (I1), a second input signal (I2), ..., and an Nth input signal (IN).

[0113]

[0113] In one embodiment, the multiplexer (200) can supply the first input signal (I1) from the above input signals as a common start signal (S11) for the first TDC (110), the second TDC (120), and the third TDC (130), and can supply the second input signal (I2) from the above input signals as a common end signal (S12) for the first TDC (110), the second TDC (120), and the third TDC (130).

[0114]

[0114] The correction calculation unit (300) can determine the average value of multiple occurrence time differences output by multiple TDCs (100) as the 'calibrated occurrence time difference' (CO10) between the start signal (S11) and the end signal (S12).

[0115]

[0115] For example, the correction calculation unit (300) can calculate the average value of the output value (out10) (occurrence time difference) of the first TDC (110), the output value (out20) of the second TDC (120), and the output (out30) of the third TDC (130). The correction calculation unit (300) can determine the above calculated average value as the calibrated occurrence time difference (CO10) between the start signal (S11) and the end signal (S12) and output it.

[0116]

[0116] The above-calibrated generation time difference (CO10) is likely to be more accurate than the above-mentioned output values ​​(out10, out20, out30) individually.

[0117]

[0117] Figure 11 shows the input signal and the input pulse of TDC in Figure 10.

[0118]

[0118] The horizontal axis of each input signal and input pulse shows the passage of time.

[0119]

[0119] Referring to both Figures 10 and 11, the multiplexer (200) may receive input signals (I1), (I2), and (IN). However, only input signals (I1) and (I2) are provided to the TDC (100) as the start signal and end signal, respectively. Therefore, all input pulses (P1) generated within the TDC (100) can be identical.

[0120]

[0120] Figure 12 shows a graph for checking jitter using TDC according to one embodiment of the present invention.

[0121]

[0121] The chart on the left (500) shows the case where the correction calculation unit (300) in Figure 10 is not applied, and the chart on the right (510) shows the case where the correction calculation unit (300) in Figure 10 is applied.

[0122]

[0122] That is, the chart on the left (500) above is a histogram showing the variance when the final result value is repeatedly measured, without using the correction calculation unit (300) of Figure 10, and one of the output values ​​(out10, out20, out30) is selected as the final result value. The chart on the right (510) above is a histogram showing the variance when the calibrated generation time difference (CO10) is selected as the final result value using the correction calculation unit (300) of Figure 10, and the final result value is repeatedly measured.

[0123]

[0123] In charts (500, 510), the horizontal axis of each graph (g1, g2, g3) represents time (in ps), and the vertical axis represents the normalized count value.

[0124]

[0124] In the left chart (500), the standard deviation (dotted line) of the first graph (g11) is 20 ps, ​​and the standard deviation (solid line) of the second graph (g12) is 18.7 ps. At this time, the full width at half maximum (FWHM) is 44 ps for both the first graph (g11) and the second graph (g12).

[0125]

[0125] On the right-hand chart (510), the standard deviation of the third graph (g13) is 7 ps. At this time, the full width at half maximum on the third graph (g13) is 17 ps.

[0126]

[0126] Comparing the full width at half maximum (FMAX) of the left chart (500) and the right chart, it can be seen that the FMAX of the right chart is more than half smaller than the FMAX of the left chart (510). In other words, it can be confirmed that the application of the correction calculation unit (300) reduces the error caused by delays such as jitter in the FPGA.

[0127]

[0127] Figure 13 is a diagram illustrating the operation of a multiplexer according to another embodiment of the present invention.

[0128]

[0128] Figure 14 shows the input pulses of the TDCs due to the signals input to each TDC in Figure 13.

[0129]

[0129] The following explanation will be given with reference to both Figure 13 and Figure 14.

[0130]

[0130] The multiple input signals (I1, I2, I3) input to the multiplexer (200) may include a first start signal (S21), a first end signal (S22), and a second end signal (S23).

[0131]

[0131] The multiplexer (200) can supply a first start signal (S21) and a first end signal (S22) to the first TDC (110) among the multiple TDCs (100), and supply a first start signal (S21) and a second end signal (S23) to the second TDC (120) among the multiple TDCs (100).

[0132]

[0132] A first input pulse (P1) can be generated within the first TDC(110) through a first start signal (S21) and a first end signal (S22). A first time difference (out41, T1), which is the generation time difference between the first start signal (S21) and the first end signal (S22) determined by the first TDC(110), can be provided to a circuit connected to the first TDC(110) (for example, a first circuit (400, 410)).

[0133]

[0133] A second input pulse (P2) can be generated within the second TDC(120) via a first start signal (S21) and a second end signal (S23). The second time difference (out42, T2), which is the generation time difference between the first start signal (S21) and the second end signal (S23) determined by the second TDC(120), can be provided to a circuit connected to the second TDC(120) (for example, a second circuit (400, 420)).

[0134]

[0134] Figure 15 is a diagram illustrating the operation of a multiplexer according to another embodiment of the present invention.

[0135]

[0135] Figure 16 shows the input pulses of the TDCs due to the signals input to each TDC in Figure 15.

[0136]

[0136] The following explanation will be given with reference to both Figure 15 and Figure 16.

[0137]

[0137] The multiple input signals (I11, I12, I13) input to the multiplexer (200) may include a first start signal (S31), a second start signal (S32), and a first end signal (S33).

[0138]

[0138] The multiplexer (200) can supply a first start signal (S31) and a first end signal (S33) to the first TDC (110) among the multiple TDCs (100), and supply a second start signal (S32) and a first end signal (S33) to the second TDC (120) among the multiple TDCs (100).

[0139]

[0139] A first input pulse (P11) can be generated within the first TDC(110) using a first start signal (S31) and a first end signal (S33). A first time difference (out41, T11), which is the time difference between the first start signal (S31) and the first end signal (S33) determined by the first TDC(110), can be provided to a circuit connected to the first TDC(110) (for example, a first circuit (400, 410)).

[0140]

[0140] A second input pulse (P12) can be generated within the second TDC(120) via a second start signal (S32) and a first end signal (S33). The second time difference (out42, T12), which is the time difference between the second start signal (S32) and the first end signal (S33) determined by the second TDC(120), can be provided to a circuit connected to the second TDC(120) (for example, a second circuit (400, 420)).

[0141]

[0141] In this case, the first circuit (410) and the second circuit (420) may be a correction calculation unit (300).

[0142]

[0142] As described above through Figures 10 to 16, by averaging the driving results of multiple TDCs and reconstructing the input signal of the TDC using a multiplexer, an FPGA with improved accuracy and usefulness for TDC can be provided.

[0143]

[0143] In one embodiment of the present invention, a non-volatile recording medium readable by an electronic device according to the present invention may record a binary file containing configuration data configured to program the FPGA to implement a digital circuit including the plurality of TDCs and the multiplexer described above using the FPGA described above.

[0144]

[0144] Figure 17 is a block diagram of a TDC system provided according to one embodiment of the present invention.

[0145]

[0145] The TDC system (1000) may include a PCB board (600) and a computing device (700).

[0146]

[0146] The PCB board (600) can be a device capable of digital signal processing and may include the FPGA (1), data interface (601), signal interface (602), clock generation unit (603), and power supply unit (604) as described above.

[0147]

[0147] The data interface (601) is a device that enables data exchange between the PCB board (600) and the computing device (700) and may consist of, but is not limited to, USB, Ethernet, or UART.

[0148]

[0148] The signal interface (602) has the function of receiving signals from an external source that attempt to measure a time difference using the FPGA (1) and transmitting them to the FPGA (1).

[0149]

[0149] The clock generation unit (603) can provide a train of clock pulses that the FPGA (1) counts.

[0150]

[0150] The time difference value of the two selected signals calculated by FPGA(1) can be output from FPGA(1) and provided to the data interface (601). The data interface (601) can provide the time difference value of the two signals to the computing device (700).

[0151]

[0151] The power supply unit (604) supplies power used by the PCB board (600).

[0152]

[0152] The computing device (700) may include a data interface (701), a CPU (702), and memory (703).

[0153]

[0153] The computing device (700) may be configured to execute a predetermined algorithm in advance using the time difference between two selected signals received from the PCB board (600). The time difference between the two received signals may be processed by a process executed by the CPU (702). A program consisting of instructions for executing the above process may be stored in memory (703). The above program may be loaded from memory (703) to the CPU (702) and executed. The above memory (703) may be non-volatile memory.

[0154]

[0154] By utilizing the embodiments of the present invention described above, persons in the art of the present invention will be able to easily make various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim can be combined with other unreferenced claims as can be understood herein. [Explanation of Symbols]

[0155]

[0155] [Explanation of the symbol]

[0156]

[0156] 1: FPGA

[0157]

[0157] 10: Input signal generation unit

[0158]

[0158] 20: First delay line section

[0159]

[0159] 30: Code conversion unit

[0160]

[0160] 40: Clock pulse counting section

[0161]

[0161] 50: Priority encoder section

[0162]

[0162] 60: Arithmetic unit

[0163]

[0163] 100: TDC

[0164]

[0164] 200: Multiplexer

[0165]

[0165] 300: Correction calculation unit

[0166]

[0166] 400: Circuit

[0167]

[0167] 500: Chart

[0168]

[0168] 510: Chart

[0169]

[0169] 600: PCB board

[0170]

[0170] 700: Computing device

[0171]

[0171] 1000: TDC System

Claims

1. An FPGA programmed to include: a plurality of Time-to-Digital Converters (TDCs), each TDC having a pair of input nodes into which the two signals are input; and a multiplexer configured to selectively connect the plurality of input signals to the input node pair of each TDC.

2. The FPGA according to claim 1, wherein the plurality of input signals include a first start signal and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to the plurality of TDCs in common, and the FPGA is further programmed to include a correction calculation unit that determines the average value of a plurality of occurrence time differences output by the plurality of TDCs as a calibrated occurrence time difference between the first start signal and the first end signal.

3. FPGA according to claim 1, wherein the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a first delay line section to which an input pulse having the time difference between the occurrence of the first start signal and the first end signal as its width is input; a code conversion section that converts the order of the elements of the thermometer code output by the first delay line section and outputs it; and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference determined by each TDC, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

4. FPGA according to claim 1, wherein the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a plurality of delay line sections to which input pulses having the time difference between the occurrence of the first start signal and the first end signal as a width are input; a code conversion section that merges a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that uses the conversion code to determine the occurrence time difference determined by each TDC, wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, and the predetermined criterion is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections.

5. The FPGA according to claim 1, wherein the plurality of input signals include a first start signal, a first end signal, and a second end signal, the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs, the FPGA is configured to provide a first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and the second time difference, which is the time difference between the first start signal and the second end signal determined by the second TDC, to a circuit connected to the second TDC.

6. The FPGA according to claim 1, wherein the plurality of input signals include a first start signal, a second start signal, and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, the FPGA is configured to provide a first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and the second time difference, which is the time difference between the second start signal and the first end signal determined by the second TDC, to a circuit connected to the second TDC.

7. An electronically readable non-volatile recording medium, on which an electronically readable non-volatile recording medium is recorded, containing a binary file containing configuration data configured to program the FPGA to implement a digital circuit comprising: a plurality of Time to Digital Converters (TDCs), each TDC configured to determine the time difference between two signals and having a pair of input nodes to which the two signals are input; and a multiplexer configured to selectively connect the plurality of input signals to the input node pair of each TDC.

8. A non-volatile recording medium readable by an electronic device according to claim 7, wherein the plurality of input signals include a first start signal and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to the plurality of TDCs in common, and the digital circuit further includes a correction calculation unit that determines the average value of a plurality of occurrence time differences output by the plurality of TDCs as a calibrated occurrence time difference between the first start signal and the first end signal.

9. A non-volatile recording medium readable by an electronic device according to claim 7, wherein the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a first delay line section to which an input pulse having the time difference between the occurrence of the first start signal and the first end signal as its width is input; a code conversion section that converts and outputs the order of the elements of the thermometer code output by the first delay line section; and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference determined by each TDC, wherein the converted code is an arrangement of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the first delay line section, characterized in that the non-volatile recording medium readable by an electronic device.

10. A non-volatile recording medium readable by an electronic device according to claim 7, wherein the plurality of input signals include a first start signal and a first end signal, and each TDC includes: a plurality of delay line sections to which input pulses having the time difference between the occurrence of the first start signal and the first end signal as a width are input; a code conversion section that merges a plurality of thermometer codes output by the plurality of delay line sections and outputs them as a single conversion code; and a calculation section that uses the conversion code to determine the occurrence time difference determined by each TDC, wherein the conversion code is obtained by arranging the order of the elements of the plurality of thermometer codes according to a predetermined criterion, and the predetermined criterion is the data path delay from the output node of the first input pulse to the output node of each of the plurality of flip-flops included in the plurality of delay line sections, characterized in that the non-volatile recording medium readable by an electronic device.

11. A non-volatile recording medium readable by an electronic device according to claim 7, wherein the plurality of input signals include a first start signal, a first end signal, and a second end signal; the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the first start signal and the second end signal to a second TDC among the plurality of TDCs; the first TDC provides a first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC; and the second TDC provides a second time difference, which is the time difference between the first start signal and the second end signal determined by the second TDC, to a circuit connected to the second TDC; the non-volatile recording medium readable by an electronic device.

12. A non-volatile recording medium readable by an electronic device according to claim 7, wherein the plurality of input signals include a first start signal, a second start signal, and a first end signal, the multiplexer is configured to supply the first start signal and the first end signal to a first TDC among the plurality of TDCs, and to supply the second start signal and the first end signal to a second TDC among the plurality of TDCs, the first TDC provides a first time difference, which is the time difference between the first start signal and the first end signal determined by the first TDC, to a circuit connected to the first TDC, and the second TDC provides a second time difference, which is the time difference between the second start signal and the first end signal determined by the second TDC, to a circuit connected to the second TDC, characterized in that the non-volatile recording medium readable by an electronic device.

13. A TDC system comprising: a PCB board (600) including an FPGA (1) according to any one of claims 1 to 6; and a computing device (700) for acquiring the generated time difference from the PCB board.

Images