Multi-acceleration card heterogeneous server and resource link reconfiguration method

Abstract

This disclosure provides a multi-accelerometer heterogeneous server and a method for reconfiguring a resource link. The multi-accelerometer heterogeneous server comprises a switch unit, a heterogeneous accelerated compute pooling unit, and a general-purpose compute resource pooling unit, wherein the general-purpose compute resource pooling unit includes at least one processor, the heterogeneous accelerated compute pooling unit includes at least two accelerator cards, the processor and the accelerator cards are heterogeneous with respect to each other, the switch unit includes a management controller and at least two switch chips, either one of which is connected via an internal port to at least one other switch chip in the switch unit, the processor and accelerator cards are each connected to the switch chips, and the management controller is connected to each switch chip to reconfigure the resource link based on a pre-configured task resource request and the current chip information of each switch chip.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on January 31, 2024, with the application number 202410131445.7 and the invention title "Multi-Acceleration Card Heterogeneous Server and Resource Link Reconfiguration Method", and the entire content thereof is incorporated herein by reference. This disclosure relates to a multi-acceleration card heterogeneous server and a resource link reconfiguration method.

Background Art

[0002] A dedicated computing acceleration server is usually a heterogeneous server. For example, an artificial intelligence (AI) server has high requirements for computing power. Currently, the load of AI applications is developing very rapidly, and the demand for computing power is growing exponentially. Especially due to the rapid development of typical AI applications such as generative AI, large-scale models, and intelligent recommendations using deep learning, the entire system of AI heterogeneous servers also faces many challenges such as improving the efficiency of computing power and the performance of the system. In order to support the sustainable development of high-performance computing infrastructure, it is necessary to continuously strengthen research and innovation.

[0003] The total training speed of an AI model is equal to the product of the speed of a single card, the number of acceleration cards, and the multi-card acceleration ratio.

[0004] The speed of a single card is determined by the computing speed and the data I / O (Input / Output) speed, and it is necessary to optimize the training of a single card. The main technical means include accurate training, operator fusion, gradient accumulation, etc., which improve the training performance of a single card.

[0005] Regarding the number of acceleration cards, theoretically, the more acceleration cards there are, the faster the model will train. However, as the size of the training dataset increases further, there are limits to data parallel processing. When training resources are scaled up to a certain size, the limiting effect of adding computing resources (i.e., acceleration cards) becomes more pronounced due to the existence of communication technology bottlenecks, and it may become impossible to accelerate even by adding computing resources. In this case, it is necessary to optimize the network communication topology to improve the training mode.

[0006] The multi-card acceleration ratio is determined by computational and communication efficiency and needs to be optimized by combining the algorithm and the network communication topology within the cluster. Multi-card training efficiency can be improved by employing a multi-dimensional mixed-parallel strategy that combines Data Parallel (DP), Model Parallel (MP), and Pipeline Parallelism (PP).

[0007] Currently, performance is limited on a single acceleration card (e.g., GPU, Graphics Processing Unit), and improving the acceleration ratio of multi-card parallel computing has reached the limits of parallel algorithms and inter-device communication bandwidth. In this situation, increasing the number of acceleration cards is a direct means of improving the computational power and training speed of AI heterogeneous server systems. Therefore, when increasing the number of acceleration cards, optimizing the network communication efficiency between multiple acceleration cards and general-purpose computing resources (e.g., CPU, Central Processing Unit) to improve the processing performance of tasks (e.g., training large-scale models) is a technical challenge that urgently needs to be addressed. [Overview of the Initiative] [Means for solving the problem]

[0008] In the embodiments disclosed herein, the first aspect provides a multi-accelerometer heterogeneous server. The multi-accelerometer heterogeneous server comprises a switch unit, a heterogeneous accelerated compute pooling unit, and a general-purpose compute resource pooling unit, wherein the general-purpose compute resource pooling unit includes at least one processor, the heterogeneous accelerated compute pooling unit includes at least two accelerator cards, the processor and accelerator cards are heterogeneous with respect to each other, the switch unit includes a management controller and at least two switch chips, either one of which is connected to at least one other switch chip in the switch unit via an internal port, the processor is connected to the uplink port of the switch chip, the accelerator cards are connected to the downlink port of the switch chip, and the management controller is connected to each switch chip to determine a resource link reconfiguration command based on a pre-configured task resource request and the current chip information of each switch chip, transmit the resource link reconfiguration command to each target switch chip, and form a resource link to complete the compute task corresponding to the task resource request.

[0009] A second embodiment provides a resource link reconfiguration method. Implemented based on the multi-accelerometer heterogeneous server described in any one of the above paragraphs, the resource link reconfiguration method is applied to a management controller, and the resource link reconfiguration method includes: obtaining a task resource request and current chip information for each switch chip; determining a resource link reconfiguration command based on the task resource request and current chip information for each switch chip; and transmitting the resource link reconfiguration command to each target switch chip to form a resource link for completing a computation task corresponding to a task resource request.

[0010] A third embodiment provides a source link reconfiguration device. Implemented based on the multi-accelerometer heterogeneous server described in any one of the above paragraphs, the resource link reconfiguration device is applied to a management controller, and the resource link reconfiguration device includes: an information acquisition module that acquires a task resource request and current chip information for each switch chip; a command determination module that determines a resource link reconfiguration command based on the task resource request and current chip information for each switch chip; and a command transmission module that transmits the resource link reconfiguration command to each target switch chip to form a resource link for completing a computation task corresponding to the task resource request.

[0011] A fourth aspect provides an electronic device. The electronic device includes a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, and when the processor executes a program, it realizes the resource link reconfiguration method described in the second aspect.

[0012] In the fifth aspect, a non-temporary computer-readable storage medium is provided. The non-temporary computer-readable storage medium stores computer-readable instructions, and when a computer-readable instruction is executed by a processor, the resource link reconstruction method described in the second aspect is realized.

[0013] A detailed description of one or more embodiments of this application is presented in the following drawings and description. Other features and advantages of this application will become apparent from the specification, drawings and claims. [Brief explanation of the drawing]

[0014] To more clearly explain the technical concept in the embodiments of this application, the drawings necessary for use in the embodiments are briefly described below. Clearly, the drawings described below represent only a portion of the embodiments of this application, and those skilled in the art can obtain other drawings based on these without any creative effort. [Figure 1]This is a schematic diagram of the structure of a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 2] This is a schematic diagram of the dual switch chip fabric interconnect routing in a multi-accelerometer heterogeneous server according to one or more embodiments of the present invention. [Figure 3] This is a schematic diagram illustrating the functionality of the management controller within the switch unit of a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 4] This is a switch network topology diagram in which eight switch chips within a switch unit of a multi-accelerometer heterogeneous server are divided into two groups, according to one or more embodiments of the present application. [Figure 5] This is a schematic diagram of a heterogeneous server structure having 32 acceleration cards based on the switch network topology diagram of Figure 4, according to one or more embodiments of the present application. [Figure 6] This is a schematic diagram of a heterogeneous server structure of 16 acceleration cards having a switch network composed of 5 switch chips, according to one or more embodiments of the present application. [Figure 7] This is a schematic diagram of the hardware connection structure of a switch unit in a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 8] This is a schematic diagram of the data management link of a switch unit in a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 9] This is a data management link topology diagram of a switch unit and a heterogeneous accelerated computing pooling unit in a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 10] This is a schematic diagram of the hardware connection structure between a switch unit and a heterogeneous accelerated computing pooling unit in a multi-accelerometer heterogeneous server according to one or more embodiments of the present application. [Figure 11]A reset logic topology diagram of a multi-accelerator card heterogeneous server according to one or more embodiments of the present application. [Figure 12] A flow schematic diagram of a resource link reconstruction method based on a multi-accelerator card heterogeneous server according to one or more embodiments of the present application. [Figure 13] A structural schematic diagram of a resource link reconstruction device based on a multi-accelerator card heterogeneous server according to one or more embodiments of the present application. [Figure 14] A structural schematic diagram of an electronic device according to one or more embodiments of the present application. [Figure 15] A structural schematic diagram of a non-transitory computer-readable storage medium according to one or more embodiments of the present application.

Embodiments for Implementing the Invention

[0015] To make the technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the drawings of the present application. It should be noted that the described embodiments are only some embodiments of the present application and do not cover all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor shall fall within the protection scope of the present application.

[0016] As shown in FIG. 1, the multi-accelerator card heterogeneous server of the embodiment of the present disclosure includes a switch unit 100, a heterogeneous acceleration computing pooling unit 200, and a general-purpose computing resource pooling unit 300.

[0017] The general-purpose computing resource pooling unit 300 includes at least one processor 301 (i.e., CPU), and one or more processors 301 form a general-purpose computing resource pool to provide general-purpose computing resources for computing tasks. The heterogeneous acceleration computing pooling unit 200 includes at least two acceleration cards 201, and two or more acceleration cards 201 form an acceleration computing resource pool to provide acceleration computing resources for computing tasks. The processor 301 and the acceleration card 201 are heterogeneous to each other, and the acceleration card 201 is classified into different types according to different computing tasks. For example, it includes a graphics processing unit (GPU) for training a graphics artificial intelligence model, or a field programmable gate array (FPGA) chip of other computing types, etc.

[0018] The switch unit 100 includes a management controller 102 and at least two switch chips 101, where the switch chips 101 are high-performance I / O switch chips. One of the switch chips 101 is connected to at least one other switch chip 101 in the switch unit 100 via an internal port, the processor 301 is connected to the uplink port of the switch chip 101, and the acceleration card 201 is connected to the downlink port of the switch chip 101. Note that all ports on the switch chip 101 are high-speed interfaces and there is no logical distinction between them. Simply put, the port connecting the two switch chips 101 is an internal port, the port connecting the processor 301 is an uplink port, and the port connecting the acceleration card 201 is a downlink port. The switch chip 101 is connected to the processor 301 and the acceleration card 201, and an interconnection also exists between the switch chips 101. This allows for high-bandwidth, low-latency, and multipath interconnection between the acceleration cards 201, meeting the computational power requirements of high-performance computing tasks. Based on the computing task, it is possible to integrate homogeneous computing resources within the resource pool according to the difference between general-purpose computing processor resources and heterogeneous accelerated computing acceleration card resources. The hardware structure allows for the reorganization of different processor resources and acceleration card resources as needed, providing prerequisites for forming resource links.

[0019] Based on pre-configured task resource requests and current chip information for each switch chip 101, the management controller 102 determines a resource link reconfiguration command, sends the resource link reconfiguration command to each target switch chip, and connects to each switch chip 101 to form a resource link for completing the computation task corresponding to the task resource request. Here, the task resource request refers to information on the processor resources and acceleration card resources required to complete the computation task. This information includes the number of resources (for example, completing a training task for a large model requires 4 CPU resources and 16 GPU resources) and the allocation relationship (for example, 4 GPUs are allocated to 1 CPU). The chip information includes the switch chip ID, the port IDs of each port on the switch chip 101, the port bandwidth, the port rate, and port status information. The port status information includes port connection information and port usage information. The port connection information includes whether the port is connected to the processor 301, acceleration card 201, or other switch chip 101, and resource information of the connected processor 301 or acceleration card 201 (e.g., model number and performance parameters). The port usage information indicates whether the port is assigned to a resource link reconfigured for a particular computing task. If assigned, the port is in use, and the processor 301 or acceleration card 201 to which the port is connected is also in use. If not assigned, it indicates that the processor 301 or acceleration card 201 corresponding to the port is not in use and can be used for resource allocation for a new computing task.

[0020] Here, the resource link reconfiguration command includes the ID of each target switch chip for the link and the ID of the target port on each target switch chip in order to transmit the resource link reconfiguration command to the corresponding target switch chip, thereby establishing a communication protocol between the target switch chip on the resource link and its ports, as well as between the processor 301 and the acceleration card 201 connected to the ports, enabling efficient communication of data processed by the processor 301 and the acceleration card 201 via the target switch chip and completing the computing task.

[0021] In the multi-accelerometer heterogeneous server of the embodiment of the present invention, the switch chip 101 is connected to the processor 301 and the accelerator card 201, and an interconnection also exists between the switch chips 101. This provides high bandwidth, low latency, and multipath interconnection between the accelerator cards 201, meeting the computational power requirements of high-performance computing tasks. Based on the computing task, homogeneous computing resources in the resource pool can be integrated according to the difference between general-purpose computing processor resources and heterogeneous accelerated computing accelerator card resource categories. The hardware structure allows for the reorganization of different processor resources and accelerator card resources as needed, providing prerequisites for forming resource links. Based on this, the management controller 102 determines a resource link reconfiguration command based on a preset task resource request and the current switch chip 101 information, and transmits the resource link reconfiguration command to each target switch chip to form a resource link for completing the computing task corresponding to the task resource request. In other words, by selecting the appropriate switch chip 101 and corresponding port based on the task resource request and the current chip information of each switch chip 101, high network communication efficiency is achieved between multiple acceleration cards 201 and between the acceleration cards 201 and the processor 301, improving task processing performance. When more acceleration cards 201 are integrated into the server system, the objective of improving system computing performance by improving communication efficiency is achieved. Furthermore, the resource link is dynamically reconfigured based on the pre-configured task resource request and the current chip information of each switch chip 101, allowing for more flexible allocation of processor resources and acceleration card resources compared to a fixed resource link, thus avoiding resource waste.

[0022] In some embodiments, in order for the management controller 102 to easily obtain the chip information of the current switch chip 101, each switch chip 101 includes an embedded controller 1011, as shown in Figure 2, and the embedded controller 1011 enumerates the chip information of the switch chip 101 on which the embedded controller 1011 is located and transmits the chip information to the management controller 102. Specifically, the enumeration process is as follows: The embedded controller 1011 obtains the ID of the switch chip 101 on which the embedded controller 1011 is located, each switch chip 101 has a unique ID, which may also be the unique identification code of the switch chip 101, and obtains the number of each port on the switch chip 101 to form the ID of each port by combining the ID of the switch chip 101 and the port number, the ID of the port is a global ID, and each port ID of each switch chip 101 is unique. In Figure 2, two switch chips 101 are shown, each with three ports, and their respective switch chip IDs are 0001 and 0002. For each port of switch chip 101 with switch chip ID 0001, the corresponding port IDs are 0001:01:00.0, 0001:02:00.0, and 0001:03:00.0. For each port of switch chip 101 with switch chip ID 0002, the corresponding port IDs are 0002:01:00.0, 0002:02:02:00.0, and 0002:03:00.0. For each port, the embedded controller 1011 can obtain whether an acceleration card 201, processor 301, or other switch chip 101 is connected to that port, and if so, can also obtain resource information for the acceleration card 201 or processor 301. The port bandwidth and port rate are technical parameters of the switch chip 101, and the embedded controller 1011 can be obtained from the technical parameters of the switch chip 101.

[0023] In this embodiment, the embedded controller 1011 in each switch chip 101 actively uploads chip information to the management controller 102. This eliminates the need for the management controller 102 to actively access the switch chip 101 to obtain further corresponding chip information, reducing the utilization of the communication network within the switch unit 100 and improving communication efficiency during computation task processing.

[0024] Specifically, after receiving chip information transmitted from each embedded controller 1011, the management controller 102 can globally control the communication network topology formed by each switch chip 101 in the switch unit 100, maintain a global information table containing the chip information of each switch chip 101, and enumerate the virtual bridges of the switch unit 100 based on this global information table, thereby enabling unified management of acceleration card resources and processor resources connected to the switch chip 101.

[0025] Furthermore, after the target switch chip receives a resource link reconfiguration command from the management controller 102, the embedded controller 1011 in each target switch chip also changes the port usage information of the corresponding port within the target switch chip and sends the updated chip information to the management controller 102. As a result, the management controller 102 updates the chip information of each switch chip 101, that is, updates the global information table described above.

[0026] In some embodiments, the management controller 102 aims to minimize link communication overhead by looking up the target switch chip ID and target port ID on each target switch chip based on a pre-configured task resource request, the switch chip ID, the port ID of each switch chip, the port bandwidth, the port rate, port connection information, and port usage information, and generates a resource link reconfiguration command that includes the target switch chip ID and target port ID on each target switch chip. Specifically, the management controller 102 can implement TLP (Transaction Layer Packet) forwarding based on global address IDs, establish Destination Look Up Tables (DLUTs), and implement TLP routing for complex topologies. Here, minimizing link communication overhead can be done by minimizing data transmission delay. Aiming to minimize link communication overhead, based on the task resource request, switch chip ID, each port ID of the switch chip, port connection information of switch chip 101, and port usage information, first, an unassigned port of switch chip 101 is searched for. Next, based on the port bandwidth and port rate, a target switch chip ID and target port ID on each target switch chip are searched for that can minimize the data transmission delay of the resource link. The specific search algorithm is similar to the routing algorithm of network routing, and it is sufficient to pre-write this routing algorithm to the management controller 102.

[0027] The management controller 102 can not only reconfigure resource links by searching for target switch chip IDs and target port IDs on each target switch chip based on a pre-configured routing algorithm, but can also reconfigure resource links based on user-selected target switch chip IDs and target port IDs on each target switch chip. Accordingly, in some embodiments, the management controller 102 displays a pre-configured task resource request, switch chip ID, each port ID of the switch chip, port bandwidth, port rate, port connection information, and port usage information on a display device as a graphical user interface, and receives resource link reconfiguration commands input from the graphical user interface. Specifically, the management controller 102 displays the acquired switch chip ID, each port ID of the switch chip, port bandwidth, port rate, port connection information of switch chip 101, and port usage information in the form of a network topology diagram on the display interface. The user can intuitively see which ports on switch chip 101 are assigned to resource links, and further, select a resource link from an unassigned port to satisfy the task resource request. Of course, the user's selection can be based on a calculation method to choose the resource link that minimizes communication overhead.

[0028] As shown in Figure 3, the management controller 102 in the above embodiment communicates with the embedded controller 1011 on the switch chip 101, unlike the management controller in a conventional link-fixed heterogeneous resource server system, and can acquire relevant information about the ports of the switch chip 101 (IO ports in Figure 3) in real time. It can also set port properties, including the port type (uplink port, internal port, or downlink port), port bifurcation (branching) settings, port clock settings, and port resource reservation settings (not connected to acceleration card 201, processor 301, and other switch chips 101). Based on the Fabric connection between the switch chips 101, it realizes TLP forwarding, GID (Global Identification) address routing, and DLUT establishment and maintenance, thereby retrieving the target switch chip ID and port ID on the target switch chip corresponding to the resource link. Of course, the management controller 102 also has other functions found in conventional link-fixed heterogeneous resource server systems, such as providing a wealth of peripheral low-speed protocols like UART (Universal Asynchronous Receiver / Transmitter) and GPIO (General-Purpose Input / Output Ports), supporting safe startup, ensuring chip safety, and supporting fault monitoring mechanisms such as AER (Advanced Error Reporting) and real-time monitoring of I / O resource health.

[0029] In some embodiments, as shown in Figure 4, the switch unit 100 includes two switch chip groups, where the top row of switch chips 101 in Figure 4 is one group and the bottom row of switch chips 101 is another group, each switch chip group includes at least one switch chip 101, where there are four switch chips 101 per group, and the number of switch chips 101 in each switch chip group is less than the total number of ports of the switch chips 101. Any one switch chip 101 in the first switch chip group is connected via an internal port to each switch chip 101 in the second switch chip group, and any one switch chip 101 in the second switch chip group is connected via an internal port to each switch chip 101 in the first switch chip group, that is, any one switch chip 101 in the same group is fully connected to all switch chips 101 in the other group, and the switch chips within the same switch chip group are not directly connected. On all remaining ports of the switch chip 101, at least one port is connected to the processor 301 as an uplink port, and at least two ports are connected to the downlink port acceleration card 201. Specifically, all remaining ports of the switch chip 101 are connected to either the processor 301 or the acceleration card 201. The server system of this embodiment can realize that multiple processors 301 share an acceleration card resource pool, and can also realize the integration of multiple heterogeneous acceleration cards 201 within a single server system.

[0030] Furthermore, as shown in Figure 5, each of the switch chip groups includes four switch chips 101, each switch chip 101 having nine ports, and each switch chip 101 in the first switch chip group is connected to each of the four switch chips 101 in the second switch chip group via four internal ports, and each switch chip 101 in the second switch chip group is connected to each of the four switch chips 101 in the first switch chip group via four internal ports, meaning that each switch chip 101 provides five external ports. Of the remaining 40 ports of all the switch chips 101, eight ports are connected to eight processors 301 as uplink ports, and the remaining 32 ports are connected to 32 acceleration cards 201 as downlink ports. Figure 5 is a schematic diagram of a multi-accelerometer heterogeneous server structure with eight processors 301 and 32 acceleration cards. The switch chip 101 is designed to be divided into two groups, with the switch chip 101 between the groups being fully connected via internal ports. Of the remaining 40 ports, eight uplink ports are connected to eight processors 301, and 32 downlink ports are connected to 32 acceleration cards 201. These 32 acceleration cards 201 could, for example, be used to create an artificial intelligence model where 32 GPUs can complete large-scale graphics training.

[0031] Here, the 32 acceleration cards 201 and the 8 processors 301 may all be different types of devices. As shown in Figure 5, the acceleration cards 201 include GPUs, FPGAs, and NPUs (Neural Processing Units) to complete different types of computational tasks simultaneously, while the processors 301 include AMD CPUs and Intel CPUs, enabling them to complete computational tasks developed under different CPU architectures and providing greater flexibility in handling computational tasks.

[0032] In some embodiments, the switch unit 100 includes multiple switch chips 101, the number of switch chips 101 being less than the number of ports on each switch chip 101, and any one switch chip 101 being connected to all the remaining switch chips 101 via its internal ports, i.e., any one switch chip 101 being fully connected to the other switch chips 101. Of the remaining ports on all switch chips 101, at least one port is connected to the processor 301 as an uplink port, and at least two ports are connected to the acceleration card 201 as downlink ports. In this embodiment, all switch chips 101 are fully connected, and the server system integrates multiple acceleration cards 201 while using the server's internal bus switch as the core, ensuring the bandwidth and efficiency of the multiple acceleration cards with an unblocked internal bus switch, reducing communication delay, improving the parallel processing capability of artificial intelligence, effectively solving the problem of insufficient computing power of a single acceleration card, and further improving the computing power of the system.

[0033] Furthermore, as shown in Figure 6, the switch unit includes six switch chips 101, namely SW0 to SW5 in Figure 6, each switch chip 101 having nine ports, with any one switch chip 101 connected to all the remaining switch chips 101 via five internal ports, and of the remaining ports of all switch chips 101, 16 ports are connected to the acceleration cards as downlink ports, namely GPU0 to GPU15 in Figure 6, and the remaining at least four ports are connected to the four processors as uplink ports, namely CPU0 to CPU3. This embodiment is a schematic diagram of a multi-accelerometer heterogeneous server structure with four processors 301 and sixteen acceleration cards 201, where the switch chips 101 form a fully connected communication topology network.

[0034] In some embodiments, at least one processor 301 is connected to the uplink ports of different switch chips 101. For example, CPU3 in Figure 6 may be replaced with CPU0, i.e., CPU0 is connected to ports connected to SW0 and SW2, respectively. In particular, when the number of resources of the processor 301 is small, one processor 301 can connect to the uplink ports of two or more switch chips 101, and when reconfiguring resource links, it is possible to select links that pass through fewer switch chips 101, thereby increasing communication efficiency and improving the processing performance of computing tasks.

[0035] As shown in Figures 7 and 8, the switch unit 100 further includes a first board controller 103 and a first complex programmable logic chip 104, the first board controller 103 being connected to the first complex programmable logic chip 104 and a management controller 102, and the first complex programmable logic chip 104 being connected to the management controller 102 and a switch chip 101. Of course, the switch unit 100 further includes a clock generator 105 and a power supply module 106, the power supply module 106 supplying power to the switch chip 101, the management controller 102, the first board controller 103, the first complex programmable logic chip 104, and the clock generator 105. The ports connecting the acceleration card 201 and the processor 301 to the switch chip 101, and the ports interconnecting the switch chips 101 are high-speed interfaces for data transmission, while the management controller 102, the first board controller 103, and the first complex programmable logic chip 104 are each connected to the switch chip 101 via control interfaces (i.e., low-speed interfaces).

[0036] The first complex programmable logic chip 104 controls the power-on / power-off sequence of the management controller 102 and the switch chip 101. Specifically, it controls the power-on / power-off sequence of the management controller 102 and the switch chip 101 in combination with the clock generator 105.

[0037] The first board controller 103 writes a pre-configured task resource request to the management controller 102 and receives link information of the resource link fed back from the management controller. The link information includes the processor ID, acceleration card ID, switch chip ID, and port ID on the switch chip that the resource link occupies. The task resource request is input to the first board controller 103 by the application, then written to the management controller 102 by the first board controller 103, and after receiving the link information of the resource link, the first board controller 103 feeds the link information back to the front-end application.

[0038] Specifically, as shown in Figures 7 and 8, the management controller 102 and the first board controller 103 are connected to the switch chip 101 based on various interconnection links such as a UART expansion board, a USB expansion board, and an I2C expansion board, thereby establishing the internal management network of the high-performance switch unit 100.

[0039] Furthermore, as shown in Figures 7 to 9, there are two management controllers 102, a first management controller 1021 and a second management controller 1022 which are redundant to each other, and the first management controller 1021 and the second management controller 1022 are connected via a first switching chip 107, the first switching chip 107 is connected to a first board controller 103, and the first board controller 103 further receives fault information transmitted from the first management controller 1021 or the second management controller 1022. After receiving fault information 1021 from the first management controller, the first switching chip 107 is controlled to disconnect the connection between the first management controller 1021 and the switch chip 101, and switch to the connection between the second management controller 1022 and the switch chip 101, or after receiving fault information 1022 from the second management controller, the first switching chip 107 is controlled to disconnect the connection between the second management controller 1022 and the switch chip 101, and switch to the connection between the first management controller 1021 and the switch chip 101. In the actual hardware structure, because there are many switch chips 101 and acceleration cards 201, the first management controller 1021 and the second management controller 1022 are connected to the switch chip 101 via an I2C expansion board, and the switch chip 101 is connected to the acceleration card 201 via an I2C expansion board.

[0040] In this embodiment, the first management controller 1021 and the second management controller 1022 are designed to be redundant with respect to each other. The first board controller 103 writes task resource requests to the first management controller 1021 and the second management controller 1022. If one management controller 102 fails, the first board controller 103 switches to the other management controller 102 to continue operation, thereby ensuring the stability of the server system.

[0041] In some embodiments, as shown in Figure 9, the heterogeneous accelerated computation pooling unit 200 further includes a second board controller 202 and a second complex programmable logic chip 203, the second board controller 202 being connected to the second complex programmable logic chip 203 and the acceleration card 201. The second complex programmable logic chip 203 controls the power-on / power-off sequence of the acceleration card 201. The second board controller 202 acquires the status information of the acceleration card.

[0042] Furthermore, the heterogeneous accelerated computing pooling unit 200 further includes a second switching chip 204, and the acceleration card 201 is connected to the second board controller 202, the second complex programmable logic chip 203, and the switch chip 101 via the second switching chip 204. The second board controller 202 controls the second switching chip 204 to switch the connection between the acceleration card 201 and the second board controller 202, and in particular, when there are many acceleration cards 201, it controls the connection between the acceleration card 201 assigned to the resource link and the second board controller 202, and obtains status information of the acceleration card 201.

[0043] In some embodiments, as shown in Figure 10, the heterogeneous accelerated computing pooling unit 200 further includes an interface board 400 and a relay board 500, on which a relay interface 501 and a slot 502 are provided. Here, the interface board 400 is a high-speed interface board for connecting the acceleration card 201 and the switch chip 101. Each connection on the interface board 400 includes two high-speed interfaces and one high-speed signal retimer, with the two high-speed interfaces each connected to the high-speed signal retimer, and of the two high-speed interfaces, one is connected to the acceleration card 201 and the other is connected to the switch chip 101. In actual applications, especially when there are many acceleration cards 201 and switch chips 101, considering the actual volume size and spatial layout of the server chassis, the multiple switch chips 101 and acceleration cards 201 can have the following three connection methods.

[0044] Method 1: The acceleration card 201 is connected to the interface board 400 via the relay card 600, and the interface board 400 is connected to the downlink port of the switch chip 101. Specifically, the acceleration card 201 is connected via the relay card 600 to the high-speed interface on the interface board 400 that is closer to the heterogeneous acceleration computation pooling unit 200, and the high-speed interface on the interface board 400 that is closer to the switch unit 100 is connected to the switch chip 101.

[0045] Method 2: The acceleration card 201 is connected to the relay interface 501 in the relay board 500 via the relay card 600, the relay interface 501 is connected to the interface board 400, and the interface board 400 is connected to the downlink port of the switch chip 101. Specifically, the relay interface 501 is connected to the high-speed interface on the interface board 400 that is closer to the heterogeneous acceleration calculation pooling unit 200, and the high-speed interface on the interface board 400 that is closer to the switch unit 100 is connected to the switch chip 101.

[0046] Method 3: The acceleration card 201 is connected to slot 502, slot 502 is connected to relay interface 501, relay interface 501 is connected to interface board 400, and interface board 400 is connected to the downlink port of switch chip 101. Specifically, relay interface 501 is connected to the high-speed interface on interface board 400 that is closer to the heterogeneous acceleration calculation pooling unit 200, and the high-speed interface on interface board 400 that is closer to the switch unit 100 is connected to switch chip 101.

[0047] The three connection methods described above enable a flexible layout of the switch chip 101 and acceleration card 201 in the multi-acceleration card server.

[0048] In some embodiments, as shown in Figure 11, the general-purpose computing resource pooling unit 300 further includes a third board controller 302 and a third complex programmable logic chip 303, with the third board controller 302 connected to the third complex programmable logic chip 303 and the processor 301. The third complex programmable logic chip 303 controls the power-on / power-off sequence of the processor 301. The third board controller 302 acquires status information of the processor 301.

[0049] In some embodiments, as shown in Figure 11, the switch unit 100 further includes a first board controller 103 and a first complex programmable logic chip 104, the first complex programmable logic chip 104 being connected to the switch chip 101, the first board controller 103, and the management controller 102, respectively, and the management controller 102 being connected to the first board controller 103.

[0050] The heterogeneous accelerated computation pooling unit 200 further includes a second board controller 202 and a second complex programmable logic chip 203, the second complex programmable logic chip 203 being connected to the acceleration card 201 and the second board controller 202, respectively.

[0051] The general-purpose computing resource pooling unit 300 further includes a third board controller 302 and a third complex programmable logic chip 303, the third complex programmable logic chip 303 being connected to the processor 301 and the third board controller 302, respectively.

[0052] The first board controller 103, the second board controller 202, the third board controller 302, and the management controller 102 are all connected to an external TOR switch 700 via Ethernet and interact with external applications through the TOR switch 700.

[0053] In this embodiment, the third complex programmable logic chip 303 is connected to the first complex programmable logic chip 104, and the first complex programmable logic chip 104 is connected to the second complex programmable logic chip 203. Each complex programmable logic chip controls the power-on / power-off sequence of each unit located therein. The second complex programmable logic chip 203 first controls the power-on of the heterogeneous accelerated computing pooling unit 200, specifically controlling the power-on of the acceleration card 201 and the second board controller 202. Next, the first complex programmable logic chip 104 controls the power-on of the switch unit 100, specifically further controlling the power-on of the switch chip 101 and the first board controller 103. Finally, the third complex programmable logic chip 303 controls the power-on of the general-purpose computing resource pooling unit 300, specifically controlling the power-on of the processor 301 and the third board controller 302, thereby ensuring the timing accuracy of the entire server system. In relation to a particular resource link, the acceleration card 201, switch chip 101, and processor 301 are powered on in that order, but the power-off and power-on sequences are reversed. In the event of an emergency (e.g., a resource link failure), each device in the link corresponding to each complex programmable logic chip performs a reset restart or power-off operation to ensure the stable and reliable operation of the other links.

[0054] In actual applications, the management controller 102 in each of the above embodiments constructs a resource reconfiguration decision system that senses business operations through software definition, realizing functions such as dynamic allocation of uplink / downlink resource links, link topology switching, and dynamic reconfiguration of data links, thereby completing intelligent reconfiguration of hardware resources. This enables pooling and centralized management of processor resources and acceleration card resources, allowing for dynamic adjustment, flexible combination, and intelligent allocation, improving the overall computational efficiency and response speed of the system, and realizing intelligent and highly efficient heterogeneous computing. As a result, the multi-accelerometer heterogeneous servers in each of the above embodiments can meet the application requirements of currently mainstream large-scale artificial intelligence models and other large-scale computing business scenarios. Furthermore, the multi-accelerometer heterogeneous servers in the above embodiments can realize an ultra-large-scale computing resource cluster by clustering the entire system network between multiple devices, and this clustering method is realized through Ethernet switches.

[0055] This disclosure provides a resource link reconfiguration method, which is implemented based on the multi-accelerometer heterogeneous server of each embodiment, and which is applied to a management controller, and as shown in Figure 12, the resource link reconfiguration method includes steps 1210, 1220, and 1230.

[0056] Step 1210: Obtain task resource requests and current chip information for each switch chip. Specifically, referring to Figures 1 and 2, the management controller 102 obtains task resource requests and current chip information for each switch chip 101. The management controller 102 can obtain current chip information for each switch chip 101 from the embedded controller 1011 within each switch chip 101. After receiving the chip information transmitted from each embedded controller 1011, the management controller 102 can globally control the communication network topology formed by each switch chip 101 in the switch unit 100, maintain a global information table containing the chip information for each switch chip 101, and based on this global information table, enumerate the virtual bridges of the switch unit 100, thereby enabling unified management of acceleration card resources and processor resources connected to the switch chip 101.

[0057] Step 1220: Determine a resource link reconfiguration command based on the task resource request and the current chip information of each switch chip. Specifically, the management controller 102 determines a resource link reconfiguration command based on a pre-configured task resource request, the switch chip ID, the port bandwidth, the port rate, the port connection information, and the port usage information.

[0058] Step 1230: Resource link reconfiguration commands are sent to each target switch chip to form a resource link for completing the computation task corresponding to the task resource request. Specifically, the management controller 102 sends a resource link reconfiguration command to each target switch chip, including the ID of each target switch chip and the ID of the target port on each target switch chip. This establishes a communication protocol between the target switch chip and its port on the resource link, as well as between the processor 301 and the acceleration card 201 connected to the port, enabling efficient communication of data processed by the processor 301 and the acceleration card 201 via the target switch chip and completing the computation task.

[0059] The resource link reconfiguration method of the present invention is implemented by the multi-accelerometer heterogeneous server. The switch chip 101 is connected to the processor 301 and the accelerator card 201, and an interconnection also exists between the switch chips 101. This provides high bandwidth, low latency, and multipath interconnection between the accelerator cards 201, meeting the computational power requirements of high-performance computing tasks. Based on the computing task, it is possible to integrate similar computing resources in the resource pool according to the difference between general-purpose computing processor resources and heterogeneous accelerated computing accelerator card resource categories. The hardware structure reorganizes different processor resources and accelerator card resources as needed, providing prerequisites for forming a resource link. Based on this, the management controller 102 determines a resource link reconfiguration command based on a preset task resource request and the current switch chip 101 information, and transmits the resource link reconfiguration command to each target switch chip to form a resource link for completing the computing task corresponding to the task resource request. In other words, by selecting the appropriate switch chip 101 and corresponding port based on the task resource request and the current chip information of each switch chip 101, high network communication efficiency is achieved between multiple acceleration cards 201 and between the acceleration cards 201 and the processor 301, improving task processing performance. When more acceleration cards 201 are integrated into the server system, the objective of improving system computing performance by improving communication efficiency is achieved. Furthermore, the resource link is dynamically reconfigured based on the pre-configured task resource request and the current chip information of each switch chip 101, allowing for more flexible allocation of processor resources and acceleration card resources compared to a fixed resource link, thus avoiding resource waste.

[0060] Step 1220: Aiming to minimize link communication overhead, the target switch chip ID and target port IDs on each target switch chip are retrieved based on a pre-configured task resource request, switch chip ID, each port ID on the switch chip, port bandwidth, port rate, port connection information, and port usage information, and a resource link reconfiguration command including the target switch chip ID and target port IDs on each target switch chip is generated. Specifically, referring to Figures 1 and 7, the management controller 102 can implement TLP (Transaction Layer Packet) forwarding based on global address IDs, establish Destination Look Up Tables (DLUTs), and implement TLP routing for complex topologies. Here, minimizing link communication overhead can be done by minimizing data transmission delay. Aiming to minimize link communication overhead, based on the task resource request, switch chip ID, each port ID of the switch chip, port connection information, and port usage information, first, an unassigned port on switch chip 101 is searched for. Then, based on the port bandwidth and port rate, a target switch chip ID and target port ID on each target switch chip are searched for that can minimize the data transmission delay of the resource link. The specific search algorithm is similar to the routing algorithm of network routing, and it is sufficient to pre-write this routing algorithm to the management controller 102.

[0061] Step 1220 described above is also implemented in the following manner, and step 1220 includes displaying a pre-configured task resource request, a switch chip ID, switch chip port connection information, and port usage information on a display device using a graphical user interface, and receiving a resource link reconfiguration command input from the graphical user interface.

[0062] Specifically, referring to Figures 1 and 7, the management controller 102 displays the pre-configured task resource request, the switch chip ID, and the port connection information and port usage information of the switch chip 101 on a display device using a graphical user interface, and receives resource link reconfiguration commands input from the graphical user interface. Specifically, based on the acquired switch chip ID, each port ID of the switch chip, the port bandwidth, the port rate, the port connection information and port usage information of the switch chip 101, the management controller 102 displays each switch chip ID, each port ID of the switch chip, the port bandwidth, the port rate, and the port connection information and port usage information of the switch chip 101 in the form of a network topology diagram on the display interface. The user can intuitively see which ports on the switch chip 101 are assigned to resource links, and can further select a resource link from an unassigned port to satisfy the task resource request. By switching the graphical user interface, a resource link reconfiguration command is input to the management controller 102. Of course, the user's selection can be based on a manual calculation method to select a resource link that minimizes communication overhead.

[0063] The resource link reconfiguration device provided in this application is described below. The following resource link reconfiguration device and the resource link reconfiguration method described above are mutually referential.

[0064] The resource link reconfiguration device of the present invention is implemented based on the multi-accelerometer heterogeneous server, and the resource link reconfiguration device is applied to the management controller of the multi-accelerometer heterogeneous server, and the resource link reconfiguration device includes, as shown in Figure 13, an information acquisition module 1310 that acquires a task resource request and current chip information for each switch chip, a command determination module 1320 that determines a resource link reconfiguration command based on the task resource request and current chip information for each switch chip, and a command transmission module 1330 that transmits a resource link reconfiguration command to each target switch chip to form a resource link for completing a computation task corresponding to the task resource request.

[0065] The resource link reconfiguration device of the present invention is implemented based on the multi-accelerometer heterogeneous server described above. Since the switch chip is connected to the processor and the accelerator card, and interconnections also exist between the switch chips, it is possible to provide high-bandwidth, low-latency, and multipath interconnections between accelerator cards, thereby meeting the computational power requirements of high-performance computing tasks. Based on the computing task, it is possible to integrate homogeneous computing resources in the resource pool according to the difference between general-purpose computing processor resources and heterogeneous accelerated computing accelerator card resource categories, and to reorganize different processor resources and accelerator card resources as needed on the hardware structure, providing the prerequisites for forming a resource link. Based on this, the management controller determines a resource link reconfiguration command based on a pre-configured task resource request and the current switch chip information, transmits the resource link reconfiguration command to each target switch chip, and forms a resource link to complete the computing task corresponding to the task resource request. In other words, by selecting the appropriate switch chip and corresponding port based on the task resource request and the current chip information of each switch chip, high network communication efficiency is achieved between multiple acceleration cards and between acceleration cards and processors, improving task processing performance. When more acceleration cards are integrated into a server system, the system achieves the objective of improving system computing performance by improving communication efficiency. Furthermore, the resource link is dynamically reconfigured based on the pre-configured task resource request and the current chip information of each switch chip, allowing for more flexible allocation of processor resources and acceleration card resources compared to conventional fixed resource links, thus avoiding resource waste.

[0066] Selectively, the command determination module 1320, aiming to minimize link communication overhead, searches for the target switch chip ID and the target port ID on each target switch chip based on a pre-configured task resource request, the switch chip ID, the port ID of each switch chip, the port bandwidth, the port rate, port connection information, and port usage information, and generates a resource link reconfiguration command that includes the target switch chip ID and the target port ID on each target switch chip.

[0067] Selectively, the command determination module 1320 displays a graphical user interface on a display device the pre-configured task resource request, the switch chip ID, the ID of each port on the switch chip, the port bandwidth, the port rate, port connection information, and port usage information, and receives resource link reconfiguration commands input from the graphical user interface.

[0068] Figure 14 is an example of a schematic diagram showing the physical structure of an electronic device. As shown in Figure 14, the electronic device includes a processor 1410, a communications interface 1420, a memory 1430, and a communications bus 1440. Here, the processor 1410, the communications interface 1420, and the memory 1430 communicate with each other via the communications bus 1440. The processor 1410 can call logical instructions in the memory 1430 to execute the resource link reconfiguration method described in one or more of the embodiments described above.

[0069] Furthermore, the logical instructions in the memory 1430 can be implemented in the form of a software function unit and, if sold or used as an independent product, can be stored on a single computer-readable storage medium. Based on this understanding, the essence of the proposed technology of the present application, or its contribution to the prior art, or a part thereof, can be embodied in the form of a software product, which is stored on a single storage medium and contains several instructions for a single computer device (which may be a personal computer, server, or network device, etc.) to perform all or some of the steps of the methods of each embodiment of the present application. The storage medium includes various media capable of storing program code, such as USB disks, portable hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] In another embodiment, the present application further provides a computer-readable instruction product comprising computer-readable instructions, the computer-readable instructions being storable on a non-temporary computer-readable storage medium, and when the computer-readable instructions are executed by a processor, the computer can perform the resource link reconfiguration method described in any one or more of the embodiments described above.

[0071] In another embodiment, the present invention further provides a non-temporary computer-readable storage medium. Referring to Figure 15, a computer-readable instruction is stored thereon, and when the computer-readable instruction is executed by a processor, it is implemented to execute the resource link reconfiguration method described in any one or more embodiments. The resource link reconfiguration method is implemented based on the multi-accelerometer heterogeneous server of any one or more embodiments, and the resource link reconfiguration method is applied to a management controller.

[0072] The embodiments of the apparatus described above are merely illustrative. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, meaning they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected as needed to achieve the objectives of this embodiment. Those skilled in the art will be able to understand and implement it without expending any creative work.

[0073] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be realized by adding software to an essential general-purpose hardware platform, and of course, by hardware alone. Based on this understanding, the essence of the above-described invention, or its contribution to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM / RAM, magnetic disk, or optical disk, and which includes several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to perform each embodiment or a part of the embodiment.

[0074] Finally, it should be noted that the above embodiments are for illustrative purposes only and do not limit the technical proposal of the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that it is still possible to modify the technical proposal described in the above embodiments or to substitute some of the technical features therein with equivalent substitutes, and such modifications or substitutions do not deviate the essence of the corresponding technical proposal from the spirit and scope of the technical proposal of each embodiment of the present application. [Explanation of symbols]

[0075] 0-3 CPU 100 Switch Units 101 Switch Chip 102 Management Controller 103 First board controller 104 First Complex Programmable Logic Chip 105 Clock Generator 106 Power Modules 107 First switching chip 200 Heterogeneous Accelerated Computing Pooling Units 201 Acceleration Card 202 Second board controller 203 Second Complex Programmable Logic Chip 204 Second switching chip 300 General-Purpose Computing Resource Pooling Units 301 Multiprocessor 302 Third board controller 303 Third Complex Programmable Logic Chip 400 Interface Board 500 relay boards 501 Relay Interface 502 slots 600 Relay Card 700 TOR switch 1011 Embedded Controller 1021 First Management Controller 1022 Second Management Controller 1310 Information Acquisition Module 1320 Command Decision Module 1330 Command Transmission Module 1410 Processor 1420 Communication Interface 1430 memory 1440 Communications Bus

Claims

1. A multi-accelerator-card heterogeneous server, It comprises a switch unit, a heterogeneous accelerated-computing pooling unit, and a general-purpose computing resource pooling unit. The general-purpose computing resource pooling unit includes at least one processor, and the heterogeneous accelerated computing pooling unit includes at least two acceleration cards, wherein the processor and the acceleration cards are heterogeneous with respect to each other. The switch unit includes a management controller and at least two switch chips, wherein one of the switch chips is connected via an internal port to at least one other switch chip in the switch unit, the processor is connected to the uplink port of the switch chip, and the acceleration card is connected to the downlink port of the switch chip. Based on a pre-configured task resource request and the current chip information of each switch chip, the management controller determines a resource link reconfiguration command, transmits the resource link reconfiguration command to each target switch chip, and connects to each of the switch chips to form a resource link for completing the computing task corresponding to the task resource request. Multi-acceleration card heterogeneous server.

2. Each switch chip includes an embedded controller, the embedded controller enumerates the chip information of the switch chip on which the embedded controller is located, and transmits the chip information to the management controller. The multi-accelerometer heterogeneous server according to claim 1.

3. The management controller aims to minimize link communication overhead by searching for the target switch chip ID and the target port ID on each target switch chip based on the pre-configured task resource request, the switch chip ID, the port ID of each switch chip, the port bandwidth, the port rate, port connection information, and port usage information, and generates a resource link reconfiguration command that includes the target switch chip ID and the target port ID on each target switch chip. The multi-accelerometer heterogeneous server according to claim 1.

4. The management controller displays the pre-configured task resource request, switch chip ID, each port ID of the switch chip, port bandwidth, port rate, port connection information, and port usage information on a display device as a graphical user interface, and receives the resource link reconfiguration command input from the graphical user interface. The multi-accelerometer heterogeneous server according to claim 1.

5. The switch unit includes two switch chip groups, each switch chip group includes at least one switch chip, the number of switch chips in each switch chip group is less than the total number of ports of the switch chips, any one switch chip in the first switch chip group is connected to each switch chip in the second switch chip group via an internal port, any one switch chip in the second switch chip group is connected to each switch chip in the first switch chip group via an internal port, and of the remaining ports of all switch chips, at least one port is connected to the processor as an uplink port, and at least two ports are connected to the acceleration card as downlink ports. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

6. Any one of the aforementioned switch chip groups includes four switch chips, each switch chip having nine ports, any one switch chip in the first switch chip group is connected to four switch chips in the second switch chip group via four internal ports, any one switch chip in the second switch chip group is connected to four switch chips in the first switch chip group via four internal ports, and of the remaining ports of all switch chips, eight ports are connected to eight of the aforementioned processors as uplink ports, and the remaining 32 ports are connected to 32 of the aforementioned acceleration cards as downlink ports. The multi-accelerometer heterogeneous server according to claim 5.

7. The switch unit includes a plurality of switch chips, the number of switch chips is less than the number of ports on the switch chips, any one of the switch chips is connected to all the remaining switch chips via an internal port, at least one port on all the remaining ports of the switch chips is connected to the processor as an uplink port, and at least two ports are connected to the acceleration card as downlink ports. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

8. The switch unit includes six switch chips, each switch chip having nine ports, any one switch chip is connected to all the remaining switch chips via five internal ports, and of the remaining ports of all the switch chips, 16 ports are connected to the acceleration card as downlink ports, and at least four of the remaining ports are connected to the four processors as uplink ports. The multi-accelerometer heterogeneous server according to claim 7.

9. At least one processor is connected to the uplink port of a different switch chip. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

10. The switch unit further includes a first board controller and a first complex programmable logic chip, the first board controller is connected to the first complex programmable logic chip and the management controller, and the first complex programmable logic chip is connected to the management controller and the switch chip. The first complex programmable logic chip controls the power-on / power-off sequence of the management controller and the switch chip, The first board controller writes the pre-configured task resource request to the management controller and receives link information of the resource link fed back from the management controller, and the link information includes the processor ID, acceleration card ID, switch chip ID, and port ID on the switch chip that the resource link occupies. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

11. The aforementioned management controllers consist of two redundant first and second management controllers, connected to each other via a first switching chip, and the first switching chip is connected to the first board controller. The first board controller further receives fault information transmitted from the first management controller or the second management controller, After receiving fault information from the first management controller, the first switching chip is controlled to disconnect the connection between the first management controller and the switch chip, and switch to the connection between the second management controller and the switch chip, or After receiving fault information from the second management controller, the first switching chip is controlled to disconnect the connection between the second management controller and the switch chip, and then the connection is switched back to the connection between the first management controller and the switch chip. The multi-accelerometer heterogeneous server according to claim 10.

12. The heterogeneous accelerated computing pooling unit further includes a second board controller and a second complex programmable logic chip, the second board controller being connected to the second complex programmable logic chip and the acceleration card. The second complex programmable logic chip controls the power-on / power-off sequence of the acceleration card, The second board controller acquires the status information of the acceleration card. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

13. The heterogeneous accelerated computing pooling unit further includes a second switching chip, and the acceleration card is connected to the second board controller, the second complex programmable logic chip, and the switch chip via the second switching chip. The multi-accelerometer heterogeneous server according to claim 12.

14. The general-purpose computing resource pooling unit further includes a third board controller and a third complex programmable logic chip, the third board controller being connected to the third complex programmable logic chip and the processor, The third complex programmable logic chip controls the power-on / power-off sequence of the processor, The third board controller acquires the state information of the processor. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

15. The heterogeneous accelerated computing pooling unit further includes an interface board and a relay board, the relay board being provided with a relay interface and slots. The acceleration card is connected to the interface board via a relay card, and the interface board is connected to the downlink port of the switch chip. Alternatively, the acceleration card may be connected to the relay interface via a relay card, the relay interface may be connected to the interface board, and the interface board may be connected to the downlink port of the switch chip. Alternatively, the acceleration card may be connected to the slot, the slot to the relay interface, the relay interface to the interface board, and the interface board to the downlink port of the switch chip. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

16. The switch unit further includes a first board controller and a first complex programmable logic chip, the first complex programmable logic chip being connected to the switch chip, the first board controller, and the management controller, respectively, and the management controller being connected to the first board controller. The heterogeneous accelerated computing pooling unit further includes a second board controller and a second complex programmable logic chip, the second complex programmable logic chip being connected to the acceleration card and the second board controller, respectively. The general-purpose computing resource pooling unit further includes a third board controller and a third complex programmable logic chip, the third complex programmable logic chip being connected to the processor and the third board controller, respectively. The third complex programmable logic chip is connected to the first complex programmable logic chip, and the first complex programmable logic chip is connected to the second complex programmable logic chip. A multi-accelerometer heterogeneous server according to any one of claims 1 to 4.

17. A method for reconfiguring resource links, Implemented based on the multi-accelerometer heterogeneous server described in any one of claims 1 to 16, wherein the resource link reconfiguration method is applied to the management controller, and the resource link reconfiguration method is To obtain task resource requests and current chip information for each switch chip, Based on the aforementioned task resource request and the current chip information of each switch chip, a resource link reconfiguration command is determined. This includes transmitting the resource link reconfiguration command to each target switch chip to form a resource link for completing the computation task corresponding to the task resource request, Resource link reconfiguration method.

18. The above-mentioned task resource request and the current chip information of each switch chip determine the resource link reconfiguration command. With the aim of minimizing link communication overhead, the system includes searching for the target switch chip ID and the target port ID on each target switch chip based on the pre-configured task resource request, the switch chip ID, the port ID of each switch chip, the port bandwidth, the port rate, port connection information, and port usage information, and generating a resource link reconfiguration command that includes the target switch chip ID and the target port ID on each target switch chip. The resource link reconstruction method according to claim 17.

19. The above-mentioned task resource request and the current chip information of each switch chip determine the resource link reconfiguration command. The aforementioned pre-configured task resource request, switch chip ID, each port ID of the switch chip, port bandwidth, port rate, port connection information, and port usage information are displayed graphically on a display device as a user interface. This includes receiving the resource link reconfiguration command input from a graphical user interface, The resource link reconstruction method according to claim 17.

20. Resource link reconfiguration device, Implemented based on the multi-accelerometer heterogeneous server described in any one of claims 1 to 15, wherein the resource link reconfiguration device is applied to the management controller, and the resource link reconfiguration device is An information acquisition module that obtains task resource requests and current chip information for each switch chip, A command determination module that determines a resource link reconfiguration command based on the aforementioned task resource request and the current chip information of each switch chip, A command transmission module that transmits the resource link reconfiguration command to each target switch chip, thereby forming a resource link for completing the computation task corresponding to the task resource request, is included. Resource link reconfiguration device.

21. An electronic device comprising memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, When the processor executes the program, it realizes the resource link reconfiguration method described in any one of claims 17 to 19. Electronic devices.

22. A non-temporary computer-readable storage medium, Computer-readable instructions are stored here. When the computer-readable instruction is executed by the processor, the resource link reconstruction method described in any one of claims 17 to 19 is realized. A non-temporary computer-readable storage medium.

23. The switch unit further includes a first board controller and a first complex programmable logic chip, the first complex programmable logic chip being connected to the switch chip, the first board controller, and the management controller, respectively, and the management controller being connected to the first board controller. The heterogeneous accelerated computing pooling unit further includes a second board controller and a second complex programmable logic chip, the second complex programmable logic chip being connected to the acceleration card and the second board controller, respectively. The general-purpose computing resource pooling unit further includes a third board controller and a third complex programmable logic chip, the third complex programmable logic chip being connected to the processor and the third board controller, respectively. The third complex programmable logic chip is connected to the first complex programmable logic chip, and the first complex programmable logic chip is connected to the second complex programmable logic chip. The second complex programmable logic chip first controls the power-on of the acceleration card and the second board controller, then the first complex programmable logic chip controls the power-on of the switch chip, the management controller and the first board controller, and finally the third complex programmable logic chip controls the power-on of the processor and the third board controller. The power-off order is the reverse of the power-on order. The multi-accelerometer heterogeneous server according to claim 1.

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