Crossing the frequency domain and power domain

Abstract

An asynchronous FIFO system (300) for transferring data from a transmit power region (302) to a receive power region (304) on a chip comprises a plurality of memory elements (308) and a plurality of cyclic multiplexers (310, 312) in the transmit power region, a data toggling multiplexer (318) and a plurality of pointer generators (314, 316) in the receive power region, and a plurality of level shifters (322a~d) positioned between the cyclic multiplexer in the transmit power region (302) and other elements in the receive power region, each The pointer generator is configured to provide each circular multiplexer with a pointer value so that each circular multiplexer can transfer discontinuous data (1, 3, 5, 7 or 0, 2, 4, 6) from multiple memory elements (308), and the data toggling multiplexer (318) is configured to periodically read the data (0, 1, 2, 3, 4, 5, 6, 7, 8) from multiple circular multiplexers (310, 312) in order to reconstruct the data from the multiple memory elements in the received power domain.

Description

Background Art

[0001] In modern computer chip designs, different components of the chip can operate at different voltages and different frequencies. For example, components with lower performance can operate at a lower voltage, for example to save power or to reduce the device temperature. Components operating at similar frequencies / voltages can be grouped into frequency domains and power domains. To cross data between the frequency domain and the power domain, a large number of level shifters, which are circuits used to convert signals from one logic level or voltage domain to another, may be required, resulting in a large amount of silicon area and potentially causing problems when designing the chip.

Summary of the Invention

[0002] This specification describes methods and systems for reducing the number of level shifters required to cross frequency domains and power domains while maintaining latency in a design, such as an asynchronous first-in-first-out (FIFO) design. For example, to cross frequency domains and power domains, often a large number of level shifters may be needed. In the methods and systems of the present invention, the number of level shifters can be reduced while maintaining the desired latency. For example, multiple circulating multiplexers can alternately read data and transmit data through a level shifter. By increasing the number of multiplexers, the amount of data crossing the frequency domain and the power domain can be increased without significantly increasing the number of level shifters.

[0003] Certain embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages.

[0004] The described method and system improve computer chip design by reducing the number of level shifters required to cross the frequency domain and power domain, thereby reducing the area required to cross the frequency domain and power domain. The described method and system can also enable single-cycle latency while reducing the number of level shifters.

[0005] Details of one or more embodiments of the subject matter of this specification are described in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawing]

[0006] [Figure 1] This is a diagram illustrating an exemplary chip design. [Figure 2] This is a diagram illustrating an example chip design with a reduced number of level shifters compared to the design in Figure 1. [Figure 3] This diagram shows an exemplary chip design that reduces the number of level shifters compared to the design in Figure 1, while maintaining single-cycle latency. [Modes for carrying out the invention]

[0007] Similar reference numbers and symbols in various drawings indicate the same elements.

[0008] Figure 1 is a diagram of an exemplary chip design 100 that crosses the level of prior art. Chip design 100 is an example of a chip design that could be included in the computing chip of any suitable stationary or mobile computing device, for example, a few examples of which include a mobile phone, tablet computer, laptop computer, or desktop computer.

[0009] The chip design 100 includes a transmit power region 102 and a receive power region 104. For example, the transmit power region 102 can operate at a different voltage than the receive power region 104, for example, a higher voltage or a lower voltage than the receive power region 104. The transmit power region 102 and the receive power region 104 are separated by a power region boundary 106, which is shown by a dashed line 106 for illustrative purposes. The transmit power region 102 includes a first-in, first-out (FIFO) queue 108 implemented by multiple memory elements to transmit data across the power region boundary 106.

[0010] The input data 110 can be stored in the FIFO 108. The FIFO can be implemented by any suitable storage logic, such as a register or random access memory. The write logic circuit 112 processes the input clock signal in the transmit power region 102 to control the operating speed of the transmit power region 102. The receive power region 104 includes a data toggling multiplexer 114 that switches the storage 108 that the multiplexer 114 reads. The receive power region 104 also includes a pointer generator 116 that gives the multiplexer 114 a pointer value to transfer data from the storage 108 to the multiplexer 114. The read logic circuit 118 processes the input clock signal in the read power region 104 to control the operating speed of the read power region 104, for example.

[0011] Several level shifters 120a to d are placed between the transmit power region 102 and the receive power region 104. Level shifters 120a to d may include circuits used to convert a signal from one logic level or voltage region to another logic level or voltage region. Level shifters 120a to d can convert a signal, for example, from the transmit power region 102 to the read power region 104, or from the read power region 104 to the transmit power region 102. Level shifters are necessary when transmitting a signal from one region 102, 104 to the other region 102, 104.

[0012] In the chip design 100 shown in Figure 1, an unacceptably large number of level shifters may be required. In the example where the FIFO 108 has m memory elements, each memory element stores n bits, and the chip design 100 requires m*n level shifters 120 to transmit signals from the transmit power region 102 to the receive power region 104, and vice versa. As the desired memory capacity increases, the number of required level shifters 120 increases quadratically. Consequently, as the number of required level shifters 120 increases, the area required to shift the levels also increases.

[0013] In the alternative design, a large number of level shifters can be reduced, increasing the area available for other components.

[0014] The arrangement of the level shifters 120 and the design of the chip can reduce the number of level shifters required, for example, to reduce the area required for these components. By reducing the area required for the level shifters 120, additional space can be provided for other components.

[0015] Figure 2 is a diagram of an exemplary prior art level-crossing chip design 200 that requires fewer level shifters than the chip design 100 shown in Figure 1. Chip design 100 is an example of a chip design that could be included in the computing chip of any suitable stationary or mobile computing device, for example, a mobile phone, tablet computer, laptop computer, or desktop computer, to name just a few examples. Chip design 200 includes a transmit power region 202 and a receive power region 204. For example, the transmit power region 202 can operate at a different voltage than the receive power region 204, for example, at a higher voltage or lower voltage than the receive power region 204. The transmit power region 202 and the receive power region 204 are separated by a power region boundary 206, indicated by a dashed line 206 for illustrative purposes. The transmit power region 202 includes FIFO queues 208a, 208b, which are implemented by multiple memory elements to transmit data across the power region boundary 206. Input data 210 can be stored in FIFOs 208a, 208b. The FIFO can be implemented by any suitable storage logic, such as registers or random access memory. The write logic circuit 212 processes an input clock signal in the transmit power region 202 to control the operating speed of the transmit power region 202. The transmit power region 202 further includes a data-toggle multiplexer 214 that switches between storage 208a and 208b, which the multiplexer 214 reads. By placing the data-toggle multiplexer 214 in the transmit power region 202, the number of level shifters required can be reduced, as will be further described below. The receive power region 204 includes a pointer generator 216 that gives the multiplexer 214 a pointer value to transfer data from storage 208a and 208b to the multiplexer 214. The read logic circuit 218 processes an input clock signal in the read power region 204, for example, to control the operating speed of the read power region 204.

[0016] Several level shifters 220a, 220b, 220c, and 220d are positioned between the transmit power area 102 and the receive power area 204. The number of required level shifters can be reduced compared to the chip design 100 in Figure 1, for example, to reduce the required area as described above. The chip design 200 shown in Figure 2 requires far fewer level shifters than the chip design 100 shown in Figure 1. The number of required level shifters 220 can be significantly reduced by moving the level shifters 220 around the multiplexer 214, for example, by moving the multiplexer into the transmit power area 202. In the example with m memory elements 208, each memory element stores n bits, and the chip design 200 requires n + log(m) level shifters 220 to transmit signals from the transmit power area 202 to the receive power area 204 and vice versa. As the desired memory capacity increases, the number of level shifters 220 required increases at a much lower rate than in chip design 100, which required n*m level shifters. Also, because the number of level shifters 220 required increases at a much lower rate than in chip design 100, the area required to shift levels increases at a much lower rate than in chip design 100.

[0017] In chip design 200 shown in Figure 2, the number of level shifters required is far fewer than in chip design 100 in Figure 1. However, reducing the number of level shifters can introduce other problems, such as timing and latency issues. One example of a problem in chip design 200 in Figure 2 is a timing problem that occurs when the voltage in the transmit power region 202 is low and the read clock timing is fast, for example, when the read power region 204 operates quickly. For example, a critical timing path 222 is shown where the signal must travel from the pointer generator 216, through level shifter 220, through multiplexer 214, and through a second level shifter 220 as output data 224. The critical timing path 222 is a long timing path for the signal to travel and can introduce timing problems. For example, the timing delay caused by level shifters increases approximately proportionally to the voltage difference between the transmit power region 202 and the receive power region 204. When the voltage in the transmit power domain 202 is low and the read clock timing is fast, i.e., when the receive voltage is high, the timing delay caused by the level shifter 220 becomes large. Furthermore, since the signal passing through the critical timing path 222 passes through two level shifters, the timing delay becomes even larger.

[0018] Another example of a problem in chip design 200 in Figure 2 is latency. For example, a high read clock may be undesirable because it can cause timing problems as described above. However, a slow read clock introduces latency into the design, significantly reducing bandwidth. For example, one simple way to solve the timing problem described above is to read data from the multiplexer 214 in alternating cycles, for example, every other cycle. However, reading data from the multiplexer 214 in alternating cycles requires twice the number of read clock cycles to read data from storage 208 compared to the number of cycles required to read data from storage in chip design 100 in Figure 1. Chip design 200 in Figure 2 may be advantageous because it reduces the number of level shifters compared to chip design 100 in Figure 1, but chip design 200 in Figure 2 also presents additional problems, such as timing and latency problems, as described above. However, in the alternative design, reducing the number of level shifters can increase the area available for other components.

[0019] Figure 3 shows a chip design 300 that requires fewer level shifters than the chip design 100 shown in Figure 1. Chip design 300 includes a transmit power region 302 and a receive power region 304. For example, the transmit power region 302 can operate at a different voltage than the receive power region 304, for example, a higher voltage or a lower voltage than the receive power region 304. The transmit power region 302 and the receive power region 304 are separated by a power region boundary 306, indicated by a dashed line 306 for illustrative purposes. The transmit power region 302 includes a FIFO queue 308 implemented by a storage element to transmit data across the power region boundary 306. Input data can be stored in the FIFO 308. In the illustrated example, the storage 308 is a register. A write logic circuit can process an input clock signal in the transmit power region 302 to control the operating speed of the transmit power region 302. The write logic circuit can be similar to the write logic circuits in Figures 1 and 2. The transmit power domain 302 further includes two cycling multiplexers 310, 312 to switch between discontinuous data of FIFO 308. For example, because there are two cycling multiplexers 310, 312, the data of FIFO 308 can be read alternately, such that one multiplexer is an odd multiplexer that reads data from addresses such as the 1st, 3rd, and 5th, and the other multiplexer is an even multiplexer that reads data from addresses such as the 2nd, 4th, and 6th.

[0020] In some embodiments, there is more storage, and more circular multiplexers, such as three multiplexers, four multiplexers, etc. In embodiments with more circular multiplexers, the multiplexers divide the register data according to the number of multiplexers. For example, in an embodiment with three circular multiplexers, the multiplexers will read every three addresses, so for example, the first multiplexer will read addresses 1, 4, 7, etc., the second multiplexer will read addresses 2, 5, 8, etc., the third multiplexer will read addresses 3, 6, 9, etc. Dividing the data according to the number of multiplexers can be done for any number of multiplexers. The number of addresses does not need to be divisible by the number of multiplexers. As shown in the figure, the first circular multiplexer 310 receives a pointer from the pointer generator 314 that instructs the first circular multiplexer 310 to read from odd addresses, such as the 1st, 3rd, and 5th addresses. The second circular multiplexer 312 receives a pointer from the pointer generator 316 that instructs the second circular multiplexer 312 to read from even addresses, such as the 2nd, 4th, and 6th addresses. By using circular multiplexers, latency problems similar to those described with respect to Figure 2, for example, can be eliminated.

[0021] Chip design 300 also includes a data-toggle multiplexer 318 in the receive power region 304. The data-toggle multiplexer 318 receives a pointer from a pointer generator 320 that instructs the data-toggle multiplexer 318 to alternately read data from a first cyclic multiplexer 310 and a second cyclic multiplexer 312. By using the data-toggle multiplexer 318 to alternately read data from the first cyclic multiplexer 310 and the second cyclic multiplexer 312, the timing problems presented in chip design 200 of Figure 2 can be reduced or eliminated, as will be further described below. The receive power region 304 includes a toggle 320 that switches the multiplexer 318 to alternately read data from the first cyclic multiplexer 310 and the second cyclic multiplexer 312. The receive power region may also include, for example, a read logic circuit that processes the input clock signal in the read power region 304 to control the operating speed of the read power region 304. For example, the read logic circuit may be similar to the read logic circuits in Figures 1 and 2.

[0022] Several level shifters 322a, 322b, 322c, and 322d are placed between the transmit power region 302 and the receive power region 304. For example, level shifters 322a and 322b are placed between the cyclic multiplexers 310 and 312 and the data toggling multiplexer 318. The chip design 300 shown in Figure 3 requires fewer level shifters than the chip design 100 shown in Figure 1, and the chip design 300 shown in Figure 3 does not have the timing and latency problems presented in Figure 2.

[0023] In the example with m storage units 308, each storage unit stores n bits, and chip design 300 requires 2(n+log(m)) level shifters to transmit signals from the transmit power area 302 to the receive power area 304, and vice versa. As the desired storage capacity increases, the number of level shifters required increases at a much lower rate than in chip design 100, which required n*m level shifters. Also, because the number of level shifters required increases at a much lower rate than in chip design 100, the area required to shift levels increases at a much lower rate than in chip design 100.

[0024] Chip design 300 can also reduce or eliminate problems presented in chip design 200, such as timing and latency problems. For example, level shifters 322a and 322b are placed between cyclic multiplexers 310 and 312 and a data toggle multiplexer 318. There is still a timing delay when data passes through one of the level shifters 322a and 322b. However, during the timing delay, the other cyclic multiplexer can read data from storage and transmit the data to the other level shifter 322a and 322b. When the data toggle multiplexer 318 receives data from one of the level shifters and transmits the data forward, the data on the other level shifter is ready to be read by the multiplexer 318. This is because, for example, the cyclic multiplexer can continue to transmit data to the level shifter during the timing delay caused by the level shifter. The timing delay is not noticeable to the end user because while one level shifter is causing a timing delay, the other cyclic multiplexer is passing data from storage through the other level shifter. For example, during the first cycle, the data toggling multiplexer 318 can receive a signal from the first level shifter 322a and forward that signal to other components. During the first cycle, the cyclic multiplexer 312 can read data from storage and transmit the data to the second level shifter 322b, which can process the data, for example, to convert the signal from the transmit power region 302 to the receive power region 304. During the second cycle, the data toggling multiplexer 318 can receive a signal from the second level shifter 322b and forward that signal to other components. During the second cycle, the circulating multiplexer 310 can read data from storage and transmit the data to the first level shifter 322a, which can process the data to convert the signal, for example, from power domain 302 to received power domain 304.In this way, the data toggling multiplexer 318 can receive and transfer data for each cycle. The cycling of the cyclic multiplexer eliminates the timing and latency problems described with reference to FIG. 2.

[0025] The chip design 300 of FIG. 3 requires a greater number of level shifters than the chip design 200 of FIG. 2, e.g., 2(n + log(m)) instead of n + log(m), but the chip design 300 also reduces or eliminates the timing and latency problems presented by the chip design of FIG. 2. The chip design 300 may be more desirable than the chip design 200 of FIG. 2 in order to reduce the timing and latency problems. The chip design 300 also requires a smaller number of level shifters than the chip design 100 of FIG. 1. The chip design 300 may be more desirable than the chip design 100 of FIG. 1 because it requires a smaller number of level shifters.

[0026] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them, of computer hardware. Also, the processes and logical flows can be executed by a special purpose logic circuit, such as an FPGA or an ASIC, or by a combination of special purpose logic circuits and one or more programmed computers.

[0027] In addition to the above embodiments, the following embodiments are also innovative.

[0028] Embodiment 1 is an asynchronous FIFO system for transferring data from a transmit power region to a receive power region on a chip, where the transmit power region includes a plurality of storage elements and a plurality of cyclic multiplexers, the receive power region includes a data toggling multiplexer and a plurality of pointer generators, and The system comprises a plurality of level shifters positioned between the circulating multiplexer in the transmitting power region and other elements in the receiving power region, Each pointer generator is configured to provide its respective pointer value to each circular multiplexer in order to transfer discontinuous data from the multiple memory elements to each circular multiplexer. The data toggling multiplexer is an asynchronous FIFO system configured to periodically read data from the multiple cyclic multiplexers in order to reconstruct the data of the multiple memory elements in the received power domain.

[0029] Embodiment 2 is the system described in Embodiment 1, wherein the circulating multiplexer is divided into an even multiplexer and an odd multiplexer.

[0030] Embodiment 3 is the system according to any one of Embodiments 1 to 2, wherein the circulating multiplexer includes two multiplexers.

[0031] Embodiment 4 is the system according to any one of Embodiments 1 to 3, wherein some of the plurality of level shifters are positioned between the circulating multiplexer and the data toggling multiplexer.

[0032] Embodiment 5 is a system according to any one of Embodiments 1 to 4, wherein the plurality of memory elements include a plurality of registers.

[0033] Embodiment 6 is the system according to any one of Embodiments 1 to 5, wherein each of the circulating multiplexers is configured to transfer the discontinuous data to each of the plurality of level shifters.

[0034] Embodiment 7 is a method for transferring data from the transmit power domain to the receive power domain on a chip, In order to transfer discontinuous data from multiple memory elements to each circular multiplexer, a pointer value is provided to each circular multiplexer, The method includes periodically reading data from the plurality of cyclic multiplexers in order to reconstruct the data of the plurality of memory elements in the received power region.

[0035] Embodiment 8 is the method according to Embodiment 7, wherein the circulating multiplexer is divided into an even multiplexer and an odd multiplexer.

[0036] Embodiment 9 is the method according to any one of Embodiments 7 to 8, wherein the circulating multiplexer includes two multiplexers.

[0037] Embodiment 10 is a method according to any one of Embodiments 7 to 9, further comprising placing a level shifter between the circulating multiplexer and the data toggling multiplexer.

[0038] Embodiment 11 is a method according to any one of Embodiments 7 to 10, wherein the plurality of memory elements include a plurality of registers.

[0039] Embodiment 12 is a method according to any one of Embodiments 7 to 11, wherein each of the circulating multiplexers transfers the discontinuous data to one of the multiple level shifters.

[0040] While this specification includes details of many specific embodiments, these should not be construed as limiting the scope of any invention or claimable content, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, individually or in any preferred subcombination. Furthermore, while features may be described above as acting in a particular combination, and may even be initially claimed as such, one or more features of a claimed combination may, in some cases, be removed from the combination, and the claimed combination may be directed towards a subcombination or a variation of a subcombination.

[0041] Similarly, although the operations are shown in a specific order in the drawings, this should not be understood as requiring that such operations be performed in a specific or sequential order shown, or that all shown operations be performed, in order to obtain the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described can generally be integrated into a single software product or packaged into multiple software products.

[0042] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions described in the claims can still achieve the desired results even if they are performed in a different order. As an example, the process depicted in the accompanying drawings does not necessarily require the specific order or sequence shown to achieve the desired results. In certain cases, multitasking and parallel processing may be advantageous.

Claims

1. An asynchronous FIFO system for transferring data from the transmit power domain to the receive power domain on a chip, The plurality of memory elements and plurality of cyclic multiplexers within the transmission power domain, The data toggling multiplexer and multiple pointer generators in the received power domain, The system comprises a plurality of level shifters positioned between the plurality of circulating multiplexers in the transmitting power domain and other elements in the receiving power domain, Each pointer generator is configured to provide its respective pointer value to each circular multiplexer in order to transfer discontinuous data from the multiple memory elements to each circular multiplexer. The data toggling multiplexer is configured to periodically read data from the plurality of cyclic multiplexers in order to reconstruct the data of the plurality of memory elements in the received power domain, in an asynchronous FIFO system.

2. The system according to claim 1, wherein the circulating multiplexer is divided into an even multiplexer and an odd multiplexer.

3. The system according to claim 1, wherein the circulating multiplexer includes two multiplexers.

4. The system according to claim 1, wherein some of the plurality of level shifters are arranged between the circulating multiplexer and the data toggling multiplexer.

5. The system according to claim 1, wherein the plurality of memory elements include a plurality of registers.

6. The system according to claim 1, wherein each of the circulating multiplexers is configured to transfer the discontinuous data to each of the plurality of level shifters.

7. A method for transferring data from the transmit power domain to the receive power domain on a chip, In order to transfer discontinuous data from multiple memory elements to each circular multiplexer, a pointer value is provided to each circular multiplexer, A method comprising periodically reading data from the plurality of cyclic multiplexers in order to reconstruct the data of the plurality of memory elements in the received power domain.

8. The method according to claim 7, wherein the circulating multiplexer is divided into an even multiplexer and an odd multiplexer.

9. The method according to claim 7, wherein the circulating multiplexer includes two multiplexers.

10. The method according to claim 7, further comprising arranging a level shifter between the circulating multiplexer and the data toggling multiplexer.

11. The method according to claim 7, wherein the plurality of memory elements include a plurality of registers.

12. The method according to claim 7, wherein each of the circulating multiplexers transfers the discontinuous data to one of the multiple level shifters.

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