Graphene BEOL Integrated Interconnect Structure

Abstract

The interconnection structure comprises a first MLG layer comprising a first line structure of at least one MLG (multilayer graphene) material, a first insulating layer comprising an electrically insulating material and positioned above the first line structure of at least one MLG material, a second MLG layer (containing MLG material) positioned above the first insulating layer, a connection path electrically connecting the first MLG layer to the second MLG layer, and at least one via having a serrated edge to reduce the effects of misalignment and enable low contact resistance between the via and the line, the connection path comprising one of the at least one via, the width of the first line structure of at least one MLG material being greater than the diameter of one of the at least one via, and both MLG layers being intercalated doped.

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 457,362, filed Apr. 5, 2023, and the priority of U.S. Patent Application No. 18 / 607,380, filed Mar. 15, 2024. The entire contents of the aforementioned applications are incorporated herein by reference.

[0002] U.S. Patent Application No. 18 / 527,043, filed Dec. 1, 2023, titled "LARGE - AREA WAFER - SCALE CMOS - COMPATIBLE 2D - MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE", U.S. Patent Application No. 17 / 863,232, filed Jul. 12, 2022, titled "LOW - TEMPERATURE / BEOL - COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL", U.S. Patent Application No. 17 / 857,954, filed Jul. 5, 2022, titled "LOW - TEMPERATURE / BEOL - COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS TOOL", U.S. Provisional Patent Application No. 63 / 218,498, filed Jul. 6, 2021, titled "WAFER - SCALE CMOS - COMPATIBLE GRAPHENE SYNTHESIS TOOL", and U.S. Provisional Patent Application No. 63 / 441,766, filed Jan. 27, 2023, titled "LARGE - AREA / WAFER - SCALE CMOS - COMPATIBLE 2D - MATERIAL DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE" are related applications. The entire contents of the aforementioned applications are incorporated herein by reference.

Background Art

[0003] Solid-phase diffusion of atoms in a "material stack" that forms a "diffusion pair" can be utilized for the synthesis of high-quality thin films at relatively low temperatures, which are required in a wide range of applications, including microelectronics, optoelectronics, bioelectronics, and quantum computing. However, enabling such solid-phase diffusion-assisted thin film growth within a reasonable growth time, especially on large "wafer-scale" substrates (e.g., 200 mm, 300 mm, etc.), requires the design and manufacture of novel apparatus capable of uniformly applying a wide range of temperatures and pressures across the entire surface area of ​​the semiconductor wafer or other substrates forming the diffusion pair. The core component of such apparatus is a reactor that not only accommodates such large-area substrates but also provides a chemically purged environment, heating of the large-area substrate with virtually zero temperature heterogeneity, and a simple mechanism for applying relatively large and uniform mechanical pressure (e.g., up to 1000 psi, etc.) to the diffusion pair. Note that in some examples, atmospheric pressure can be utilized. The above references cited in paragraph

[0002] of this specification describe embodiments of the invention relating to such apparatus. Furthermore, Patent Nos. 18 / 527,043 and 63 / 441,766, referenced in paragraph

[0002] of this specification, describe doping devices that can generally be adapted to intercalation doping required for most 2D materials.

[0004] The pressing need for such large-area diffusion pairs lies in the emerging field of atomically thin two-dimensional (2D) materials, particularly graphene or multi-layered graphene (MLG) (single or more atomic layers of carbon atoms arranged in a hexagonal lattice), which must be synthesized directly onto the desired substrate (typically dielectric or metal) without requiring transfer steps that are considered impractical and cost-ineffective in the mainstream electronic components (or CMOS) industry. Such graphene / MLG layers are preferred materials for several back-end-of-line (BEOL) applications, particularly on-chip interconnects. However, BEOL interconnects must be synthesized under a strict thermal budget of less than approximately 400°C to avoid damage to the underlying active and passive devices (e.g., transistors, diodes, etc. due to increased diffusion of impurities).

[0005] The above references cited in paragraph

[0002] of this specification describe embodiments of the invention relating to such apparatus. Furthermore, Patent No. 63 / 441,766, also referenced in paragraph

[0002] of this specification, describes a doping apparatus that is generally suitable for intercalation doping required for most 2D materials and is referenced in reference to MLG as illustrated herein.

[0006] However, there are challenges not only in achieving effective electrical contact of graphene / MLG layers with low resistance, which is particularly useful for commercial circuits, but also in other integration challenges associated with the latest processes, such as process nodes below 15 nm. This disclosure teaches and describes embodiments of the invention that address these integration challenges. [Overview of the project]

[0007] In one embodiment, an integrated BEOL process flow includes low-temperature MLG synthesis on a wafer / substrate, doping of MLG, and formation of sidewall contacts, such as serrated contacts, to maximize the contact area of ​​vias to the MLG and to MGL interconnect lines / structures.

[0008] This application can be best understood by referring to the following description in conjunction with the attached drawings, where the same number may refer to the same part. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an exemplary 3D representation of a typical copper (Cu) wiring process (BEOL) for semiconductor devices / integrated circuits. [Figure 2A-2D] Figure 2A is an exemplary cross-sectional view of a first exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2B is an exemplary cross-sectional view of a second exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2C is an exemplary cross-sectional view of a third exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2D is an exemplary cross-sectional view of a fourth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. [Figure 2E-2J]Figure 2E is an exemplary cross-sectional view of a fifth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2F is an exemplary cross-sectional view of a sixth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2G is an exemplary cross-sectional view of a seventh exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2H is an exemplary cross-sectional view of an eighth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2I is an exemplary cross-sectional view of a ninth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. Figure 2J is an exemplary cross-sectional view of a tenth exemplary intermediate structure, which is part of an exemplary BEOL process flow according to several embodiments. [Figure 3A-3B] Figure 3A is an exemplary top view showing a layout / design structure that enables maximum edge connection between the edge of an MLG line / structure and a contact or via, according to several embodiments. Figure 3B is an exemplary top view showing a further layout / design structure that enables maximum edge connection between the edge of an MLG line / structure and a contact or via, according to several embodiments. [Figure 4A] This diagram shows an exemplary conventional / typical via or contact. [Figure 4B] This figure shows an exemplary via / contact where the upper perimeter length has increased, thereby increasing the contact area between the interconnecting line and the contact / via sidewall. [Figure 4C] This figure shows a further exemplary via / contact where the upper perimeter length is increased, thereby increasing the contact area between the interconnecting line and the contact / via sidewall. [Figure 5A] This figure illustrates, in one example, a generalized and illustrative explanation of how a via or contact with a serrated edge increases the upper perimeter length, thereby increasing the contact area between the interconnecting line and the contact / via sidewall. [Figure 5B]This figure illustrates, in one example, a generalized and illustrative explanation of how a serrated edge via or contact can increase the upper perimeter length, thereby increasing the contact area between the interconnecting line and the contact / via sidewall, and reducing the effects of contact / via misalignment. [Modes for carrying out the invention]

[0010] The diagrams described above are representative sets and are not exhaustive for realizing the present invention.

[0011] Systems, methods, micro / nanostructures, and products for graphene-based BEOL integration techniques are disclosed. The following description is presented to enable those skilled in the art to fabricate and use various embodiments. Descriptions of specific devices, techniques, and applications are provided merely as examples. Various modifications to the examples described herein will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples and applications without departing from the spirit and scope of the various embodiments.

[0012] Throughout this specification, any reference to “one embodiment,” “an embodiment,” “an example,” or similar phrases means that a particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment of the present invention. Therefore, throughout this specification, any occurrence of phrases such as “in one embodiment,” “in an embodiment,” and similar phrases may, but not necessarily, all refer to the same embodiment.

[0013] Furthermore, the features, structures, or properties of the present invention described herein may be combined in any preferred manner in one or more embodiments. The following description provides numerous specific details, including examples of processing, integration techniques, design and layout techniques, alternative materials for various substeps or substructures, programming, software modules, user selection, network trading, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., in order to enable a full understanding of embodiments of the present invention. However, those skilled in the art will recognize that the present invention may be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail, in order to avoid obscuring aspects of the present invention.

[0014] The schematic flowcharts (if any) included herein are generally presented as logical flowcharts. Therefore, the order and labeled steps shown represent one embodiment of the presented method. Other steps and methods may be considered equivalent in function, logic, or effect to one or more steps, or parts of steps, of the presented method. Furthermore, the forms and symbols used are provided to illustrate the logical steps of the method and should not be understood as limiting the scope of the method. While various types of arrows and lines may be used in the flowcharts, these should not be understood as limiting the scope of the corresponding method. In fact, some arrows or other connectors may be used solely to indicate the logical flow of the method. Arrows may, for example, indicate waiting or monitoring periods, which are unspecified durations, between enumerated steps of the presented method. Furthermore, the order in which a particular method is performed may or may not strictly follow the order of the corresponding steps shown.

[0015] (definition) The backend-of-line (BEOL) process is the second part of IC manufacturing where interconnects (e.g., metal cladding layers) separated by intra- or inter-layer insulators and other elements are formed between individual devices (mainly transistors) on a wafer / substrate and on top of individual devices.

[0016] Complementary metal-oxide-semiconductor (CMOS) is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) manufacturing process that uses a pair of complementary and electrically symmetric p-type MOSFETs and n-type MOSFETs to realize logical functions.

[0017] A grain boundary (GB) is the boundary between two grains and / or crystallites in a polycrystalline material.

[0018] The grain size may be the average of the longest axes of each deposited metal grain, such as Ni, Co, or W, or in some cases, it may refer to the longest axis of a single grain.

[0019] Graphene is an allotrope of carbon consisting of a single layer of atoms arranged in a two-dimensional honeycomb lattice.

[0020] A graphene nanoribbon (GNR) is a narrow piece of graphene with a width less than one hundred (100) nm.

[0021] MLG may refer to multilayer graphene, which may include an interconnect structure in an ultra-low RC delay BEOL process and typically contains two or more layers of graphene.

[0022] Graphite is in the form of layered crystallites of the carbon element (3D allotrope), and the atoms of graphite arranged and covalently bonded form a hexagonal structure within the layer.

[0023] Silicon dioxide is an oxide of silicon, and its chemical formula is SiO2; it is an insulator.

[0024] A wafer is a thin piece of semiconductor material (such as crystalline silicon, germanium, or GaAs) used in the manufacture of integrated circuits and other devices.

[0025] (Exemplary process flow and structure of MLG-based BEOL) It should be noted that the following exemplary embodiments discuss graphene as an example source. However, other exemplary embodiments may utilize other carbon sources (including any carbon-carrying compound).

[0026] Figure 1 shows an exemplary 3D internal diagram of a typical semiconductor BEOL, where the circuit and substrate 108, located at what is conventionally called the “bottom” of the integrated circuit structure, may comprise interconnect “wiring” located on top of the circuit and substrate 108. The interconnect “wiring” may include LI layer 106, 1X layer 104, 2X layer 102, and 4X layer 100. The circuit and substrate 108 may be connected to the LI layer 106 or 1X layer 104 through contacts (not shown or very small) and / or to each other through vias (not shown or very small). The dimensions of this interconnect pair of contacts / vias and the metal wires (LI layer 106 and / or 1X layer 104) may generally be the minimum line resolution of the lithography and etching capabilities at the process node of the technology. This is conventionally referred to as the “1X” design rule metal layer. The next metal layer, 1X metal 114, which is typically paired with a 1X via 112, may also follow the "1X" design rule, depending on engineering and design considerations and trade-offs, if necessary. The next few metal layers, 2X metal layers 124 (paired with 2X vias 122), may often be constructed with twice the minimum lithography and etching capability and are conventionally called "2X" layers (2X layers 102), and may have thicker metal (generally about twice as thick) than the 1X layers 104 to provide higher conductivity. Thus, a pair of 4X metal 144 and 4X vias 142 represents a "4X" 100 metal coating layer, whose planar and thickness dimensions are also larger and thicker than the 2X layers 102 and 1X layers 104, and may be roughly twice and four times, respectively.

[0027] The LI layer 106 (Local Interconnect) is used in some cases as a layer of minimum lithography dimensions, and in some cases as a layer smaller than the minimum lithography dimensions, and is mainly used to fabricate intracellular memory and / or intercellular connections / crossovers. It may be constructed from materials other than Cu, such as W or Co, and generally has a short path length.

[0028] The exact number of 1X, 2X, or 4X layers may vary depending on interconnection needs and other requirements, but the general trend is that as the metal layers move further away from the silicon transistors and closer to the bond pads, the dimensions of the metal wires, metal spaces, and vias become progressively larger (increasing metal / interconnection spacing and metal / interconnection thickness). This is generally not true for monolithic 3D structures and devices. The order of metal cladding between transistor layers or levels can be roughly 1X, 2X, 4X, 2X, 1X, as dense geometric interconnects are required not only for the back connections of the "top" layer / level pairs but also for the conventional upper contacts of the "bottom" transistor layers / levels.

[0029] As scaling progresses and attempts are made to satisfy the economic relationships revealed by Moore's Law, the need has arisen to scale the diameters (and overlaps) of tracks, spaces, and vias. This has made it difficult to maintain scaling according to Dennard's Law for several reasons, one of which is that it has become increasingly necessary to fill the cross-sections of metal wires, whether 1X, 2X, or 4X, with high-resistance materials, primarily barrier metals. Barrier metals that hold the Cu atoms that destroy transistors cannot be scaled and are a physical barrier. And the cross-sections of metal interconnects containing low-resistance Cu are decreasing. However, what many people have almost forgotten is the other part of the interconnect performance equation for RC: the capacitance (C) of the interconnect wire. In the demand to keep R as low as possible, scaling of height (thickness) is not so sufficient. Thus C has now become a challenge to overcome.

[0030] Graphene, specifically MLG (multilayer graphene), is currently considered the next interconnect material in the semiconductor industry. The precise arrangement of carbon atoms not only achieves very low resistance (R) especially when doping, but also allows the same current capacitance to flow reliably through MLG using considerably thinner "wires." Therefore, in MLG interconnects, the carbon content of RC is significantly reduced compared to conventional Cu interconnects. However, until recent technological advancements, graphene or MLG had to be formed on specially treated substrates at temperatures generally above BEOL (Below-Earth) temperatures, such as 600-900°C, resulting in a very defective and expensive process. In recent years, a direct MLG synthesis method has been invented, which allows for the production of high-quality MLG on desired circuit wafers at BEOL temperatures, i.e., below 400°C.At least U.S. Patent Application No. 63 / 123,587 and PCT / US21 / 61361, and at least the papers, J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, J. Jiang, et al., "All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias," IEEE IEDM, pp. 14.3.1-14.3.4, 2017, J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018, K. Agashiwala, et al., "Reliability and Performance of CMOS-Compatible Please refer to "Multi-Level Graphene Interconnects Incorporating Vias" IEEE IEDM, 2020, and K. Agashiwala, et al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias" IEEE Transactions on Electron Devices, vol. 68, No. 4, April 2021, pp. 2063-2091, where the entire content above is incorporated by reference.

[0031] However, this new set of methodologies has several integration challenges in creating the cheapest, fewest-step process flow while maintaining quality (such as MLG, low-k dielectric, via EM). This is the main objective of the novel and non-obvious embodiments of the present invention, which are included in at least Figures 2 and 3 of this specification.

[0032] As shown in Figure 2A, the intermediate structure 270 is an exemplary cross-sectional view of a typical intermediate structure near the beginning of the process flow BEOL, and further comprises two additional layers deposited on top. The structure 270 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, a sacrificial nickel layer 210, and an amorphous carbon layer 212. The silicon substrate 202 may include a single crystalline substrate and is sometimes referred to as the “substrate”. The silicon substrate 202 is not limited to the single-crystal form of a silicon device and therefore may include glass, quartz, Ga, GaAs, GaN, SiGe, etc. The circuit layer 204 may comprise transistors, capacitors, resistors, etc., and is generally laid out so that desired electrical and / or optical subcircuits and circuits are formed when connected using upper and possibly lower metal layers.

[0033] The insulating layer 206 typically contains SiO2 and may be doped with phosphorus and / or boron, and is generally called an ILD (Intra-Layer Dielectric). In some cases, other oxide and oxide forms, e.g., thermally annealed doped or undoped SOG (Spin-On-Glass), may be used. The primary purpose of the insulating layer 206 is to electrically isolate the first metal layer (or local interconnection) from electrical coupling with any devices on the substrate, unless necessary. Generally, this is vertical electrical isolation between BEOL conductive layers. Desired connections may be made by selectively removing the ILD material within a small top-view area, usually called a "contact," and replacing its volume with an electrically conductive material.

[0034] The sacrificial nickel layer 210 may be deposited on top of the insulating layer 206. This layer has the function of diffusing the carbon source so that carbon atoms are uniformly spread until they reach the Ni / oxide interface, in order to form high-quality sp2 bonded MLG. The sacrificial nickel layer 210 may be heat annealed to obtain the desired particle size and edge fraction.

[0035] The amorphous carbon layer 212 may be deposited on top of the sacrificial nickel layer 210. The interface between the amorphous carbon layer 212 and the sacrificial nickel layer 210, as well as the interface between the sacrificial nickel layer 210 and the insulating layer 206, can be critical to the formation of MLG of the desired quality, which is formed at the sacrificial nickel layer 210-insulating layer 206 interface. The typical thickness of the sacrificial nickel layer 210 may be about 100 nm, about 80 nm, about 50 nm, about 130 nm, about 150 nm, or about 200 nm, depending on technical and material considerations, and the typical thickness of the amorphous carbon layer 212 may be, for example, about 10 nm, about 15 nm, about 20 nm, about 25 nm, or about 30 nm, depending on technical and material considerations. However, both of the aforementioned thicknesses may be adjusted to obtain a desired number of graphene layers in the MLG layer 208, according to technical, chemical, and materials science considerations.

[0036] As shown in Figure 2B, the second intermediate structure 271 is an exemplary cross-sectional view of the first intermediate structure 270, which has been treated to form an MLG layer 208. The second intermediate structure 271 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, an MLG layer 208, and a sacrificial nickel layer 210. The silicon substrate 202, the circuit layer 204, and the insulating layer 206 remain relatively unchanged throughout this treatment. The amorphous carbon layer 212 may be subjected to pressure and temperature acceleration to diffuse through the nickel layer 210 and form the MLG layer 208. Further details can be found in at least U.S. Provisional Patent Application No. 63 / 123,587, filed December 10, 2020, and International Application PCT / US21 / 61361, filed December 1, 2021.Furthermore, at least U.S. Patent Application No. 63 / 123,587 and PCT / US21 / 61361, and at least the papers, J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, J. Jiang, et al., "All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias," IEEE IEDM, pp. 14.3.1-14.3.4, 2017, J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018, K. Agashiwala, et al., "Reliability and Performance of CMOS-Compatible See "Multi-Level Graphene Interconnects Incorporating Vias" IEEE IEDM, 2020, and K. Agashiwala, et al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias" IEEE Transactions on Electron Devices, vol. 68, No. 4, April 2021, pp. 2063-2091, all of the above is incorporated by reference. Although the amorphous carbon layer 212 is not shown in Figure 2B, carbon residues (not shown) may be present after the MLG formation process due to the non-uniformity of various processes and other technical considerations. Such carbon residues may be located on top of the sacrificial nickel layer 210.

[0037] As shown in Figure 2C, the third intermediate structure 272 is an exemplary cross-sectional view of the second intermediate structure 271, in which the structure has been treated to remove carbon residue (if any) from a previously present amorphous carbon layer 212 and the sacrificial nickel layer 210 without damaging the MLG layer 208. The third intermediate structure 272 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, and an MLG layer 208. The silicon substrate 202, the circuit layer 204, and the insulating layer 206 remain relatively unchanged throughout this treatment. The treatment temperature should preferably be kept below about 450°C so as not to impede / disturb at least the transistor dopant profile, contact reliability, via reliability, and low-k dielectric stability (if any). Details of the process for removing carbon residues and nickel without damaging MLG can be found in at least U.S. Provisional Patent Application No. 63 / 123,587, filed on December 10, 2020, and International Application PCT / US21 / 61361, filed on December 1, 2021.At least U.S. Patent Application No. 63 / 123,587 and PCT / US21 / 61361, and at least the papers, J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, J. Jiang, et al., "All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias," IEEE IEDM, pp. 14.3.1-14.3.4, 2017, J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018, K. Agashiwala, et al., "Reliability and Performance of CMOS-Compatible See "Multi-Level Graphene Interconnects Incorporating Vias," IEEE IEDM, 2020, and K. Agashiwala, et al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias," IEEE Transactions on Electron Devices, vol. 68, No. 4, April 2021, pp. 2063-2091, all of which are incorporated by reference.

[0038] As shown in Figure 2D, the fourth intermediate structure 273 is an exemplary cross-sectional view of the third intermediate structure 272, which has been processed to define, etch, and fill the contacts 220 using an optional but preferably hard mask 214. The fourth intermediate structure 273 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, an MLG layer 208, a hard mask 214, and contacts 220. The fourth intermediate structure 273 is processed to form a hard mask 214, then processed to form contact openings in a photoresist (not shown) by lithography, and then etched to open the hard mask 214 material at the locations of all desired contacts. The photoresist is then stripped, the wafer / substrate is cleaned, and deep etching is performed to form the contact 220, which may sequentially and possibly selectively remove a portion / region of the thin MLG layer 208, then a portion / region of the insulating layer 206, creating a non-destructive opening above the desired circuit elements (S / D, gate, etc.) of the circuit layer 204 so that the metal coating of the contact 220 can be connected. The material of the hard mask 214 may include, for example, SiN, Si3N4, or a Si-rich oxide, and will be selected with due technical consideration to be selectively etchable with respect to at least the MLG layer 208 and the insulating layer 206. Initial intercalation doping through the formed contact 220 holes may be performed as technically appropriate.Details of intercalation doping can be found in at least U.S. Provisional Patent Application No. 63 / 441,766, as well as in J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, and J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018. The contact 220 may be filled with a desired surface clean and barrier metal, and generally, the majority of the volume of the contact 220 is W metal. The top of the contact 220 is CMP'd, and a hard mask 214 may be used as a finish. The MLG layer 208 may then be defined by lithography on a photoresist (not shown) and subsequently etched to form a number of MLG lines / structures 209.

[0039] An alternative process flow is to etch the MLG layer 208 to form a number of MLG lines / structures 209 before forming and filling the contacts 220. However, this flow is more difficult in lithography and may be more susceptible to the effects of metal stringer formation between the MLG lines / structures 209.

[0040] As shown in Figure 2E, the fifth intermediate structure 274 is an exemplary cross-sectional view of the fourth intermediate structure 273, and the fifth intermediate structure 274 is the fourth intermediate structure 273 rotated 90 degrees to show multiple MLG lines / structures 209, whereas in Figure 2D only a single MLG layer 208 was shown (for clarity in Figure 2D). Similarly, for clarity in the figures, only one contact 220 is shown in the remaining Figures 2E-2J, although of course a typical device / circuit should have multiple contacts 220.

[0041] As shown in Figure 2F, the sixth intermediate structure 275 is an exemplary cross-sectional view of the fifth intermediate structure 274, which has been processed to form a second insulating layer 236, a second sacrificial nickel layer 230, and a second amorphous carbon layer 232. The sixth intermediate structure 273 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, a number of MLG lines / structures 209, contacts 220, a second insulating layer 236, a second sacrificial nickel layer 230, and a second amorphous carbon layer 232. The silicon substrate 202, the circuit layer 204, and the insulating layer 206 remain relatively unchanged throughout this process.

[0042] The second insulating layer 236 typically contains a low-k compound of a carbon-containing oxide and is commonly referred to as IMD (Intra-Metal Dielectric). In some cases, other oxides and oxide forms may be used. The primary purpose of the second insulating layer 236 is to electrically isolate the signals transmitted in the numerous MLG lines / structures 209 from the signals transmitted in the numerous second MLG lines / structures 239 that will soon be formed, unless necessary. Desired connections may be made by selectively removing at least IMD second insulating layer 236 material within a small top-view area, usually referred to as a "via," and replacing its volume with an electrically conductive material.

[0043] A second sacrificial nickel layer 230 may be deposited on top of the second insulating layer 236. This layer has the function of diffusing carbon atoms so that they spread uniformly until they reach the Ni / oxide interface, in order to form high-quality sp2 bonded MLG. The second sacrificial nickel layer 230 may be heat annealed to obtain the desired grain size and edge ratio.

[0044] The second amorphous carbon layer 232 may be deposited on top of the second sacrificial nickel layer 230. The interface between the second amorphous carbon layer 232 and the second sacrificial nickel layer 230, as well as the interface between the second sacrificial nickel layer 230 and the second insulating layer 236 of the IMD, can be critical to the formation of the MLG of the desired quality formed at the interface between the second sacrificial nickel layer 230 and the second insulating layer 236. The typical thickness of the second sacrificial nickel layer 230 may be about 100 nm, about 80 nm, about 50 nm, about 130 nm, about 150 nm, or about 200 nm, depending on technical and material considerations, and the typical thickness of the amorphous carbon layer 232 may be, for example, about 10 nm, about 15 nm, about 20 nm, about 25 nm, or about 30 nm, depending on technical and material considerations. However, both of the aforementioned thicknesses may be adjusted to obtain the desired number of graphene layers within the MLG layer 238, according to technical, chemical, and materials science considerations.

[0045] As shown in Figure 2G, the seventh intermediate structure 276 is an exemplary cross-sectional view of the sixth intermediate structure 275, which has been processed to form a second MLG layer 238. The seventh intermediate structure 276 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, a number of MLG lines / structures 209, contacts 220, a first hard mask region 214, a second insulating layer 236, a second sacrificial nickel layer 230, and a second graphene layer 238. The silicon substrate 202, the circuit layer 204, and the insulating layer 206 are processed at low temperatures (below 400°C, typically below 350°C) and remain relatively unchanged throughout this process due to the formation of the MLG. The second amorphous carbon layer 232 may be subjected to pressure and temperature acceleration to diffuse through the second sacrificial nickel layer 230 and form the second MLG layer 238. Further details can be found in at least U.S. Provisional Patent Application No. 63 / 123,587, filed on December 10, 2020, and International Application PCT / US21 / 61361, filed on December 1, 2021.Furthermore, at least U.S. Patent Application No. 63 / 123,587 and PCT / US21 / 61361, and at least the papers, J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, J. Jiang, et al., "All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias," IEEE IEDM, pp. 14.3.1-14.3.4, 2017, J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018, K. Agashiwala, et al., "Reliability and Performance of CMOS-Compatible See "Multi-Level Graphene Interconnects Incorporating Vias" IEEE IEDM, 2020, and K. Agashiwala, et al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias" IEEE Transactions on Electron Devices, vol. 68, No. 4, April 2021, pp. 2063-2091, all of the above is incorporated by reference. Although the second amorphous carbon layer 232 is not shown in Figure 2G, carbon residues (not shown) may be present after the MLG formation process due to the non-uniformity of various processes and other technical considerations. Such carbon residues may be located on top of the second sacrificial nickel layer 230.

[0046] As shown in Figure 2H, the eighth intermediate structure 277 is an exemplary cross-sectional view of the seventh intermediate structure 276, where the structure has been treated to remove carbon residue (if any) from a previously present second amorphous carbon layer 232 and the second sacrificial nickel layer 230 without damaging the second MLG layer 238. The eighth intermediate structure 277 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, numerous MLG lines / structures 209, contacts 220, a first hard mask region 214, a second insulating layer 236, a second MLG layer 238, and a second hard mask layer 234. The silicon substrate 202, the circuit layer 204, and the insulating layer 206 are treated at low temperatures (below about 400°C, typically below about 350°C) and remain relatively unchanged throughout this treatment due to the formation of the MLG. The processing temperature should preferably be kept below about 350°C so as not to impair / disturb at least the transistor dopant profile, contact reliability, via reliability, and low-k dielectric stability (if any). Details of the process for removing carbon residue and nickel without damaging the MLG can be found at least in U.S. Provisional Patent Application No. 63 / 123,587 filed on 10 December 2020 and International Application PCT / US21 / 61361 filed on 1 December 2021.Furthermore, at least U.S. Patent Application No. 63 / 123,587 and PCT / US21 / 61361, and at least the papers, J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017, J. Jiang, et al., "All-carbon interconnect scheme integrating graphene wires and carbon-nanotube-vias," IEEE IEDM, pp. 14.3.1-14.3.4, 2017, J. Jiang, et al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE IEDM, pp. 34.5.1-34.5.4, 2018, K. Agashiwala, et al., "Reliability and Performance of CMOS-Compatible See "Multi-Level Graphene Interconnects Incorporating Vias," IEEE IEDM, 2020, and K. Agashiwala, et al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects with Metal Vias," IEEE Transactions on Electron Devices, vol. 68, No. 4, April 2021, pp. 2063-2091, all of which are incorporated by reference.

[0047] As shown in Figure 2I, the ninth intermediate structure 278 is an exemplary cross-sectional view of the eighth intermediate structure 277, which has been processed to define, etch, and fill vias 240 using an optional but preferably second hard mask 234. The ninth intermediate structure 278 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, a number of MLG lines / structures 209, contacts 220, a first hard mask region 214, a second insulating layer 236, a second MLG layer 238, a second hard mask layer 234, and vias 240. The ninth intermediate structure 278 is processed by lithography to form via openings in a photoresist (not shown), and then etched to open the second hard mask 234 material at the desired locations of all desired vias 240. Next, the photoresist may be stripped, the wafer / substrate may be cleaned, and deep etching may be performed to form vias 240, in which a portion / region of the thin second MLG layer 238, then a portion / region of the second insulating layer 236 and the hard mask 240, and then a number of MLG lines / structures 209 may be sequentially, and possibly selectively, removed by completely penetrating the MLG material to maximize the sidewall contact area between the vias 240 and the number of MLG lines / structures 209. The material of the hard mask 234 may include, for example, SiN, Si3N4, or a Si-rich oxide, and will be selected with sufficient technical consideration to be selectively etchable with respect to at least the second MLG layer 238, the second insulating layer 236, the first hard mask region 214, and the number of MLG lines / structures 209. The vias 240 may be subjected to desired surface cleaning (if any), followed by barrier metal deposition and via 240 filling. The majority of the volume of the via 240 may be a conductive and EM-resistant metal such as Co, Ti, Ta, W, or CNT (carbon nanotube). Depending on technical considerations, intercalation doping may be performed through the formed via 240 holes before filling the etched open vias 240.Details of intercalation doping can be found in U.S. Provisional Patent Application No. 63 / 441,766 and J. Jiang, et al., "Intercalation doped multilayer-graphene-nanoribbons for next generation interconnect," Nano Letters, 17(3), pp. 1482-1488, 2017. The top of via 240 is CMP'd, and a second hard mask 234 may be used as a polishing stop, especially since a large number of second MLG lines / structures 238 have not yet been defined or etched in this process flow.

[0048] As shown in Figure 2J, the tenth intermediate structure 279 is an exemplary cross-sectional view of the ninth intermediate structure 278, wherein a thin second MLG layer 238 may then be defined by lithography into a photoresist (not shown) and then etched to form a number of second MLG lines / structures 239. The tenth intermediate structure 279 may comprise a silicon substrate 202, a circuit layer 204, an insulating layer 206, a number of first MLG lines / structures 209, contacts 220, a first hard mask region 214, a second insulating layer 236 (sometimes referred to in the industry as "IMD" = Inter-Metal Dielectric), a number of second MLG lines / structures 239, a second hard mask layer 234, and vias 240.

[0049] An alternative process flow is to etch the MLG layer 238 to form a number of MLG lines / structures 239 before forming and filling the vias 240. However, this flow is more difficult in lithography and may be more susceptible to the effects of metal stringer formation between the number of second MLG lines / structures 239.

[0050] An alternative process flow is to etch the second MLG layer 238 to form a number of second MLG lines / structures 209 before forming and filling the vias 240. However, this flow is more difficult in lithography and may be more susceptible to the effects of metal stringer formation between the number of second MLG lines / structures 239.

[0051] The above process flow may be replicated to form the required or desired number of MLG interconnect layers within the device's BEOL. The MLG synthesis processing steps are kept below time / temperature stress levels that could damage the underlying material / interconnection and the device. This MLG processing may be utilized in one or more layers of the device's BEOL, which is determined at least by technical considerations of the process, device, and design.

[0052] The ultra-defect-free directional atomic structure of MLG allows for effective, low-R electrical contact to the MLG to be best generated from the sides of the MLG, rather than from the top or bottom of the MLG thin film structure. MLG doping at its edge surface is crucial. Furthermore, the maximum contact edge area is critical. Therefore, techniques to ensure maximum edge overlap of the MLG line / structure, which overlaps the contact or via edge, are important. As shown in Figure 3A, a typical MLG line structure 302 overlaps the edge of the exemplary contact or via 396 by an MLG overlap value of 308. This can be designed in the device database so that the masked and etched MLG line / structure has overlap to the edge of the contact or via 306. This may be designed in at least two ways. The first is an MLG line / structure 302 with a width of contact or via 306 plus overlap 308. An alternative structure is shown in Figure 3B. In this case, the width of track 312 is equal to or narrower than its sum. As a result, the width of the MLG track / structure is 310, except for the overlap that "bulges" by 308 each time a contact or via 316 appears. For either method / structure, the overlap may be designed regardless of whether the via is located below or above its particular MLG track / structure level. Thus, the overlap of the final structure is guaranteed, ensuring that the minimum contact or via resistance is obtained.

[0053] Another technique to maximize the sidewall area of ​​the MLG line / structure that is in direct contact with the via or contact material is to intentionally serrate or "roughen" the contact / via image formed on the hard mask and / or photoresist to create a via / contact structure that maximizes the perimeter of the contact or via edge, thereby maximizing the MLG edge that is in direct contact with the via / contact material during etching. For example, as shown in Figure 4A, a conventional / normal via or contact, when properly imaged, creates a near-circular shape in the resist image with a perimeter 401 of the associated circle, which is then transferred to the hard mask material in a reasonably near-circular shape, and when the hard mask image is etched into the MLG line / structure 402, a cylindrical shape of the exposed MLG sidewall is formed. The MLG line / structure 402 has a width / diameter 405 plus overlap 408 of the contact or via 406. The line width 404 of the MLG line / structure 402 includes twice the width / diameter 405 plus overlap 408 of the contact or via 406. In order to "ensure" that the edges of the contact or via 406 are entirely covered by the MLG line / structure 402, thereby obtaining a reproducible minimum contact or via resistance value, the width 404 (405 + twice 408) of the MLG line / structure 402 in this case must be greater than the width / diameter 405 of the contact or via 406. The size / value of the overlap 408 is the result of complex calculations and determinations, including process variations, such as the value of the 1-sigma or 2-sigma misalignment between the line and via, which may be direct or indirect, increases or decreases in the critical dimension of the width 404 of the MLG line / structure 402, and / or the diameter of the via etched on the device, the roughness of the line edges, and masks to suppress misalignment and variation.

[0054] In conventional via and contact resistance control, and in enabling the smallest possible connection resistance values, controlling variability and maximizing the area of ​​the via or contact structure in contact with the track structure is the driving force and most critical factor. However, to obtain minimum resistance values ​​and resistance variability control for connections to 2D layered materials such as MLG, for example, the area of ​​the sidewalls of the 2D material relative to the via / contact metal is the driving force and most critical factor. There are various methods and structures in which via or contact structures can be formed to maximize their perimeter in a top view, thereby maximizing the contact area of ​​the sidewalls of the 2D track / structure material with the via / contact material. Via or contact images on a mask (or raster operations by direct writing) can be formed (using OPC, etc.) using a selected lithography machine to image via or contact structures with the largest possible perimeter, such as the "star" pattern shown in Figure 4B, the notched structure in Figure 4C, and the toothed structure in Figures 5A and 5B. This exemplary maximum perimeter pattern, when properly imaged, can create a near-star-shaped maximum perimeter in the resist image, which is transferred relatively close to the hard mask material. When the hard mask image is then etched into the MGL line / structure, this creates a sawtooth maximum surface edge area of ​​the exposed MGL sidewall contacts. It should be noted that this maximum perimeter concept is entirely different from those previously used in the industry, despite numerous attempts to maximize the bottom contact / via area to obtain the lowest and most uniform contact or via resistance values. This is a result of the need for direct contact with the edges of the 2D material, which facilitates the formation of effective connections in the electronic band structure. Furthermore, while conventional via / contact structures avoid etching through the thickness of the line structure, these novel 2D material vias / contacts require maximizing the sidewall connection area, thus making etching through the line desirable.

[0055] As shown in Figure 4B, the MLG line / structure 412 may have an increased upper perimeter length 411 and may include vias / contacts 416. The structure may also have a line width 414 of the MLG line / structure 412 and via overlap 418 of the MLG line / structure 412.

[0056] As shown in Figure 4C, the MLG line / structure 422 may have an increased upper perimeter length 421 and may include vias / contacts 426. The structure may also have a line width 424 of the MLG line / structure 422 and via overlap 428 of the MLG line / structure 422.

[0057] Figure 5A provides a generalized illustrative explanation of how serrated edge vias or contacts increase the edge surface contact area between the 2D transmission material (e.g., MLG transmission) and the via / contact metal and metal-like (silicide, alloy, etc.) material. The improved contact / via can have a length of 2L (and thus a significantly increased contact area between the MLG and the contact / via sidewall) for the same lateral length L, thereby improving the absolute value and variability of the contact or via resistance. This concept can be applied to various graphene / MLG edge shapes, including circular, square, rectangular, and triangular shapes.

[0058] Figure 5B provides a generalized illustrative explanation of how increased contact / via perimeter and edge-only contact with 2D materials, particularly layered 2D structures such as rough / serrated or sawtoothed MLG edges, can reduce the effects of contact / via misalignment. This can represent a significant improvement over the susceptibility of conventional contacts and vias to misalignment. For example, suppose a perfectly aligned via metal 520 has a contact / via edge L that results in a contact resistance Rc. Now, if we "introduce" a 50% misalignment of the contact / via 525, this results in a lateral overlap of L / 2. The perimeter of the contact is still L if the contact / via shape has a serrated / rough or sawtoothed edge, and therefore the contact resistance Rc is still obtained. This concept can be applied to various graphene / MLG edge shapes, including circular, square, rectangular, and triangular, maintaining the degree of alignment variation, and even to various other 2D materials.

[0059] MLG tracks / structures may include many 2D materials and are not limited to graphene or multilayer "track" structures.

[0060] (Conclusion) While this embodiment has been described with reference to specific exemplary embodiments, various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the various embodiments. Therefore, this specification and the drawings should be considered illustrative rather than restrictive.

Claims

1. An interconnection structure, The first BEOL (Wiring Process) level, The first MLG (multilayer graphene) layer, The first insulating layer, The first BEOL level comprises the first MLG layer and the first insulating layer, The first MLG layer comprises a first track structure of at least one MLG material, The first insulating layer includes an electrically insulating material, The first insulating layer is arranged above the first line structure of the at least one MLG material. The first insulating layer, The second BEOL level, The second MLG layer, Connection path and At least one beer, The second BEOL level comprises the second MLG layer, The second MLG layer is positioned above the first insulating layer. The second MLG layer comprises an MLG material, The aforementioned connection path electrically connects the first MLG layer to the second MLG layer. The connection path comprises one of the at least one vias, The width of the first track structure of the at least one MLG material is greater than the diameter of one of the at least one vias. The first MLG layer and the second MLG layer are doped (n-type or p-type) by intercalation. At least one beer and An interconnection structure comprising:

2. The interconnection structure according to claim 1, further comprising a hard mask, wherein the hard mask is positioned above the second MLG layer.

3. The interconnect structure according to claim 1, further comprising a second insulating layer disposed below the first line structure of the at least one MLG material, wherein the at least one via is partially etched into the second insulating layer.

4. The interconnect structure according to claim 1, wherein the at least one via has a first perimeter that, in top view, has a sawtooth pattern, which is longer than the second perimeter of a conventional circular via having a diameter equivalent to that of the at least one via, thereby maximizing the area of ​​the side wall of the first track structure of the at least one MLG material that is in direct contact with the at least one via.

5. The interconnection structure according to claim 1, wherein the electrically insulating material includes a low-k dielectric, an air gap, or a combination of the air gap and the low-k dielectric.

6. The interconnection structure according to claim 1, wherein the first MLG layer comprises at least one graphene layer.

7. The interconnection structure according to claim 1, wherein the second width of the second track structure of the second MLG layer is greater than the diameter of one of the at least one vias.

8. An interconnection structure, The first BEOL (Wiring Process) level, The first MLG (multilayer graphene) layer, The first insulating layer, The first BEOL level comprises the first MLG layer and the first insulating layer, The first MLG layer comprises a first track structure of at least one MLG material, The first insulating layer includes an electrically insulating material, The first insulating layer is arranged above the first line structure of the at least one MLG material. The first insulating layer, The second BEOL level, The second MLG layer, Connection path and At least one beer, The second BEOL level comprises the second MLG layer, The second MLG layer is positioned above the first insulating layer. The second MLG layer comprises an MLG material, The aforementioned connection path electrically connects the first MLG layer to the second MLG layer. The connection path comprises one of the at least one vias, The second MLG layer comprises a second track structure of at least one MLG material, The width of the second track structure of the at least one MLG material is greater than the diameter of one of the at least one vias. The first MLG layer and the second MLG layer are doped (n-type or p-type) by intercalation. At least one beer and An interconnection structure comprising:

9. The interconnection structure according to claim 8, further comprising a hard mask, wherein the hard mask is positioned above the second MLG layer.

10. The interconnect structure according to claim 8, further comprising a second insulating layer disposed below the first line structure of the at least one MLG material, wherein the at least one via is partially etched into the second insulating layer.

11. The interconnection structure according to claim 8, wherein the second width of the first track structure of the at least one MLG material is greater than the diameter of one of the at least one vias.

12. The interconnection structure according to claim 8, wherein the electrically insulating material includes a low-k dielectric.

13. The interconnection structure according to claim 8, wherein the first MLG layer comprises at least one graphene layer.

14. The interconnect structure according to claim 8, wherein the at least one via has a first perimeter that, in top view, has a sawtooth pattern, which is longer than the second perimeter of a conventional circular via having a diameter equivalent to that of the at least one via, thereby maximizing the area of ​​the side wall of the first track structure of the at least one MLG material that is in direct contact with the at least one via.

15. An interconnection structure, The first BEOL (Wiring Process) level, Conventional conductor layer, The first insulating layer, The first BEOL level comprises the conventional conductor layer and the first insulating layer, The conventional conductor layer comprises a first line structure of at least one conventional conductor material, The aforementioned conventional conductive materials include Al, AlCu, Cu, TiN, Ti, TaN, Ta, W, carbon nanotubes, and CoSi 2 , TiSi 2 NiSi 2 , and WSi 2 Includes metals and metal alloys, including metal silicides such as The first insulating layer includes an electrically insulating material, The first insulating layer is arranged above the first line structure of the at least one conventional conductor material. The first insulating layer, The second BEOL level, The first MLG layer, Connection path and At least one beer, The second BEOL level comprises the MLG layer, The first MLG layer is positioned above the first insulating layer. The first MLG layer comprises an MLG material, The first MLG layer comprises a first track structure of at least one MLG material, The aforementioned connection path electrically connects the conventional conductor layer to the first MLG layer. The connection path comprises one of the at least one vias, The width of the first track structure of the at least one MLG material is greater than the diameter of one of the at least one vias. The connection path electrically connects the second MLG layer to one of the at least one vias with the minimum contact resistance. The first MLG layer is doped (n-type or p-type) by intercalation. At least one beer and An interconnection structure comprising:

16. The interconnection structure according to claim 15, further comprising a hard mask, wherein the hard mask is positioned above the first MLG layer.

17. The interconnection structure according to claim 15, wherein at least one via is partially etched into the first line structure of the at least one conventional conductor material.

18. The interconnect structure according to claim 15, wherein the at least one via has a first perimeter that, in top view, has a sawtooth pattern, which is longer than the second perimeter of a conventional circular via having a diameter equivalent to that of the at least one via, thereby maximizing the area of ​​the side wall of the first track structure of the at least one MLG material that is in direct contact with the at least one via.

19. The interconnection structure according to claim 15, wherein the first MLG layer comprises at least one graphene layer.

20. The interconnection structure according to claim 15, wherein the width of the conventional conductor line structure of the conventional conductor layer is equal to or greater than the diameter of one of the at least one vias.

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