Analog Front-End Integrated Test and Measurement System

Abstract

The test measurement device has an integrated analog front end, which includes one or more amplifiers mounted on a die of a high-speed amplifier integrated circuit, one or more signal taps and one or more impedance-controlled attenuation stages mounted on the die of the amplifier integrated circuit, an impedance-controlled signal path between the input and a reference voltage, and a switching network mounted on the die of the amplifier integrated circuit, configured to selectively couple the signal taps of the impedance-controlled signal path to the corresponding amplifiers among the one or more amplifiers.

Description

[Technical Field]

[0001] This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 461,571, filed on April 24, 2023, entitled “Attenuation Circuit Switching Circuit Integrated Amplifier Input Section,” the disclosures thereof which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to test and measurement devices, and more particularly to analog front-ends for test and measurement devices such as oscilloscopes. [Background technology]

[0003] The analog front-end (AFE) of an oscilloscope generally plays the role of amplifying or attenuating the customer's input signal as needed to obtain the optimal amplitude for driving the analog-to-digital converter (ADC). This is generally achieved by a combination of a programmable gain amplifier followed by a switched attenuation circuit. The switched attenuation circuit reduces large input amplitudes as needed to match the breakdown voltage and slew rate limitations of the amplifier's (amplification circuit's) input stage. In high-speed (several GHz) applications, this attenuation circuit is typically implemented in an impedance-controlled environment (e.g., 50Ω) to minimize reflections between the attenuation circuit and the amplifier. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2017 / 0059618 [Overview of the project] [Problems that the invention aims to solve]

[0005] Many technologies have been considered for switching such attenuation circuits, including electromechanical relays (e.g., conventional slab-line MEMS), semiconductor (solid-state) relays (e.g., FETs), and PIN diode switches. Electromechanical approaches are often large, expensive, or lack desirable reliability, while solid-state methods have inferior figures of performance (insertion loss, return loss, crosstalk, etc.) and poor handling of DC signals (they alter the bias conditions of the switching device).

[0006] The standard figure of merit for semiconductor switching devices is R ON ·C OFF It is the product of R, and in the first-order approximation, this does not depend on the scaling (miniaturization or vice versa) of the device. As the device gets larger, R ON It becomes smaller (which is beneficial in minimizing insertion losses when driving impedance-controlled loads), but C OFF This R becomes larger (this increases high-frequency crosstalk through the "open" switch). ON ·C OFF The product of these two factors fundamentally limits the high-frequency (HF) performance of impedance-controlled (impedance-controlled) switch circuits. [Means for solving the problem]

[0007] One embodiment of the present disclosure is a test measurement apparatus 100 having an analog front-end 108 that tightly integrates an attenuation circuit and associated switching functions on the die of a high-speed amplifier (amplifier circuit). This allows the attenuation circuit to be placed physically close enough to the amplifier and the switching to be performed outside the impedance-controlled signal path. Specifically, the signal path always passes through one or more impedance-controlled attenuation circuits, and the switching circuit may be placed between various attenuation signal taps and one or more amplifier inputs. ON This is not an impedance-controlled signal line, but nominally drives the input of a high-impedance amplifier, and also switches COFF is nominally matched to the input capacitance C IN of the amplifier and can be corrected by the T-coils and other inductive peaking circuits that have long been required for the amplifier. This significantly decouples the switching performance of the attenuation circuit from the ON ·C OFF figure of merit, thereby enabling high performance even under the constraint of using switching devices existing on the same semiconductor process selected for high-speed amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] [Figure 1] FIG. 1 is a block diagram of a test and measurement device that tightly integrates an analog front end according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram showing an example of integrating an analog front end according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 1 is a block diagram of a test and measurement device 100, such as an oscilloscope, that tightly integrates an analog front end (AFE) 108 according to an embodiment of the present disclosure. The test and measurement device 100 has one or more ports 102, which may be any electrical or optical signal transmission medium. The ports 102 may include receivers, transmitters, or transceivers. Each port 102 is connected to one channel of the test and measurement device 100. In some embodiments, the test and measurement device 100 includes 8, 16, or more independent ports. The test and measurement device 100 may be coupled to a device under test (DUT) 101 through one or more ports 102. A DUT 101 having multiple outputs may connect each output to the test and measurement device 100 through multiple independent ports 102.

[0010] The input signal received at port 102 is sent to the analog front-end 108, which adjusts the input signal. The adjusted input signal is input to one or more ADCs 104. As described above, the analog front-end (AFE) 108 generally attenuates or amplifies the input signal to make optimal use of the dynamic range of the ADCs 104. In various embodiments, there may be multiple AFEs 108, each connected to a different input port 102, to adjust the input signal received at that port. The attenuated / amplified analog signal from the AFEs 108 may be output to one or more ADCs 104. The ADCs 104 convert the analog signal received through one or more ports 102 into digital data representing the input signal. In some embodiments, the ADCs 104 may have an interleaved structure. Interleaving multiple ADCs means that each individual ADC in the interleaved ADCs 104 processes only a portion of the data from input ports 102 / AFEs 108. The ADC 104 has a sampling rate sufficient to sample the input signal with a resolution that is available to the test measurement device 100, and may have a resolution of 8 bits, 12 bits, or more. The output data from the interleaved ADC 104 is recombined by the de-interleaver 110 to generate a full-bandwidth signal that the test measurement device 100 receives.

[0011] In some embodiments, the digital output of the ADC 104 is also coupled to a trigger detector 106. The trigger detector 106 is configured to monitor the digitized input signals and detect when a trigger event occurs with one or more input signals. The trigger event may be specified by the user through the user input 130. When a trigger event is detected, the trigger detector 106 outputs a trigger signal, which the acquisition processor 112 may use to determine which information from the DUT to store in the acquisition memory 114 as input waveforms for measurement and testing of the DUT.

[0012] The acquisition memory 114 is a relatively large memory that is structured to quickly store large amounts of received data. The acquisition memory 114 may be implemented as volatile memory or as solid-state memory, such as a solid-state disk drive.

[0013] The test measurement device 100 also includes one or more main processors 120 configured to execute instructions from the main memory 121, which can perform any method or associated steps indicated by these instructions.

[0014] The user input unit 130 is coupled to one or more processors 120 and may have a keyboard, mouse, touchscreen, or other optional operating device that the user can use to interactively operate the GUI on the output display 132. In some embodiments, the user input unit 130 may be connected to or controlled by a remote interface 134, so that the user can control the operation of the test measurement device 100 from a remote location physically separated from the test measurement device. The display 132 may be a digital screen such as an LCD or other monitor for displaying waveforms, measurements, and other data to the user. In some embodiments, the output display 132 is also located far away from the test measurement device 100.

[0015] One or more measurement units 140 are shown as part of the test measurement apparatus 100. These measurement units 140 perform the primary function of measuring the parameters and other characteristics of the signal from the DUT 101 that the test measurement apparatus 100 measures. Typical measurements include measuring the voltage, current, and power of the input signal in the time domain, and measuring the characteristics of the input signal in the frequency domain. The measurement units 140 typically provide any measurements that the test measurement apparatus would perform.

[0016] The components of the test measurement device 100 are depicted as being integrated within the test measurement device 100. However, one of ordinary skill in the art will understand that any of these components may exist outside of the test measurement device 100 and be connected to the test measurement device 100 by any conventional method (e.g., wired or wireless communication media or mechanisms). For example, in some embodiments, the display 132 may be located remotely from the test measurement device 100, or data and images from the output of the test measurement device may be available on other devices through a cloud or other communication network 150.

[0017] FIG. 2 shows an example of an analog front end 208 that is closely integrated within a test measurement device, according to some embodiments of the present disclosure. The analog front end 208 may be an example of the analog front end 108 of FIG. 1. As shown in FIG. 2, the analog front end (AFE) includes one or more amplifiers 210a and 210b. These amplifiers (amplification circuits) may be single-ended or differential depending on the various embodiments. These amplifiers are high-bandwidth and high-speed amplifiers that amplify an analog input signal up to the full bandwidth of the test measurement device. This test measurement device may reach a range of several gigahertz in modern oscilloscopes. For this reason, these amplifiers are physically implemented on a die of a high-speed amplifier integrated circuit (IC). That is, the die is made from a semiconductor material and is based on a semiconductor process that can support broadband analog signals and high-speed switching. According to some embodiments, the amplifiers are all physically implemented on the same common die. That is, all of the amplifiers are within the same IC.

[0018] AFE208 also has an impedance-controlled signal path 212. The impedance-controlled signal path 212 shown in FIG. 2 proceeds from the input section 214 to the reference voltage 216, moving downward along the left side of the figure. The input section 214 is connected to any one of the plurality of input ports 102 in FIG. 1 and may receive the analog signal received from the DUT at that input port. The reference voltage 216 may be ground (earth) as shown in FIG. 2. The impedance-controlled signal path 216 may have a final termination resistor 218 to the reference voltage, such as a final termination resistor to ground, as shown in FIG. 2. In some embodiments, the impedance of the impedance-controlled signal path 212 may be 50 ohms.

[0019] The impedance-controlled signal path 212 has one or more impedance-controlled attenuation circuits or attenuation stages 220. Each attenuation stage 220 is configured to attenuate the signal passing through the signal path 212 with various attenuation factors, such as 100×, 50×, 25×, 10×, 5×, 2.5×. In some embodiments, as in the example of FIG. 2, each attenuation stage 220 may be implemented as a resistive voltage divider circuit. The example embodiment shown in FIG. 2 shows only one attenuation stage 220, but in another embodiment, one or more additional attenuation stages may be included. One or more impedance-controlled attenuation stages 220 are implemented on the same integrated circuit die as amplifiers 210a and 210b. In some embodiments, the connection of the impedance-controlled signal path to the reference voltage / ground 216 and the connection of the attenuation stage 220 to ground are provided on the integrated circuit as, for example, a reference voltage pin, and this may be connected to a programmable "Vterm" termination voltage "off-chip (outside the chip)".

[0020] The impedance-controlled signal path 212 also has one or more signal taps 222a and 222b. The signal taps 222a and 222b branch (tap) the signal passing through the signal path 212 before and after each attenuation circuit 220, so that the signals appearing at each of the signal taps 222a and 222b are subjected to a succession of attenuation coefficients. In the example in Figure 2, the uppermost signal tap 222a is connected to the unattenuated input signal, and the subsequent tap 222b is connected to the input signal attenuated by a predetermined attenuation coefficient of the attenuation stage 220. In another embodiment, there may be two or more signal taps and associated amplifiers before the first attenuation stage. This can be useful for realizing a high-gain, distributed amplifier circuit configuration and also allows for additional gain switching when used without attenuation (when the amplitude of the input signal is small).

[0021] In some embodiments of this disclosure, the signal path 212 may further include inductive peaking circuits 224a and 224b at signal taps 222a and 222b, respectively. The inductive peaking circuits 224a and 224b may consist of well-known T-coils or other inductive peaking methods. Each of the taps 222a and 222b is inductively peaked (using an inductor) to cancel out the load capacitance of the associated amplifiers 210a and 210b (when selected) and the off capacitance of the switch (when not selected).

[0022] According to some embodiments of this disclosure, the outputs of impedance-controlled signal path attenuation circuits and subsequent attenuation circuits may be designed to progressively lower impedances (for example, to reduce the amount of inductive peaking required). Furthermore, according to some embodiments, the attenuation circuits may be designed to reduce attenuation as the frequency increases (a so-called "positive gain slope"). This is to compensate for the increased losses in inductors and impedance-controlled input signal lines as the frequency increases. This results in a nominally flat response across many attenuation stages and improves the flexibility of the overall attenuation circuit selection. In yet another embodiment, some attenuation circuits may be replaced with continuous-time linear equalizers (CTLEs) having a larger positive gain slope, allowing for additional compensation for high-frequency losses in the customer's internal connections outside the oscilloscope.

[0023] The AFE208 also includes a switching network 240. The switching network 240 may also include switching circuits 230a and 230b associated with the signal taps 222a and 222b, respectively, and the corresponding amplifiers 210a and 210b. The switching network 240 is configured to selectively couple either of the signal taps 222a and 222b to the inputs of the corresponding amplifiers 210a and 210b. The switching network 240 is physically mounted on the same integrated circuit die as one or more amplifiers 210a and 210b. A controller (not shown) controls the operation of the switching network 240, for example, in response to user inputs received at the user input unit 130 or remote commands received at the interface 134. In some embodiments, the controller may be the main processor 120.

[0024] The switching network 240 and the individual switching circuits 230a and 230b can be implemented using various switching devices based on various embodiments of this disclosure. In the example of the embodiment in Figure 2, each switching circuit 230a and 230b uses PIN diodes 232a and 232b (basically NPN base-collector junctions) as switching devices, which are generally available in high-speed bipolar processes and are suitable for high-speed broadband amplifiers used in the AFE of an oscilloscope. However, other semiconductor switches such as FETs can also be used based on other embodiments (if available in the selected process, R ON ·C OFF (If they are equivalent). PIN diodes 232a and 232b are sometimes called input PIN diodes or series PIN diodes.

[0025] In the embodiment shown in Figure 2, switching circuits 230a and 230b each further include shunt PIN diodes 234a and 234b connected to bias voltages Vbias 235a and 235b, and relatively high-value resistors 236a and 236b connected to control voltages Vcntrl 237a and 237b. Vbias 235a and 235b are nominally fixed bias voltages (e.g., +2V), capacitively coupled to ground, and provide very low AC impedance. When the control voltages Vcntrl 237a and 237b of amplifiers 210a and 210b, respectively, are set to low values ​​(e.g., -5V), the respective input PIN diodes 232a and 232b are forward-biased (turned on), and the shunt PIN diodes 234a and 234B are reverse-biased (turned off) with respect to Vbias. As a result, the input signal is transmitted to amplifiers 210a and 210b selected from signal taps 222a and 222b, respectively. When the amplifier's Vcntrl is set to a high value (e.g., +5V), the input PIN diode is off and the shunt PIN diode is on. In this setting, the amplifier's input is quiescent, and a capacitor is connected to the signal tap. OFF This loads the amplifier's net capacitance. IN (C of shunt PIN diode)OFF It can be selected to match (including), thereby keeping the load on the tap nominally constant and maintaining the characteristic of controlling the impedance of the impedance-controlled signal path 212.

[0026] Two similar PIN diode switches may be inserted into the inputs of the opposing offsets of the differential operation of each amplifier (not shown) and controlled by the same Vcntrl, thus also serving as input switches for those amplifiers. This provides a differentially balanced voltage drop across the amplifier when selected, and zero drive to the amplifier when deselected (to avoid reverse Vbe stress on the amplifier device).

[0027] In some embodiments, to better match the amplifier's input impedance across the entire frequency range, the series PIN diode switches 232a and 232b may be shunted by an impedance matching (e.g., RC) circuit instead of shunt PIN diodes 234a and 234b.

[0028] In some embodiments of this disclosure, the same functionality as described above may be achieved by reversing the polarities of the diode connection, Vcntrl, and Vbias.

[0029] The PIN diode switches 232a and 234a, shown before the first attenuation circuit in Figure 2, provide some degree of protection (clamping) against a strike-type positive electrostatic discharge (ESD) at the input. According to some embodiments of this disclosure, there are two amplifiers before the first attenuation circuit, one of which is implemented with the diode polarity reversed, so this combination provides bidirectional ESD protection.

[0030] The selected amplifier 210a or 210b amplifies the signal from the corresponding signal tap 222a or 222b, respectively. In some embodiments, all amplifiers may have predetermined gains, which may differ from one another. In other embodiments, the amplifiers may have programmable gains. In yet another embodiment, some of these amplifiers may have predetermined gains, and some may have programmable gains. In some embodiments, the power to unselected amplifiers may be turned off to minimize crosstalk and power waste. In some embodiments, two or more amplifiers may be selected (and powered on) simultaneously. This further increases the flexibility of overall gain selection.

[0031] The amplified signal may then be output to a multiplexer 250. The output multiplexer (MUX) 250 selects the output from the selected input amplifier to observe the input signal (or its attenuated form). The output of the MUX 250 is sent to one or more ADCs 104 for sampling and digitization, as shown in Figure 1.

[0032] According to some embodiments of this disclosure, the output MUX function can be moved to the amplifier input side by adding another series PIN diode (orientation reversed) to the right of a high-value (also known as long-tail) control resistor. The anodes of these diodes are coupled to each other and connected to a single long-tail pull-up resistor and the amplifier input. This not only allows a single amplifier stage to be driven by selecting only one input tap at a time, but also minimizes the amplifier layout area and eliminates the need for independent output multiplexer functionality.

[0033] During operation, if the amplitude of the input signal is small, the first amplifier 210a is selected. For large input signals, an amplifier that would be overdriven (and the input signal would be applied in a non-linear manner) (e.g., 210a) is deselected, and one or more later amplifiers (e.g., 210b) that receive a sufficiently attenuated signal to operate linearly are selected. The allowable linear input signal amplitude is limited only by the breakdown voltage of the PIN diode (or other switching device) and is not dependent on the dynamic range or slew limit of the amplifier device.

[0034] Figure 2 shows an embodiment for receiving a single-ended input signal. According to some embodiments of this disclosure, the entire structure described above may be implemented differentially (i.e., with two input signal paths, two switch circuits, etc.).

[0035] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data type expressions. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, and RAM. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0036] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0037] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0038] A communication medium means any medium that can be used to transmit computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, sound, or other types of signals.

[0039] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular embodiment, that feature may also be available in relation to other embodiments, to the extent possible.

[0040] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0041] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention.

Claims

1. One or more amplifiers mounted on a die of a high-speed amplifier integrated circuit, It has one or more signal taps and one or more impedance-controlled attenuation stages mounted on the die of the amplifier integrated circuit, and an impedance-controlled signal path between the input and the reference voltage, The signal taps of the impedance-controlled signal path are configured to be selectively coupled to the corresponding amplifiers among the one or more amplifiers, and the switching network is mounted on the die of the amplifier integrated circuit. A test and measurement device with an integrated analog front-end.

2. The test and measurement apparatus according to claim 1, further comprising a multiplexer having an input coupled to the output of one or more of the above-mentioned amplifiers, and configured to output an amplified signal from a selected amplifier among the one or more of the above-mentioned amplifiers.

3. The test and measurement apparatus according to claim 2, wherein the multiplexer is mounted on the die of the amplifier integrated circuit.

4. The test and measurement apparatus according to claim 2, further comprising a controller for controlling the operation of the switching network and the multiplexer.

5. The test and measurement apparatus according to claim 3, wherein the controller is configured to turn off the power to the unselected amplifier among the one or more amplifiers.

6. The test and measurement apparatus according to claim 1, wherein the switching network has a switching circuit associated with each amplifier in the one or more amplifiers, and the switching circuit has a PIN diode.

7. The test and measurement apparatus according to claim 1, wherein each of the one or more amplifiers has a different gain.

8. The test and measurement apparatus according to claim 1, wherein at least one of the one or more amplifiers described above has a predetermined gain.

9. The test and measurement apparatus according to claim 1, wherein at least one of the one or more amplifiers described above has a programmable gain.

10. The test and measurement apparatus according to claim 1, wherein each of the one or more damping stages has a different damping coefficient.

11. The test measurement apparatus according to claim 1, wherein one or more of the above-mentioned attenuation stages are composed of a plurality of stepped attenuation stages, each having an impedance that decreases in steps.

12. The test measurement apparatus according to claim 1, wherein one or more of the above-mentioned attenuation stages are configured such that the attenuation decreases as the frequency increases.

13. The test measurement apparatus according to claim 1, wherein the impedance-controlled signal path has one or more continuous-time linear equalizers (CTLEs).

14. The test and measurement apparatus according to claim 1, wherein the first signal tap is connected to the impedance-controlled signal path between the input section and the first attenuation stage, and the unattenuated input signal is selectively coupled to the corresponding first amplifier.

15. The test and measurement apparatus according to claim 1, wherein the impedance-controlled signal path has an inductive peaking circuit at each of the signal taps.

16. The test and measurement apparatus according to claim 1, wherein the above reference voltage is ground.

17. The test and measurement apparatus according to claim 16, wherein the impedance-controlled signal path has a termination resistor to the ground.

18. The test and measurement apparatus according to claim 1, wherein the die of the amplifier integrated circuit has a pin configured to receive a programmable termination voltage as the reference voltage.

19. The test and measurement apparatus according to claim 1, wherein the above-mentioned test and measurement apparatus is comprised of an oscilloscope.

20. An integrated circuit that provides an analog front end for an oscilloscope, One or more amplifiers, It has one or more signal taps and one or more impedance-controlled attenuation stages, and an impedance-controlled signal path between the input and a reference voltage, A switching network configured to selectively couple the signal taps of the impedance-controlled signal path to the corresponding amplifiers among the one or more amplifiers, An integrated circuit equipped with [a certain feature].

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