High aspect ratio contact etching using additional gases

Abstract

A method for processing a substrate, comprising the steps of: flowing a fluorocarbon, a metal halide, and dihydrogen (H2) into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate comprising a dielectric layer containing silicon oxide as an etching target and a patterned hard mask containing polycrystalline silicon (poly-Si) on the dielectric layer; generating plasma in the plasma processing chamber while flowing a gas; and forming high aspect ratio feature portions by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during exposure.

Description

[Technical Field]

[0001] Cross-reference of related applications This disclosure asserts the interests of U.S. Patent Application No. 18 / 191,098, filed on 28 March 2023, which is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to a method for processing a substrate, and in particular embodiments to high aspect ratio contact (HARC) etching using an additional gas. [Background technology]

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing layers of dielectric material, conductive material, and semiconductor material onto a substrate, patterning them, and forming a network of integrated electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) as a monolithic structure. Many of the processing steps used to form the constituent structures of semiconductor devices are carried out using plasma processing. [Overview of the project] [Problems that the invention aims to solve]

[0004] The semiconductor industry has repeatedly strived to reduce the size of the smallest feature region of semiconductor devices to a few nanometers in order to increase the integration density of components. Accordingly, the semiconductor industry is increasingly demanding plasma processing technologies that can pattern feature regions at atomic-scale dimensions, often with accuracy, precision, and profile control. Meeting this challenge along with the uniformity and reproducibility required for mass production of ICs necessitates further innovation in plasma processing technologies. [Means for solving the problem]

[0005] According to embodiments of the present invention, a method for processing a substrate includes the steps of flowing a fluorocarbon, a metal halide, and dihydrogen (H2) into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate including a dielectric layer containing silicon oxide as an etching target and a patterned hard mask containing polycrystalline silicon (poly-Si) on the dielectric layer; generating plasma in the plasma processing chamber while flowing gas; and forming high aspect ratio feature portions by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during exposure.

[0006] According to embodiments of the present invention, a method for processing a substrate includes the steps of flowing a fluorocarbon and a silane compound into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate including a dielectric layer containing silicon as an etching target and a patterned hard mask on the dielectric layer; generating plasma in the plasma processing chamber while flowing a gas; and forming high aspect ratio feature portions by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during exposure.

[0007] According to embodiments of the present invention, a method for processing a substrate includes the steps of: flowing a fluorocarbon into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate including a dielectric layer as an etching target and a patterned hard mask on the dielectric layer; maintaining a plasma generated from the fluorocarbon in the plasma processing chamber while flowing the fluorocarbon; flowing a metal halide and dihydrogen (H2) into the plasma processing chamber while maintaining the plasma; flowing a silane compound into the plasma processing chamber while maintaining the plasma; and forming a high aspect ratio feature portion by exposing the substrate to the plasma and etching the recesses of the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure.

[0008] To fully understand the present invention and its advantages, refer hereto to the following description, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1A-1C] The following are cross-sectional views of exemplary substrates during a semiconductor manufacturing process, including a plasma etching process for forming high aspect ratio (HAR) features according to various embodiments: Figure 1A shows an incoming substrate including a patterned hard mask layer, a dielectric layer, and an etching stop layer (ESL); Figure 1B shows the substrate during the formation of HAR features by the plasma etching process; and Figure 1C shows the substrate after the plasma etching process is complete. [Figure 2] This diagram shows the energy levels for the adsorption / desorption of metal fluoride species (WF4) on a silicon oxide surface. [Figure 3] This diagram shows the energy levels for adsorption / desorption of a metal fluoride species (WF4) on a silicon surface. [Figure 4]This diagram shows the energy levels of the formation of a deposition precursor (WF5) from a metal fluoride species (WF6) via heavy-particle-assisted dissociation. [Figure 5] This shows the energy level diagram for the formation of deposition precursors (SiH3) from silane species (SiH4) via heavy particle-assisted dissociation. [Figure 6A-6C] The process flow diagrams of the plasma etching process method for forming the characteristic parts of HAR according to various embodiments are shown, with Figure 6A showing one embodiment, Figure 6B showing another embodiment, and Figure 6C showing yet another embodiment. [Figure 7] An exemplary plasma processing tool according to an embodiment of the present disclosure is shown. [Modes for carrying out the invention]

[0010] This application relates to the manufacture of semiconductor devices, such as integrated circuits including semiconductor devices, and more specifically, high-capacity three-dimensional (3D) memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random-access memory (DRAM) devices. The manufacture of such devices may generally require the formation of conformal high aspect ratio (HAR) feature areas (e.g., contact holes) of circuit elements. Feature areas with an aspect ratio (ratio of the height of a feature area to its width) higher than 50:1 are generally considered high aspect ratio feature areas, and in some cases, the creation of even higher aspect ratios, such as 100:1, may be desirable for advanced 3D semiconductor devices. However, conventional HAR etching methods often involve tens, and sometimes hundreds, of processing steps, typically used, for example, as a periodic process, which complicates process optimization and reduces the amount of etching. Furthermore, conventional HAR etching methods can often result in serious distortion and twisting in the final structure. Therefore, the HAR etching process still faces challenges such as low wafer processing capacity, insufficient uniformity, and contact loss. Thus, a simple but effective HAR process is desired. Embodiments of this application disclose a method for manufacturing HAR features by a plasma etching process based on fluorocarbons enhanced with additional gases such as metal fluorides and silane compounds. HAR features having aspect ratios higher than 50:1, for example, from 50:1 to 200:1, can be manufactured using the embodiments considered in this application.

[0011] The plasma etching method described herein can overcome various challenges posed to plasma etching processes for feature areas of HARs. In various embodiments, the plasma etching process can advantageously achieve a high AR of 100:1 or more with good selectivity for hard masks. In particular, additional gases can improve mask selectivity (e.g., etching selectivity for masks containing polycrystalline silicon) by selectively providing a metal-containing or silicon-containing passivation layer on the mask. Using this method, dielectric layers such as silicon oxide can be etched with improved selectivity while maintaining a good etching rate. This plasma etching process according to the present method can be carried out in a single step, rather than being a periodic etching process requiring multiple steps.

[0012] Below, exemplary plasma etching processes assisted by additional gases to form desired high aspect ratio (HAR) features, according to various embodiments, are discussed in Figures 1A to 1C. The selective deposition of metal-containing passivation layers on a hard mask onto an etching target is described with reference to Figures 2 and 3, using the calculated formation energy of the deposition precursor. Possible reaction pathways for forming metal-containing or silicon-containing deposition precursors are described with reference to Figures 4 and 5. Then, exemplary process flow diagrams are shown in Figures 6A to 6C. An exemplary capacitively coupled plasma (CCP) processing tool for the methods of the embodiments is shown in Figure 7. All figures are for illustrative purposes only and are not to scale.

[0013] Figure 1A shows a cross-sectional view of an exemplary input substrate 100, including a dielectric layer 110 and a patterned hard mask layer 120, according to various embodiments.

[0014] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate may include heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, and silicon or silicon on an SOI substrate.

[0015] In various embodiments, the substrate 100 is part of a semiconductor device or includes a semiconductor device and can undergo several steps of processing following a conventional process, for example. For example, the semiconductor structure may include the substrate 100 on which various device regions are formed. At this stage, the substrate 100 may include isolated regions such as shallow trench isolation (STI) regions and other regions formed therein. In various embodiments, high aspect ratio (HAR) feature regions may be formed on the substrate 100 by a plasma etching method described herein and can then be used to manufacture 3D memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM).

[0016] The dielectric layer 110 can be formed on the substrate 100. In various embodiments, the dielectric layer 110 is a target layer that will be patterned into one or more high aspect ratio (HAR) features. In certain embodiments, the HAR features etched in the dielectric layer 110 can be other suitable structures including contact holes, slits, or recesses. In certain embodiments, the dielectric layer 110 can be a silicon oxide layer or other layers that may be useful for DRAM. In another embodiment, the dielectric layer 110 can include silicon nitride, silicon oxynitride, an O / N / O / N layer stack (a stacked layer of oxide and nitride), or any suitable material that can be used, for example, in a 3D-NAND stack. The dielectric layer 110 can be deposited using suitable techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD) and other processes. In one embodiment, the dielectric layer 110 has a thickness of 1 μm to 10 μm. In another embodiment, the dielectric layer 110 can include a layer stack, and each layer of the stack has a thickness of 50 nm to 2.5 μm.

[0017] In certain embodiments, the substrate 100 can further include an etching stop layer (ESL) 105 between the substrate 100 and the dielectric layer 110. The substrate 105 can include a dielectric material that provides high etching selectivity during a plasma etching process (e.g., FIG. 1C) to prevent unwanted damage to the substrate 100. In various embodiments, the ESL is merely optional and may not be present on the substrate 100, and the substrate 100 itself can stop etching during a plasma etching process.

[0018] Referring further to FIG. 1, the patterned hard mask layer 120 is formed on the dielectric layer 110. In various embodiments, the patterned hard mask layer 120 may include polycrystalline silicon (poly-Si). In one or more embodiments, the patterned hard mask layer 120 may include spin-on carbon, tungsten carbide, boron carbide, or other suitable mask materials. Although not shown in FIG. 1A, the patterned hard mask layer 120 may include a layer stack of different materials, such as poly-Si and another material. The patterned hard mask layer 120 may be formed by first depositing the hard mask layer using, for example, suitable spin coating techniques, or vapor growth techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma enhanced CVD (PECVD) and other processes. The deposited hard mask layer may then be patterned using, for example, lithography processes and anisotropic etching processes, such as using oxygen-based etching chemistries. The relative thicknesses of the patterned hard mask layer 120 and the dielectric layer 110 may have any suitable relationship. For example, the patterned hard mask layer 120 may be thicker than, thinner than, or the same thickness as the dielectric layer 110. In certain embodiments, the patterned layer 120 has a thickness of 1 μm to 4 μm. In one embodiment, the patterned hard mask layer 120 includes poly-Si, has a thickness of 2.5 μm, and a critical dimension (CD) of 75 nm, although in other embodiments, the thickness and CD of the patterned hard mask layer 120 may have any suitable values, respectively.

[0019] The patterned hard mask layer 120 and the dielectric layer 110 can be collectively regarded as part of the substrate 100. Further, the substrate 100 may include other layers. For example, for the purpose of patterning the hard mask layer, there may be a three-layer structure including a photoresist layer, a SiON layer, and an optical planarization layer (OPL).

[0020] Figure 1B shows the substrate 100 during the formation of the HAR feature area by a plasma etching process.

[0021] The fabrication of HAR features in the dielectric layer 110 can be carried out by a plasma etching process using a combination of process gases, including additional gases for passivation according to various embodiments.

[0022] Plasma etching processes may include reactive ion etching (RIE) processes using halogen-containing etching gases. In various embodiments, the etching gas may include hydrofluorocarbons, combinations of hydrocarbons and fluorine-containing gases, or combinations of fluorocarbons and hydrogen-containing gases. In certain embodiments, one or more fluorocarbons may be used as primary etching gases. In one embodiment, saturated fluorocarbons, unsaturated fluorocarbons, or combinations thereof may be included in the process gas. In this disclosure, unsaturated fluorocarbons refer to any compound containing carbon and fluorine having at least one carbon-carbon double bond (C=C bond) or triple bond (C≡C bond), and saturated fluorocarbons refer to any compound containing carbon and fluorine without any C=C bond or C≡C bond. Examples of unsaturated and saturated fluorocarbons include hexafluorobutadiene (C4F6), hexafluoro-2-butyne (C4F6), and hexafluorocyclobutene (C4F6), as well as octafluoropropane (C3F8), perfluorobutane (C4F6) 10 ), and perflanepent (C5F 12 These are some examples, but are not limited to them.

[0023] In certain embodiments, other gases, such as inert gases (e.g., Ar, He, or N2) or equilibrators (e.g., O2 or CO), may also be added to the process gas. In various embodiments, one or more equilibrators may be included in the process gas of the plasma etching process to control the degree of polymer deposition. Generally, some polymer deposition can be beneficial in providing passivation of the sidewalls of the mask and etching target, but excessive deposition can slow the etching rate and lead to irregularities in the etching profile and even clogging. Therefore, polymer deposition may need to be appropriately controlled, for example, using equilibrators, to achieve a good balance between sidewall passivation and etching rate / profile.

[0024] In this disclosure, any list presenting possible compositions, conditions, or process variations includes any reasonable combination thereof, and therefore the term “or” used in the list does not indicate any exclusive selection of any particular composition, condition, or process variation. For example, in certain embodiments, argon (Ar) and dioxygen (O2) may be included as an inert gas and equilibrator, respectively. In other embodiments, dinitrogen (N2) and O2 may be included as process gases.

[0025] In another embodiment, the gas combination may further include a third fluorocarbon. In one embodiment, the third fluorocarbon may be octafluorocyclobutane (C4F8), octafluoro-2-butene (C4F8), hexafluoropropylene (C3F6), carbon tetrafluoride (CF4), or fluorofoam (CHF3). While the above examples are mainly fluorine-based etching gases, other halogen-containing gases (e.g., BCl3, Cl2, and HBr) may also be used.

[0026] While carbon and fluorine species from these primary etching gases can form polymer layers deposited on the surface and provide some degree of passivation, the inventors of this application have identified that the etching process may still suffer from problems such as insufficient mask selectivity and warping. For example, warping may still occur, especially when the etching process time is extended and the aspect ratio of the feature area increases.

[0027] To improve the plasma etching process, various embodiments of the methods of this disclosure employ the incorporation of an additional gas for better passivation. In various embodiments, the additional gas may include a mixture of a metal halide and a hydrogen-containing gas, or a silane compound (silane). In this disclosure, silane compounds and silanes refer to a general category of compounds including silicon, and are distinguished from SiH4, which is called monosilane in this disclosure. The metal halide may include a heat-resistant metal. In certain embodiments, the metal halide may include tungsten hexafluoride (WF6), molybdenum hexafluoride (MoF6), niobium hexafluoride (NbF6), or tungsten hexachloride (WCl6). In other embodiments, the metal halide may include aluminum or titanium, for example, in one embodiment, aluminum trichloride (AlCl3) or titanium tetrachloride (TiCl4). In one or more embodiments, the hydrogen-containing gas may include dihydrogen (H2), hydrogen fluoride (HF), hydrogen bromide (HBr), or methane (CH4). In various embodiments, the silane compound may be monosilane (SiH4), disilane (Si2H6), or halogenated silane (SiH x X y ) may include.

[0028] While we do not wish to be limited by any theory, as will be further explained below with reference to Figures 5 and 6, the use of a hydrogen-containing gas (e.g., H2) in addition to a metal halide (e.g., WF6) can favorably promote the formation of deposition precursors via heavy particle-assisted dissociation. In contrast, such secondary additives (e.g., H2) can be omitted when using silane compounds, as other plasma species (e.g., fluorine species) can adequately induce heavy particle-assisted dissociation.

[0029] In one embodiment, the plasma etching process may be oxide etching for etching silicon oxide using poly-Si as an etching mask and an etching process gas containing C4F8, C4F6, C3F8, O2, NF3, WF6, and H2. In another embodiment, the plasma etching process may be the same oxide etching, but the etching process gas may contain C4F8, C4F6, C3F8, O2, NF3, and SiH4.

[0030] Only small amounts of additional gas may be required to favorably influence the plasma etching process. In various embodiments, the flow rate of the metal halide (e.g., WF6) may be less than 1% of the total process gas flow rate, for example, from 0.01% to 1%. In certain embodiments, it may be less than 0.3% of the total process gas flow rate. In another embodiment, the flow rate of the metal halide may be determined with respect to one component of the primary etching gas (e.g., fluorocarbon), for example, from 1% to 5% of the flow rate of that component. Excess amounts of metal halide (e.g., more than 5% of the total gas flow rate) can result in undesirable deposits on the substrate, chamber walls, and other surfaces in the apparatus, thus allowing the use of minimal amounts of metal halide addition in various embodiments.

[0031] In various embodiments, the gas flow rate may be mass-based and may be controlled by one or more mass flow controllers in the gas inlet system to introduce the gas into the plasma processing chamber. Therefore, unless otherwise stated, the gas flow rate refers to the gas flow rate at the time of entry into the plasma processing chamber.

[0032] In certain embodiments, the flow rate of the metal halide (e.g., WF6) is less than 2 sccm, for example, 0.1 sccm to 2 sccm. In certain embodiments, the additional gas can be pulsed into the plasma processing chamber instead of a constant flow rate, which may allow the introduction of a gas amount below the lower limit of the constant flow rate provided by the mass flow controller.

[0033] Referring further to Figure 1B, the recess 125 can be formed in the dielectric layer 110 by a plasma etching process. The recess 125 can be of any shape and structure and may be designed to produce, for example, a contact hole, a slit, or other suitable structure including a recess useful for semiconductor device manufacturing. In various embodiments, the feature defined by the recess 125 has a limiting dimension (CD) of 200 nm or less. In certain embodiments, the CD may be between 50 nm and 200 nm. For example, the feature may include a slit with a CD of about 150 nm. In another embodiment, the recess 125 may include a hole with an upper opening of 80 nm or less in diameter.

[0034] Furthermore, as shown in Figure 1B, a passivation layer 130 can be formed on the patterned hard mask layer 120. In various embodiments, additional gases can alter the chemical composition of the passivation layer 130, resulting in improved mask selectivity and overall etching performance. Generally, depending on the type of additional gas (i.e., metal-containing or silicon-containing), the passivation layer 130 may contain metal or silicon. For example, a metal or silicon species may be incorporated into the carbonaceous polymer layer. Alternatively, the passivation layer may contain metal fluorides or silicon fluorides. As shown in Figure 1B, the passivation layer 130 can cover the entire top surface and sidewalls of the patterned hard mask layer 120. In certain embodiments, the passivation layer 130 may be selectively deposited on the patterned hard mask layer 120 without being on the surface of the dielectric layer 110 within the recess 125, while in other embodiments, it may be deposited on a portion of the surface of the dielectric layer 110.

[0035] Figure 1C shows the substrate 100 after the plasma etching process is completed.

[0036] Continuing the plasma etching process, the recess 125 shown in Figure 1B may be further expanded by etching through the entire thickness of the target layer (i.e., the dielectric layer 110), as shown in Figure 1C, to reach / land on the upper surface of the ESL 105.

[0037] In certain embodiments, although not shown in Figure 1C, a polymer passivation layer containing carbon and fluorine may still be present on the surface of the dielectric layer 110 within the recess 125, which can provide some degree of sidewall protection. In one embodiment, polymer deposition on the exposed surface of the ESL 105 can advantageously improve the etching stopping capability of the ESL 105.

[0038] In various embodiments, HAR features with high critical dimensional uniformity (CDU) and good sidewall passivation can be obtained (e.g., Figures 1B and 1C). Various process parameters and processing systems of the method can be selected so that the plasma etching conditions are suitable for producing HAR features. Factors to consider may include, in particular, controlled levels of deposition, mask selectivity, sidewall passivation in the HAR features, and good CDU. In certain embodiments, the plasma etching process may be advantageously carried out as a single-step process to form high aspect ratio (HAR) features with an aspect ratio of 100:1 or greater. While a continuous process flow for the plasma etching process may be advantageous, other embodiments in which the method is applied as part of a periodic or multi-step process are also possible.

[0039] In various embodiments, RF pulsing in the kHz range may be used to power the plasma. Using RF pulsing can help generate high-energy ions (>keV) in the plasma for the plasma etching process while reducing the charge effect. The charge effect during the process is a phenomenon in which electrons accumulate charge in insulating materials (e.g., silicon oxide in dielectric layer 110), forming a local electric field, which can induce charged ions on the sidewalls and cause non-perpendicular etching. Therefore, it may also be important to fine-tune the power conditions of the plasma etching process to minimize the broadening of the limiting dimension (CD) and profile distortion of high aspect ratio (HAR) features. In certain embodiments, a kHz-modulated dual-frequency RF generator is used to power the plasma with a typical pulse duty cycle of 20% to 90%. In one embodiment, bias powers of 40 MHz at 2 kW and 400 kHz at 18 kW can be pulsed at a frequency of 5 kHz and a duty cycle of 50%.

[0040] As has been considered in various embodiments, when plasma etching a dielectric layer with plasma, capacitively coupled plasma (CCP) may be advantageous over inductively coupled plasma (ICP) to achieve an improved etching profile with better anisotropic etching and controllable strain while maintaining good etching selectivity. However, the HARC etching method can be applied to any type of plasma processing system (e.g., CCP, ICP, microwave, etc.).

[0041] Figure 2 shows the energy level diagram for the adsorption / desorption of a metal fluoride species (WF4) on a silicon oxide surface.

[0042] Figure 3 shows the energy level diagram for the adsorption / desorption of a metal fluoride species (WF4) on a silicon surface.

[0043] The inventors of this application calculated possible adsorption / desorption energies of surface species through simulations to demonstrate the effect of additional gases on plasma etching processes in various embodiments. As shown in Figures 2 and 3, the desorption energy of surface metal fluoride species (WF4) from silicon (4.643 eV) is shown to be more than twice that of WF4 from silicon oxide (2.248 eV). This clear contrast in desorption energies demonstrates that surface metal fluoride species (WF4) may be energetically more favorable to silicon than silicon oxide. Thus, it can be suggested that a passivation layer containing metal fluoride species may be selectively generated in the poly-Si mask material than in the etching target containing silicon oxide during the plasma etching process. In other words, in the case of high aspect ratio (HAR) etching processes, species induced by additional gases may "adhere" more near the top of the substrate (e.g., the mask layer) compared to the bottom of the substrate (e.g., the etching front of the etching target layer). Such selective deposition of the passivation layer may be advantageous in improving mask selectivity while preventing any adverse effects on the oxide etching rate.

[0044] The inventors of this application have further confirmed through controlled experiments that excellent mask selectivity can be obtained by adding WF6 to a fluorine-based plasma etching process. In one embodiment, etching selectivity of over 180 for silicon oxide versus poly-Si can be achieved. In another embodiment, the etching selectivity of oxide versus nitride can be improved by at least twofold by adding WF6.

[0045] Figure 4 shows the energy level diagram of the formation of a deposition precursor (WF5) from a metal fluoride species (WF6) via heavy particle-assisted dissociation.

[0046] Figure 5 shows the energy level diagram for the formation of a deposition precursor (SiH3) from a silane species (SiH4) via heavy particle-assisted dissociation.

[0047] Furthermore, to demonstrate possible reaction pathways for deposition, the inventors of this application calculated the formation energy of hypothetical deposition precursors from additional gas components through simulations. Stable forms of metal halides (e.g., WF6) or silane compounds (e.g., SiH4) may be less likely to directly form a deposition layer on their surface due to their closed shell structure and lack of dangling bonds; therefore, it may be necessary to first form the deposition precursor under plasma conditions, for example, via dissociation. The inventors of this application have identified that such dissociation can be induced not only by electron impact but also facilitated by collisions with heavy particles (e.g., H atoms). By including secondary additives such as H2, this heavy particle-assisted dissociation can further increase the likelihood of dissociation of metal halides. In Figure 4, the calculated energy level diagram demonstrates a thermodynamically favorable process (-1.125 eV) for a possible deposition precursor (WF5) induced by a reaction between WF6 and H atoms. The activation energy for forming the transition state (TS) was also found to be small (0.024 eV). Continuous dissociation via the same heavy particle-assisted dissociation (i.e., WF n +H→WF n-1+HF) can occur and it should be noted that reactive deposition precursors can be generated. As a result, in various embodiments using secondary additives such as H2, without increasing the flow rate of WF6 or without increasing the source power of the plasma, a greater amount of WF x radicals can be advantageously generated.

[0048] In contrast to metal halides, silane compounds can dissociate relatively easily without the assistance of secondary additive gases. This is because silane compounds can react directly with fluorine species in the plasma to dissociate. As shown in FIG. 5, the calculated energy level diagram demonstrates a thermodynamically favorable process (-1.418 eV) of the potential deposition precursor (SiH3) induced by the reaction between SiH4 and F atoms. Successive dissociation via the same heavy particle-assisted dissociation (i.e., SiH n +F→SiH n-1 +HF) can occur and reactive deposition precursors can be generated.

[0049] As described above, using various embodiments of the method of the plasma etching process, useful HAR features for 3D memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices, or other semiconductor devices including logic devices can be manufactured. Additional gases that can enhance mask selectivity can include a combination of metal fluoride and hydrogen-containing gas, or silane compounds. In certain embodiments, it is possible to use both metal fluoride and silane compounds together in the additional gas. In one embodiment, the process gas can include fluorocarbon, WF6, and SiH4 regardless of the presence or absence of other gas components (e.g., O2, H2, Ar, or NF3). In such embodiments, the passivation layer formed during the plasma process can include both metal and silicon from the additional gas.

[0050] In further embodiments, the process gas composition may be dynamically adjusted during the plasma etching process. In one or more embodiments, both metal halides and silane compounds can be used as process gases, allowing for the maintenance of a constant total gas flow rate while their flow rates can be controlled individually. Various other process parameters, such as process time, substrate temperature, plasma source power, and bias power, may also be adjusted according to the process recipe depending on the application.

[0051] Figures 6A to 6C show process flowcharts of plasma etching process methods according to various embodiments. The process flow can follow the diagrams discussed above (Figures 1C to 1E) and will therefore not be described again.

[0052] In Figure 6A, process flow 60 begins by flowing fluorocarbons, metal halides, and dihydrogen (H2) into a plasma processing chamber configured to hold a substrate containing a dielectric layer with silicon oxide as an etching target and a patterned hard mask containing polycrystalline silicon (poly-Si) on the dielectric layer (block 610, Figure 1A). Subsequently, while the gas flows, plasma may be generated in the plasma processing chamber (block 620), and the substrate may be exposed to the plasma to etch recesses in the dielectric layer, thereby forming high aspect ratio (HAR) feature areas, and a metal-containing passivation layer may be formed on the patterned hard mask during exposure (block 630, Figures 1B and 1C).

[0053] In Figure 6B, another process flow 62 begins by flowing fluorocarbon and silane compounds into a plasma processing chamber configured to hold a substrate including a dielectric layer containing silicon as an etching target and a patterned hard mask on the dielectric layer (block 612, Figure 1A). Subsequently, while the gas flows, plasma may be generated in the plasma processing chamber (block 620), and the substrate may be exposed to the plasma to etch recesses in the dielectric layer, thereby forming the features of the HAR, and a silicon-containing passivation layer may be formed on the patterned hard mask during exposure (block 632, Figures 1B and 1C).

[0054] In Figure 6C, another process flow 64 begins by flowing fluorocarbon into a plasma processing chamber configured to hold a substrate including a dielectric layer as an etching target and a patterned hard mask on the dielectric layer (block 614, Figure 1A). Subsequently, while the fluorocarbon is flowing, plasma may be generated from the fluorocarbon and maintained in the plasma processing chamber (block 624). While maintaining the plasma, metal halides and H2 may be flowed into the plasma processing chamber (block 626), and silane compounds may also be flowed into the plasma processing chamber (block 628). Subsequently, the substrate may be exposed to the plasma to etch recesses in the dielectric layer, thereby forming the features of the HAR, and a passivation layer may be formed on the patterned hard mask during exposure (block 634, Figures 1B and 1C).

[0055] Figure 7 shows an exemplary capacitively coupled plasma (CCP) treatment tool 70 according to an embodiment of the present disclosure.

[0056] For illustrative purposes, Figure 7 shows a substrate 100 placed in a substrate holder 754 (e.g., a circular electrostatic chuck (ESC)) inside a plasma processing chamber 710 near the bottom. The substrate 100 may optionally be maintained at a desired temperature using a heater / cooler 756 surrounding the substrate holder 754. The temperature of the substrate 100 may be maintained by a temperature controller 740 connected to the substrate holder 754 and the heater / cooler 756. The ESC may be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that it can be electrically connected to the substrate holder 754.

[0057] As shown in Figure 7, the substrate holder 754 may be the bottom electrode of the plasma processing chamber 710. In the exemplary example in Figure 7, the substrate holder 754 is connected to two RF bias power supplies 770 and 780 via blocking capacitors 790 and 791. In some embodiments, a conductive circular plate near the top inside the plasma processing chamber 710 is the upper electrode 752. In Figure 7, the upper electrode 752 is connected to the DC power supply 750 of the plasma processing system 70.

[0058] The gas can be introduced into the plasma processing chamber 710 by a gas delivery system 720. The gas delivery system 720 includes multiple gas flow controllers for controlling the flow of multiple gases into the chamber. Each of the gas flow controllers of the gas delivery system 720 may be assigned to a fluorocarbon, a noble gas, and / or an equilibrator, respectively. In some embodiments, an optional center / edge splitter can be used to independently adjust the gas flow at the center and edges of the substrate 100.

[0059] RF bias power supplies 770 and 780 may be used to supply continuous wave (CW) power or pulsed RF power to maintain the plasma, such as plasma 760. The plasma 760 shown between the upper electrode 752 and the bottom electrode (which is also the substrate holder 754) exemplifies the direct plasma generated near the substrate 100 within the plasma processing chamber 710 of the plasma processing system 70. Etching may be performed by exposing the substrate 100 to the plasma 760 while supplying power to the substrate holder 754 using the RF bias power supplies 770 and 780, and optionally supplying power to the upper electrode 752 using the DC power supply 750.

[0060] The configuration of the plasma processing system 70 described above is merely illustrative. In alternative embodiments, various alternative configurations can be used for the plasma processing system 70. For example, instead of the CCP in Figure 7, an inductively coupled plasma (ICP) can be used, the RF source power can be coupled to a planar coil on the upper dielectric cover, and the gas inlet or gas outlet can be coupled to the upper wall or the like. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rate, and other plasma process parameters can be selected according to the respective process recipe. In some embodiments, the plasma processing system 70 may be a resonator such as a helical resonator.

[0061] Although not described herein, embodiments of the present invention may also be applicable to remote plasma systems and batch systems. For example, a substrate holder may be capable of supporting multiple wafers that are spun around a central axis as they pass through different plasma zones.

[0062] Herein, exemplary embodiments of the present invention are summarized. Other embodiments can also be understood from the entirety of this specification and the claims filed herein. [Examples]

[0063] Example 1. A method for processing a substrate, comprising the steps of: flowing a fluorocarbon, a metal halide, and dihydrogen (H2) into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate comprising a dielectric layer containing silicon oxide as an etching target and a patterned hard mask containing polycrystalline silicon (poly-Si) on the dielectric layer; generating plasma in the plasma processing chamber while flowing a gas; and forming high aspect ratio feature portions by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during exposure.

[0064] Example 2. The method of Example 1, further comprising the step of flowing dioxygen (O2).

[0065] Example 3. The fluorocarbon comprises C4F6, C4F8, CF4, C3F8, CHF3, or CH2F2, according to one of the methods in Example 1 or 2.

[0066] Example 4. The metal halide is tungsten hexafluoride (WF6), using any one of the methods from Examples 1 to 3.

[0067] Example 5. The metal halide is molybdenum hexafluoride (MoF6), niobium hexafluoride (NbF6), tungsten hexachloride (WCl6), aluminum trichloride (AlCl3), or titanium tetrachloride (TiCl4), according to any one of the methods in Examples 1 to 4.

[0068] Example 6. The flow rate of the metal halide is 0.01% to 1% of the total gas flow rate, according to any one of the methods in Examples 1 to 5.

[0069] Example 7. One of the methods from Examples 1 to 6, wherein a metal halide is intermittently flowed while the substrate is exposed to plasma.

[0070] Example 8. The dielectric layer comprises a layer stack of silicon oxide and silicon nitride, according to any one of the methods in Examples 1 to 7.

[0071] Example 9. Any one of the methods of Examples 1 to 8, wherein the aspect ratio of the recess is at least 50:1.

[0072] Example 10. A method for processing a substrate, comprising the steps of: flowing a fluorocarbon and a silane compound into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate including a dielectric layer containing silicon as an etching target and a patterned hard mask on the dielectric layer; generating plasma in the plasma processing chamber while flowing a gas; and forming high aspect ratio feature portions by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during exposure.

[0073] Example 11. The method of Example 10, further comprising the step of flowing dioxygen (O2).

[0074] Example 12. The fluorocarbon comprises C4F6, C4F8, CF4, C3F8, CHF3, or CH2F2, according to one of the methods in Example 10 or 11.

[0075] Example 13. The silane compound is monosilane (SiH4), according to any one of the methods in Examples 10 to 12.

[0076] Example 14. The silane compound is disilane (Si2H6) or silane halogen (SiH x X y ) one of the methods described in Examples 10 to 13.

[0077] Example 15. The dielectric layer comprises silicon oxide, according to any one of the methods in Examples 10 to 14.

[0078] Example 16. The dielectric layer comprises silicon nitride, according to any one of the methods in Examples 10 to 15.

[0079] Example 17. The patterned hard mask is made of polycrystalline silicon (poly-Si) using any one of the methods from Examples 10 to 16.

[0080] Example 18. A method for processing a substrate, comprising the steps of: flowing a fluorocarbon into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate including a dielectric layer as an etching target and a patterned hard mask on the dielectric layer; maintaining a plasma generated from the fluorocarbon in the plasma processing chamber while flowing the fluorocarbon; flowing a metal halide and dihydrogen (H2) into the plasma processing chamber while maintaining the plasma; flowing a silane compound into the plasma processing chamber while maintaining the plasma; and forming a high aspect ratio feature by exposing the substrate to the plasma and etching the recesses of the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure.

[0081] Example 19. The method of Example 18, wherein a metal halide, H2, and a silane compound are simultaneously flowed into a plasma treatment chamber.

[0082] Example 20. The method of either Example 18 or 19, further comprising the step of alternately repeating the process of flowing a metal halide and H2, and then flowing a silane compound.

[0083] Although the present invention has been described with reference to exemplary embodiments, this description is not intended to be constrained. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art by reference to the description. Accordingly, the appended claims are intended to encompass any such modifications or embodiments.

Claims

1. A method for processing a substrate, Fluorocarbons, metal halides, and dihydrogen (H ２ A step of flowing a substance into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate, and the substrate has a dielectric layer containing silicon oxide as an etching target, and a patterned hard mask containing polycrystalline silicon (poly-Si) on the dielectric layer, During the process of flowing the gas, the process of generating plasma in the plasma processing chamber is performed. A step of forming a high aspect ratio feature portion by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a metal-containing passivation layer is formed on the patterned hard mask during the exposure step, Methods that include...

2. Furthermore, dioxygen (O ２ The method according to claim 1, further comprising the step of flowing )

3. The fluorocarbon is C ４ F ６ , C ４ F ８ , CF ４ , C ３ F ８ , CHF ３ , or CH ２ F ２ The method according to claim 1, comprising

4. The aforementioned metal halide is tungsten hexafluoride (WF ６ The method according to claim 1, wherein the method is as follows:

5. The aforementioned metal halide is molybdenum hexafluoride (MoF ６ ), niobium hexafluoride (NbF ６ ), tungsten hexachloride (WCl ６ ), aluminum trichloride (AlCl ３ ), or titanium tetrachloride (TiCl ４ The method according to claim 1, wherein the method is as follows:

6. The method according to claim 1, wherein the flow rate of the metal halide is between 0.01% and 1% of the total flow rate of the gas.

7. The method according to claim 1, wherein the metal halide is flowed intermittently during the step of exposing the substrate to the plasma.

8. The method according to claim 1, wherein the dielectric layer includes a layer stack of silicon oxide and silicon nitride.

9. The method according to claim 1, wherein the aspect ratio of the recess is at least 50:

1.

10. A method for processing a substrate, A step of flowing a fluorocarbon and a silane compound into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate, and the substrate has a dielectric layer containing silicon as an etching target, and a patterned hard mask on the dielectric layer. During the process of flowing the gas, the process of generating plasma in the plasma processing chamber is performed. A step of forming a high aspect ratio feature portion by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a silicon-containing passivation layer is formed on the patterned hard mask during the exposure step, Methods that include...

11. Furthermore, dioxygen (O ２ The method according to claim 10, further comprising the step of flowing )

12. The aforementioned fluorocarbon is C ４ F ６ , C ４ F ８ CF ４ , C ３ F ８ CHF ３ , or CH ２ F ２ The method according to claim 10, including the method described in claim 10.

13. The silane compound is monosilane (SiH ４ The method according to claim 10, wherein the method is as follows:

14. The silane compound is disilane (Si ２ H ６ ) or silane halogens (SiH ｘ X ｙ The method according to claim 10, wherein the method is as follows:

15. The method according to claim 10, wherein the dielectric layer includes a silicon oxide.

16. The method according to claim 10, wherein the dielectric layer includes silicon nitride.

17. The method according to claim 10, wherein the patterned hard mask comprises polycrystalline silicon (poly-Si).

18. A method for processing a substrate, A step of flowing fluorocarbon into a plasma processing chamber, wherein the plasma processing chamber is configured to hold a substrate, and the substrate includes a dielectric layer as an etching target, and a patterned hard mask on the dielectric layer. During the process of flowing the fluorocarbon, the process of maintaining the plasma generated from the fluorocarbon in the plasma processing chamber, During the process of maintaining the plasma, metal halide and dihydrogen (H) ２ The process of flowing ) into the plasma processing chamber, During the process of maintaining the plasma, the process includes flowing a silane compound into the plasma processing chamber, A step of forming a high aspect ratio feature portion by exposing the substrate to the plasma and etching recesses in the dielectric layer, wherein a passivation layer is formed on the patterned hard mask during the exposure step, Methods that include...

19. The aforementioned metal halide, H ２ The method according to claim 18, wherein the silane compound and the silane compound are simultaneously flowed into the plasma processing chamber.

20. Furthermore, the metal halide and H ２ The method according to claim 18, comprising the step of alternately repeating the step of flowing a substance and the step of flowing the silane compound.

Images