Direct connection on buried power rails

Abstract

An integrated circuit comprising a plurality of transistors and a method for manufacturing the same, wherein each transistor comprises a source, a drain, and a channel located between the source and the drain. The integrated circuit also comprises a plurality of embedded power rails comprising a plurality of VSS power rails and a plurality of VDD power rails, at least one VSS pad and at least one VDD pad, a plurality of vias electrically connecting at least one VSS pad to at least two of the plurality of VSS power rails, and a plurality of vias electrically connecting at least one VDD pad to at least two of the plurality of embedded VDD power rails.

Description

Technical Field

[0001] (Cross-reference to related applications) This application claims priority to U.S. Patent Application Nos. 18 / 345,607 and 18 / 345,581, each of which claims the benefit of U.S. Provisional Application No. 63 / 456,453, filed Mar. 31, 2023, the contents of each of which are hereby incorporated by reference in their entirety.

[0002] This field relates to integrated circuit dies having embedded power rails.

Background Art

[0003] Conventional integrated circuits are fabricated using only the front side of a semiconductor wafer. In the first part of fabrication, individual components (e.g., transistors, resistors, capacitors) are formed on the front side. This first device part is called the front end of line (FEOL). After the FEOL is completed, the back end of line (BEOL), the second part of the integrated circuit, is fabricated on the front side of the wafer over the FEOL. The BEOL comprises a stack of alternating dielectric and metallization layers where interconnects and vias are formed. The interconnects include power lines that supply power to the devices and signal lines that are used to obtain data from the devices. The signal lines are broadly referred to as a signal distribution network (SDN), and the power lines may be referred to as a power distribution network (PDN). The BEOL also includes pads for bonding the chip to a package or circuit board.

[0004] As electrical components, particularly transistors, have become smaller and their number per chip has increased, the amount of wiring has increased proportionally, yet the chip size has remained relatively constant. While the size of interconnects at the transistor device level has decreased proportionally, the total number of metallization layers has increased significantly to accommodate the increase in interconnects at the chip level. Interconnection layers are connected to each other and to devices by increasingly smaller vias at each level, especially near the device level.

[0005] However, the resistance of interconnects and vias increases as the via size decreases. As a result, resistance increases exponentially as interconnects and vias shrink to less than 10 nm. Furthermore, as the number of interconnects increases, the total ohmic drop from the upper metallization layer to the device gradually worsens. This ohmic drop also contributes to the Joule heating of the wiring layer, effectively raising the operating temperature of the chip. This increase in resistance, ohmic drop due to resist, and rising chip temperature cast a shadow over the advantages of miniaturizing various electrical components.

[0006] Therefore, it would be desirable and useful to provide a structure and method for manufacturing an integrated circuit to address this problem.

[0007] Next, specific embodiments will be described with reference to the following drawings, but these are provided as examples only and are not limiting. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] U.S. Patent No. 9,564,414 [Patent Document 2] U.S. Patent No. 9,391,143 [Patent Document 3] U.S. Patent No. 10,434,749 [Patent Document 4] U.S. Patent No. 9,716,033 [Patent Document 5] U.S. Patent No. 9,852,988 [Patent Document 6] U.S. Patent No. 11,195,748 [Brief Description of the Drawings]

[0009] [Figure 1] Cross-sectional view of a conventional integrated circuit.

[0010] [Figure 2A] Cross-sectional view of an integrated circuit having buried power rails.

[0011] [Figure 2B] Top view of the integrated circuit shown in FIG. 2A.

[0012] [Figure 3A] Cross-sectional view of an integrated circuit according to some embodiments of the disclosed technology.

[0013] [Figure 3B] Top view of the integrated circuit shown in FIG. 2A.

[0014] [Figure 4A] Cross-sectional view of an integrated circuit according to some embodiments of the disclosed technology.

[0015] [Figure 4B] Top view of the integrated circuit shown in FIG. 2A.

[0016] [Figure 4C] Cross-sectional view of a modified example of the integrated circuit shown in FIGS. 4A and 4B.

[0017] [Figure 4D] Cross-sectional view of another modified example of the integrated circuit shown in FIGS. 4A and 4B.

[0018] [Figure 5A] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5B] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5C] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5D] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5E] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5F] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5G] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology. [Figure 5H] A cross-sectional view showing a method of manufacturing an integrated circuit according to some embodiments of the disclosed technology.

[0019] [Figure 6] A cross-sectional view of an integrated circuit hybrid-bonded to a power distribution die. [[ID=3V2]]

[0020] [Figure 7] A process flow diagram showing a method of manufacturing an exemplary integrated circuit according to some embodiments of the disclosed technology.

[0021] [Figure 8] A process flow diagram showing another method of manufacturing an exemplary integrated circuit according to some embodiments of the disclosed technology.

[0022] [Figure 9A] A diagram schematically showing a process of forming a direct hybrid bonding structure without an intervening adhesive according to some embodiments. [Figure 9B]This diagram schematically illustrates a process for directly forming a hybrid bonded structure without the use of adhesive, according to several embodiments. [Modes for carrying out the invention]

[0023] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. Specific examples of components and arrangements are described below for the sake of brevity of this disclosure. Of course, these are merely illustrative and not intended to limit. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplification and clarity and does not in itself indicate relationships between the various embodiments and / or configurations described.

[0024] Furthermore, spatially relative terms such as “directly below,” “downward,” “below,” “up,” and “above” may be used herein to describe the relationship between one element or feature and another, as illustrated, for the sake of clarity. Spatially relative terms are intended to include different orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may also be in other orientations (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0025] The following description refers to integrated circuits. Specifically, it refers to integrated circuits having embedded power lines and integrated circuits configured to have a power distribution network located on the back surface of the wafer.

[0026] Figure 1 shows a conventional integrated circuit 100. The integrated circuit is fabricated on the front surface of a substrate 104. In the first part of the fabrication, individual electrical components 106 (e.g., transistors, resistors, capacitors) are formed. This first device part is called the front end of line (FEOL). After the FEOL is completed, the back end of line (BEOL), which is the second part of the integrated circuit, is fabricated on top of the FEOL. The BEOL has a stack of alternating dielectric and metallization layers, where interconnects 110 (wiring connecting the electrical connections) and vias 108 are formed. The interconnects 110 include power lines that supply power to and from the devices and signal lines used to obtain data from the devices. The signal lines can be broadly called a signal distribution network (SDN), and the power lines can be called a power distribution network (PDN). The BEOL also includes contact pads 152 for bonding the chip to a package or circuit board. The integrated circuit 100 may also include solder bumps 102 that allow the integrated circuit 100 to be attached to a circuit board or another integrated circuit 100.

[0027] Various embodiments disclosed herein relate to directly bonded structures, such as an integrated circuit 100, in which two or more elements can be directly bonded to one another without the interposition of an adhesive. In some embodiments, the direct bonding may include bonding a single material on one element to a single material on another element, where the single materials on the different elements may be the same or different. The direct bonding may also include bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0028] Figures 9A and 9B schematically illustrate a process for forming a directly hybrid-bonded structure (sometimes referred to as a “directly hybrid-bonded structure”) without the interposition of an adhesive, according to several embodiments. In this specification, the term “hybrid bonding” refers to a chemical species of direct bonding in which both i) non-conductive features directly bonded to non-conductive features and ii) conductive features directly bonded to conductive features are present. In Figures 9A and 9B, the bonded structure 101 includes two elements 103 and 105 that can be directly bonded to each other at a bonding interface 119 without the interposition of an adhesive. To form the bonded structure 101, one or more microelectronic elements 103 and 105 (e.g., semiconductor elements including individual active devices such as integrated device dies, wafers, passive devices, and power switches) can be stacked or bonded to each other. A conductive feature portion 107a of the first element 103 (e.g., a contact pad, an exposed end of a via (e.g., a TSV), or a through-substrate electrode) can be electrically connected to the corresponding conductive feature portion 107b of the second element 105. Any appropriate number of elements can be stacked on the joint structure 101. For example, a third element (not shown) can be stacked on the second element 105, and a fourth element (not shown) can be stacked on the third element. In addition or alternatively, one or more additional elements (not shown) can be stacked adjacent to each other laterally along the first element 103. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the laterally stacked additional elements can be twice as small as the second element.

[0029] In some embodiments, elements 103 and 105 are directly bonded to each other without adhesive. In various embodiments, a nonconductive field region containing a nonconductive or dielectric material can function as a first bonding layer 109a of the first element 103, which can be directly bonded without adhesive to a corresponding nonconductive field region containing a nonconductive or dielectric material that functions as a second bonding layer 109b of the second element 105. The nonconductive bonding layers 109a and 109b can be placed on the respective front surfaces 115a and 115b of the device portions 111a and 111b, such as the semiconductor (e.g., silicon) portions of elements 103 and 105. Active devices and / or circuits can be arranged within or on the device portions 111a and 111b by patterning and / or other means. Active devices and / or circuits may be located on the front surfaces 115a, 115b or near thereto of device portions 111a, 111b, and / or on the opposite back surfaces 117a, 117b or near thereto of device portions 111a, 111b. Bonding layers may be provided on the front and / or back surfaces of the elements. Nonconductive material may be referred to as nonconductive bonding portions, direct bonding layers, or bonding layers 109a of the first element 103. In some embodiments, the nonconductive bonding layer 109a of the first element 103 may be directly bonded to the corresponding nonconductive bonding layer 109b of the second element 105 using dielectric-to-dielectric bonding techniques. For example, nonconductive bonding or dielectric-dielectric bonding may be formed without adhesive using direct bonding techniques disclosed in at least U.S. Patents 9,564,414; 9,391,143; and 10,434,749, the entirety of each of these patents is incorporated herein by reference in whole for all purposes. It should be understood that in various embodiments, the bonding layers 109a and / or 109b may include dielectric materials such as silicon oxide, or nonconductive materials such as undoped semiconductor materials such as silicon.Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride. Examples of carbon materials include silicon carbide, silicon oxynitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or materials containing diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic materials despite containing carbon. In some embodiments, the dielectric material does not include polymer materials such as epoxy, resin, or molding materials.

[0030] In some embodiments, device portions 111a and 111b may have significantly different coefficients of thermal expansion (CTE) that define heterogeneous structures. The CTE difference between device portions 111a and 111b, and particularly between the bulk semiconductors, typically single-crystal portions, of device portions 111a and 111b, can be 5 ppm or greater, or 10 ppm or greater. For example, the CTE difference between bulk substrates can be in the range of 5 ppm to 101 ppm, 5 ppm to 40 ppm, 10 ppm to 101 ppm, or 2 ppm to 20 ppm. In some embodiments, one of the bulk substrates may include a photoelectron single-crystal material, including a perovskite material useful for photopiezoelectric or pyroelectric applications, while the other of the bulk substrates 111a and 111b includes a more conventional substrate material. For example, one of the device portions 111a, 111b comprises lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the device portions 111a, 111b comprises silicon (Si), quartz, quartz glass, sapphire, or glass. In other embodiments, one of the device portions 111a, 111b comprises a III-V single semiconductor material such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or gallium nitride (GaN), and the other of the device portions 111a, 111b comprises a non-III-V semiconductor material such as silicon (Si), or may include other materials having a similar CTE such as quartz, quartz glass, sapphire, or glass.

[0031] In various embodiments, direct hybrid bonding can be formed without the interposition of an adhesive. For example, the non-conductive bonding surfaces 113a and 113b can be highly smoothed by polishing. The non-conductive bonding surfaces 113a and 113b can be polished, for example, using chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 113a and 113b can be less than 30 Årms. For example, the roughness of the bonding surfaces 113a and 113b can be in the range of about 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. The bonding surfaces 113a and 113b can be cleaned and exposed to plasma and / or etchant to activate the surfaces 113a and 113b. In some embodiments, the surfaces 113a and 113b can be terminated with chemical species after or during activation (e.g., during the plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process may be performed to break chemical bonds at bonding surfaces 113a and 113b, and a termination process may provide additional chemical species to bonding surfaces 113a and 113b that improve bond energy during direct bonding. In some embodiments, activation and termination are provided in the same step, for example, in a plasma for activating and terminating surfaces 113a and 113b. In other embodiments, bonding surfaces 113a and 113b may be terminated in separate treatments to provide additional species for direct bonding. In various embodiments, the termination species may include nitrogen. For example, in some embodiments, bonding surfaces 113a and 113b may be exposed to a nitrogen-containing plasma. Furthermore, in some embodiments, bonding surfaces 113a and 113b may be exposed to fluorine. For example, one or more fluorine peaks may be present at or near the bonding interface 119 between the first and second elements 103 and 105. Therefore, in a directly bonded structure 101, the bonding interface 119 between two nonconductive materials (e.g., bonding layers 109a and 109b) can have a very smooth interface with a higher nitrogen content and / or a fluorine peak at the bonding interface 119.Examples of additional activation and / or termination treatments can be found in U.S. Patents 9,564,414; 9,391,143; and 10,434,749, the entirety of each of these is incorporated herein by reference for its whole and all purposes. The roughness of the polished bond surfaces 113a and 113b may be slightly rough after the activation treatment (e.g., about 1 Årms to 30 Årms, 3 Årms to 20 Årms, or optionally, rougher).

[0032] In various embodiments, the conductive feature 107a of the first element 103 can also be directly bonded to the corresponding conductive feature 107b of the second element 105 without adhesive (e.g., without solder or other conductive adhesive interposed between conductive features 107a and 107b). For example, direct hybrid bonding techniques can be used to provide a conductor-to-conductor direct bond along a bonding interface 119 that includes covalently bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces prepared as described above. In various embodiments, conductor-to-conductor (e.g., conductive feature 107a-conductive feature 107b) direct bonds and dielectric-to-dielectric hybrid bonds can be formed using at least the direct bonding techniques disclosed in U.S. Patents 9,716,033 and 9,852,988, the entirety of each of these patents is incorporated herein by reference in whole and for all purposes. In the direct hybrid bonding embodiments described herein, the conductive features are provided within the non-conductive bonding layer, and both the conductive and non-conductive features are prepared for direct bonding by the planarization, activation and / or termination processes described above. Thus, the bonding surface prepared for direct bonding includes both the conductive and non-conductive features.

[0033] For example, non-conductive (e.g., dielectric) bonding surfaces 113a, 113b (e.g., inorganic dielectric surfaces) can be prepared without the interposition of an adhesive and bonded directly to each other, as described above. Conductive contact features (e.g., conductive features 107a, 107b that can be at least partially surrounded by non-conductive dielectric field portions within bonding layers 109a, 109b) can also be bonded directly without the interposition of an adhesive. In various embodiments, conductive features 107a, 107b may include discrete pads or traces at least partially embedded in the non-conductive electric field portions. In some embodiments, conductive contact features may include exposed contact surfaces of through-substrate vias (e.g., through-silicon vias (TSVs)). In some embodiments, the conductive features 107a and 107b can be recessed below the dielectric field region or the outer (e.g., upper) surface (non-conductive bonding surfaces 113a and 113b) of the non-conductive bonding layers 109a and 109b, for example, in the range of 2nm to 20nm or 4nm to 10nm, by a size of less than 30nm, less than 20nm, less than 15nm, or less than 10nm. The recess can be located in or near the center of the cavity in which the conductive features 107a and 107b are located, and additionally or alternatively, can extend or be located along the sides of the cavity in which the conductive features 107a and 107b are located. In various embodiments, before direct bonding, the recesses of the opposing elements can be sized such that the total gap between the opposing contact pads 152 is less than 15nm or less than 10nm. In some embodiments, the non-conductive bonding layers 109a and 109b are directly bonded to each other at room temperature without adhesive, and the bonded structure 101 can then be annealed. Upon annealing, the conductive features 107a and 107b expand and come into contact with each other, enabling direct metal-to-metal bonding.Beneficially, by using the Direct Bond Interconnect (DBI®) technology commercially available from Adeia, Inc. of San Jose, California, high-density conductive features 107a and 107b can be connected across the direct bond interface 119 (e.g., small or fine pitch for regular arrays). In some embodiments, the pitch of conductive features 107a and 107b, such as conductive traces embedded in one bond surface of the bonded elements, may be less than 101 microns, less than 10 microns, or less than 2 microns. In some applications, the ratio of the pitch of conductive features 107a and 107b to one of the dimensions (e.g., diameter) of the bonded pad is preferably less than 20, less than 10, less than 5, less than 3, or less than 2. In other applications, the width of the conductive trace embedded in one bond surface of the bonded elements may be between 0.3 microns and 20 microns, for example, in the range of 0.3 microns to 3 microns. In various embodiments, the conductive features 107a and 107b and / or traces may include copper, nickel, gold, indium, silver, or alloys thereof, but other metals may be suitable. For example, the conductive features disclosed herein, such as conductive features 107a and 107b, may include fine-grained metals (e.g., fine-grained copper).

[0034] Accordingly, in a direct bonding process, the first element 103 can be directly bonded to the second element 105 without the interposition of an adhesive. In some configurations, the first element 103 may include a fragmented element, such as a fragmented integrated device die. In other configurations, the first element 103 may include a carrier or substrate (e.g., wafer) containing multiple (e.g., tens, hundreds, or more) device regions that form multiple integrated device dies when fragmented. In some embodiments, the first element may include a package or a single-package. Similarly, the second element 105 may include a fragmented element, such as a fragmented integrated device die. In other configurations, the second element 105 may comprise a carrier or substrate (e.g., wafer) or a package. Embodiments disclosed herein can be appropriately applied to wafer-to-wafer (W2W), die-to-die (D2D), die-to-wafer (D2W), package-to-wafer (P2W), package-to-package, die-to-flat panel, and package-to-flat panel bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers are directly bonded to each other (e.g., directly hybrid bonded) and can be pieced using an appropriate pieced-out process. After pieced-out, the side edges of the pieced structures (e.g., the side edges of two bonded elements) may be substantially flush and may include markings indicating a common pieced-out process of the bonded structures (e.g., sawtooth markings if a sawtooth pieced-out process is used).

[0035] As described herein, the first element 103 and the second element 105 can be directly joined to each other without adhesive, which differs from the deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element 103 in the joined structure is similar to the width of the second element 105. In some other embodiments, the width of the first element 103 in the joined structure 101 is different from the width of the second element 105. Similarly, the width or area of ​​the larger element in the joined structure may be at least 10% greater than the width or area of ​​the smaller element. Accordingly, the first element 103 and the second element 105 may include non-deposited elements. Furthermore, unlike deposited layers, the directly joined structure 101 may include defect sites along the joining interface 119 where nanometer-scale voids (nanovoids) exist. Nanovoids can be formed as a result of activation (e.g., exposure to plasma) of the joining surfaces 113a and 113b. As described above, the joining interface 119 may include the concentration of material from the activation and / or final chemical treatment step. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bonding interface 119. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, for example, nitrogen termination (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace the OH groups of the hydrolyzed (OH-terminated) surface with NH2 molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak can be formed at the bonding interface 119. In some embodiments, the bonding interface 119 may include silicon oxynitride, silicon oxycarbonite, or silicon carbonitride. As described herein, direct bonding can include covalent bonds stronger than van der Waals bonds. Bonding layers 109a and 109b may also include polished surfaces planarized to a high degree of smoothness.

[0036] In various embodiments, the intermetallic bonding between conductive features 107a and 107b can be achieved by bonding such that metal grains grow toward each other across the bonding interface 119. In some embodiments, the metal is or contains copper, and the copper may have grains oriented along the crystal plane 111 to improve the diffusion of copper across the bonding interface 119. In some embodiments, the conductive features 107a and 107b may include a nanotwin copper grain structure, which can help fuse the conductive features during annealing. The bonding interface 119 can extend substantially completely to at least a portion of the bonded conductive features 107a and 107b, and there can be substantially no gap between the non-conductive bonding layers 109a and 109b in or near the bonded conductive features 107a and 107b. In some embodiments, a barrier layer (which may include, for example, copper) can be provided surrounding the conductive features 107a and 107b below and / or laterally. However, in other embodiments, a barrier layer may not be provided beneath the conductive features 107a and 107b, for example, as described in U.S. Patent No. 11,195,748.

[0037] Beneficially, the use of the hybrid bonding techniques described herein can enable extremely fine pitches between adjacent conductive features 107a and 107b, and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive features 107a (or 107b) (i.e., the distance from edge to edge or center to center, as shown in Figure 9A) can be in the range of 0.5 to 50 microns, 0.75 to 25 microns, 1 to 25 microns, 1 to 10 microns, or 1 to 5 microns. Furthermore, the main lateral dimension (e.g., pad diameter) can also be reduced to, for example, 0.25 to 30 microns, 0.25 to 5 microns, or 0.5 to 5 microns.

[0038] As described above, the non-conductive bonding layers 109a and 109b are directly bonded to each other without adhesive, and the bonded structure 101 can then be annealed. Upon annealing, the conductive features 107a and 107b expand and come into contact with each other, resulting in a direct metal-to-metal bond. In some embodiments, materials having conductive features 107a and 107b can interdiffuse during the annealing process.

[0039] As described above and illustrated in Figure 1, in conventional integrated circuits 100, electrical components 106 (e.g., transistors or other devices), signal distribution networks, and power distribution networks (vias 108 - vertically oriented electrical connections and interconnects 110 - horizontally oriented electrical connections, also known as traces) are all fabricated on the front surface of the substrate 104. Typically, solder bumps 102 are provided to allow the integrated circuit 100 to be flip-chip mounted onto the circuit board. In some integrated circuits, wire junction pads may be provided instead of solder bumps 102. As mentioned above, as the number of transistors per chip decreases and increases, the amount of wiring increases. However, since the chip size remains basically constant, the space for accommodating extra wiring (signal, power, and ground) does not increase. The solution to this problem was to add an additional layer to the BEOL for the extra wiring. However, the use of thin wiring and additional layers increases the wiring length, leading to an increase in resist and ohmic drop.

[0040] Another solution for adding an additional metal layer to the BEOL is to use embedded power rails (power rails located within the semiconductor substrate, rather than a metal layer on the substrate). However, previous attempts to use embedded power rails often resulted in degraded device performance due to stress, degradation, and metal contamination from the manufacturing process. Furthermore, the small size of the embedded power rails and their proximity to VDD and / or VSS made it difficult to land nanovias on them. In addition, the formation of nano-through-substrate vias (TSVs) is difficult due to space constraints and potential stresses induced in conductive channels between fins.

[0041] In contrast, as will be described in more detail below, in embodiments of this disclosure, the embedded power rails can be fabricated in the BEOL on the back surface of the substrate 104, extending beneath the electrical components 106. Furthermore, the signal distribution and power distribution networks are located separately with respect to the front and back surfaces of the substrate 104, respectively. That is, in various embodiments, the signal distribution network can be fabricated in the BEOL on the front surface of the substrate 104, while the power distribution network (including connections to power and ground) can be fabricated in a separate die that can then be bonded to the back surface of the substrate 104 by a hybrid direct bonding process. In another embodiment, the signal distribution network may be fabricated in the BEOL on the front surface of the substrate 104, while the power distribution network (including connections to power and ground) may be fabricated on the back surface of the wafer after the wafer has been thinned and the embedded power rails have been exposed by a separate BEOL process performed on the back surface of the thinned substrate. In yet another embodiment, the power distribution network may be fabricated in the BEOL and the signal distribution network may be fabricated on a separate die and then bonded to the back surface of the substrate 104 by a hybrid direct bonding process.

[0042] Figures 2A and 2B are exemplary cross-sectional and top views, respectively, of a portion of an integrated circuit 100 having embedded power rails. As shown, the integrated circuit 100 includes first and second embedded power rails, e.g., a VDD embedded power rail 112 and a VSS embedded power rail 114, configured to supply power and ground or reference voltage, respectively, to an electrical component 106. The illustrated electrical component 106 may comprise a transistor (e.g., a FinFET transistor having multiple (e.g., three) fins 116) and a gate electrode 118. However, the electrical component 106 may be any suitable passive or active electrical component. As shown, the VDD embedded power rail 112, the VSS embedded power rail 114 and the electrical component 106 are fabricated on the front of a die or wafer in a FEOL, with the power rails 112 and 114 extending into a substrate 104 below the electrical component 106. The VDD embedded power rail 112 and VSS embedded power rail 114 extend into the substrate 104 from a dielectric layer (e.g., shallow trench insulating layer (STI) 124). The shallow trench insulating layer may include any suitable type of insulating material, such as silicon oxide. In some embodiments, stress transfer to the conduction channel can be minimized by embedding the tungsten embedded power rails deep within the shallow trench insulating layer, beneath the fins of the FinFET. Note that in various embodiments, this is not limited to FinFETs. In other embodiments, other node technologies, such as gate-all-around (GAA) including nanosheet and nanowire configurations, may be used. In embodiments where the node is 2 nm or larger, the pitch between adjacent embedded rails VDD and VSS may be only a few tens of nm, e.g., about 20 to 100 nm or less. Also, although only one power rail VDD is shown and described as a single voltage line, two or more such power lines may be provided, for example, VDD1, VDD2, VDD3, etc., supplying two or more voltages to different parts of the chip.

[0043] Figures 3A and 3B are schematic cross-sectional and top views, respectively, of an integrated circuit 100 according to one embodiment. As shown, the first and second bond pads (e.g., VDD bond pad 128 and VSS bond pad 130) are formed on the back surface 117a of the substrate 104, and the electrical component 106 is formed on the active front surface 115a of the substrate 104. In one embodiment, a dielectric layer 144 is formed on the back surface 117a of the substrate 104, and the VDD bond pad 128 and VSS bond pad 130 are formed on the dielectric layer 144. As further shown, the VDD bond pad 128 and VSS bond pad 130 are separated laterally on the back surface of the substrate 104 and electrically insulated from each other. The VDD bond pad 128 and VSS bond pad 130 are electrically insulated from each other by the dielectric layer, as shown in Figures 5A to 5G and described in more detail below with respect to Figures 5A to 5G. The VDD bond pad 128 and VSS bond pad 130 extend over the source and drain of multiple transistor cells, respectively, and are bonded to the source and drain by their respective VDD vias 126DD and VSS vias 126SS. In this embodiment, each of the VDD bond pad 128 and VSS bond pad 130 is electrically connected to at least two of their respective VDD embedded power rails 112 or VSS embedded power rails 114.

[0044] Furthermore, each of the VDD bond pads 128 and VSS bond pads 130 is electrically connected to at least two transistor cells, where the transistor cells or unit cells can function as basic functional blocks, circuit blocks, or transistor layouts of the chip. For example, transistors or unit cells include, but are not limited to, memory cells, logic cells, combination cells, etc. As a further example, the transistors or unit cells may be 6T SRAM cells having six transistors. In embodiments, multiple transistors in a unit cell or transistor layout can share VDD and VSS embedded power rails 112, 114 using one or two (or a few) VDD or VSS vias 126DD, 126SS that ultimately connect to the VSS or VDD bond pads 128, 130 (e.g., vias in the routing / RDL layer). In embodiments, for example, a single cell fabricated using 5nm technology may have a footprint of tens or hundreds of nanometers, thereby allowing the pitch of conductive features 107a and 107b to be relaxed from ~5nm at the transistor level to tens to hundreds of nanometers at the direct junction level. In embodiments, several such unit cells may share VDD and VSS embedded power rails 112, 114, which may help to further widen the minimum pitch at the direct junction level. In addition, multiple VDD / VSS embedded power rails 112, 114 from multiple unit cells may be connected using a limited number of vias to one or two VSS or VDD bond pads 128, 130.

[0045] In various embodiments, the VDD bond pad 128 and VSS bond pad 130 may be electrically connected to the respective VDD embedded power rail 112 and VSS embedded power rail 114 using a plurality of respective VDD vias 126DD and VSS vias 126SS. Furthermore, in various embodiments, each of the VDD embedded power rail 112 and VSS embedded power rail 114 can supply power and / or ground to a plurality of transistor cells in the integrated circuit 100.

[0046] In one embodiment, the power distribution network, which was conventionally located within the BEOL, may be fabricated on a separate chip (not shown), for example, a power distribution chip. In one embodiment, the power distribution chip may have bond pads configured to be directly bonded to the corresponding VDD bond pads 128 and VSS bond pads 130 of the integrated circuit 100. In this embodiment, the power distribution chip may be hybrid bonded to the back surface of the integrated circuit 100 along a bond interface 119 (as described with respect to Figures 9A-9B), thereby providing the integrated circuit 100 with a back surface power distribution network. Advantageously, in this embodiment, the hybrid bonded VDD bond pads 128 and VSS bond pads 130 may be connected to separate VDD and VSS embedded power rails 112, 114 and transistor cells using one or more back surface vias 126DD, 126SS. Resistance is reduced by connecting to the VDD and VSS embedded power rails 112, 114 and transistor cells using multiple back surface vias 126DD, 126SS. Furthermore, the VDD bond pads 128 and VSS bond pads 130, as well as the VDD back vias and VSS back vias, can be formed simultaneously using a dual damascene process, thereby saving several processes. Additionally, the VDD bond pads 128 and VSS bond pads 130 may be elongated, having a length-to-width ratio of 1:1 to 10:1, such as greater than 2:1, greater than 4:1, or greater than 5:1. Elongated VDD bond pads 128 and VSS bond pads 130 facilitate alignment in the hybrid bonding process. Even more advantageously, by using multiple vias to bond to a larger bond pad, efficient fan-out from very small-pitch vias to relatively large-pitch pads is essentially possible. Thus, the transition from fine pitch to large pitch is relatively easy. Furthermore, as will be described in detail in some embodiments below, the use of relatively large VDD bond pads 128 and VSS bond pads 130 formed very close to the conduction channel can shield the conduction channel from interference.

[0047] Figures 4A and 4B are a cross-sectional view and a top view of an integrated circuit in another embodiment, respectively. In this embodiment, the VSS ground plane or reference plane 134 may be formed between the VDD and VSS bond pads 128, 130 and a conductive channel or VDD and VSS vias 126DD, 126SS so that the VSS embedded power rail 114 is grounded to the VSS ground plane or reference plane 134 via the VSS via 126SS. Similar to the previous embodiment, the VDD bond pad 128 and VSS bond pad 130 may be formed in a dielectric layer 144 formed on the back surface 117a of the substate 104. As shown, an opening 142 may be formed in the VSS ground plane or reference plane 134 so that the VDD via 126DD is bonded to the VDD bond pad 128 without being short-circuited to ground. In various embodiments, the reference plane 134 may be located 100 nm to 3 microns below the VDD embedded power rail 112 and VSS embedded power rail 114. Furthermore, as shown in Figures 4A and 4B, the length, width, and height or thickness of the VDD bond pad 128 and the VSS bond pad 130 may differ from each other. In particular, even if the VSS bond pad 130 is narrower than the VDD bond pad 128, it can have a similar cross-sectional area because the height of the VSS bond pad 130 is greater. The VSS ground plane can be made larger, allowing the VSS bond pad 130 to be made smaller. Also, because the VSS bond pad 130 extends deeper into the dielectric layer 144, the VSS bond pad 130 can be made even smaller. In various embodiments, the vertical separation between the VDD embedded power rail 112 and the VSS embedded power rail 114 and the VDD bond pad 128 and the VSS bond pad 130 can be 100 nm to 3 microns.

[0048] Figure 4C is a cross-sectional view of a modified example of the integrated circuit shown in Figures 4A and 4B. In this embodiment, the VSS bond pad 130 is bonded to the VSS ground plane or reference plane 134 by VSS back-side vias 126SS. In this embodiment, the gap between the conduction channel and the ground plane or reference plane 134 may be in the range of 50 to 500 nm, for example, greater than 100 nm, greater than 200 nm, and for example, greater than 300 nm.

[0049] Figure 4D is a cross-sectional view of another modification of the integrated circuit shown in Figures 4A and 4B. In this embodiment, the integrated circuit includes at least one redistribution or redistribution layer (RDL) 154 located between the electronic components 106 or VDD, VSS embedded power rails 112, 114 and the VDD or VSS bond pads 128, 130. The redistribution layer is a metal layer patterned on a dielectric layer and redistributes the inputs and outputs (I / O) of the integrated circuit 100 to different lateral positions. The new lateral positions can be lateral outward or inward. RDL technology allows for die placement in a compact and efficient manner, thereby reducing the overall footprint of the device. As shown, the RDL 154 is located below the reference plane 134, i.e., between the reference plane 134 and the VDD bond pads 128 and VSS bond pads 130. Alternatively, the RDL154 may be positioned above the reference plane 134, i.e., between the reference plane 134 and the electronic components 106 or VDD, VSS embedded power rails 112, 114. In some embodiments, the metallization of the reference plane 134 can also be used for some routing, redistribution, or redistribution. In another embodiment, one or more redistribution layers 154 may be added below the VSS and VDD bond pads 128, 130 to allow expansion from the narrow-pitch transistor cells or VDD, VSS embedded power rails 112, 114 to the wider pitch of the VSS and VSS bond pads 128, 130.

[0050] Figures 5A to 5H are cross-sectional views showing methods for manufacturing integrated circuits according to several embodiments. As shown in Figure 5A, an in-process integrated circuit is provided. The in-process integrated circuit includes a VDD embedded power rail 112 and a VSS embedded power rail 114. An etching stop layer 138 in the wafer 104 is also included. In this step, the in-process integrated circuit is mounted to the front carrier 136. In some embodiments, the in-process integrated circuit can be bonded directly to the front carrier 136 without adhesive. In other embodiments, the in-process integrated circuit can be bonded directly to the front carrier 136 using any other temporary bonding material suitable for back grinding, thinning, and back BEOL formation processes.

[0051] Referring to Figure 5B, the wafer 104 is thinned. Thinning can be performed by a combination of polishing, wet etching, or dry etching. The wafer 104 is thinned until the etching stop layer 138 is reached. The etching stop layer 138 can then be removed in another etching step. In an embodiment, the wafer 104 is made of Si, and the etching stop layer 138 can consist of silicon oxide, silicon nitride, SiGe, or other suitable embedded etching stop layer. Other combinations of material layers for the wafer and etching stop layer can be used.

[0052] Referring to Figure 5C, via holes 140 can be formed on the back surface of the wafer 104 extending to the VDD embedded power rail 112 and the VSS embedded power rail 114. In one embodiment, via holes 140 can be formed by etching such as wet etching or dry etching.

[0053] Referring to Figure 5D, a conductive material can be deposited in the via holes 140 (e.g., by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable process) to form VDD vias 126DD, VSS vias 126SS, and VSS ground planes or reference planes 134. The conductive material may be a metal or a silicide. Subsequently, the VSS ground planes or reference planes 134 can be polished and planarized. Planarization can be performed by chemical mechanical polishing or other suitable methods.

[0054] Referring to Figure 5E, the VSS ground plane or reference plane 134 can be patterned, and an opening 142 can be formed in the VSS ground plane or reference plane 134 so that the subsequently formed VDD embedded power rail is not grounded to the VSS ground plane or reference plane 134.

[0055] Referring to Figure 5F, one or more dielectric layers 144 can be deposited on the back surface of an in-process integrated circuit. The one or more dielectric layers 144 may be made of any suitable material such as SiO2 or silicon nitride.

[0056] Referring to Figure 5G, via holes 140 can be formed through the dielectric layer 144 to the VSS ground plane or reference plane 134 and the VDD embedded power rail 112. Next, trenches 146 can be formed in the dielectric layer 144, connecting the multiple via holes 140 to the VSS ground plane or reference plane 134 and the VDD embedded power rail 112, respectively.

[0057] Referring to Figure 5H, via holes 140 and trenches 146 can be filled with conductive material to form VSS vias 126SS, VDD vias 126DD, and VDD bond pads 128 and 130. This embodiment for forming VSS vias 126SS, VDD vias 126DD, VDD bond pads 128 and 130 is sometimes called a dual damascene process. In an alternative process, via holes 140 are formed and filled with conductive material to first form VSS vias 126SS and VDD vias 126DD in a first damascene process. Next, trenches 146 are formed and filled with conductive material to form VDD bond pads 128 and 130 in a second, separate damascene process.

[0058] In one embodiment, the power distribution network is formed on a separate chip (shown in Figure 6 and described in more detail below) and can be directly bonded to the in-process integrated circuit shown in Figure 5H using a direct hybrid bonding process. In this way, the PDN can be formed on the back surface of the integrated circuit, while the electrical components and signal distribution network can be formed on the front surface of the integrated circuit.

[0059] In the various embodiments described above, the VDD vias 126DD and VSS vias 126SS may be made of W, Ru, Co, or Cu when processed at higher temperatures. In such embodiments, the VDD bond pads 128 and VSS bond pads 130 may be made of different materials such as copper, which can be formed using a lower temperature process when forming the BEOL. If the VDD vias 126DD and VSS vias 126SS are made of Cu, a barrier layer such as silicon nitride and a linter layer such as titanium nitride can be deposited as first layers before forming the VDD vias 126DD and VSS vias 126SS. In various embodiments, the power line pitch is in the range of 10nm to 500nm, such as 10nm to 100nm, 20nm to 200nm, or 50nm to 500nm. In various embodiments, the device pitch is in the range of 1nm to 200nm, such as 1nm to 10nm, 15nm to 150nm, 20nm to 100nm, or 40nm to 80nm. In various embodiments, the thickness of the VDD bond pad 128 and VSS bond pad 130 can be at least 0.2 microns, such as 200nm, 500nm, or 1 micron. The pitch of the VDD bond pad 128 and VSS bond pad 130 is 0.1 microns to 1.0 micron, and the thickness is 0.1 microns to 0.5 microns. In various embodiments, the vertical separation between the embedded power lines and the bottom of the VDD bond pad 128 and VSS bond pad 130 may be in the range of 200nm to 5 microns. In various embodiments, the vertical separation between the buried power line and the ground plane or reference plane 134 may be in the range of 100 nm to 3 microns.

[0060] Figure 6 shows a cross-sectional view of an embodiment in which the power distribution network PDN is formed on a separate chip 150 and can be hybrid-bonded to the integrated circuit 100. The illustrated integrated circuit 100 corresponds to the embodiment shown in Figure 3A above, but any of the integrated circuit 100s of the above embodiments may have a separate chip 150 on which the PDN formed thereon is hybrid-bonded.

[0061] Figure 7 is a process flow diagram showing a method 700 for manufacturing an exemplary integrated circuit in some embodiments of the disclosed technology. Referring to step 702, a first substrate is provided. Referring to step 704, a transistor is formed on the front surface of the first substrate. Referring to step 706, a plurality of embedded power rails are formed on the front surface of the first substrate. Referring to step 708, a plurality of signal lines are formed on the front surface of the first substrate. Referring to step 710, a carrier is bonded to the front surface of the first substrate. Referring to step 712, the back surface of the first substrate is thinned. Referring to step 714, a plurality of vias are formed on the back surface of the first substrate to the embedded power rails. Referring to step 716, a bond pad is formed on the back surface of the first substrate, which electrically contacts at least two embedded power rails via a plurality of vias to each of at least two embedded power rails.

[0062] Figure 8 is a process flow diagram showing another method for manufacturing an exemplary integrated circuit in some embodiments of the disclosed technology. Referring to step 802, a first substrate is provided. Referring to step 804, a transistor is formed on the front surface of the first substrate. Referring to step 806, a plurality of embedded rails are formed on the front surface of the first substrate. Referring to step 808, a plurality of first interconnects are formed on the front surface of the first substrate. Referring to step 810, a carrier is bonded to the front surface of the first substrate. Referring to step 812, the back surface of the first substrate is thinned. Referring to step 814, a plurality of vias are formed through the back surface of the first substrate to the embedded rails. Referring to step 816, a bond pad is formed on the back surface of the first substrate, which electrically contacts at least two embedded rails via a plurality of vias for each of at least two embedded rails.

[0063] Unless the context clearly indicates otherwise, terms such as “includes” and “contains” throughout this specification and claims should be considered in a comprehensive, not restrictive, sense, meaning “includes but not limited.” As commonly used herein, the term “joined” refers to two or three or more elements that are directly connected or can be connected via one or more intermediate elements. Similarly, as commonly used herein, the term “connected” refers to two or three or more elements that are directly connected or can be connected via one or more intermediate elements. Furthermore, “this specification,” “above,” “below,” and similar terms, when used in this application, refer to the entire application and not to any particular part of this application. Furthermore, where used herein, if it is stated that the first element is “on top of” or “covering” the second element, the first element may be directly on top of or covering the second element so that the first and second elements are in direct contact, or the first element may be indirectly on top of or covering the second element so that one or more elements are interposed between the first and second elements. Where the context allows, the terms in the above detailed description that use singular or plural numbers may each include plural or singular numbers. In relation to a list of two or more items, the term “or” encompasses all interpretations of the term, including any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0064] Furthermore, conditional language used herein, in particular, such as “can,” “may,” “might,” “for example,” and “like,” is generally intended to convey that certain embodiments include certain features, elements, and / or states, and that other embodiments do not, unless otherwise specified or understood within the context in which they are used. Therefore, such conditional expressions are generally not intended to suggest that features, elements, and / or states are required in any way in one or more embodiments.

[0065] While specific embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of this disclosure. In fact, the novel apparatus, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and modifications in the forms of methods and systems described herein can be made without departing from the spirit of this disclosure. For example, while blocks are shown in a given arrangement, in alternative embodiments, similar functions may be performed with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in a variety of different ways. Further embodiments can be provided by combining any suitable combination of elements and actions in the various embodiments described above. The appended claims and their equivalents are intended to cover forms or modifications that fall within the scope and spirit of this disclosure. [Explanation of symbols]

[0066] 100 Integrated Circuits 104 106 Electrical components 112 VDD buried power rail 114 VSS Embedded Power Rail 116 FINFET fins 118 Guard gate 124 Shallow trench insulating layer

Claims

1. It is an integrated circuit, Multiple transistors located on the first side of the substrate, A plurality of buried power rails connected to the plurality of transistors, comprising a plurality of VSS power rails and a plurality of VDD power rails, At least one VSS pad and at least one VDD pad, A plurality of vias electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails, wherein the at least one VSS pad is located on the second side of the substrate opposite to the first side, The at least one VDD pad is electrically connected to at least two of the embedded plurality of VDD power rails by a plurality of vias, wherein the at least one VDD pad is located on the second side of the substrate opposite to the first side, An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, wherein the plurality of VSS and VDD pads are provided on the back surface of the die.

3. The integrated circuit according to claim 1, wherein the plurality of VSS and VDD pads are configured for hybrid bonding.

4. The integrated circuit according to claim 1, wherein multiple buried VSS power rails or multiple buried VDD power rails supply power to multiple transistors.

5. The integrated circuit according to claim 1, wherein the plurality of buried power rails are arranged at the front end of line (FEOL).

6. The integrated circuit according to claim 1, wherein the at least one VSS pad and / or the at least one VDD pad has a length-to-width ratio in the range of 1:1 to 10:

1.

7. The integrated circuit according to claim 1, wherein the plurality of transistors are Finn field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAs).

8. The integrated circuit according to claim 1, further comprising a ground plane or reference plane located below the plurality of buried power rails.

9. The integrated circuit according to claim 1, wherein the at least one VSS pad and the at least one VDD pad are located 100 nm to 3 μm below the plurality of buried power rails.

10. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is located 100 nm to 3 μm below the plurality of buried power rails.

11. The integrated circuit according to claim 8, wherein at least one of the length, width, and thickness of the at least one VSS pad is different from the length, width, and thickness of the at least one VDD pad.

12. The integrated circuit according to claim 8, wherein a plurality of vias include VSS vias and VDD vias, and all of the VSS vias are short-circuited to the ground plane or reference plane.

13. The integrated circuit according to claim 8, wherein the ground plane or the reference plane includes an opening that allows the VDD via to pass through the ground plane or the reference plane without being short-circuited to the ground plane or the reference plane.

14. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is directly located on the at least one VSS pad.

15. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is electrically connected to the at least one VSS pad by vias.

16. It is an integrated circuit, Multiple transistors located on the first side of the substrate, A plurality of buried power rails connected to the plurality of transistors, comprising a plurality of VSS power rails and a plurality of VDD power rails, Located on the second side of the substrate opposite to the first side, at least one VSS pad and at least one VDD pad, A power distribution network element hybrid-bonded to a hybrid bonding surface including the at least one VSS pad and the at least one VDD pad, An integrated circuit equipped with the following features.

17. The at least one VSS pad is electrically connected to at least two of the plurality of VSS power rails via a plurality of vias, The at least one VDD pad is electrically connected to at least two of the embedded plurality of VDD power rails via a plurality of vias, The integrated circuit according to claim 16, further comprising the above.

18. A method for manufacturing an integrated circuit having a back-side power supply, The first substrate is provided on its front surface, having a plurality of transistors, a plurality of embedded power rails, and a plurality of signal lines. The back surface of the first substrate is made thinner, To form multiple vias from the back surface of the first substrate to the multiple embedded power rails, The method involves forming a bond pad on the back surface of the first substrate, wherein the bond pad is in electrical contact with each of the at least two embedded power rails via the plurality of vias, Methods that include...

19. The method according to claim 18, further comprising bonding a carrier to the front surface of the first substrate before thinning the back surface of the first substrate.

20. The method according to claim 18, further comprising hybrid bonding a second substrate having a power supply network formed inside to the back surface of the first substrate.

21. The method according to claim 18, wherein the bond pad includes a VSS pad and a VDD pad.

22. The method according to claim 21, further comprising forming a ground plane or reference plane electrically connected to the VSS bond pad.

23. The method according to claim 22, wherein the VSS bond pad is formed directly on the ground plane or the reference plane.

24. The method according to claim 22, wherein forming the ground plane or the reference plane includes forming a ground plane via or reference plane via connecting the ground plane or the reference plane to the VSS bond pad.

25. Forming the ground plane or the reference plane is A conductive material is deposited on the plurality of vias formed from the back surface of the first substrate to the plurality of embedded power rails, Patterning the ground plane or the reference plane such that it contacts only a portion of the plurality of buried power rails, Depositing one or more dielectric layers on the patterned ground plane or reference plane, By forming via holes in the one or more dielectric layers, and exposing a portion of the patterned ground plane or reference plane, Forming trenches in the one or more dielectric layers, Filling the via holes in the one or more dielectric layers to form vias in the one or more dielectric layers, The trenches in the one or more dielectric layers are filled to form the VSS bond pad, The method according to claim 24, including the method described in claim 24.

26. The method according to claim 21, further comprising forming a VSS pad and a VDD pad having one or more different dimensions relative to each other.

27. The method according to claim 18, wherein the plurality of buried power rails contain tungsten, and the plurality of vias from the back surface of the first substrate to the plurality of buried power rails contain ruthenium.

28. A method for manufacturing an integrated circuit having a back-side interconnect network, The first substrate is provided on its front surface, having a plurality of transistors, a plurality of embedded power rails, and a plurality of first interconnection parts. The back surface of the first substrate is made thinner, To form multiple vias from the back surface of the first substrate to the embedded rail, Forming a bond pad on the back surface of the first substrate, wherein the bond pad is in electrical contact with each of the at least two embedded rails via a plurality of vias, Methods that include...

29. The method according to claim 28, further comprising bonding a carrier to the front surface of the first substrate before thinning the back surface of the first substrate.

30. The method according to claim 28, wherein the first interconnection unit includes either a power distribution network or a signal distribution network.

31. The method according to claim 28, further comprising hybrid bonding a second substrate having a second interconnection portion formed inside to the back surface of the first substrate.

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