Semiconductor devices having selectively doped gate electrode structures

Abstract

A semiconductor device comprising a selectively doped gate electrode is described. The semiconductor device comprises a substrate (103) including a body region and a drift region (126), and a gate dielectric layer (134) on the substrate (103), comprising a gate dielectric layer (134) extending over the body region and the drift region (126), and a gate dielectric layer (134) on the drift region (126), wherein a field reduction dielectric layer (120) abuts laterally with the gate dielectric layer (134) at a certain location in the drift region (126). The semiconductor device also comprises a gate electrode (142) having an n-doped first portion (164), a p-doped second portion (165), and an n-doped third portion (166). The selectively doped second portion (165) of the gate electrode (142) is located above the intersection (167) between the gate dielectric layer (134) and the field reduction dielectric layer (120).

Description

[Technical Field]

[0001] This description relates to the field of microelectronic devices. More specifically, this description relates to, but is not limited to, semiconductor devices having selectively doped gate electrode structures. [Background technology]

[0002] Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing semiconductor devices with increasingly higher performance while meeting reliability specifications is becoming increasingly challenging. [Overview of the project]

[0003] This summary is provided to introduce, in a simplified form, some of the concepts described below, which are further described in the detailed description, including the attached drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0004] The examples described include semiconductor devices having selectively doped gate electrode structures. The semiconductor device includes a substrate having a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type; a gate dielectric layer on the substrate, extending over the body region and the drift region; a field reduction dielectric layer on the drift region, in lateral contact with the gate dielectric layer at a certain position in the drift region; a gate electrode on the gate dielectric layer and the field reduction dielectric layer, having a second conductivity type and having a first portion extending over the body region and a first portion of the drift region; a second portion having a first conductivity type, in contact with the first portion, and extending over a second portion of the drift region and a first portion of the field reduction dielectric layer; and a third portion having a second conductivity type, in contact with the second portion, and extending over a second portion of the field reduction dielectric layer. The semiconductor device also includes a source region located in the body region and having a second conductivity type, and a drain region located in the drift region and having a second conductivity type. [Brief explanation of the drawing]

[0005] [Figure 1A] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1B] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1C] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1D] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1E] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1F] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1G] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1H] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1I] This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. [Figure 1J]A cross-sectional view of an exemplary microelectronic device including transistors having selectively doped gate electrode structures at various stages of formation.

[0006] [Figure 2] A top view of an exemplary microelectronic device including selectively doped transistors.

[0007] [Figure 3] A cross-section of an alternative exemplary microelectronic device including transistors having selectively doped gate electrodes.

[0008] [Figure 4] A graph of time-dependent dielectric breakdown (TDDB) reliability data from transistors having uniformly doped gate electrode structures and transistors having selectively doped gate electrode structures.

Best Mode for Carrying Out the Invention

[0009] This description will be explained while referring to the accompanying drawings. The drawings are not drawn to a fixed scale and are provided merely to explain this description. Some aspects of this description will be described hereinafter while referring to exemplary application examples for the purpose of explanation. It should be understood that many specific details, relationships, and methods are shown to understand this description. Since some acts can be performed in a different order and / or simultaneously with other acts or events, this description is not limited by the order in which such acts or events are described. Also, not all acts or events described are required to implement the methodology according to this description.

[0010] Also, some of the embodiments shown in this specification are illustrated in two-dimensional diagrams having various regions with depth and width, but these regions are only examples of a part of a device that is actually a three-dimensional structure. Therefore, these regions have three dimensions including length, width, and depth when manufactured on an actual device. Also, this description is illustrated by examples directed to active devices, but these examples are not intended to be limitations on the scope or applicability of this description. It is not is not intended that the active devices of this description be limited to the illustrated physical structures. These structures are included to demonstrate the usefulness and application examples of this description for currently preferred embodiments.

[0011] Note that terms such as top, bottom, on, above, and below may be used in this description. These terms should not be construed as limiting the position or orientation of a structure or element, but are used to provide a spatial relationship between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to a plane corresponding to the surface of a layer, for example, the top surface of a semiconductor substrate. Also, the term "about" used in this specification may, in some cases, refer to a variation of ±5% to ±10% of the value described. In other cases, the term "about" may refer to a variation of ±10% to ±20% of the value described.

[0012] Semiconductor components or devices are constantly being improved to operate reliably at smaller feature sizes. Manufacturing such semiconductor components or devices while meeting area scaling and reliability requirements is challenging. Certain metal-oxide-semiconductor (MOS) transistors include features to support high-voltage operation, for example, with voltages applied to the drain (or drain structure) of about 20V, 30V, 40V, or higher. Such MOS transistors may include a drain diffusion profile (or drain junction profile) designed to support high voltages applied to the drain, for example, having an extension to distribute the voltage drop over a wider area. Thus, such MOS transistors may also be referred to as drain-extended MOS transistors, e.g., drain-extended n-channel MOS (DENMOS) transistors, drain-extended p-channel MOS (DEPMOS) transistors, lateral diffusion MOS (LDMOS) transistors, and the group of DENMOS and DEPMOS transistors (which may also be referred to as complementary drain-extended MOS or DECMOS transistors).

[0013] Furthermore, drain-extended MOS (DEMOS) transistors include a field-reducing dielectric layer in addition to the gate dielectric layer, so that the field-reducing dielectric layer can mitigate various undesirable effects during transistor operation, such as damaging the gate dielectric layer in the absence of the field-reducing dielectric layer, taking into account the high voltage applied to the drain. As will be described in more detail herein, the field-reducing dielectric layer abuts laterally with the gate dielectric layer and extends over the drift region of the DEMOS transistor (e.g., the extended portion of the drain junction profile). The DEMOS transistor includes a gate (gate electrode or gate electrode structure) on the gate dielectric layer and the field-reducing dielectric layer, which controls the current conduction in the channel (e.g., a semiconductor channel) between the drain and source of the DEMOS transistor, for example, turning the DEMOS transistor on / off. The gate (or gate electrode structure) may include n-type polysilicon for DENMOS (or p-type polysilicon for DEPMOS). The transition region (e.g., the intersection) between the gate dielectric layer and the field-reducing dielectric layer beneath the gate may correspond to the position where the electric field during DEMOS transistor operation can reach its maximum value. Therefore, gate dielectric layers near (or adjacent to) the intersection can be susceptible to various degradation mechanisms.

[0014] For example, during high-voltage operation, a peak electric field in or near the transition region can generate electron-hole pairs in the channel's drift region, for instance, by collisional ionization. Electrons and holes can gain energy under the electric field (e.g., "get hot"), which may be sufficient to overcome the energy barrier between the gate dielectric layer and the drift region. Therefore, while the n-type polysilicon gate above the gate dielectric layer can inject electrons, at least some hot holes can be injected into the gate dielectric layer. When holes and electrons recombine within the gate dielectric layer, each recombination event is estimated to release approximately 9 eV of energy, which is expected to accelerate the gate dielectric degradation rate (also known as gate oxide wear). Such degradation of the gate dielectric layer can be expressed as time-dependent dielectric breakdown (TDDB) reliability, e.g., under on-state TDDB stress.

[0015] For the gate electrode of a DEMOS transistor (for example, a gate electrode structure extending across the gate oxide and the field-reducing oxide), it may be advantageous to use a selectively doped gate electrode to improve TDDB reliability characteristics. For example, in an n-channel DEMOS transistor, a portion of the n-type polysilicon gate can be selectively doped to form p-type polysilicon. Furthermore, the p-doped portion covers the intersection of the gate dielectric layer and the field-reducing dielectric layer, as well as the portions of the gate dielectric layer and field-reducing dielectric layer that are close to (adjacent to) the intersection.

[0016] In this way, when a DEMOS transistor operates under high voltage conditions, p-type polysilicon with holes as majority carriers (and electrons as minority carriers) above the intersection can reduce electron injection into the gate dielectric layer. As a result, even if holes injected by hot hole injection are present, the probability of electron-hole recombination events can be reduced, thereby reducing the degradation of the gate dielectric (e.g., wear of the gate oxide), and improving the on-state TDDB characteristics. In other words, the TDDB characteristics of the gate dielectric layer can be improved by suppressing the electron-hole recombination mechanism at or near the intersection of the gate dielectric layer and the field-reducing dielectric layer.

[0017] The examples described include doped regions of various semiconductor structures that may be characterized as p-doped and / or n-doped regions or portions, and include regions having multiple dopants of a particular type, such as n-type dopants (providing electrons as charge carriers) or p-type dopants (providing holes as charge carriers). For the purposes of this description, the first type of doping may be n-type doping (n-doped, first conductivity type), and the second type of doping may be p-type doping (p-doped, second conductivity type).

[0018] Figures 1A to 1J are cross-sectional views of an exemplary microelectronic device 100, including a DEMOS transistor 101, in a series of steps of an exemplary formation method. The DEMOS transistor 101 may have a racetrack layout as described with respect to Figure 2. The DEMOS transistor 101 described herein is an n-channel type (or n-channel DEMOS), but a p-channel DEMOS transistor (or p-channel DEMOS) may be formed if n-doped regions are replaced with p-doped regions and p-doped regions are replaced with n-doped regions according to this description.

[0019] FIG. 1A shows a cross-section of a microelectronic device 100 including a substrate 103 after a shallow trench isolation (STI) structure 116 and an electric field reducing dielectric layer 120 are formed. Also, FIG. 1A shows the area of the DEMOS transistor 101. The substrate 103 includes a semiconductor material (e.g., silicon, germanium, etc.) and has a surface 104. The substrate 103 may be, for example, a part of a bulk semiconductor wafer, a part of a semiconductor wafer having an epitaxial layer, a part of a silicon-on-insulator (SOI) wafer, or other structure suitable for forming the microelectronic device 100.

[0020] The substrate 103 may include an optional n-type buried layer (NBL) 106 on a p-type layer 105. The p-type layer 105 may be a part of the bulk semiconductor wafer on which the microelectronic device 100 is formed, and may have, for example, a p-type impurity concentration of 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 . Alternatively, the p-type layer 105 may be doped at a low concentration with an average p-type dopant concentration of less than 1×10 18 atoms / cm 3 . The NBL 106 may have a thickness of, for example, 2 microns to 10 microns and may have an n-type dopant (e.g., arsenic, antimony) exceeding 1×10 19 atoms / cm 3 . The substrate 103 may include an epitaxial layer 108 on the NBL 106. The epitaxial layer 108 includes silicon. The epitaxial layer 108 can be regarded as a part of the substrate 103 and may have a thickness of, for example, 2 microns to 12 microns. The epitaxial layer 108 may be, for example, p-type with a concentration of 1×10 15 atoms / cm 3 ~1×10 16 atoms / cm 3 . When there is no NBL 106 in the substrate 103, the epitaxial layer 108 may be directly above the p-type layer 105.

[0021] The STI structure 116 can be formed by creating trenches in the substrate 103, for example, by etching a portion of the epitaxial layer 108 through openings in a hard mask containing a stack of pad oxide and nitride layers (not shown). The trenches can then be filled with one or more dielectric materials, such as high-density plasma (HDP) oxide. As will be described in more detail with reference to Figures 1G to 1J, the STI structure 116 is located between the source region 154 and the back gate region 162 of the DEMOS transistor 101.

[0022] The field-reducing dielectric layer 120 may be formed by a localized oxidation (LOCOS) process of silicon, for example, by exposing the surface 104 of the substrate 103 (or epitaxial layer 108) to a thermal oxidation treatment that grows the field-reducing dielectric layer 120 through openings in a stack of pad oxide and nitride layers (not shown). The field-reducing dielectric layer 120 may have a thickness in the range of 50 nm to 150 nm. The field-reducing dielectric layer 120 may have tapered edges along their periphery adjacent to the surface 104 of the substrate 103. The tapered edges of the field-reducing dielectric layer 120 are sometimes referred to as "birdsbeak" regions. As will be explained in more detail with reference to Figure 1J, the "birdsbeak" regions may generate a relatively large electric field during the operation of the DEMOS transistor 101.

[0023] An exemplary DEMOS transistor 101, including an STI structure 116 and a field-reducing dielectric layer 120, is illustrated in Figures 1A to 1J, but the description is not limited thereto. For example, as shown in Figure 3, the field-reducing dielectric layer 120 may be replaced with another STI structure (e.g., an STI-based field-reducing dielectric layer 320). Similarly, the STI structure 116 may be replaced with another LOCOS structure, for example, a LOCOS structure similar to the field-reducing dielectric layer 120.

[0024] Figure 1B shows a cross-section after the n-drift resist 122 has been deposited and patterned to form n-drift resist openings 123. Figure 1B also shows that one or more n-type injections 124 are performed to form drift regions 126 (which may be referred to as n-drift regions) in the exposed areas of the substrate 103. The n-type injections 124 for defining the drift regions 126 can be performed in multiple steps. For example, phosphorus is 1 × 10⁻⁶ 12 cm -2 ~1 × 10 13 cm -2 The total dose during this period can be injected with or without subsequent thermal cycling, at an energy suitable for forming a drift region 126. Arsenic can also be injected at a similar dose, but at a relatively lower energy than phosphorus. After the n-type injection 124, the n-drift resist 122 is removed.

[0025] Figure 1C shows a cross-section after the p-type well resist 128 has been deposited and patterned to form p-type well resist openings 129. Figure 1C also shows that p-type injection 130 has been performed to form p-type well regions 132 (which may be referred to as p-type well regions). The p-type dopants injected by p-type injection 130 may include boron and / or indium. To inject the p-type well regions 132, for example, energies of 80 keV to 3 MeV and 4.0 × 10⁻¹⁰ 12 cm -2 ~1.5×10 14 A series of boron implantations with a dose of cm can be used at an inclination angle of less than 10 degrees. The p-type well region 132 (along with the epitaxial layer 108 in some examples) may also be referred to as the body region of the DEMOS transistor 101 (e.g., the p-type body region). After the p-type implantation 130, the p-type well resist 128 is removed. Subsequently, dopants such as the dopant in the drift region 126 and the dopant in the p-type well region 132 may be activated using a thermal process.

[0026] Figure 1D shows a cross-section after the gate dielectric layer 134 has been formed. In some examples, the gate dielectric layer 134 is formed by high-temperature furnace operation or a rapid thermal process. In some examples, the gate dielectric layer 134 is grown on the surface 104 of the epitaxial layer 108. In some examples, the gate dielectric layer 134 is deposited across the entire substrate 103. The thickness of the gate dielectric 134 may be slightly thinner than the dielectric constant of silicon dioxide, approximately 3.9 nm as an example, but can range from approximately 3 nm to 15 nm for silicon dioxide or silicon oxynitride (SiON) gate dielectrics with higher dielectric constants.

[0027] Continuing to refer to Figure 1D, a gate layer 136 is formed on the gate dielectric layer 134. In some examples, the gate layer 136 is formed by a deposition process using one or more silane precursors to deposit polycrystalline silicon (sometimes referred to as polysilicon). In other examples, a substitution gate process may be used to form the gate layer 136. In this example, the gate layer 136 contains polycrystalline silicon and may also be referred to as the gate polysilicon layer 136. The gate polysilicon layer 136 has a thickness 171 which can range from approximately 50 nm to 300 nm. The gate polysilicon layer 136 does not need to be doped during deposition. Subsequently, the gate polysilicon layer 136 is selectively doped, as described in more detail with reference to Figures 1G and 1H.

[0028] Figure 1E shows a cross-section after the gate resist 144 has been deposited and patterned, after which the gate dielectric layer 134 and gate polysilicon layer 136 are patterned based on the gate resist 144 pattern. Gate plasma etching 146 is used to define the gate electrode 142. As described with reference to Figure 2, the gate electrode 142 may have a racetrack layout. After the gate plasma etching 146 is complete, the gate resist 144 is removed, and a wet or dry process may be used to clean the wafer surface. As shown in Figure 1E, the gate electrode 142 extends over a portion of the p-type well region 132, a portion of the epitaxial layer 108, and a portion of the drift region 126 of the DEMOS transistor 101. One end of the gate electrode 142 is terminated on the field-reducing dielectric layer 120, while the other end of the gate electrode 142 is terminated on the source-side n-type doped region within the p-type well region 132, which is electrically connected to a source region 154 that is later formed, for example, as shown in Figure 1G.

[0029] Figure 1F shows a spacer 148 formed on the lateral surface (e.g., sidewall) of the gate electrode 142. The spacer 148 is formed by blanket forming one or more conformal layers of dielectric material on the substrate 103 and on the gate electrode 142. Subsequently, the dielectric material is removed from the horizontal surface, i.e., the surface substantially parallel to the surface 104 of the substrate 103, by an anisotropic etching process such as a reactive ion etching (RIE) process, leaving the dielectric material on the lateral surface of the gate electrode 142. The spacer 148 may contain dielectric materials such as silicon dioxide, silicon nitride, or both. The spacer 148 may extend 50 to 200 nanometers from the lateral edge of the gate electrode 142. Also, n-type implantation may be performed before forming one or more conformal layers of the spacer 148. Such implantation forms a source-side n-doped region (not explicitly shown) which is coupled to a source region 154 that is later formed as shown in Figure 1G. In this way, the source region 154 (together with the source-side n-doped region below the spacer 148) can electrically overlap with the gate electrode 142.

[0030] Figure 1G shows a cross-section after the source / drain resist 150 has been deposited and patterned to form various openings for the subsequent source / drain injection 152. Some openings are designed to form source regions 154 and drain regions 156. Some openings are designed to selectively introduce the n-type dopant of the source / drain injection 152 into portions of the gate polysilicon layer 136, which correspond to the first portion 164 and third portion 166 of the gate electrode 142 as described with reference to Figures 1H and 1I. Additionally, the patterned source / drain resist 150 covers portions of the gate polysilicon layer 136 (as indicated by segments 151 of the source / drain resist 150 blocking the source / drain injection 152), which correspond to the second portion 165 of the gate electrode 142 as described with reference to Figures 1H and 1I.

[0031] The patterned source / drain resist 150 is shown to have an edge above the STI structure 116 so that an opening for forming the source region 154 can overlap with the STI structure 116. Such overlap can ensure that the source / drain injection 152 is performed over the entire source region 154, despite statistical process variations present during the manufacturing process, such as variations in critical dimensions and variations in lithography registration performance. Similarly, the patterned source / drain resist 150 is shown to have an edge above the gate polysilicon layer 136. In this way, it is ensured that the source / drain injection 152 does not overlap with the field-reducing dielectric layer 120 so that the n-type dopant of the source / drain injection 152 does not penetrate the field-reducing dielectric layer 120, despite process variations.

[0032] Referring also to Figure 1G, the source / drain injection 152 injects an n-type dopant into the source region 154 within the p-type well region 132 and into the drain region 156 within the drift region 126. The source / drain injection 152 performs 5 × 10⁻¹⁰ injections in one or more steps using an injection species containing one or more of phosphorus and arsenic. 13 cm -2 ~4.5×10 15 cm -2 The total dose can be performed at energies of 2 keV to 80 keV. In some examples, source / drain injection 152 is designed to provide degenerate doping to the source region 154 and drain region 156, for example, 1 × 10⁻¹⁶ near the dissolution limit of the dopant atoms in the source region 154 and drain region 156. 19 / cm 3It has a larger active average dopant density than the drift region 126. The drain region 156 may have an average dopant density at least twice that of the drift region 126. The source region 154 may have an average dopant density at least twice that of the p-type well region 132. As shown in Figure 1G, the source region 154 appears to be laterally separated from the edge of the gate electrode 142, but the source region 154 (together with the source-side n-type doped region under the spacer 148) electrically overlaps with the gate electrode 142, and thus the source region 154 may be electrically coupled to the channel under the gate electrode 142. After source / drain injection 152, the source / drain resist 150 is removed.

[0033] Figure 1H shows a cross-section after another source / drain resist 158 ​​has been deposited and patterned to form various openings for the subsequent source / drain injection 160. The source / drain injection 160 injects p-type dopants into the source and drain regions of a p-channel transistor (e.g., a DEPMOS, not shown) that is simultaneously formed within the substrate 103. Similar to the source / drain injection 152, the source / drain injection 160 injects p-type dopants into, for example, 1 × 10¹⁶ dopants near the dissolution limit of dopant atoms in the source and drain regions. 19 / cm 3 This can be accomplished in one or more steps using an injection species containing boron (or indium) having a total dose and energy suitable for providing degenerate doping to the source and drain regions of DEPMOS, with an active average dopant density greater than that of the above.

[0034] At least one opening in the patterned source / drain resist 158 ​​is designed to form a back gate region 162. The patterned source / drain resist 158 ​​includes an opening 159 designed to selectively introduce a p-type dopant of the source / drain injection 160 into a portion of the gate polysilicon layer 136 corresponding to a second portion 165 of the gate electrode 142. The source / drain injection 160 injects one or more p-type dopants into the back gate region 162 and the second portion 165 of the gate electrode 142. The back gate region 162 is electrically isolated from the source region 154. However, the back gate region 162 is electrically coupled to the p-type well region 132 and the epitaxial layer 108.

[0035] As a result of source / drain injection 160, the second portion 165 of the gate electrode 142 is p-doped, for example, 1 × 10⁻¹⁶ 19 / cm 3 It is degenerately doped with a greater active average dopant density than the first portion 164 of the gate electrode 142. The third portion 166 of the gate electrode 142 also remains n-type doped. In other words, the second portion 165 of the gate electrode 142 is selectively doped to be oppositely doped to the rest of the gate electrode 142. The second portion 165 of the gate electrode 142 has a center located in the drift region 126, which is approximately corresponding to the intersection between the gate dielectric layer 134 and the field-reducing dielectric layer 120 (e.g., the birdsbeak region or its vicinity). In other words, the second portion 165 of the gate electrode 142 can be considered to have two halves joined in the middle, with the first half abutting the first portion 164 of the gate electrode 142 (for example, the left half of the second portion 165 as shown in Figure 1H), and the second half abutting the third portion 166 of the gate electrode 142 (for example, the right half of the second portion 165 as shown in Figure 1H). Thus, the center is located between the first portion 164 of the gate electrode 142 and the third portion 166 of the gate electrode 142.

[0036] Figure 1H illustrates a second portion 165 of the gate electrode 142 that receives the same injection (e.g., source / drain injection 160) as the back gate region 162 by sharing common process steps (e.g., source / drain resist 158 ​​and source / drain injection 160), but the description is not limited thereto. For example, the second portion 165 of the gate electrode 142 may receive additional p-type injection (in addition to source / drain injection 160) via an additional photolithography step that opens the second portion 165 of the gate electrode 142. In some examples, the second portion 165 of the gate electrode 142 may receive p-type injection independently of source / drain injection 160 via an additional photolithography step that defines the second portion 165 of the gate electrode 142 covering the back gate region 162.

[0037] Figure 1I shows a cross-section of the DEMOS transistor 101 after the back gate resist 158 ​​has been removed. As described with reference to Figure 1H, selective doping of the gate electrode 142 results in an n-type first portion 164, a p-type second portion 165 abutting the first portion 164, and an n-type third portion 166 abutting the second portion 165. The second portion 165 of the gate electrode 142 (e.g., the doped section opposite the gate electrode 142) has a width 169. The width 169 corresponds to the distance between the first portion 164 and the third portion 166 of the gate electrode 142. Also, the footprint of the second portion 165 is confined to the drift region 126 and does not extend into, for example, the p-type well region 132. In some examples, the width 169 of the second portion 165 is at least twice the thickness 171 of the gate polysilicon layer 136 (or the thickness of the gate electrode 142 including the gate polysilicon layer 136 and the gate dielectric layer 134). In some examples, the width 169 of the second portion 165 is greater than 300 nm. In some examples, selective doping of the second portion 165 of the gate electrode 142 degenerates the second portion 165. In other words, the second portion 165 of the gate electrode 142 is 1 × 10⁻¹⁶. 19 / cm 3It has an average concentration of electrically active dopants (e.g., dopants that contribute to holes) that is greater than [a certain value].

[0038] The second portion 165 of the gate electrode 142 lies on the intersection 167 where the gate dielectric layer 134 and the field-reducing dielectric layer 120 intersect. In other words, the footprint of the second portion 165 includes the intersection 167. The intersection 167 lies on the drift region 126. The intersection 167 (or its vicinity) may include a location where the electric field reaches its maximum value during DEMOS transistor operation. As described above, a strong electric field at or near the intersection 167 (e.g., the "birdsbeak" region) can generate electron-hole pairs, for example, in the drift region 126. In some cases, energy holes ("hot" holes) can be injected from the drift region 126 into the gate dielectric layer 134. Therefore, the gate dielectric layer 134 near (adjacent or adjacent to) the intersection 167 may be relatively more susceptible to TDDB reliability issues compared to other areas of the gate dielectric layer 134.

[0039] By selectively doping the gate electrode 142, the second portion 165 of the gate electrode 142 above the intersection 167 becomes p-type, for example, degenerately p-type doped. When the DEMOS transistor 101 operates under high voltage conditions (and hot holes are injected into the gate dielectric layer 134), the p-type doped second portion 165 above (and near) the intersection 167 is expected to reduce electron-hole recombination in the gate dielectric layer 134, in the sense that electrons are minority carriers in the p-type doped second portion 165. Thus, the p-type doped second portion 165 can suppress electron-hole recombination in the gate dielectric layer 134, and as a result, the gate oxide wear mechanism can be improved. In other words, the TDDB characteristics of the gate dielectric layer 134 can be improved by reducing the probability of electron-hole recombination events in the gate dielectric layer 134 near the intersection 167.

[0040] Figure 1J shows a cross-section of the DEMOS transistor 101 after the first level of interconnection 172 is completed. In some examples, a metal silicide layer (not specifically shown) may be formed on an exposed area of ​​the surface 104 of the substrate 103. A premetallic dielectric (PMD) layer 168 is formed on the surface 104 of the substrate 103. The PMD layer 168 may include one or more dielectric layers, such as silicon nitride, silicon oxynitride, or silicon dioxide. In some examples, the PMD layer 168 includes a PMD liner and a main dielectric sublayer formed on the PMD liner. The PMD layer 168 may then be planarized by a chemical mechanical polishing (CMP) process.

[0041] A contact 170 can be formed through the PMD layer 168. The contact 170 can be formed by patterning and etching holes through the PMD layer 168. The contact 170 can be filled by sputtering titanium to form a titanium adhesive layer, followed by forming a titanium nitride diffusion barrier. Next, a tungsten core can be formed by a process using tungsten hexafluoride (WF6). Subsequently, tungsten, titanium nitride, and titanium are removed from the top surface of the PMD layer 168 by a plasma etching process, a tungsten CMP process, or a combination of both, leaving a contact 170 extending to the top surface of the PMD layer 168.

[0042] An interconnect 172 may be formed on the contact 170. The contact 170 and interconnect 172 provide electrical contact between the DEMOS transistor 101 and other components of the microelectronic device 100. In this example version, where the interconnect 172 has an etched aluminum structure, the interconnect 172 may be formed by depositing an adhesive layer, an aluminum layer, and an anti-reflective layer, forming an etch mask (not explicitly shown), followed by a RIE process to etch the anti-reflective layer, aluminum layer, and adhesive layer in the areas exposed by the etch mask, and then removing the etch mask.

[0043] In this example version where the interconnect 172 has a damascene structure, the interconnect 172 may be formed by forming an intermetallic dielectric (IMD) layer (not specifically shown) on the PMD layer 168 and etching interconnect trenches through the IMD layer to expose the contacts 170. The interconnect trenches may be filled with barrier liners and copper. The copper and barrier liners may then be removed from the top surface of the IMD layer by a copper CMP process.

[0044] Figure 2 is a top view of a microelectronic device 200 including a DEMOS transistor 202 in a racetrack configuration, which is a racetrack layout (or a generally rectangular layout with rounded corners) in which, for example, the dimensions are generally larger in the first orientation than in the second orientation which is perpendicular to the first orientation. The DEMOS transistor 202 includes embodiments of the DEMOS transistor 101 described with reference to Figures 1A-1I. For example, the DEMOS transistor 202 includes a gate electrode 242 having a selectively doped portion. The DEMOS transistor 202 also has a gate electrode 242 in a racetrack configuration (which includes embodiments of the gate electrode 142). The gate electrode 242 includes a first portion 264 of a first conductivity type (e.g., n-type), a second portion 265 of a second conductivity type (e.g., p-type), and a third portion 266 of the first conductivity type (e.g., n-type). As shown in Figure 2, the gate electrode 242 surrounds the drain region 256 (which includes an embodiment of the drain region 156). The source region 254 (which includes an embodiment of the source region 154) surrounds the gate electrode 242.

[0045] Similar to the DEMOS transistor 101, the gate electrode 242 extends between the source region 254 and the drain region 256, and a second portion 265 of the gate electrode 242 extends over the intersection between the gate dielectric layer and the field reduction layer of the DEMOS transistor 202 (not explicitly shown), so that the gate dielectric layer may be less susceptible to wear mechanisms, e.g., on-state TDDB stress. Other elements of the DEMOS transistor 202 include a drift region 220 (which includes an embodiment of the drift region 126, with the portion extending below the gate electrode 242 not explicitly shown), an STI structure 216 (which includes an embodiment of the STI structure 116), a p-type well region 232 (which includes an embodiment of the p-type well region 132, with the portion extending below the gate electrode 242 not explicitly shown), a spacer 248 around the gate electrode 242 (which includes an embodiment of the spacer 148), and an isolation region 280 configured to provide isolation from the DEMOS transistor 202, for example, to suppress noise propagation through the substrate 103.

[0046] Figure 3 is a cross-section of an alternative microelectronic device 300, which includes a DEMOS transistor 301 having a selectively doped gate electrode structure. The DEMOS transistor 301 includes embodiments of DEMOS transistors 101 and 202 described with reference to Figures 1A to 1J and Figure 2. For example, the DEMOS transistor 301 includes a gate electrode 345 (which includes an embodiment of gate electrode 142) having a selectively doped portion. The DEMOS transistor 301 differs from the DEMOS transistor 101 in that the field-reducing dielectric layer 320 utilizes an STI structure instead of a LOCOS structure. Also, although the p-well region 332 (which includes an embodiment of p-type well region 132) is shown in contact with the drift region 326 (which includes an embodiment of drift region 126), the description is not limited thereto. For example, the p-well region 332 may be spaced apart from the drift region 326 so that the epitaxial layer 108 can extend between them to the surface 104 of the substrate 103.

[0047] Since the electrolytic reduction dielectric layer 320 provides a relatively flat surface topography (compared to, for example, the electrolytic reduction dielectric layer 120), the gate electrode 345 has a relatively uniform surface profile (compared to, for example, the gate electrode 142). In the exemplary DEMOS transistor 301, for the first conductivity type, the first portion 364 of the gate electrode 345 is located closer to the source region 154 (compared to, for example, other portions of the gate electrode 345). Also, the first portion 364 of the gate electrode 345 extends over a portion of the p-well region 332 and a portion of the drift region 326. For the second conductivity type, opposite to the first conductivity type, the second portion 365 of the gate electrode 345 abuts against the first portion 364 and the third portion 366 of the gate electrode 345. The second portion 365 of the gate electrode 345 is located on the intersection 367 between the gate dielectric layer 134 and the electrolytic reduction dielectric layer 320. Furthermore, the footprint of the second portion 365 is limited to the drift region 326 and does not extend, for example, into the p-well region 332. In some examples, the second portion 365 has a width 369 which is at least twice the thickness 371 of the gate polysilicon layer of the gate gate 345 (or the thickness of the gate gate 345 including the gate polysilicon layer and the gate dielectric layer 134). In some examples, the width 369 may be greater than 300 nm. The third portion 366 of the gate gate 345 is of the first conductivity type and lies on the field-reducing dielectric layer 320.

[0048] Figure 4 is a graph of TDDB reliability data from transistors with uniformly doped gate electrode structures, as well as from transistors with selectively doped gate electrode structures, such as the DEMOS transistors 101, 201, and 301 described in Figures 1A to 3. The vertical axis of the graph is the logarithmic representation of gate leakage current in any unit. The horizontal axis of the graph is the logarithmic representation of time in any unit while the transistor is subjected to reliability stress, such as on-state TDDB stress. A sharp increase in gate leakage current indicates significant degradation of the gate oxide (e.g., gate dielectric layer 134) under stress. Due to the nature of the logarithmic representation of time, the time to failure appears similar between the two transistors, but the time to failure for transistors with selectively doped gate electrode structures is approximately twice as long as the time to failure for transistors with uniformly doped gate electrode structures. This represents a significant improvement in gate dielectric reliability as a result of having selectively doped gate electrode structures as described herein. Furthermore, considering that selective gate doping is performed using existing source / drain injection masks and source / drain injections (e.g., source / drain resist 158, source / drain injection 160), the mask requirements or additional processing steps do not increase compared to DEMOS transistors with uniformly doped gate electrode structures.

[0049] While various embodiments have been described above, it should be understood that these are merely examples and not limiting. Therefore, although the aforementioned examples describe the use of various resist layers (e.g., photoresist or photomask layers) to carry out various process steps (e.g., injection or etching), this description is not limited to these. For example, one or more hard masks (including one or more layers) may be patterned to define various regions for subsequent process steps to be applied (e.g., regions for receiving dopant atoms, regions for blocking etchants). Furthermore, the resist layers may include multi-level resists instead of single-level resists in some examples. Many modifications can be made to the examples described without departing from the spirit or scope of this description. Therefore, the breadth and scope of this description are not limited by any of the embodiments described above. Rather, the scope of this description is defined according to the following claims and their equivalents.

Claims

1. It is a semiconductor device, A substrate including a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type, The gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, The electric field reducing dielectric layer on the drift region, wherein the electric field reducing dielectric layer abuts laterally against the gate dielectric layer at a certain position in the drift region, The gate electrode on the gate dielectric layer and the field-reducing dielectric layer, wherein the gate electrode is A first portion having the second conductivity type, the first portion extending over the body region and the first portion of the drift region, A second portion having the first conductivity type and in contact with the first portion, the second portion extending over the second portion of the drift region and the first portion of the field-reducing dielectric layer, A third portion having the second conductivity type and in contact with the second portion, the third portion extending on the second portion of the field-reducing dielectric layer, The aforementioned shutdown terminal, Displaced in the body region and having the second conductivity type, A drain region having the second conductivity type is arranged in the drift region, Semiconductor devices, including those mentioned above.

2. A semiconductor device according to claim 1, wherein the center of the second portion of the gate electrode substantially corresponds to the position in the drift region, and the center is located between the first portion of the gate electrode and the third portion of the gate electrode.

3. A semiconductor device according to claim 1, wherein the width of the second portion of the gate electrode is at least twice the thickness of the gate electrode, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.

4. A semiconductor device according to claim 1, wherein the width of the second portion of the gate electrode is greater than 300 nanometers, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.

5. A semiconductor device according to claim 1, wherein the second portion of the gate electrode is degenerately doped, or 1 × 10 １９ / cm ３ A semiconductor device having a larger active average dopant density than [a certain value].

6. A semiconductor device according to claim 1, wherein the field-reducing dielectric layer comprises silicon dioxide for a localized oxidation of silicon (LOCOS) layer, or a dielectric material for a shallow trench isolation (STI) layer.

7. A semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

8. A semiconductor device according to claim 1, wherein the gate electrode has a racetrack layout.

9. A semiconductor device according to claim 1, The gate dielectric layer has a first thickness, The electric field reducing dielectric layer has a second thickness that is greater than the first thickness. Semiconductor devices.

10. A semiconductor device according to claim 1, The source region has a first average dopant density that is greater than the second average dopant density of the body region. The drain region has a first average dopant density that is greater than the fourth average dopant density of the drift region. Semiconductor devices.

11. A semiconductor device according to claim 1, A back gate region disposed in the body region and having the first conductivity type, the back gate region being electrically insulated and separated from the source region, Semiconductor devices, which further include the following.

12. A semiconductor device according to claim 11, wherein the back gate region and the second portion of the gate electrode are formed simultaneously.

13. It is a method, The method involves forming a body region and a drift region within a substrate, wherein the body region has a first conductivity type, and the drift region has a second conductivity type opposite to the first conductivity type. The process involves forming a gate dielectric layer on the substrate, wherein the gate dielectric layer extends over the body region and the drift region. Forming an electric field reducing dielectric layer on the drift region, wherein the electric field reducing dielectric layer is in lateral contact with the gate dielectric layer at a certain position in the drift region. Forming a gate electrode on the gate dielectric layer and the field-reducing dielectric layer, wherein the gate electrode is A first portion having the second conductivity type, the first portion extending over the body region and the first portion of the drift region, A second portion having the first conductivity type, in contact with the first portion, and extending over the second portion of the drift region and the first portion of the field-reducing dielectric layer, A third portion having the second conductivity type, in contact with the second portion, and extending over the second portion of the field-reducing dielectric layer, Forming the gate electrode, The source region having the second conductivity type is formed within the body region, The drain region having the second conductivity type is formed within the drift region, Methods that include...

14. A method according to claim 13, wherein the center of the second portion substantially corresponds to the position in the drift region, and the center is located between the first portion and the third portion of the gate electrode.

15. A method according to claim 13, wherein the width of the second portion of the gate electrode is at least twice the thickness of the gate electrode, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.

16. A method according to claim 13, wherein the width of the second portion of the gate electrode is greater than 300 nanometers, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.

17. The method according to claim 13, wherein the second portion of the gate electrode is degenerately doped, or 1 × 10 １９ / cm ３ A method having a larger active mean dopant density.

18. The method according to claim 13, The further includes forming a back gate region in the body region, wherein the back gate region has the first conductivity type, and the back gate region is electrically insulated and separated from the source region. method.

19. A method according to claim 18, wherein forming the back gate region includes forming the second portion of the gate electrode.

20. It is a semiconductor device, A substrate including a p-type body region and an n-type drift region, A first dielectric layer on the substrate, the first dielectric layer extending over the p-type body region and the n-type drift region, A second dielectric layer on the n-type drift region, which is thicker than the first dielectric layer and contacts the first dielectric layer laterally at a certain position in the n-type drift region, A gate electrode on the first dielectric layer and the second dielectric layer, wherein the gate electrode is An n-type first portion extending over the p-type body region and the first portion of the n-type drift region, A second portion of the p type abuts against the first portion of the n type and extends over the second portion of the n type drift region and the first portion of the second dielectric layer, A third n-type portion abuts against the second p-type portion and extends over the second portion of the second dielectric layer, The aforementioned shutdown terminal, An n-type source region is arranged in the aforementioned p-type body region, An n-type drain region is arranged in the aforementioned n-type drift region, Semiconductor devices, including those mentioned above.

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