Low-temperature selective epitaxy contact approach

Abstract

A semiconductor device and a method for manufacturing the same are provided. The method includes the steps of epitaxially growing a doped crystalline silicon-containing layer on source / drain features and growing a doped amorphous silicon-containing layer on the field region of the semiconductor layer. A trench is formed in the semiconductor layer, and the trench exposes the source / drain features. The method further includes the steps of epitaxially growing an undoped crystalline silicon-containing capping layer on the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer on the doped silicon-containing amorphous layer. The method further includes the step of selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer from the silicon-containing crystalline capping layer. The method further includes the step of removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the interests of U.S. Provisional Patent Application No. 63 / 462,695, filed on 28 April 2023, which is incorporated herein by reference in its entirety.

[0002] This disclosure generally relates to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, this disclosure relates to low-temperature selective deposition of epitaxial silicon-containing films. [Background technology]

[0003] A typical selective epitaxy process involves a deposition reaction and an etching reaction. The deposition reaction forms an epitaxial layer on the single-crystal surface of the substrate, and a polycrystalline and / or amorphous layer on a non-single-crystal surface, such as a patterned dielectric layer deposited on the substrate. The etching reaction removes the epitaxial layer and the polycrystalline and / or amorphous layer at different rates, resulting in a net selective process where the deposition of epitaxial material can be increased, while the deposition of polycrystalline and / or amorphous material can be limited or eliminated.

[0004] As the critical dimensions of devices continue to shrink, selective epitaxial deposition methods require lower processing temperatures (e.g., below approximately 500°C). Unfortunately, typical etching gases cannot provide a suitable selection window between the epitaxial layer and the polycrystalline and / or amorphous layer at low processing temperatures. In addition, current periodic deposition / etching processes are complex, difficult to maintain, and may have low throughput.

[0005] For the reasons stated above, there is a need for selective epitaxial processes that can be performed at lower temperatures. [Overview of the Initiative]

[0006] This disclosure generally relates to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, this disclosure relates to low-temperature selective deposition of epitaxial silicon-containing films.

[0007] In one embodiment, a method for forming a semiconductor device is provided. The method includes the steps of epitaxially growing a doped crystalline silicon-containing layer on source / drain features and growing a doped amorphous silicon-containing layer on the field region of the semiconductor layer. A trench is formed in the semiconductor layer, and the trench exposes the source / drain features. The method further includes the steps of epitaxially growing an undoped crystalline silicon-containing capping layer on the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer on the doped silicon-containing amorphous layer. The method further includes the step of selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer from the silicon-containing crystalline capping layer. The method further includes the step of removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

[0008] Embodiments may include one or more of the following: The method further includes the step of forming a metallic silicon compound layer from a doped silicon-containing crystalline layer. The method further includes the step of forming a metal-filled layer in a trench, the metal-filled layer being formed on top of the metallic silicon compound layer. The steps of epitaxially growing the doped crystalline silicon-containing layer and epitaxially growing the undoped crystalline silicon-containing capping layer are performed at a temperature below the thermal budget of the semiconductor device, which is 500°C or less. The steps of epitaxially growing the doped silicon-containing crystalline layer, epitaxially growing the undoped crystalline silicon-containing capping layer, and selectively removing the doped amorphous silicon-containing layer are performed in a processing area of ​​a processing chamber. The step of selectively removing the doped amorphous silicon-containing layer is performed in a second processing area of ​​a second processing chamber, and the semiconductor device is transferred from one processing area to the second processing area without breaking the vacuum. The method further includes the step of forming a back-side power rail on the back side of a semiconductor device, the back-side power rail being electrically coupled to a metal-filled layer.

[0009] In another embodiment, a method for forming a semiconductor device is provided. This method includes the steps of epitaxially growing a doped crystalline silicon-containing layer on source / drain features and growing a doped amorphous silicon-containing layer on the field region of the semiconductor layer. Trenches are formed in the semiconductor layer, and the trenches expose the source / drain features. The epitaxial growth step includes introducing a higher-order silane precursor gas and an n-type dopant precursor gas into the processing region of a process chamber, wherein the higher-order silane precursor gas has the chemical formula Si x H (2x+2)The formula has the following characteristics, where x is 2 or greater. The method further includes the steps of epitaxially growing an undoped crystalline silicon-containing capping layer on a doped crystalline silicon-containing layer, including introducing a higher-order silane precursor gas into a processing region, and growing an undoped amorphous silicon-containing layer on a doped amorphous silicon-containing layer. The method further includes the steps of selectively removing a doped amorphous silicon-containing layer and an undoped amorphous silicon-containing layer from an undoped crystalline silicon-containing capping layer, including flowing an etching gas containing Cl2, GeCl2, GeCl4, GeH4, or a combination thereof.

[0010] Embodiments may include one or more of the following: The method further includes the step of removing an undoped crystalline silicon-containing capping layer to expose a doped silicon-containing crystalline layer. The higher-order silane precursor gas is selected from trisilane, tetrasilane, or a combination thereof. The n-type dopant precursor gas is a phosphorus-containing precursor gas, an antimony-containing precursor gas, an arsenic-containing precursor gas, or a combination thereof. The etching gas does not contain hydrogen chloride (HCl) gas. The steps of epitaxially growing the doped crystalline silicon-containing layer and epitaxially growing the undoped crystalline silicon-containing capping layer are performed at a temperature below the thermal budget of the semiconductor device. This temperature is 500°C or less. The trenches formed in the semiconductor layer are formed on the back side of the semiconductor device.

[0011] In yet another embodiment, a method for forming a semiconductor device is provided. The method includes the step of providing a device structure in which trenches are formed in a semiconductor layer. The trenches expose source / drain features from the back side of the device structure, and the semiconductor layer is formed on a device substrate. The method further includes the step of performing a first epitaxial deposition process to grow a doped crystalline silicon layer on the source / drain features and a doped amorphous silicon layer on the field region of the semiconductor layer. The method further includes the step of performing a second epitaxial deposition process to grow an undoped crystalline silicon capping layer on the doped crystalline silicon layer and an undoped amorphous silicon layer on the doped amorphous silicon layer. The method further includes the step of performing a selective etching process to remove the undoped amorphous silicon layer and the doped amorphous silicon layer from the crystalline silicon capping layer.

[0012] The embodiments may include one or more of the following: A first epitaxial deposition process includes the step of introducing a deposition gas containing a higher-order silane precursor gas and / or a chlorosilane precursor gas and a dopant precursor gas containing an n-type dopant precursor gas into a processing area of ​​a process chamber, wherein the higher-order silane precursor gas is Si x H (2x+2) The chemical formula is as follows, where x is 2 or greater. The method further includes a step of purging the treatment area after the first epitaxial deposition process and before the second epitaxial deposition process. The second epitaxial deposition process includes a step of introducing a deposition gas containing a higher-order silane precursor gas.

[0013] In another embodiment, a non-temporary computer-readable medium, when executed by a processor, stores instructions that cause a process to perform the operation of the above-described apparatus and / or method.

[0014] To better understand the above features of the present disclosure, a more specific description of the present disclosure briefly summarized above can be obtained by referring to the embodiments shown in part in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be regarded as limiting the scope, and other equally valid embodiments may be recognized.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a schematic top view of an example of a multi-chamber processing tool according to one or more embodiments of the present disclosure. [Figure 2A] FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 2B] FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3A] FIG. 4 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3B] FIG. 5 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3C] FIG. 6 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3D] FIG. 7 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3E] FIG. 8 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3F] FIG. 9 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3G] FIG. 10 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3H] FIG. 11 is a diagram of a step of manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

Best Mode for Carrying Out the Invention

[0016] For ease of understanding, where possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further description.

[0017] The present disclosure generally relates to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the present disclosure relates to the low-temperature selective deposition of epitaxial silicon-containing films.

[0018] A power delivery network (PDN) supplies power to active devices on a semiconductor device. Conventional PDNs include power rails and are designed to supply power through the front side of a semiconductor structure. For example, conventional integrated circuits (ICs) are constructed in a stacked orientation and have bottom-layer transistors, interconnects above the transistors to provide connectivity to the transistors, and power rails also disposed above the transistors. As the IC continues to shrink, the power rails also shrink, resulting in an increased voltage drop between the power rails and potentially increased power consumption of the IC. A backside PDN moves the power to the backside of the semiconductor device, thereby allowing only signals to be carried by the front side. The manufacture of a backside PDN involves, among other things, providing power rails on the backside of a semiconductor structure that already includes, for example, FinFET transistors in addition to an interconnect structure on the front side of the semiconductor structure (which may also include power rails). The presence of transistors and interconnects already formed on the front side of the semiconductor structure presents numerous manufacturing challenges, one of which is the thermal budget limitation imposed by the transistors and interconnects already formed on the front side of the semiconductor structure.

[0019] Conventional selective epitaxial deposition processes struggle to achieve selective epitaxial deposition at the low temperatures required (e.g., below 450°C) due to limitations in the thermal budget for the back-side contacts of the logic. The deposition precursors used in conventional selective epitaxial deposition processes typically require high temperatures, such as above 550°C, for sufficient growth rates. Furthermore, hydrogen chloride (HCl), the etching gas used in conventional selective epitaxial deposition, does not etch actively at low temperatures. In addition, achieving high active dopant concentrations in epitaxial films deposited at low temperatures is more difficult.

[0020] Embodiments of this disclosure provide methods, systems, and structures for achieving selective epitaxial deposition at low temperatures, for example, below 500°C or below 450°C. Embodiments of this disclosure are suitable for back-side contacts of logic and other applications involving low-temperature, selective, and highly active dopant epitaxial deposition, thus enabling the formation of back-side PDNs. One or more embodiments, which can be combined with other embodiments, provide a method for low-temperature epitaxial deposition. This method is performed at temperatures below 450°C. This method involves the use of a higher-order silane precursor and / or a higher-order chlorosilane precursor and an n-type dopant precursor selected from an antimony-containing precursor, a phosphorus-containing precursor, an arsenic-containing precursor, or a combination thereof.

[0021] Figure 1 shows a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 can be used for low-temperature selective epitaxial deposition of silicon-containing epitaxial films without breaking the vacuum, according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having transfer robots 112, 114 respectively, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100, for example, the atmospheric environment that may be present inside the fab. The substrate can be processed in various chambers maintained at low pressure (e.g., approximately 300 Torr or less) or in a vacuum environment, without disrupting the low-pressure or vacuum environment between the various processes performed on the substrate within the processing system 100, and can be transferred between these chambers. Thus, the processing system 100 can provide an integrated solution for processing substrates.

[0022] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems, commercially available from Applied Materials, Inc. in Santa Clara, California. It is intended that other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0023] In the example illustrated in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 for facilitating the transfer of substrates. The docking station 132 is adapted to receive one or more forward-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 located at one end of the respective factory interface robot 134, adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0024] The load lock chambers 104 and 106 have ports 140 and 142, respectively, connected to the factory interface 102, and ports 144 and 146, respectively, connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150, respectively, connected to the holding chambers 116 and 118, and ports 152 and 154, respectively, connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158, respectively, connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166, respectively, connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 can be slit valve openings having slit valves for transferring substrates through them by, for example, transfer robots 112 and 114, and for sealing between each chamber to prevent gas from passing between them. Generally, each port is open for transferring substrates through it; otherwise, the port is closed.

[0025] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluid-coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and fluid-coupled conduits to the various chambers. In operation, the factory interface robot 134 transfers the substrate from the FOUP 136 through port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, exhausting the load lock chamber 104 or 106 facilitates, for example, the transfer of substrates between the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0026] With the substrates in the load lock chamber 104 or 106 evacuated, the transfer robot 112 transfers the substrates from the load lock chamber 104 or 106 to the transfer chamber 108 through port 144 or 146. The transfer robot 112 can then transfer the substrates to and / or between the processing chambers 120 or 122 through their respective ports 152 or 154 for processing, and to the holding chambers 116 or 118 through their respective ports 148 or 150 for holding, awaiting further transfer. Similarly, the transfer robot 114 can access the substrates in the holding chamber 116 or 118 through port 156 or 158, and transfer the substrates to and / or between the processing chambers 124, 126, 128, or 130 through their respective ports 160, 162, 164, or 166 for processing, and to the holding chambers 116 or 118 through their respective ports 156 or 158 for holding, awaiting further transfer. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0027] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing the substrate. In some examples, processing chamber 120 can perform an etching process, processing chamber 122 can perform a cleaning process, and processing chambers 124, 126, 128, and 130 can perform their respective growth processes. Processing chamber 116 may be a Preclean XT chamber available from Applied Materials, Inc. Processing chamber 120 may be a SiCoNi® Pre-clean chamber or an alternative available from Applied Materials, Santa Clara, California. Processing chamber 122 may be a Selectra® Etch chamber available from Applied Materials, Santa Clara, California. Processing chambers 124, 126, 128, or 130 may be Centura® Epi chambers, Volta® CVD / ALD chambers, or a combination thereof, all of which are available from Applied Materials in Santa Clara, California.

[0028] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. In operation, the system controller 168 enables data acquisition and feedback from each chamber and adjusts the performance of the processing system 100.

[0029] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172, non-temporary computer-readable medium, or machine-readable storage device is accessible by the CPU 170 and may be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The support circuitry 174 is coupled to the CPU 170 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein may generally be implemented under the control of the CPU 170, for example, by the CPU 170 executing computer instruction code stored in memory 172 (or memory of a particular processing chamber) as software routines. That is, a computer program product is tangibly embodied on memory 172 (or non-temporary computer-readable medium or machine-readable storage device). When computer instruction code is executed by CPU 170, CPU 170 controls the chamber and executes the process according to various methods.

[0030] Instructions in instruction memory 172 are in the form of a program product, such as a program that implements the methods of the present disclosure. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program in the program product defines the functionality of the embodiments (including the methods of the present specification). Thus, a computer-readable storage medium is an embodiment of the present disclosure if it carries computer-readable instructions that direct the functionality of the methods of the present specification. The system controller 168 is configured to execute methods such as a portion of method 200 stored in memory 172.

[0031] In certain embodiments, at least one of the processing chambers 120 and 116 is a pre-cleaning chamber configured to perform the pre-treatment process of operation 220; at least one of the processing chambers 124, 126, 128, and 130 is an EPI chamber configured to perform at least one of the epitaxial deposition processes of operations 230 and 240 of method 200 and the selective removal process of operation 250; and another of the processing chambers 124, 126, 128, and 130 is an etching chamber configured to perform the undoped silicon decapping etching of operation 260 of method 200 without breaking the vacuum between any of operations 210 to 260.

[0032] In operation, the substrate with the feature formed inside may be transferred to a first processing chamber, which is one of processing chambers 116 and 120, where the feature is exposed to a pretreatment process to remove, for example, native oxides formed on the feature. The substrate may then be transferred without breaking the vacuum to a second processing chamber, which is one of processing chambers 124, 126, 128, and 130, where a doped crystalline layer, for example, a doped crystalline silicon-containing layer, is deposited on the feature. The substrate may then be transferred without breaking the vacuum to a third processing chamber, which is one of processing chambers 124, 126, 128, and 130, where an undoped silicon-containing crystalline capping layer is grown on the doped crystalline layer.

[0033] Other processing systems may have different configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device within the processing system.

[0034] Figures 2A to 2B show flowcharts of a method 200 for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Figures 3A to 3H show diagrams of various stages in manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Although Figures 3A to 3H are described in relation to method 200, it should be understood that the structures disclosed in Figures 3A to 3H are not limited to method 200 and may instead exist independently as structures separate from method 200. Similarly, although method 200 is described in relation to Figures 3A to 3H, it should be understood that method 200 is not limited to the structures disclosed in Figures 3A to 3H and may instead exist independently as structures separate from those disclosed in Figures 3A to 3H. Figures 3A to 3H show only partial schematic diagrams of a semiconductor device 300, and it should be understood that the semiconductor device 300 may include any number of transistor sections and additional materials having aspects not shown in the figures. While Method 200 shown in Figures 2A and 2B is described step by step, it should be noted that other process sequences, including one or more operations that are omitted and / or added, and / or rearranged in a different preferred order, are also within the scope of the embodiments of this disclosure provided herein.

[0035] Referring to Figure 2A, operation 210 provides a semiconductor device (or semiconductor structure) 300 with features formed internally. Figure 3A shows a cross-sectional view of the semiconductor device 300 during an intermediate stage of manufacturing corresponding to operation 210. In some embodiments, the semiconductor device 300 is part of an IC chip, a system-on-a-chip (SoC), or a part thereof, and includes a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. Figures 3A–3H are simplified for clarity to better understand embodiments of the present disclosure. Further features can be added to the semiconductor device 300, and in other embodiments of the semiconductor device 300, some of the features described below can be replaced, modified, or deleted.

[0036] The semiconductor device 300 includes a device substrate 310 on which one or more layers, for example, a semiconductor layer 320 as shown in Figure 3A, is formed. Trenches 322 are formed in the semiconductor layer. The trenches 322 expose source / drain features 330 from the back side 302 of the semiconductor device 300. The device substrate 310 may be a bulk semiconductor substrate, a semiconductor on-insulator (SOI) substrate, or include these, and may be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. In some embodiments, the semiconductor material of the device substrate 310 may include elemental semiconductors such as silicon (Si) or germanium (Ge), compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimony, alloy semiconductors including SiGe, GaAsP, AlInAs, GaInAs, GaInP, and / or GaInAsP, and combinations thereof. The device substrate 310 may include additional materials, such as a silicon compound layer, a metallic silicon compound layer, a metal layer, a dielectric layer, an etching stop layer, an interlayer dielectric, or a combination thereof.

[0037] The device substrate 310 may further include integrated circuit devices (not shown). For example, the device substrate 310 may further include FinFET transistors in addition to interconnect structures. As those skilled in the art will recognize, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, or combinations thereof, can be formed in and / or on the device substrate 310 to generate the structural and functional requirements for the design of the resulting semiconductor device 300.

[0038] The device substrate 310 has a front side 310f (also called the front surface) and a back side 310b (also called the back surface) opposite the front side 310f. Note that the terms “front side” and “back side” of the device substrate 310 refer to the orientation of the device substrate 310 as shown in the illustration. The semiconductor layer 320 is formed on the front side 310f of the device substrate 310. The semiconductor layer 320 may include multiple layers. The semiconductor layer 320 includes a top surface 320u or a field region. In some embodiments, the semiconductor layer 320 is made of a low dielectric constant (low k) dielectric (SiCOH), silicon oxide, silicon dioxide (SiO2), silicon nitride (Si x N y ), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), combinations thereof, or multilayers thereof, are dielectric materials or dielectric materials. In one example, the semiconductor layer 320 is silicon oxide or contains silicon oxide. In another example, the semiconductor layer 320 is silicon nitride or contains silicon nitride. In some embodiments, the semiconductor layer 320 is composed essentially of silicon oxide. Note that the above descriptor, for example, silicon oxide, should not be interpreted as disclosing any particular stoichiometric ratio. Therefore, “silicon oxide,” etc., will be understood by those skilled in the art as a material composed essentially of silicon and oxygen without disclosing any particular stoichiometric ratio.

[0039] The semiconductor layer 320 is patterned to form a trench 322. The trench exposes a source / drain feature 330. The trench 322 may also be a high aspect ratio (HAR) feature. In some embodiments, the trench 322 extends from the top surface 320u of the semiconductor layer 320 toward the front surface 310f of the device substrate 310. The trench 322 includes a sidewall 322s. In some embodiments, the sidewall 322s is tapered. The sidewall 322s may be defined by the semiconductor layer 320, and the bottom of the trench 322 may be defined by the source / drain feature 330. The source / drain feature 330 may be formed from an epitaxially grown semiconductor material. The semiconductor material may be or include silicon, silicon germanium, silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. The semiconductor material may be doped, for example, with an n-type dopant. The epitaxial source / drain feature 330 may be doped by insitu doping during epitaxial growth or by injecting a dopant into the epitaxial source / drain feature 330 after epitaxial growth. In some embodiments, the source / drain feature 330 may be formed from phosphorus-doped silicon or p-doped silicon (Si:P). The source / drain feature 330 has an upper surface 330u exposed by a trench 322.

[0040] In some embodiments, the semiconductor device 300 has native oxides or other contaminants formed on exposed surfaces, e.g., the top surface 320u, the sidewall surfaces 322s of the trench 322, and / or the top surface 330u of the source / drain feature 330. The semiconductor device 300 may be exposed to the atmosphere before or during processing, which may cause native oxides to form on the exposed surfaces. For example, if a vacuum break occurs before or during method 200, the vacuum break may cause native oxides to form on the exposed silicon surface. In addition, other processes performed before or during method 200 may cause further contaminants or residues to form on the exposed surfaces.

[0041] Referring to Figure 2A, optionally, in operation 220, the semiconductor device 300 is exposed to a pretreatment process. Figure 3B shows a cross-sectional view of the semiconductor device 300 during the intermediate manufacturing stage corresponding to operation 220. The pretreatment process of operation 220 may include one or more native oxide removal processes to remove native oxides (if present). The pretreatment process of operation 220 may include another dry cleaning process. Any suitable dry cleaning process may be performed. The dry cleaning process may include plasma etching processes such as a two-step dry chemical cleaning process using NF3 and NH3, an H2 and O2 plasma etching process, an H2 plasma etching process, an NF3 / H2 plasma etching process, a remote plasma etching process including one or more of H2, H2O, NH3, and argon, or a combination thereof.

[0042] In one or more embodiments, which can be combined with other embodiments, the semiconductor device 300 is exposed to a dry cleaning process and / or degassing process prior to operation 230. The dry cleaning process may be used to remove oxides from the exposed surfaces of the semiconductor device 300. For example, if the semiconductor device 300 contains silicon, Applied Materials' SICONI® cleaning process may be performed to remove oxides from the exposed surfaces of the semiconductor layer 320 and source / drain feature 330. The SICONI® cleaning process removes native oxides through a low-temperature, two-step dry chemical cleaning process using NF3 and NH3. The cleaning process can be performed in a processing chamber located on a cluster tool, for example, chamber 116 and / or processing chamber 120 of processing system 100 (see Figure 1). Exemplary pre-cleaning chambers in which the dry cleaning process of operation 220 may be performed include the SICONI® cleaning chamber and Preclean XT chamber, available from Applied Materials, Inc., Santa Clara, California.

[0043] In one or more embodiments that can be combined with other embodiments, the pretreatment process is a plasma treatment process. The plasma treatment process may be an inductively coupled plasma (ICP) process or a capacitively coupled plasma (CCP) process. The plasma may be formed ex-situ in a remote plasma source (RPS). The plasma may be formed in-situ, for example, a direct plasma generated within a treatment area. In one or more embodiments that can be combined with other embodiments, the plasma treatment process includes exposing the semiconductor device 300 to a plasma formed from a process gas containing a hydrogen-containing gas. In one or more embodiments that can be combined with other embodiments, the plasma treatment process includes exposing the semiconductor device 300 to a plasma formed from a process gas containing both a hydrogen-containing gas and an oxygen-containing gas. In one example, the plasma treatment process includes exposing a trench 322 to an ICP formed from a process gas containing a hydrogen-containing gas and an oxygen-containing gas. The process gas may further include inert gases, such as argon (Ar), helium (He), krypton (Kr), or combinations thereof. In one or more embodiments that can be combined with other embodiments, the plasma treatment process includes exposing the feature to a plasma formed from a process gas containing one or more of H2, O2, Ar, or combinations thereof. In one or more embodiments that can be combined with other embodiments, the plasma treatment process includes exposing the feature to a plasma formed from a process gas containing one or more of NF3, H2, or combinations thereof. In one or more embodiments that can be combined with other embodiments, the plasma treatment process includes exposing the feature to a plasma formed from a process gas containing one or more of H2, H2O, NH3, Ar, or combinations thereof. In one or more embodiments that can be combined with other embodiments, the plasma treatment process may include exposing the feature to hydrogen and oxygen plasma treatment.Hydrogen and oxygen plasma treatment may include saturated conformation treatments, which may involve longer immersion times and / or higher reactant treatments, to provide better metal filling of subsequent features.

[0044] Referring to Figure 2A, in operation 230, a doped crystalline silicon-containing layer 340 is epitaxially grown on the source / drain feature 330, and a doped amorphous silicon-containing layer 342 is formed on the upper surface 320u of the semiconductor layer 320. Figure 3C shows a cross-sectional view of the semiconductor device 300 during an intermediate stage of manufacturing corresponding to operation 230. The doped crystalline silicon-containing layer 340 and the doped amorphous silicon-containing layer 342 may be doped with an n-type dopant. In some embodiments, the n-type dopant is phosphorus. The doped crystalline silicon-containing layer 340 and the doped amorphous silicon-containing layer 342 are formed on the underlying material during the same deposition process. For example, the doped crystalline silicon-containing layer 340 is epitaxially grown on the upper surface 330u of the source / drain feature 330, while the doped amorphous silicon-containing layer 342 is formed on the upper surface 320u of the semiconductor layer 320.

[0045] In some embodiments, the doped crystalline silicon-containing layer 340 has a doping ratio of 1.4E20 atoms / cm², depending on the target conductivity of the doped crystalline silicon-containing layer 340. -3 The device is doped with an n-type dopant having an active dopant concentration exceeding, for example, in the range of approximately 2E20 to approximately 1E22, or in the range of approximately 5E20 to approximately 5E21.

[0046] It should be noted that the doped amorphous silicon-containing layer 342 formed on the upper surface 320u is an undesirable deposition. During conventional epitaxial deposition performed at higher temperatures, the doped crystalline silicon-containing layer 340 is grown while the doped amorphous silicon-containing layer 342 is simultaneously removed using an etching solution such as HCl. However, due to thermal budget limitations that may exist when method 200 is performed, the low-temperature epitaxial deposition process described is performed at a temperature where the etching rate of HCl is very low. Therefore, the undesirable deposition of the doped amorphous silicon-containing layer 342 occurs on the upper surface 320u.

[0047] The epitaxial growth process of operation 230 is typically performed at lower temperatures, e.g., below 500°C, below 480°C, below 450°C, or below 400°C. The epitaxial growth process of operation 230 further includes the step of forming a doped amorphous silicon-containing layer 342 by introducing higher silanes and / or higher chlorosilanes, as well as n-type dopants, into the processing area of ​​the process chamber while epitaxially growing a doped crystalline silicon-containing layer 340 on the upper surface 330u of the source / drain feature 330. During the epitaxial growth process of operation 230, the step of positioning the substrate in the processing area of ​​the processing chamber may include adjusting one or more reactor conditions, such as temperature, pressure, and / or carrier gas (e.g., Ar, N2, H2, or He) flow rate, to conditions suitable for epitaxial film formation. The epitaxial deposition process of operation 230 can be performed in any of the processing chambers located on the cluster tool, for example, processing chambers 124, 126, 128, and 130 of the processing system 100 (see Figure 1).

[0048] During the epitaxial growth process of operation 230, the semiconductor device 300 is heated to a temperature below the thermal budget of the semiconductor device 300, for example, a temperature of 500°C or less or a temperature of 480°C or less. In at least one embodiment, the temperature in the processing chamber can be adjusted so that the reaction region formed on or near the exposed surface of the semiconductor device 300, or the surface of the semiconductor device 300, is about 480°C or less, or about 480°C or less, or about 450°C or less, or about 400°C or less, or about 350°C or less. In one example, the substrate is heated to a temperature in the range of about 350°C to about 500°C, or about 350°C to about 480°C, or about 350°C to about 400°C, or about 400°C to about 480°C. While not bound by theory, in some embodiments where Si:P is formed, Si:P deposition at temperatures below 350°C results in very slow growth rates, and deposition at temperatures above 480°C may affect the thermal budget of other materials formed on the semiconductor device 300. By heating the substrate to the lowest temperature sufficient to thermally decompose the process reagents, it is possible to epitaxially deposit layers on the substrate while minimizing the thermal budget of the final device. The pressure in the processing chamber can be adjusted so that the reaction region pressure is in the range of about 1 to about 760 Torr, or about 1 Torr to about 600 Torr, or about 10 Torr to about 300 Torr, or about 10 Torr to about 100 Torr. In some embodiments, a carrier gas (e.g., nitrogen) can be flowed into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters / min). The nitrogen remains inert during the low-temperature deposition process. Therefore, nitrogen is not incorporated into the deposited layer during the low-temperature epitaxial growth process of operation 230. Furthermore, nitrogen carrier gases do not form hydrogen termination surfaces like hydrogen carrier gases do. However, it will be understood that in some embodiments, different carrier / diluent gases, such as inert carrier gases like argon or helium, may be used, different flow rates may be used, or such gases may be omitted.

[0049] The epitaxial growth process of operation 230 further includes the step of introducing a deposition gas containing a higher-order silane precursor gas and / or a chlorosilane precursor gas and a dopant precursor gas containing an n-type dopant precursor gas into the processing region of the process chamber. The higher-order silane includes silane of the chemical formula Si x H (2x+2) , where x is 2 or more, for example, x is 2, 3, 4, 5, 6, 7, 8, or more. Examples of higher-order silanes include disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ), or other higher-order silanes. The chlorosilane includes chlorosilane of the chemical formula Cl y Si x H (2x+2-y) , where y is 1 or more, 2 or more, 3 or more, or 5 or more, and x is 1 or more, or 2 or more, or 3 or more. In one example, y is 5 to 8 and x is 2 to 3. In at least one embodiment, the second chlorosilane precursor gas includes, consists of, or consists essentially of chlorosilane (ClSiH3), dichlorosilane (Cl2SiH2), trichlorosilane (Cl3SiH), hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof. In one example, the deposition gas is introduced into the processing region at a flow rate in the range of about 1 sccm to about 500 sccm, or in the range of about 10 sccm to about 400 sccm, or in the range of about 50 sccm to about 300 sccm, or in the range of about 100 sccm to about 200 sccm.

[0050] The epitaxial growth process of operation 230 further includes the step of introducing an n-type dopant precursor gas into the processing area. In at least one embodiment, the n-type dopant precursor includes, is composed of, or is essentially composed of, a phosphorus-containing precursor, an antimony precursor, an arsenic-containing precursor, or a combination thereof. In at least one embodiment, the antimony-containing precursor includes one or a combination thereof from stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenyl antimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. In at least one embodiment, the phosphorus-containing precursor includes one or a combination thereof from phosphine and alkylphosphine. Suitable alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P), tert-butylphosphine, and diethylphosphine ((CH3CH2)2PH). In at least one particular embodiment, a phosphine is used. In at least one embodiment, the arsenic-containing precursor is arsine (AsH3), arsenic halogenated compounds, trimethylarsenide, and silylarsine [(H3Si)] 3-x AsR x ](In the equation, x = 0, 1, 2, R x The n-type dopant precursor gas may have a flow rate in the range of about 0.1 sccm to 10,000 sccm, or about 100 sccm to about 5,000 sccm, or about 500 to about 3,000 sccm.

[0051] In some embodiments where the epitaxial layer is a silicon germanium (SiGe) layer, the deposit gas further contains a germanium source. Suitable germanium sources include Germanine (GeH4) and higher-order Germanine. Higher-order Germanine includes empirically formulated Ge x H (2x+2)The compounds include those in the formula where x is 2 or greater, for example, x is 2, 3, 4 or more. Examples of higher-order Germanic compounds include sigermann (Ge2H6), trigermann (Ge3H8), and tetragermann (Ge4H 10 ) and others are included.

[0052] The deposition precursor gas and the n-type dopant precursor gas are intended to be introduced simultaneously, substantially simultaneously, or in any desired order. In at least one embodiment, the deposition precursor gas and the n-type dopant precursor gas are co-circulated into the process area simultaneously. In one embodiment, at least two of the precursor gases are mixed before being supplied to the processing area. In another embodiment, at least two of the precursor gases are supplied separately to the processing area and mixed within the processing area.

[0053] In some embodiments where operations 230 and 240 are optionally performed in the same processing area, a purging process is performed after operation 230 and before operation 240 to remove any residual higher-order silane precursor gas, n-type dopant precursor gas, and byproducts from the processing area. For example, excess higher-order silane precursor gas, n-type dopant precursor gas, and reaction byproducts (if any) can be removed from the surface of the semiconductor device 300, for example, by pumping with an inert gas. In some embodiments where an inert carrier gas is introduced into the processing area along with the higher-order silane precursor gas and / or n-type dopant precursor gas, the flow of the higher-order silane precursor gas and / or n-type dopant precursor gas can be stopped while the inert carrier gas continues to flow to purge the processing area. In other embodiments, the flow of the n-type dopant precursor gas is stopped while the higher-order silane precursor gas continues to flow to purge the processing area. In some embodiments, the purging process may include a purge cycle in which the processing area is purged for a period of less than approximately 5 seconds, less than approximately 3 seconds, or even less than approximately 2 seconds. For example, excess gas-phase reactants such as excess higher-order silane precursor gas, n-type dopant precursor gas, and possible reaction byproducts can be removed with the help of a vacuum generated by a pumping system that is fluidly coupled to the processing area.

[0054] Referring to Figure 2A, in operation 240, an undoped crystalline silicon-containing capping layer 350 is epitaxially grown on or directly above the upper surface 340u of the doped crystalline silicon-containing layer 340, and an undoped amorphous silicon-containing layer 360 is formed on or directly above the upper surface 342u of the doped amorphous silicon-containing layer 342. Figure 3C shows a cross-sectional view of the semiconductor device 300 during the intermediate manufacturing stage corresponding to operation 240. In this disclosure, "undoped" means that the undoped crystalline silicon-containing capping layer 350 and the undoped amorphous silicon-containing layer 360 are either unintentionally doped or doped with a very low dopant concentration, and therefore do not contain enough carriers (electrons or holes) to be conductive under a typical electric field. The undoped crystalline silicon-containing capping layer 350 protects the underlying doped crystalline silicon-containing layer 340 during a subsequent selective etching process performed during operation 250 to remove the doped amorphous layer and the undoped amorphous layer.

[0055] During the same epitaxial deposition process, an undoped crystalline silicon-containing capping layer 350 is grown on or directly above the upper surface 340u of the doped crystalline silicon-containing layer 340, and an undoped amorphous silicon-containing layer 360 is grown on or directly above the upper surface 342u of the doped amorphous silicon-containing layer 342. The epitaxial growth process of operation 240 can be carried out using a higher-order silane precursor gas and an optional carrier gas, as described above. The higher-order silane precursor gas and the optional carrier gas may be the same gases used during the epitaxial growth process of operation 230. The epitaxial growth process of operation 240 can be carried out using the same or similar processing conditions, for example, the same or similar temperature and pressure used during the epitaxial deposition process of operation 230. During the subsequent selective removal process of operation 250, the undoped crystalline silicon-containing capping layer 350 is grown to a thickness such that at least a portion of the undoped crystalline silicon-containing capping layer 350 remains on top of the doped crystalline silicon-containing layer 340.

[0056] The epitaxial deposition process of operation 240 can be performed in any of the processing chambers located on the cluster tool, for example, in processing chambers 124, 126, 128, and 130 of processing system 100 (see Figure 1). In some embodiments, operations 230 and 240 are performed in the same processing chamber. In other embodiments, operations 230 and 240 are performed in different processing chambers in the same chamber.

[0057] Referring to Figure 2B, in operation 250, the doped amorphous silicon-containing layer 342 and the undoped amorphous silicon-containing layer 360 are selectively removed, while the undoped crystalline silicon-containing capping layer 350 is partially removed. Figure 3E shows a cross-sectional view of the semiconductor device 300 during the intermediate stage of manufacturing corresponding to operation 250. During operation 250, the etching process is selective for the amorphous materials (such as doped amorphous silicon and undoped amorphous silicon) of the undoped amorphous silicon-containing layer 360 and the doped amorphous silicon-containing layer 342, and is adjusted so that there is no etching or minimal etching of the undoped crystalline silicon-containing capping layer 350 and the semiconductor layer 320. As a result, the undoped amorphous silicon-containing layer 360 and the doped amorphous silicon-containing layer 342 are removed, exposing the upper surface 320u of the semiconductor layer 320, while the doped crystalline silicon-containing layer 340 remains protected by at least a portion of the undoped crystalline silicon-containing capping layer 350. The etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching method. In some embodiments, the etching process of operation 250 is self-aligning, meaning that an etching mask is not required. Rather, the etching process of operation 250 depends on the material etching selectivity of the doped amorphous silicon-containing layer 342 and the undoped amorphous silicon-containing layer 360 relative to the undoped crystalline silicon-containing capping layer 350.

[0058] During the etching process of operation 250, an etching gas is introduced into the processing area to selectively remove the amorphous silicon-containing layer from the crystalline silicon-containing layer. In some embodiments, the etching gas is selected from chlorine, Germanium, germanium chloride, or a combination thereof. In some embodiments, the etching gas is selected from Cl2, GeCl2, GeCl4, GeH4, or a combination thereof. In some embodiments, the etching gas does not contain hydrogen chloride (HCl). In this disclosure, the hydrogen chloride (HCl)-free etching gas includes embodiments in which the etching gas unintentionally contains HCl, or otherwise contains a very low concentration of HCl, so that the HCl gas does not etch under typical etching conditions. The etching gas may be introduced into the processing area at a flow rate in the range of about 1 sccm to about 1,000 sccm, or in the range of about 1 sccm to about 200 sccm, or in the range of about 1 sccm to about 100 sccm.

[0059] In some embodiments, the doped amorphous silicon-containing layer 342 and the undoped amorphous silicon-containing layer 360 have etching selectivity over the undoped crystalline silicon-containing capping layer 350 (i.e., the etching rate of the amorphous silicon-containing material is faster than that of the silicon-containing crystalline material). In some embodiments, the etching selectivity (i.e., the ratio of the etching rate of the amorphous silicon-containing material to that of the silicon-containing crystalline material) is in the range of about 100:1 to about 3000:1, 300:1 to about 3000:1, or about 300:1 to about 2000:1, or about 300:1 to about 1500:1.

[0060] The selective removal process of operation 250 can be performed in any of the processing chambers located on the cluster tool, for example, in processing chambers 124, 126, 128, and 130 of processing system 100 (see Figure 1). In some embodiments, operations 230, 240, and 250 are performed in 120 in the same processing chamber. In other embodiments, operation 250 is performed 120 in a different processing chamber from operations 230 and 240.

[0061] Referring to Figure 2B, in operation 260, the undoped crystalline silicon-containing capping layer 350 is removed, exposing the top surface 340u of the doped crystalline silicon-containing layer 340. Figure 3F shows a cross-sectional view of the semiconductor device 300 during the intermediate manufacturing stage corresponding to operation 260. During operation 260, the etching process is selective for the undoped crystalline silicon-containing capping layer 350 and is adjusted so that there is no etching or minimal etching of the materials forming the semiconductor layer 320 and the doped crystalline silicon-containing layer 340. As a result, the undoped crystalline silicon-containing capping layer 350 is removed, exposing the top surface 340u of the doped crystalline silicon-containing layer 340. The etching process in operation 260 can be dry etching, wet etching, reactive ion etching, or other suitable etching method. In some embodiments, the etching process in operation 260 is self-aligning, meaning that an etching mask is not required. Rather, the etching process of operation 260 depends on the etching selectivity of the material of the undoped crystalline silicon-containing capping layer 350 relative to the material of the semiconductor layer 320.

[0062] In some embodiments, where the semiconductor layer 320 is made of a dielectric material, such as silicon oxide or silicon nitride, the material of the undoped crystalline silicon-containing capping layer 350 has etching selectivity over the dielectric material of the semiconductor layer 320 (i.e., the etching rate of the undoped crystalline silicon-containing capping layer 350 is faster than the etching rate of the dielectric material). In some embodiments, the etching selectivity (i.e., the ratio of the etching rate of the undoped silicon-containing crystalline material to the etching rate of the dielectric material) is in the range of about 100:1 to about 3000:1, or in the range of about 1000:1 to about 2000:1.

[0063] Referring to Figure 2B, in operation 270, the metallic silicon compound feature 370 is formed on the source / drain feature 330. Figure 3G shows a cross-sectional view of the semiconductor device 300 during the intermediate manufacturing stage corresponding to operation 270. In some embodiments, operation 270 includes the steps of depositing one or more metals in a trench 322 and performing an annealing process on the semiconductor device 300 to induce a reaction between the one or more metals and the doped crystalline silicon-containing layer 340 to produce the metallic silicon compound feature 370. Operation 270 may further include the step of removing unreacted portions of the one or more metals to leave the metallic silicon compound feature 370. One or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or combinations thereof (e.g., alloys of two or more metals), and can be deposited using CVD, PVD, ALD, or other suitable methods. Examples of metallic silicon compounds with characteristic properties 370 include titanium silicon compounds (TiSi), nickel silicon compounds (NiSi), tungsten silicon compounds (WSi), nickel-platinum silicon compounds (NiPtSi), nickel-platinum-germanium silicon compounds (NiPtGeSi), nickel-germanium silicon compounds (NiGeSi), ytterbium silicon compounds (YbSi), platinum silicon compounds (PtSi), iridium silicon compounds (IrSi), erbium silicon compounds (ErSi), cobalt silicon compounds (CoSi), or other suitable compounds.

[0064] Referring to Figure 2B, in operation 280, the metal-filled layer 380 is formed within the trench 322. Figure 3H shows a cross-sectional view of the semiconductor device 300 during the intermediate manufacturing stage corresponding to operation 280. The metal-filled layer 380 is formed on or directly on the metal-silicon compound feature 370, as shown in Figure 3H. The metal-filled layer 380 may contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes.

[0065] Referring to Figure 2B, optionally, in operation 290, the semiconductor device 300 may be exposed to additional processing. Operation 290 may include the step of performing a CMP process to remove overbarden from the metal-filled layer 380. Operation 290 may also include the step of forming a back-side power rail (not shown) and a back-side interconnect (not shown). The back-side power rail is electrically connected to the metal-filled layer 380.

[0066] In summary, the aforementioned embodiments of this disclosure offer numerous advantages, including low-temperature, selective, and highly active dopant epitaxial deposition for logic back contacts and other applications. The method can be performed at temperatures below the thermal budget of semiconductor devices, e.g., below 480°C. The method involves the use of higher-order silane precursors and / or higher-order chlorosilane precursors with n-type dopant precursors selected from antimony-containing precursors, phosphorus-containing precursors, arsenic-containing precursors, or combinations thereof. The described methods, systems, and structures enable the formation of back PDNs. However, this disclosure does not seek to claim all advantageous features, and all advantages should be incorporated into any embodiment of this disclosure.

[0067] Certain features of this disclosure (including method operations) are referenced in the summary of the invention, the modes for carrying out the invention, the claims, and the accompanying drawings. It should be understood that the disclosure herein includes all possible combinations of such specific features. For example, if a particular feature is disclosed in the context of a particular aspect, embodiment, or example of this disclosure, or in the context of a particular claim, that feature may, to the extent possible, be used in combination with and / or in the context of other particular aspects and embodiments of this disclosure, as well as throughout the disclosure.

[0068] All embodiments and functional operations described herein may be implemented in digital electronic circuits, or in computer software, firmware, or hardware including the structural means and their structural equivalents disclosed herein, or in combination thereof. The practical embodiments described herein may be implemented as one or more non-transient computer program products, i.e., one or more computer programs tangibly embodied in a machine-readable storage device for execution by or control of the operation of a data processing device, such as a programmable processor, a computer, or a plurality of processors or computers.

[0069] Computer-readable media suitable for storing computer program instructions and data include, as an example, all forms of non-volatile memory, media, and memory devices, including semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be complemented by or incorporated into special-purpose logic circuits.

[0070] The term “comprises” and its grammatical equivalents, such as “including” and “having,” are used herein to mean the presence of other components, elements, actions, etc., of an optional nature. For example, an article “comprising” (or “which comprises”) components A, B, and C may consist of (i.e., consist only of) components A, B, and C, or may consist of not only components A, B, and C, but also one or more other components. Furthermore, whenever the transitional phrase “comprising” or its grammatical equivalent is placed before a composition, element, or group of elements, it is understood that the transitional phrases “consisting essentially of,” “consisting of,” “selected from the group of consisting of,” or “is” may be placed before the same composition or group of elements, and vice versa.

[0071] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper,” “backside,” and “frontside” may be used herein to describe the relationship between one element or feature and another, as shown in the diagrams, for the sake of clarity. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the diagrams. The device may be oriented in other orientations (such as a 90-degree rotation or other orientations), and the spatially relative descriptors used herein may also be incorporated accordingly.

[0072] Where this specification refers to a method that includes two or more defined operations, the defined operations may be performed in any order or simultaneously (unless the context excludes such possibility), and the method may include one or more other operations performed before any of the defined operations, between two of the defined operations, or after all of the defined operations (unless the context excludes such possibility). In addition, some of the operations described in Method 200 may be omitted unless otherwise specified.

[0073] When describing elements of this disclosure or its exemplary aspects or embodiments, the articles "a," "an," "the," and "said" are intended to indicate that there is one or more elements.

[0074] While the foregoing applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A step of epitaxially growing a doped crystalline silicon-containing layer on source / drain features, and growing a doped amorphous silicon-containing layer on the field region of a semiconductor layer, wherein trenches are formed in the semiconductor layer and the trenches expose the source / drain features. The steps include: epitaxially growing an undoped crystalline silicon-containing capping layer on the doped crystalline silicon-containing layer, and growing an undoped amorphous silicon-containing layer on the doped silicon-containing amorphous layer; The steps include selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer from the silicon-containing crystalline capping layer, The steps include removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer, A method for forming a semiconductor device, including [a specific component].

2. The method according to claim 1, further comprising the step of forming a metallic silicon compound layer from the doped silicon-containing crystalline layer.

3. The method according to claim 2, further comprising the step of forming a metal-filled layer in the trench, wherein the metal-filled layer is formed on the metal-silicon compound layer.

4. The method according to claim 1, wherein the steps of epitaxially growing a doped crystalline silicon-containing layer and epitaxially growing an undoped crystalline silicon-containing capping layer are performed at a temperature below the thermal budget of the semiconductor device.

5. The method according to claim 4, wherein the temperature is 500°C or less.

6. The method according to claim 1, wherein the steps of epitaxially growing a doped silicon-containing crystalline layer, epitaxially growing an undoped crystalline silicon-containing capping layer, and selectively removing a doped amorphous silicon-containing layer are performed in the processing area of ​​the processing chamber.

7. The method according to claim 6, wherein the step of selectively removing the doped amorphous silicon-containing layer is performed in a second processing region of a second processing chamber, and the semiconductor device is transferred from the processing region to the second processing region without breaking the vacuum.

8. The method according to claim 3, further comprising the step of forming a back-side power rail on the back side of the semiconductor device, wherein the back-side power rail is electrically coupled to the metal-filled layer.

9. A step of epitaxially growing a doped crystalline silicon-containing layer on source / drain features and growing a doped amorphous silicon-containing layer on the field region of a semiconductor layer, wherein trenches are formed in the semiconductor layer and the trenches expose the source / drain features, and the epitaxial growth step is The process includes introducing a higher-order silane precursor gas and an n-type dopant precursor gas into the processing area of ​​the process chamber, wherein the higher-order silane precursor gas has the chemical formula Si x H (2x+2) The formula has such that x is 2 or greater, Steps and The steps include epitaxially growing an undoped crystalline silicon-containing capping layer on a doped crystalline silicon-containing layer, and growing an undoped amorphous silicon-containing layer on a doped silicon-containing amorphous layer, Introducing the aforementioned higher-order silane precursor gas into the processing area, Steps including, A step of selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer from the undoped crystalline silicon-containing capping layer, Cl 2 GeCl 2 GeCl 4 GeH 4 , or flowing etching gas containing a combination of these, Steps including, A method for forming a semiconductor device, including [a specific component].

10. The method according to claim 9, further comprising the step of removing the undoped crystalline silicon-containing capping layer to expose the doped silicon-containing crystalline layer.

11. The method according to claim 9, wherein the higher-order silane precursor gas is selected from trisilane, tetrasilane, or a combination thereof.

12. The method according to claim 11, wherein the n-type dopant precursor gas is a phosphorus-containing precursor gas, an antimony-containing precursor gas, an arsenic-containing precursor gas, or a combination thereof.

13. The method according to claim 12, wherein the etching gas does not contain hydrogen chloride (HCl) gas.

14. The method according to claim 9, wherein the steps of epitaxially growing a doped crystalline silicon-containing layer and epitaxially growing an undoped crystalline silicon-containing capping layer are performed at a temperature below the thermal budget of the semiconductor device.

15. The method according to claim 14, wherein the temperature is 500°C or less.

16. The method according to claim 9, wherein the trench formed in the semiconductor layer is formed on the back side of the semiconductor device.

17. A step of providing a device structure in which a trench is formed in a semiconductor layer, wherein the trench exposes source / drain features from the back side of the device structure, and the semiconductor layer is formed on a device substrate. The steps include performing a first epitaxial deposition process to grow a doped crystalline silicon layer on the source / drain features and growing a doped amorphous silicon layer on the field region of the semiconductor layer, The steps include performing a second epitaxial deposition process to grow an undoped crystalline silicon capping layer on the doped crystalline silicon layer and to grow an undoped amorphous silicon layer on the doped amorphous silicon layer, A step of performing a selective etching process to remove the undoped amorphous silicon layer and the doped amorphous silicon layer from the undoped crystalline silicon capping layer, including, A method for forming semiconductor devices.

18. The first epitaxial deposition process includes the step of introducing a deposition gas containing a higher-order silane precursor gas and / or a chlorosilane precursor gas and a dopant precursor gas containing an n-type dopant precursor gas into the processing area of ​​a process chamber, wherein the higher-order silane precursor gas is Si x H (2x+2) The method according to claim 17, wherein the chemical formula is such that x is 2 or more.

19. The method according to claim 18, further comprising the step of purging the processing area after the first epitaxial deposition process and before the second epitaxial deposition process.

20. The method according to claim 19, wherein the second epitaxial deposition process includes the step of introducing a deposition gas containing the higher-order silane precursor gas into the processing area.

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