Display panel, method for manufacturing the same, and display device.

Abstract

The display panel comprises a base 10, a display structure layer, a touch structure layer 50, a plurality of pads 71, 72, and a first inorganic insulating layer 701. The display structure layer is located on the base 10 of the display area AA and includes a plurality of display area metal layers. The touch structure layer 50 is located on the side of the display structure layer away from the base 10. The plurality of pads 71, 72 are located in the first bezel area B1, and at least one of the pads 71, 72 includes at least one pad metal layer. The first inorganic insulating layer 701 exposes at least a portion of the surface of the pad metal layers of the plurality of pads 71, 72 that are separated from the base 10. The pad metal layer exposed by the first inorganic insulating layer 701 of at least one of the pads 71, 72 and the display area metal layer of one of the plurality of display area metal layers of the display structure layer have the same layer structure.

Description

Technical Field

[0001] This article relates to the display technology field, but is not limited thereto, and particularly relates to a display panel, its manufacturing method, and a display device.

Background Art

[0002] An organic light-emitting diode (OLED) is an active light-emitting display device, and has advantages such as self-luminous, wide viewing angle, high contrast ratio, low power consumption, and extremely high response speed. With the continuous development of display technology, a display device using an OLED as a light-emitting device and performing signal control by a thin film transistor (TFT) has become the main product in the current display field.

Summary of the Invention

Means for Solving the Problems

[0003] The following is an outline of the subject matter that this article will explain in detail. This outline is not for limiting the protection scope of the claims.

[0004] Embodiments of the present disclosure provide a display panel, its manufacturing method, and a display device.

[0005] In one embodiment, this embodiment provides a display panel comprising a base, a display structure layer, a touch structure layer, a plurality of pads, and a first inorganic insulating layer. The base includes a display area and a first bezel area located on one side of the display area. The display structure layer is located at the base of the display area and includes a plurality of display area metal layers. The touch structure layer is located on the side of the display structure layer away from the base. The plurality of pads are located in the first bezel area, and at least one pad includes at least one pad metal layer. The first inorganic insulating layer is located in the first bezel area and on the side of the plurality of pads away from the base. The first inorganic insulating layer exposes at least a portion of the surface of the pad metal layers that are separated from the base of the plurality of pads. The pad metal layer exposed by the first inorganic insulating layer of at least one pad and one display area metal layer of the display structure layer have the same layer structure.

[0006] In some exemplary embodiments, the pad metal layer exposed by the first inorganic insulating layer of at least one pad includes a laminated structure of at least two metallic materials.

[0007] In some exemplary embodiments, the pad metal layer exposed by the first inorganic insulating layer of at least one pad includes a titanium-aluminum-titanium triple-layer structure.

[0008] In some exemplary embodiments, the first inorganic insulating layer covers the edge of the pad metal layer exposed by the first inorganic insulating layer of at least one pad.

[0009] In some exemplary embodiments, the overlap length between the first inorganic insulating layer and one side edge of the exposed pad metal layer is 10 microns or less.

[0010] In some exemplary embodiments, the first inorganic insulating layer does not overlap with the edge of the pad metal layer exposed by the first inorganic insulating layer of the at least one pad.

[0011] In some exemplary embodiments, the display structure layer includes a plurality of subpixels, at least one of the subpixels includes a pixel circuit and a light-emitting element, the pixel circuit is electrically connected to the light-emitting element via a first relay electrode and a second relay electrode, the second relay electrode being located on the side of the first relay electrode away from the base. The pad metal layer exposed by the first inorganic insulating layer of the at least one pad and the second relay electrode are of the same layer structure.

[0012] In some exemplary embodiments, the first bezel region includes a signal access region, which includes a first signal access region and a second signal access region, the second signal access region being located on the side of the first signal access region away from the display region. The plurality of pads includes a plurality of first pads located in the first signal access region and a plurality of second pads located in the second signal access region. The number of pad metal layers of at least one of the plurality of first pads is greater than the number of pad metal layers of at least one of the plurality of second pads.

[0013] In some exemplary embodiments, the at least one first pad includes a first pad metal layer, a second pad metal layer, a third pad metal layer, and a fourth pad metal layer that are sequentially stacked along a direction away from the base.

[0014] In some exemplary embodiments, the pixel circuit includes at least one thin-film transistor and at least one capacitor. The first pad metal layer of the at least one first pad and the first or second plate of the at least one capacitor have the same layer structure, the second pad metal layer and the source and drain electrodes of the at least one thin-film transistor have the same layer structure, the third pad metal layer and the first relay electrode have the same layer structure, and the fourth pad metal layer and the second relay electrode have the same layer structure.

[0015] In some exemplary embodiments, the at least one second pad includes a fifth pad metal layer and a sixth pad metal layer that are sequentially stacked along a direction away from the base.

[0016] In some exemplary embodiments, the fifth pad metal layer of at least one second pad and the first relay electrode have the same layer structure, and the sixth pad metal layer and the second relay electrode have the same layer structure.

[0017] In some exemplary embodiments, the first bezel region further includes a bend region and a fan-out wiring region located on the side of the signal access region closer to the display region, wherein the fan-out wiring region is located on the side of the bend region closer to the display region. At least a plurality of touch lead lines are provided in the fan-out wiring region, at least a plurality of touch bend connection lines are provided in the bend region, and at least a plurality of touch relay lines are provided in the signal access region. The touch bend connection lines electrically connect the touch lead lines and the touch relay lines, and the touch relay lines and one pad metal layer of the first pad to which they are connected are integrated into a single structure.

[0018] In some exemplary embodiments, the touch bending connection line and the connecting touch relay line are integrated into a single structure.

[0019] In some exemplary embodiments, the touch bending connection line and the first relay electrode have the same layer structure, and the touch relay line and the second relay electrode have the same layer structure.

[0020] In some exemplary embodiments, the display structure layer includes a plurality of subpixels, at least one of the subpixels includes a pixel circuit and a light-emitting element, the pixel circuit is electrically connected to the light-emitting element via a first relay electrode. The pad metal layer exposed by the first inorganic insulating layer of the at least one pad and the first relay electrode have the same layer structure.

[0021] In some exemplary embodiments, the touch structure layer includes a touch buffer layer, a first touch conductive layer, an intertouch insulating layer, and a second touch conductive layer, which are sequentially laminated on the side away from the base. The first inorganic insulating layer and the touch buffer layer have the same layer structure, and the intertouch insulating layer is an organic insulating layer.

[0022] In some exemplary embodiments, the display panel further comprises a color filter layer located on the side of the touch structure layer away from the base, the color filter layer including a color film buffer layer, a black matrix, a plurality of filter units and a color film protective layer, which are sequentially installed on the side away from the base, and both the color film buffer layer and the color film protective layer are organic insulating layers.

[0023] In another embodiment, this embodiment provides a display device comprising the display panel described above.

[0024] In another embodiment, this embodiment provides a method for manufacturing a display panel, comprising: providing a base which includes a display area and a first bezel area located on one side of the display area; forming a display structure layer in the display area; forming a plurality of pads in the first bezel area, the display structure layer comprising a plurality of display area metal layers, at least one of the plurality of pads comprising at least one pad metal layer; forming a touch structure layer on the side of the display structure layer away from the base; and forming a first inorganic insulating layer in the first bezel area. The first inorganic insulating layer is located on the side of the plurality of pads away from the base and exposes at least a portion of the surface of the pad metal layers of the plurality of pads away from the base, and the pad metal layer exposed by the first inorganic insulating layer of at least one pad and one of the display area metal layers of the plurality of display area metal layers of the display structure layer have the same layer structure.

[0025] In some exemplary embodiments, forming the first inorganic insulating layer in the first bezel region includes depositing a first inorganic insulating thin film covering a plurality of pads in the first bezel region after forming the display structure layer, and etching the first inorganic insulating thin film after forming the touch structure layer to form the first inorganic insulating layer.

[0026] In some exemplary embodiments, the manufacturing method further includes forming a color filter layer on a side away from the base of the touch structure layer before etching the first inorganic insulating thin film after forming the touch structure layer. The color filter layer includes a color film buffer layer, a black matrix, a plurality of filter units, and a color film protection layer that are sequentially installed on a side away from the base. Both the color film buffer layer and the color film protection layer are organic insulating layers.

[0027] In another aspect, the present embodiment provides a display panel, which includes a base, a display structure layer, a touch structure layer, a color filter layer, and a plurality of pads. The base includes a display region and a first bezel region located on one side of the display region. The display structure layer is located on the base of the display region, the touch structure layer is located on a side away from the base of the display structure layer, and the color filter layer is located on a side away from the base of the touch structure layer.The plurality of pads are located in the first bezel region. The orthographic projection of the touch structure layer and the color filter layer on the base does not overlap with the orthographic projection of the plurality of pads on the base.

[0028] In some exemplary embodiments, the display panel further includes a first inorganic insulating layer located in the first bezel region. The first inorganic insulating layer is located on a side away from the base of the plurality of pads, and the first inorganic insulating layer exposes at least a part of the surface that deviates from the base of the plurality of pads. The touch structure layer includes a touch buffer layer, a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer that are sequentially laminated on a side away from the base. The first inorganic insulating layer and the touch buffer layer have the same layer structure.

[0029] In some exemplary embodiments, at least one of the plurality of pads includes at least one pad metal layer. The first bezel region includes a first signal access region and a second signal access region, and the second signal access region is located on a side away from the display region of the first signal access region. The plurality of pads includes a plurality of first pads located in the first signal access region and a plurality of second pads located in the second signal access region. The number of pad metal layers of at least one of the plurality of first pads is greater than the number of pad metal layers of at least one of the plurality of second pads.

[0030] After reading and understanding the drawings and the detailed description, other aspects can be understood.

[0031] The drawings are provided for a further understanding of the technical solutions of the present disclosure, form a part of the specification, and are used to interpret the technical solutions of the present disclosure together with the embodiments of the present disclosure, rather than to limit the technical solutions of the present disclosure. The shapes and sizes of one or more components in the drawings do not reflect the actual proportions and are for schematically explaining the content of the present disclosure.

Brief Description of the Drawings

[0032] [Figure 1] It is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 2] It is a schematic partial cross-sectional view of a display region of a display panel according to at least one embodiment of the present disclosure. [Figure 3] It is a schematic partial plan view of a touch structure layer according to at least one embodiment of the present disclosure. [Figure 4] It is a schematic partial plan view of a first signal access region according to at least one embodiment of the present disclosure. [Figure 5] It is a schematic partial cross-sectional view along the P-P' direction in FIG. 4. [Figure 6] It is a schematic partial plan view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a local cross-section along the R-R' direction in Figure 6. [Figure 8] This is a local plan schematic view of the wiring in the first bezel region according to at least one embodiment of the present disclosure. [Figure 9] This is a schematic diagram of a local cross-section along the Q-Q' direction in Figure 8. [Figure 10A] This is a schematic local cross-sectional view of a first signal access region after the formation of a first inorganic insulating thin film according to at least one embodiment of the present disclosure. [Figure 10B] This is a schematic local cross-sectional view of a second signal access region after the formation of a first inorganic insulating thin film according to at least one embodiment of the present disclosure. [Figure 11A] This is another schematic cross-sectional view of a first signal access region according to at least one embodiment of the present disclosure. [Figure 11B] This is another schematic local cross-sectional view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 12] This is another schematic diagram of a display panel according to at least one embodiment of the present disclosure. [Figure 13] Figure 12 is a schematic local plan view of the wiring in the first bezel region. [Figure 14] This is a schematic diagram of a local cross-section along the U-U' direction in Figure 13. [Figure 15] This is another schematic diagram of a local cross-section along the U-U' direction in Figure 13. [Figure 16] This is another schematic cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. [Figure 17] This is a schematic local cross-sectional view of a signal access region according to at least one embodiment of the present disclosure. [Figure 18A] This is another schematic cross-sectional view of a first signal access region according to at least one embodiment of the present disclosure. [Figure 18B] This is another schematic local cross-sectional view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 19A]This is another schematic cross-sectional view of a first signal access region according to at least one embodiment of the present disclosure. [Figure 19B] This is another schematic local cross-sectional view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 20] This is a schematic local cross-sectional view of a signal access region according to at least one embodiment of the present disclosure. [Figure 21] This is another schematic local cross-sectional view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 22] This is another schematic local cross-sectional view of a second signal access region according to at least one embodiment of the present disclosure. [Figure 23] This is another schematic cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. [Figure 24] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0033] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments can be carried out in many different forms. The methods and content can be converted to other forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0034] In the drawings, for clarity, the size, layer thickness, or area of ​​one or more components may be shown in an enlarged manner. Therefore, one embodiment of the present disclosure is not limited to such size, and the shape and size of one or more components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically represent ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0035] In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion of constituent elements and do not limit them in terms of quantity. The term “plural” in this disclosure refers to two or more quantities.

[0036] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of components may be appropriately changed depending on the orientation of the component being described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0037] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or a connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the meaning of these terms in this disclosure depending on the specific circumstances.

[0038] In this specification, “electrical connection” includes cases where components are connected via an element having an electrical function. The “element having an electrical function” is not particularly limited and only needs to be capable of transmitting electrical signals between the connected components. Examples of “elements having an electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements with different functions.

[0039] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0040] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" may be converted to each other. The gate electrode may also be referred to as the control electrode.

[0041] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0042] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons, and small deformations due to tolerances may exist, such as chamfers, arcs, and other deformations.

[0043] In this disclosure, "approximately" and "nearly" do not strictly define boundaries and allow for tolerances within the process and measurement error range. In this disclosure, "nearly the same" means that the numerical difference is within 10%. In this disclosure, "symmetrical" does not strictly define boundaries and allows for approximate symmetry within the process and measurement error range.

[0044] In this disclosure, "A extends along direction B" means that A includes a main body and secondary parts connected to the main body, the main body is a line, line segment or elongated object, the main body extends along direction B, and the length of the main body extending along direction B is greater than the length of the secondary parts extending in other directions. In this disclosure, "A extends along direction B" always means "the main body of A extends along direction B." In this disclosure, "A and B are an integrated structure" means that A and B are connected to each other and integrally molded.

[0045] In some implementations, a touch structure may be integrated into the display panel. The display panel may include a liquid crystal display (LCD) substrate, an organic light-emitting diode (OLED) display substrate, a plasma display (PDP) display substrate, or an electrophoretic display (EPD) display substrate. For example, the display panel may include an OLED display substrate and a touch structure. The touch structure may be installed in the encapsulation layer of the display substrate to form a structure in which the touch structure is on a thin film encapsulation (abbreviated as Touch on Thin Film Encapsulation, or Touch on TFE). The display structure and touch structure are integrated, offering advantages such as weight reduction and foldability, and can satisfy product demands such as flexible folding and narrow bezels.

[0046] In some examples, Touch on TFE structures primarily include Flexible Multi-Layer On Cell (FMLOC) and Flexible Single-Layer On Cell (FSLOC) structures. FMLOC structures are based on the principle of mutual capacitance detection, and generally consist of two layers of metal forming a drive (Tx) electrode and a sensing (Rx) electrode. The integrated circuit (IC) then detects the mutual capacitance between the drive and sensing electrodes to achieve touch operation. FSLOC structures are based on the principle of self-capacitance (or voltage) detection, and generally consist of a single layer of metal forming the touch electrode. The integrated circuit then detects the self-capacitance (or voltage) of the touch electrode to achieve touch operation.

[0047] In their research, the inventors discovered that integrated display structures and touch-type display panels have poor bending performance and are prone to cracking during reliability testing. To improve the cracking problem, some inorganic film layers in the touch structure can be changed to organic film layers. However, if organic film layers are used in the touch structure, the pads installed in the bezel area of ​​the display panel may corrode during the manufacturing process, causing problems such as poor brightness.

[0048] This embodiment provides a display panel comprising a base, a display structure layer, a touch structure layer, a plurality of pads, and a first inorganic insulating layer. The base may include a display area and a first bezel area located on one side of the display area. The display structure layer is located at the base of the display area and includes a plurality of display area metal layers. The touch structure layer is located on the side of the display structure layer away from the base. The plurality of pads are located in the first bezel area. At least one of the plurality of pads includes at least one pad metal layer. The first inorganic insulating layer is located in the first bezel area and on the side of the plurality of pads away from the base, and the first inorganic insulating layer exposes at least a portion of the surface of the pad metal layer away from the base of the plurality of pads. The pad metal layer exposed by the first inorganic insulating layer of at least one pad and the display area metal layer of one of the plurality of display area metal layers of the display structure layer have the same layer structure. In some examples, the pad metal layer exposed by the first inorganic insulating layer of at least one pad may be the pad metal layer furthest from the base of the pad.

[0049] In the display panel according to this embodiment, by setting the pad metal layer furthest from the base of the multiple pads in the first bezel area and the display area metal layer of one of the display structure layers to be the same layer structure, the condition of pad corrosion during the manufacturing process can be improved, the yield rate of the display panel can be improved, and further, the bending resistance of the display panel can be improved.

[0050] In some exemplary embodiments, the pad metal layer exposed by the first inorganic insulating layer of at least one pad may include a laminated structure of at least two metallic materials. For example, the pad metal layer exposed by the first inorganic insulating layer of at least one pad may include a titanium-aluminum-titanium triple laminated structure. For example, the pad metal layer exposed by the first inorganic insulating layer of the pad and furthest from the base may be located in the source drain metal layer of the display panel.

[0051] In some exemplary embodiments, the first inorganic insulating layer may cover the edge of the pad metal layer exposed by the first inorganic insulating layer of at least one pad. In some examples, the overlap length between the first inorganic insulating layer and one side edge of the exposed pad metal layer may be 10 microns or less, for example, 5 microns or more and 10 microns or less. In this example, the protective effect on the pad can be improved by using the first inorganic insulating layer to perform edge covering treatment on the pad metal layer that is exposed by the first inorganic insulating layer of the pad and is furthest from the base.

[0052] In some exemplary embodiments, the first bezel region may include a signal access region, and the signal access region may include a first signal access region and a second signal access region, the second signal access region may be located on the side of the first signal access region away from the display region. The plurality of pads may include a plurality of first pads located in the first signal access region and a plurality of second pads located in the second signal access region. The number of pad metal layers of at least one of the plurality of first pads may be greater than the number of pad metal layers of at least one of the plurality of second pads. For example, the pad metal layers of at least one first pad may be four layers, and the pad metal layers of at least one second pad may be two layers. Alternatively, for example, the pad metal layers of at least one first pad may be three layers, and the pad metal layers of at least one second pad may be two layers or one layer. However, this is not limited to this example. In this example, designing the pad metal layers of the first pads and the second pads respectively contributes to the wiring layout design of the signal access region. Furthermore, by installing pads formed by stacking multiple metal pad layers, the resistance of the pads can be reduced, contributing to improved signal transmission performance.

[0053] The method of this embodiment will be explained below with examples.

[0054] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1 shows a schematic plan view of the display panel before the folding process is carried out. In some examples, as shown in Figure 1, the display panel may include a display area AA and a peripheral area BB surrounding the outside of the display area AA. For example, the peripheral area BB may include a first bezel area B1 located on one side of the display area AA, and bezel areas located on the other side of the display area AA (for example, including a second bezel area B2, a third bezel area B3, and a fourth bezel area B4). The first bezel area B1 may be, for example, the bottom bezel of the display panel, the second bezel area B2 may be, for example, the top bezel of the display panel, the third bezel area B3 may be, for example, the left bezel of the display panel, and the fourth bezel area B4 may be, for example, the right bezel of the display panel.

[0055] In some examples, as shown in Figure 1, the display area AA may be a flat area and may include multiple subpixels PX that constitute a pixel array, and the multiple subpixels PX may be configured to display a moving image or a still image. The display area AA may be called the Active Area. In some examples, the display area AA may be rectangular, however, this embodiment is not limited to this. For example, the display area AA may be circular or elliptical or other shapes. In some examples, the display panel may be a flexible panel, and therefore the display panel may be deformable, such as being able to curl, bend, fold, or roll up.

[0056] In some examples, as shown in Figure 1, the display area AA may include at least a plurality of subpixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthogonal projections of the plurality of gate lines GL and the plurality of data lines DL on the base may intersect to form a plurality of subpixel regions, each of which may contain one subpixel PX. The plurality of data lines DL and the plurality of subpixels PX may be electrically connected, and the plurality of data lines DL may be configured to provide data signals to the plurality of subpixels PX. The plurality of gate lines GL may be electrically connected to the plurality of subpixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of subpixels PX. In some examples, the gate control signals may include a scan signal and an emission control signal, or may include a scan signal, a reset control signal, and an emission control signal.

[0057] In some examples, as shown in Figure 1, the first direction X may be the direction of extension of the gate lines GL in the display area AA (e.g., the row direction), and the second direction Y may be the direction of extension of the data lines DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y may intersect each other, or they may be perpendicular to each other, for example.

[0058] In some examples, one pixel unit of display area AA may contain three subpixels, where the three subpixels are a red subpixel, a green subpixel, and a blue subpixel, respectively. However, this embodiment is not limited to this. In some examples, one pixel unit may contain four subpixels, where the four subpixels are a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, respectively.

[0059] In some examples, the shape of the subpixels may be rectangular, rhombus, pentagonal, or hexagonal. If a pixel unit contains three subpixels, the three subpixels may be arranged in a horizontal parallel, vertical parallel, or U-shape. If a pixel unit contains four subpixels, the four subpixels may be arranged in a horizontal parallel, vertical parallel, or square shape, but this embodiment is not limited to these arrangements.

[0060] In some examples, a single sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. By using the same type of transistors in the pixel circuit, the process flow can be simplified, the process difficulty of the display substrate can be reduced, and the yield rate of the product can be improved. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0061] In some examples, multiple transistors in a pixel circuit may be low-temperature polysilicon film transistors, oxide film transistors, or both low-temperature polysilicon film transistors and oxide film transistors. The active layer of low-temperature polysilicon film transistors uses low-temperature polysilicon (LTPS), while the active layer of oxide film transistors uses oxide semiconductors. Low-temperature polysilicon film transistors have advantages such as high mobility and fast charging, while oxide film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon film transistors and oxide film transistors onto a single display substrate, i.e., an LTPS+Oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display properties.

[0062] In some examples, the light-emitting element may be any one of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element may be an OLED, which can emit red, green, blue, or white light under the drive of the corresponding pixel circuit. The emission color of the light-emitting element can be determined according to the requirements. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit, however, this is not limited in this embodiment.

[0063] Figure 2 is a schematic local cross-sectional view of a display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 2 shows the structure of one subpixel of the display area as an example. In this example, it is explained that the type of multiple transistors in the pixel circuit is the same, for example, all of the multiple transistors in the pixel circuit may be low-temperature polysilicon film transistors or oxide film transistors. In other examples, the multiple transistors in the pixel circuit may be low-temperature polysilicon film transistors and oxide film transistors. Furthermore, in this example, it is explained that a mutually capacitive touch structure is integrated into the display panel to form an FMLOC structure.

[0064] In some examples, as shown in Figure 2, the display area of ​​the display panel may include a base 10 and, sequentially, a circuit structure layer 20, a light-emitting structure layer 30, a sealing structure layer 40, a touch structure layer 50, and a color filter layer 60, all mounted on the base 10. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include pixel circuits for at least a plurality of subpixels, and each subpixel's pixel circuit may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 30 may include light-emitting elements for at least a plurality of subpixels.

[0065] In some examples, Figure 2 shows that each subpixel includes one thin-film transistor 21 and one capacitor 22. In some examples, the display area circuit structure layer 20 may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are placed on the base 10. The multiple display area metal layers of the display structure layer in this example may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 101 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be provided between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first flat layer 105 may be provided between the first source-drain metal layer and the second source-drain metal layer, a second flat layer 106 may be provided between the second source-drain metal layer and the third source-drain metal layer, and a third flat layer 107 may be provided on the side of the third source-drain metal layer away from the base 10. The first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 may be inorganic insulating layers, and the first flat layer 105, the second flat layer 106 and the third flat layer 107 may be organic insulating layers. However, this embodiment is not limited to these materials. In other examples, a buffer layer may be further provided on the side of the semiconductor layer closer to the base. The buffer layer can prevent harmful substances from entering the display panel from the base and can also increase the adhesion of the film layer to the base of the display panel. In other examples, a bottom shielding metal (BSM) layer may be provided on the side of the buffer layer closer to the base. To avoid the influence of external light on the performance of the thin-film transistors, the bottom shielding metal layer may be configured so that at least a portion of it covers the active layer of the thin-film transistors of the pixel circuit. In other examples, a passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first flat layer may be provided between the first source-drain metal layer and the second source-drain metal layer.

[0066] In some examples, as shown in Figure 2, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first area 2101, a second area 2102, and a channel region 2100 located between the first area 2101 and the second area 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 on the base 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the base 10. The second gate metal layer may include at least the second plate 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the base 10 may at least partially overlap, for example, they may overlap completely. The first source-drain metal layer may include at least the source electrode 211 and drain electrode 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias in the display area (for example, including a first pixel via and a second pixel via). The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first area 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second area 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 may be electrically connected to the first area 2101 of the active layer 210 via the first pixel via, and the drain electrode 212 may be electrically connected to the second area 2102 of the active layer 210 via the second pixel via. The second source-drain metal layer may include at least a first relay electrode 231. The first relay electrode 231 may be electrically connected to the drain electrode 212 of the thin-film transistor 21 of the pixel circuit via a third pixel via opened in the passivation layer 104 and the first flat layer 105. The third source-drain metal layer may include at least a second relay electrode 232. The second relay electrode 232 may be electrically connected to the first relay electrode 231 located in the second source-drain metal layer via a fourth pixel via opened in the second flat layer 106.The second relay electrode 231 may be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element via a fifth pixel via opened in the third flat layer 107. In this example, the first relay electrode 231 and the second relay electrode 232 enable the electrical connection between the pixel circuit and the light-emitting element.

[0067] In some examples, the gate lines of the display area may be located in, for example, the first gate metal layer, the data lines of the display area may be located in, for example, the second source-drain metal layer or the third source-drain metal layer, and the high-potential power lines of the display area may be located in, for example, at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited thereto. The circuit structure layer in this example may include three source-drain metal layers, which avoids the need for many wiring arrangements within a single source-drain metal layer and contributes to the realization of a narrow bezel structure.

[0068] In some examples, as shown in Figure 2, the light-emitting structure layer 30 may include a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode, and the first electrode 301 may be installed in a third flat layer 107 and electrically connected to a second relay electrode 232 via a fifth pixel via opened in the third flat layer 107. The pixel definition layer 304 is installed in the first electrode 301 and the third flat layer 107, and a plurality of pixel apertures may be opened in the pixel definition layer 304, with one pixel aperture exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be installed in one pixel aperture and connected to a corresponding first electrode 301. The second electrode 303 may be installed in the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light rays of the corresponding color under the driving of the first electrode 301 and the second electrode 303. A spacer pillar layer may be further installed on the side of the pixel definition layer 304 away from the base 10, and the spacer pillar layer may include multiple spacer pillars (PS).

[0069] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an Emitting Layer (EML) and one or more film layers from among a Hole Injection Layer (HIL), Hole Transport Layer (HTL), Hole Block Layer (HBL), Electron Block Layer (EBL), Electron Injection Layer (EIL), and Electron Transport Layer (ETL). Under voltage driving of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to produce light according to the required grayscale.

[0070] In some examples, the light-emitting layers of different colored light-emitting elements may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process difficulty and improve yield, the hole injection layer and hole transport layer located on one side of the light-emitting layer may be common layers, and the electron injection layer and electron transport layer located on the other side of the light-emitting layer may also be common layers. In some examples, one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer may be fabricated by a primary process (primary deposition process or primary inkjet printing process), and isolation can be achieved by means of surface steps or surface treatment of the formed film layer. For example, one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent subpixels may be isolated. In some examples, the organic light-emitting layer may be fabricated by deposition using a fine metal mask (FMM) or an open mask, or by an inkjet process.

[0071] In some examples, as shown in Figure 2, the sealing structure layer 40 may include a first sealing layer 401, a second sealing layer 402, and a third sealing layer 403 that are stacked. The first sealing layer 401 and the third sealing layer 403 may be made of inorganic materials, and the second sealing layer 402 may be made of organic materials. The second sealing layer 402 is installed between the first sealing layer 401 and the third sealing layer 403 to prevent external water vapor from entering the light-emitting element. However, this embodiment is not limited to this. For example, the sealing structure layer may employ a stacked structure of five layers: inorganic / organic / inorganic / organic / inorganic.

[0072] Figure 3 is a schematic local plan view of a touch structure layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the touch structure layer of the display area may include a plurality of first touch units 530 and a plurality of second touch units 540. The first touch units 530 may have a linear configuration extending along a first direction X, and the plurality of first touch units 530 may be arranged sequentially along a second direction Y. The second touch units 540 may have a linear configuration extending along a second direction Y, and the plurality of second touch units 540 may be arranged sequentially along the first direction X. Each first touch unit 530 may include a plurality of first touch electrodes 531 and first connectors 532 arranged sequentially along the first direction X, and the first touch electrodes 531 and first connectors 532 may be arranged alternately and connected sequentially. Each second touch unit 540 may include a plurality of second touch electrodes 541 arranged sequentially along a second direction Y, the plurality of second touch electrodes 541 may be spaced apart, and adjacent second touch electrodes 541 may be connected to each other via a second connector 542. In some examples, the film layer on which the second connector 542 is located may be different from the film layer on which the first touch electrode 531 and the second touch electrode 541 are located.

[0073] In some examples, as shown in Figure 2, the touch structure layer 50 of the display area may include a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, which are sequentially installed in a direction perpendicular to the display panel. The touch buffer layer 501 may be an inorganic insulating layer, and the touch interlayer insulating layer 502 may be an organic insulating layer. In this example, by installing the touch interlayer insulating layer 502 as an organic insulating layer, crack problems in reliability testing of the display panel (e.g., crack problems in warping tests of foldable display panels) can be improved, increasing the bending resistance of the display panel and contributing to an improved yield rate and competitiveness of the display panel.

[0074] In some examples, as shown in Figures 2 and 3, a plurality of first touch electrodes 531, a plurality of second touch electrodes 541, and a plurality of first connection portions 532 may be installed in the same layer of the first touch conductive layer 511, or may be formed by the same patterning process, and the first touch electrodes 531 and the first connection portions 532 may be an integrated structure connected to each other. The second connection portions 542 may be installed in the second touch conductive layer 512, and the second connection portions 542 may be connected to adjacent second touch electrodes 221 via vias opened in the intertouch insulating layer 502. In other examples, multiple first touch electrodes 531, multiple second touch electrodes 541, and multiple second connection portions 542 may be installed in the same layer on the first touch conductive layer 511, the second touch electrodes 541 and the second connection portions 542 may be an integrated structure connected to each other, the first connection portions 532 may be installed on the second touch conductive layer 512, and the first connection portions 532 may be connected to adjacent first touch electrodes 531 via vias opened in the intertouch insulating layer 502. In some examples, the first touch electrodes 531 may be drive (Tx) electrodes and the second touch electrodes 541 may be sensing (Rx) electrodes. Alternatively, the first touch electrodes 531 may be sensing (Rx) electrodes and the second touch electrodes 541 may be drive (Tx) electrodes. This embodiment is not limited thereto.

[0075] In some examples, as shown in Figure 3, the first touch electrode 531 and the second touch electrode 541 may have a rhombus shape, for example, a regular rhombus, a transverse rhombus, or a vertical rhombus. In other examples, the first touch electrode 531 and the second touch electrode 541 may have one or more of the shapes of a triangle, square, trapezoid, parallelogram, pentagon, hexagon, and other polygons, and are not limited to these in the embodiments of this disclosure.

[0076] In some examples, as shown in Figure 3, the first touch electrode 531 and the second touch electrode 541 may be in the form of transparent conductive electrodes. In other examples, the first touch electrode 531 and the second touch electrode 541 may be in the form of a metal mesh, the metal mesh may be formed by the intersection of multiple metal wires, the metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon made up of multiple metal wires. The metal mesh type first touch electrode 531 and second touch electrode 541 have advantages such as low resistance, small thickness, and fast response speed.

[0077] In some examples, as shown in Figure 2, the color filter layer 60 may be located on the side of the touch structure layer 50 away from the display structure layer. The color filter layer 60 may include a plurality of filter units of different colors (e.g., including filter unit 611), a black matrix 610 located between the different filter units, a color film buffer layer (CBL) 601 located on the side of the black matrix 610 and the plurality of filter units closer to the base 10, and a color film protective layer (COC) 602 located on the side of the black matrix 610 and the plurality of filter units away from the base 10. In some examples, the plurality of filter units of the color filter layer 60 may include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units. The filter units of different colors may correspond to light-emitting elements of the light-emitting structure layer 30 that emit light of different colors. For example, a blue filter unit may correspond to a blue light-emitting element, and the orthographic projection of the blue filter unit on the base may at least partially overlap the orthographic projection of the light-emitting region of the blue light-emitting element on the base, for example, the orthographic projection of the blue filter unit on the base may cover the orthographic projection of the light-emitting region of the blue light-emitting element on the base. In this example, a filter unit can allow light of one color to pass through while absorbing light of other colors. For example, a blue filter unit can allow blue light to pass through while absorbing light of other colors.

[0078] In this example, the color filter layer 60 may be formed using Color On Encapsulation (COE) technology, which significantly reduces the thickness compared to a polarizing plate and achieves a superior flexibility effect. Furthermore, compared to the natural light removal function of a circular polarizing plate, both the black matrix 610 and the filter unit of the color filter layer 60 have light absorption functions. When natural light from the outside is irradiated, the natural light passes through the filter unit and irradiates the subpixels below it. After being reflected by the subpixels, the natural light is emitted from the filter unit along with the light generated by the subpixels themselves. This improves the emission rate of natural light and enables a function of reducing power consumption.

[0079] In some examples, as shown in Figure 2, both the color film buffer layer 601 and the color film protective layer 602 may be organic insulating layers. In this example, by setting the color film buffer layer 601 as an organic insulating layer, crack problems in reliability testing of display panels (for example, crack problems in warping tests of foldable display panels) can be improved, the bending resistance of the display panel can be increased, and this contributes to improving the yield rate and competitiveness of the display panel.

[0080] In some examples, as shown in Figure 1, the display structure layers of the third bezel region B3 and the fourth bezel region B4 of the display panel may each include a peripheral circuit region, a power line region, a crack dam region, and a cut region, which are sequentially arranged along the direction away from the display region AA. The peripheral circuit region is connected to the display region AA and may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), which may be electrically connected to a plurality of gate lines GL in the display region AA and may be configured to provide gate control signals to the plurality of gate lines GL. The power line region is connected to the peripheral circuit region and may include at least low-potential power lines, which may extend along a direction parallel to the edge of the display region and be connected to the cathode of a light-emitting element in the display region AA. The crack dam region may be connected to the power line region and may include a plurality of cracks provided in at least a composite insulating layer. The cutting region may be connected to the crack dam region and may include cutting grooves provided in at least the composite insulating layer, the cutting grooves being configured so that a cutting device can cut along each groove after the manufacturing of all the film layers of the display panel is complete.

[0081] In some examples, as shown in Figure 1, the touch structure layers of the third bezel area B3 and the fourth bezel area B4 of the display panel may each include a plurality of touch leads 252. The plurality of touch leads 252 may each be electrically connected to a first touch unit and a second touch unit. The plurality of touch leads 252 may all be located in the first touch conductive layer, or all may be located in the second touch conductive layer. Alternatively, the plurality of touch leads 252 may be arranged alternately in the first touch conductive layer and the second touch conductive layer. However, this embodiment is not limited to this.

[0082] In some examples, as shown in Figure 1, the first bezel area B1 of the display panel may include a fan-out wiring area B11, a bend area B12, and a signal access area B13, which are sequentially arranged along the direction away from the display area AA. Figure 1 illustrates only a few of the wirings within the first bezel area B1. In this embodiment, the number of wirings in the first bezel area B1 is not limited.

[0083] In some examples, as shown in Figure 1, the fan-out wiring area B11 may be connected to the display area AA. The fan-out wiring area B11 may have at least a first power line, a second power line, a plurality of display lead lines, and a plurality of touch lead lines 252. The first power line may be configured to connect the high-potential power line of the display area AA, and the second power line may be configured to connect the low-potential power lines in the third bezel area B13 and the fourth bezel area B14. The plurality of display lead lines may include at least a plurality of data lead lines 251 and a plurality of drive lead lines (not shown). The plurality of data lead lines 251 may be electrically connected to a plurality of data lines DL of the display area AA, for example, the plurality of data lead lines 251 may be electrically connected to the plurality of data lines DL in a one-to-one correspondence. The plurality of data lead lines 251 may extend from the fan-out wiring area B11 to the bending area B12 in a fan-out wiring configuration. Multiple drive leads may extend from the third bezel area B3 and the fourth bezel area B4 to the fan-out wiring area B11. Multiple drive leads may be electrically connected to gate drive circuits within the third bezel area B3 and the fourth bezel area B4. Multiple drive leads may be configured to provide control signals to the gate drive circuits. For example, control signals may include start signals, clock signals, etc. Multiple touch leads 252 may extend from the third bezel area B3 and the fourth bezel area B4 to the fan-out wiring area B11 and may be located on the side away from the base of the multiple display leads.

[0084] In some examples, as shown in Figure 1, the folding area B12 may be connected between the fan-out wiring area B11 and the signal access area B13, and the signal access area B13 may be folded to the back of the display area AA. Multiple folding connection lines may be installed in the folding area B12, for example, including multiple data folding connection lines 261, multiple drive folding connection lines (not shown), multiple touch folding connection lines 262, a first power supply folding connection line (not shown), and a second power supply folding connection line (not shown). The first power supply folding connection line may be electrically connected to the first power line, and the second power supply folding connection line may be electrically connected to the second power line. Multiple data folding connection lines 261 may be electrically connected to multiple data lead lines 251, multiple drive folding connection lines may be electrically connected to multiple drive lead lines, and multiple touch folding connection lines 262 may be electrically connected to multiple touch lead lines 252. For example, in the edge region of the fan-out wiring region B11 near the bending region B12, the data bending connection line 261 may be electrically connected to the data lead line 251 via the first relay via V1, and the touch bending connection line 262 may be electrically connected to the touch lead line 252 via the third relay via V3.

[0085] In some examples, as shown in Figure 1, multiple bend connection lines may all extend along the second direction Y. In some examples, multiple bend connection lines may be in the same layer structure. In some examples, multiple touch bend connection lines 262 may be located on opposite sides of the multiple data bend connection lines 261 and the multiple drive bend connection lines in the first direction X. This embodiment is not limited thereto.

[0086] In some examples, as shown in Figure 1, the signal access area B13 may have multiple relay lines, which may include, for example, multiple data relay lines 271 and multiple touch relay lines 272. The multiple data relay lines 271 are electrically connected to multiple data bending connection lines 261, which may be electrically connected in a one-to-one correspondence, for example. The multiple touch relay lines 272 are electrically connected to multiple touch bending connection lines 262, which may be electrically connected in a one-to-one correspondence, for example. For example, in the edge area of ​​the signal access area B13 near the bending area B12, the data relay lines 271 may be electrically connected to the data bending connection lines 261 via a second relay via V2, and the touch relay lines 272 may be electrically connected to the touch bending connection lines 262 via a fourth relay via V4.

[0087] In some examples, as shown in Figure 1, the signal access area B13 may include at least one first signal access area B131 and at least one second signal access area B132. In this example, one first signal access area B131 and one second signal access area B132 are shown as examples. In other examples, the display panel may be a large-size panel and may include multiple first signal access areas B131 and multiple second signal access areas B132, where the multiple first signal access areas B131 may be arranged sequentially along a first direction X, and the multiple second signal access areas B132 may be arranged sequentially along the first direction X. The first signal access area B131 may be located on the side of the second signal access area B132 closer to the display area AA. In other words, the second signal access area B132 may be located on the side of the first signal access area B131 away from the folded area B12 in the second direction Y. In some examples, the signal access area B13 may further include a first circuit area located on the side of the first signal access area B131 closer to the bending area B12, and the first circuit area may contain multiple test circuits (not shown). The test circuits may be electrically connected to multiple data lead lines 251 via data relay lines 271 and data bending connection lines 261, and configured to provide test data signals to multiple data lines DL of the display area AA during the test phase. The first circuit area may include multiple electrostatic discharge circuits to provide electrostatic discharge paths. In this example, the data bending connection line 261 may be electrically connected to the test circuit after being relayed by the data relay line 271, and the data relay line 271 is located on the side of the data bending connection line 261 closer to the base, contributing to the wiring arrangement connected to the test circuit.

[0088] Figure 4 is a schematic local plan view of a first signal access area according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 1 and 4, the first signal access area B131 may also be referred to as a drive chip installation area. A plurality of first pads (bumps) 71 may be installed in the first signal access area B131, and the plurality of first pads 71 ​​may be configured to be bound to at least one drive chip (Integrated Circuit, IC). The drive chip may be configured to generate the drive signals necessary to drive subpixels and to provide the drive signals to the data lines DL of the display area AA. For example, the drive signals may be data signals that drive the subpixels.

[0089] In some examples, as shown in Figures 1 and 4, the multiple first pads 71 ​​in the first signal access area B131 may be electrically connected in a one-to-one correspondence to multiple indicator lead lines. The multiple first pads 71 ​​in the first signal access area B131 may be arranged in multiple rows (e.g., three rows), and the multiple first pads 71 ​​contained in each row may be arranged sequentially along a first direction X, and the multiple rows may be arranged sequentially along a second direction Y. However, this embodiment is not limited to this. In other examples, the first pads in the first signal access area B131 may be arranged in a single row.

[0090] Figure 5 is a schematic local cross-sectional view along the P-P' direction in Figure 4. Figure 5 shows the cross-sectional structure of one first pad 71 as an example. In some examples, as shown in Figures 4 and 5, the first pad 71 may include four pad metal layers that are stacked, for example, a first pad metal layer 711, a second pad metal layer 712, a third pad metal layer 713, and a fourth pad metal layer 714. The first inorganic insulating layer 701 is located on the side of the fourth pad metal layer 714 away from the base 10, so that a portion of the surface of the fourth pad metal layer 714 can be exposed, thereby allowing the fourth pad metal layer 714 to be electrically connected to the pins of the drive chip. The fourth pad metal layer 714 is located on the third source-drain metal layer and may be a single layer with the second relay electrode of the display area. The third pad metal layer 713 is located on the second source-drain metal layer and may be a single layer with the first relay electrode of the display area. The second pad metal layer 712 is located on the first source-drain metal layer and may have the same single-layer structure as the source and drain electrodes of the thin-film transistor in the display area. The first pad metal layer 711 may be located on the first gate metal layer. The first pad metal layer 711 may be electrically connected to the data relay line 271, for example, and may have an integrated structure with the data relay line 271. In another example, the first pad metal layer 711 may be located on the second gate metal layer.

[0091] In some examples, as shown in Figure 5, at least a portion of the first inorganic insulating layer 701 may be located in the gap between adjacent first pads 71. The edges of the fourth pad metal layer 714 of the first pad 71 may be covered by the first inorganic insulating layer 701. In this example, the first inorganic insulating layer 701 and the touch buffer layer 501 of the display area may have the same layer structure. Taking both edges of the fourth pad metal layer 714 in a first direction X as an example, the overlap length between the first inorganic insulating layer 701 and one edge of the fourth pad metal layer 714 in a first direction X may be a first length L1, and the overlap length with the other edge in a first direction X may be a second length L2. For example, the first length L1 and the second length L2 may be approximately the same. For example, the first length L1 and the second length L2 may be greater than 0 and 10 microns or less, for example, 5 microns or more and 10 microns or less. In this example, the first inorganic insulating layer 701 covers the edge of the pad metal layer on the side of the first pad furthest from the base 10 (in this example, the fourth pad metal layer 714), thereby better protecting the first pad and improving the damage to the first pad during the drive chip binding process.

[0092] Figure 6 is a schematic local plan view of a second signal access area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6, the second signal access area B132 may also be referred to as a circuit binding area. A plurality of second pads 72 may be installed in the second signal access area B132. The plurality of second pads 72 may be arranged in a single row, for example, along a first direction X. The plurality of second pads 72 may be configured to be bound to at least one circuit board (e.g., a Flexible Printed Circuit, FPC). For example, the externally connected circuit board may be configured to generate touch signals to provide to the touch structure and to receive touch sensing signals. The plurality of second pads 72 may be electrically connected to a plurality of touch lead lines, or to a first power line and a second power line. In some examples, a plurality of first pads may be electrically connected to a plurality of second pads via a plurality of pin connection lines to transmit signals between the first signal access area and the second signal access area.

[0093] Figure 7 is a schematic local cross-sectional view along the R-R' direction in Figure 6. Figure 7 shows the cross-sectional structure of one second pad 72 as an example. In some examples, as shown in Figures 6 and 7, the second pad 72 may include two pad metal layers that are stacked, for example, a fifth pad metal layer 721 and a sixth pad metal layer 722. The first inorganic insulating layer 701 can expose a portion of the surface of the sixth pad metal layer 722, thereby allowing the sixth pad metal layer 722 to be subsequently bound to a pin on a circuit board. For example, the orthographic projection of the sixth pad metal layer 722 on the base 10 may cover the orthographic projection of the fifth pad metal layer 721 on the base 10, and the edge of the fifth pad metal layer 721 along the first direction X may be covered by the sixth pad metal layer 722. The stacking design of the pad metal layers in this example contributes to ensuring the stability of the stacked structure of the pad. In other examples, the edge of the fifth pad metal layer 721 along the first direction X may be covered by the second flat layer 106, and the sixth pad metal layer 722 may be in direct contact with the surface of the fifth pad metal layer 721 exposed by the second flat layer. In some examples, the sixth pad metal layer 722 is located in the third source-drain metal layer and may be a single layer with the second relay electrode of the display area. The fifth pad metal layer 721 is located in the second source-drain metal layer and may be a single layer with the first relay electrode of the display area.

[0094] In some examples, as shown in Figure 7, at least a portion of the first inorganic insulating layer 701 may be located in the gap between adjacent second pads 72. The edge of the sixth pad metal layer 722 of the second pad 72 may be covered by the first inorganic insulating layer 701. The surface of the sixth pad metal layer 722 exposed by the third flat layer 107 may be in partial contact with the first inorganic insulating layer 701, and the first inorganic insulating layer 701 may cover the edge of the sixth pad metal layer 722 exposed by the third flat layer 107. Taking both edges of the sixth pad metal layer 722 in a first direction X as an example, the overlap length between the first inorganic insulating layer 701 and one edge of the sixth pad metal layer 722 in the first direction X may be a third length L3, and the overlap length with the other edge in the first direction X may be a fourth length L4. The third length L3 and the fourth length L4 may be approximately the same. For example, the third length L3 and the fourth length L4 may be greater than 0 and 10 microns or less, or for example, 5 microns or more and 10 microns or less. In some examples, the third length L3 and the first length L1 may be approximately the same. In this example, the first inorganic insulating layer 701 covers the edge of the pad metal layer on the side of the second pad 72 furthest from the base 10 (in this example, the sixth pad metal layer 722), better protecting the second pad and improving the damage to the second pad during the circuit board binding process.

[0095] Figure 8 is a schematic local plan view of the wiring in the first bezel region according to at least one embodiment of the present disclosure. Figure 9 is a schematic local cross-sectional view along the Q-Q' direction in Figure 8. In some examples, as shown in Figures 8 and 9, the touch lead wire 252 in the fan-out wiring region B11 of the first bezel region may be located in the first or second touch conductive layer. The touch lead wire 252 may be electrically connected to a touch bend connection wire 262 located in the second source-drain metal layer via a third relay via V3 near the bend region B12 of the fan-out wiring region B11. The touch bend connection wire 262 in the bend region B12 may extend to the signal access region B13 and be electrically connected to a touch relay wire 272 located in the third source-drain metal layer via a fourth relay via V4 opened in the second flat layer 106. The touch relay line 272 may extend to the second signal access area B132 and be electrically connected to the second pad 72 of the second signal access area B132. For example, the sixth pad metal layer 722 of the second pad 72 and the touch relay line 272 may be an integrated structure. In this example, the second signal access area B132 may be configured to transport touch control signals and touch sensing signals, but this embodiment is not limited thereto. In other examples, a Touch and Display Driver Integration (TDDI) chip may be installed in the first signal access area, and the touch relay line may be electrically connected to the first pad of the first signal access area.

[0096] In some examples, as shown in Figure 8, the touch bending connection line 262 in the bending region B12 may have a wavy edge, and the touch bending connection line 262 may further have a plurality of hollow sections, which may be arranged in a row along the second direction Y. The shape of the remaining wiring in the bending region B12 may be similar to the shape of the touch bending connection line 262 and will not be described again here. In this example, by setting the edge of the bending connection line in the bending region to be wavy and having hollow sections, the bending stress received by the bending connection line during the bending process can be distributed, stress concentration can be avoided, the risk of crack occurrence in the bending region can be reduced and the bending effect can be improved.

[0097] The manufacturing process of a display panel will be illustrated below with reference to Figures 2 to 9. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, but is not limited to these. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the manufacturing process, the “thin film” is also referred to as a “layer.” If the “thin film” requires a patterning process throughout the manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. Each "layer" after the patterning process contains at least one "pattern".

[0098] As described in this disclosure, “A and B are identical layer structures” means that A and B are formed simultaneously by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display panel. In exemplary embodiments of this disclosure, “the orthographic projection of A includes the orthographic projection of B” or “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0099] In one example, the manufacturing process of a display panel may include the following operations:

[0100] (1) A base is manufactured on the glass carrier plate. In some examples, the base 10 may be a flexible base and may include, for example, a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer that are laminated on the glass carrier plate. The first flexible material layer and the second flexible material layer may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silica (SiOx), etc., to improve the water and oxygen resistance of the base. The first inorganic material layer and the second inorganic material layer may also be called barrier layers, however, this is not limited in this embodiment.

[0101] In some examples, a laminated structure consisting of a first flexible material layer / first barrier layer / second barrier layer / second flexible material layer is used as an example, and its manufacturing process includes the following steps. First, one layer of polyimide is applied to a glass carrier plate, cured, and formed to create the first flexible material layer. Then, one barrier thin film is deposited on the first flexible material layer to form the first barrier layer covering the first flexible layer. Next, another layer of polyimide is applied to the first barrier layer, cured, and formed to create the second flexible material layer. Finally, one barrier thin film is deposited on the second flexible material layer to form the second barrier layer covering the second flexible material layer, completing the manufacturing of base 10.

[0102] (2) A semiconductor layer is fabricated on the base. In some examples, a semiconductor thin film is deposited on the base 10, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer. As shown in Figure 2, the semiconductor layer may be formed in the display region AA and includes at least the active layer 210 of the thin-film transistor 21.

[0103] (3) A first gate metal layer is manufactured on the base. In some examples, a first insulating thin film and a first conductive thin film are sequentially deposited on the base 10 on which the above structure is formed, and the first conductive thin film is patterned by a patterning process to form a first gate insulating layer 101 that covers the semiconductor layer and a first gate metal layer that is installed on the first gate insulating layer 101. As shown in Figures 1, 2 and 5, the first gate metal layer may include at least the first plate 221 of the capacitor 22 located in the display area AA, the gate 213 and several gate lines (not shown) of the thin-film transistor 21, some data lead lines 251 and some drive lead lines (not shown) located in the fan-out wiring area B11 of the first bezel area B1, some data relay lines 271 and some drive control relay lines (not shown) located in the signal access area B13, and a first pad metal layer 711 of at least one first pad 71 located in the first signal access area B131. For example, the data relay line 271 located in the first gate metal layer and the first pad metal layer 711 of the connected first pad 71 may be an integrated structure. The data relay line 271 in the signal access area B13 may be electrically connected to the test circuit.

[0104] (4) A second gate metal layer is fabricated on the base. In some examples, a second insulating thin film and a second conductive thin film are sequentially deposited on the base 10 on which the above structure is formed, and the second conductive thin film is patterned by a patterning process to form a second gate insulating layer 102 and a second gate metal layer. As shown in Figures 1 and 2, the second gate metal layer may include at least the second plate 222 of the capacitor 22 located in the display area AA, some data lead lines 251 and some drive lead lines located in the fan-out wiring area B11, some data relay lines 271 and some drive relay lines located in the signal access area B13, and the first pad metal layer 711 of at least one first pad 71 located in the first signal access area B131. For example, the data relay line 271 located in the second gate metal layer and the first pad metal layer 711 of the connected first pad 71 may be an integrated structure. The data relay line 271 in the signal access area B13 may be electrically connected to a test circuit. In this example, by placing the data relay line 271 in the signal access area B13 on the first or second gate metal layer, access to the test circuit of the data relay line 271 is improved, eliminating the need for film layer change relays and simplifying the wiring design.

[0105] In some examples, multiple data lead lines 251 in the fan-out wiring area B11 may be arranged alternately on the first gate metal layer and the second gate metal layer, thereby reducing crosstalk between adjacent data lead lines 251, improving signal transport performance, and reducing the spacing between adjacent data lead lines, contributing to the realization of a narrow bezel. Similarly, multiple drive lead lines in the fan-out wiring area B11 may be configured to be arranged alternately on the first gate metal layer and the second gate metal layer. Multiple data relay lines in the signal access area B13 may be configured to be arranged alternately on the first gate metal layer and the second gate metal layer. Multiple drive relay lines in the signal access area B13 may be configured to be arranged alternately on the first gate metal layer and the second gate metal layer. However, this embodiment is not limited to this. In other examples, multiple data lead lines in the fan-out wiring area may be installed on the same layer, and multiple drive lead lines may be installed on the same layer. Alternatively, multiple data relay lines in the signal access area may be installed on the same layer, and multiple drive relay lines may be installed on the same layer.

[0106] (5) An interlayer insulating layer is manufactured on the base. In some examples, a third insulating thin film is deposited on the base 10 on which the above structure is formed, and the third insulating thin film is patterned by a patterning process to form an interlayer insulating layer 103. As shown in Figure 2, at least two pixel vias may be opened in the interlayer insulating layer 103 of the display area AA (for example, including a first pixel via and a second pixel via). The interlayer insulating layer 103 in the first and second pixel vias, the second gate insulating layer 102 and the first gate insulating layer 101 may be etched to expose at least a portion of the surface of the first area 2101 and the second area 2102 of the active layer 210, respectively. Multiple contact vias may be opened in the interlayer insulating layer 103 of the first signal access area B131, for example, including a first contact via that exposes at least a portion of the surface of the first pad metal layer 711 of the first pad 71. For example, the interlayer insulating layer 103 and the second gate insulating layer 102 within the first contact via may be removed to expose a portion of the surface of the first pad metal layer 711 located in the first gate metal layer. Alternatively, the interlayer insulating layer 103 within the first contact via may be removed to expose a portion of the surface of the first pad metal layer 711 located in the second gate metal layer.

[0107] (6) A first source-drain metal layer is fabricated on the base. In some examples, a third conductive thin film is deposited on the base 10 on which the above structure is formed, and the third conductive thin film is patterned by a patterning process to form the first source-drain metal layer. As shown in Figures 2, 5 and 7, the first source-drain metal layer may include at least the source pole 211 and drain pole 212 of the thin-film transistor 21 located in the display area AA, and the second pad metal layer 712 of the first pad 71 located in the first signal access area B131. The source pole 211 of the thin-film transistor 21 may be electrically connected to the first area 2101 of the active layer 210 via a first pixel via, and the drain pole 212 may be electrically connected to the second area 2101 of the active layer 210 via a second pixel via. The second pad metal layer 712 of the first pad 71 may be electrically connected to the first pad metal layer 711 via a first contact via opened in the interlayer insulating layer 103. A portion of the second pad metal layer 712 may extend to the surface of the interlayer insulating layer 103 that is away from the base 10.

[0108] (7) A second source-drain metal layer is fabricated on the base. In some examples, a fourth insulating thin film is deposited on the base 10 on which the above structure is formed, then a fifth insulating thin film is applied, and the fifth insulating thin film and the fourth insulating thin film are patterned by a patterning process to form a passivation layer 104 and a first flat layer 105. Then, a fourth conductive thin film is deposited on the base on which the above structure is formed, and the fourth conductive thin film is patterned by a patterning process to form a second source-drain metal layer. As shown in Figures 2, 5, and 7-9, the second source-drain metal layer may include at least a first relay electrode 231 located in the display area AA, a plurality of bend connection lines located in the bend area B12 (e.g., a plurality of data bend connection lines 261 and a plurality of touch bend connection lines 262), a third pad metal layer 713 of the first pad 71 located in the first signal access area B131, and a fifth pad metal layer 721 of the second pad 72 located in the second signal access area B132. The first relay electrode 231 of display area AA may be electrically connected to the drain electrode 212 of the thin-film transistor 21 of the pixel circuit via a third pixel via opened in the first flat layer 105 and the passivation layer 104.

[0109] In some examples, as shown in Figure 5, in the first signal access region B131, the passivation layer 104 may cover the edge of the second pad metal layer 712 and may not overlap with the orthographic projection of the first flat layer 105 and the base of the second pad metal layer 712. However, this embodiment is not limited to this. For example, the edge of the second pad metal layer 712 may be covered by the first flat layer 105, or it may be covered by both the passivation layer 104 and the first flat layer 105. In this example, by using an insulating layer to cover the edge of the pad metal layer, the corrosion resistance of the pad can be increased, which contributes to improving the yield rate of the display panel.

[0110] In some examples, as shown in Figure 5, the third pad metal layer 713 of the first pad 71 may be electrically connected to the second pad metal layer 712 via second contact vias opened in the first flat layer 105 and the passivation layer 104. A portion of the third pad metal layer 713 may extend to the surfaces of the passivation layer 104 and the first flat layer 105 on the side away from the base 10. For example, the orthographic projection of the third pad metal layer 713 on the base 10 may cover the orthographic projection of the second pad metal layer 712 on the base 10.

[0111] In this example, all of the multiple bent connection lines in the bent region B12 are located in the second source-drain metal layer and may be electrically connected to the corresponding wiring in the fan-out wiring region and the signal access region via relay vias. In this example, by placing all the wiring in the bent region in the second source-drain metal layer, it is possible to reduce the deformation of the wiring in the bent region and ensure the signal transport performance of the wiring in the bent region.

[0112] In some examples, before forming the second source-drain metal layer, the bending region B12 may include a first gate insulating layer 101, a second gate insulating layer 102, an interlayer insulating layer 103, a passivation layer 104, and a first flat layer 105, which are laminated on the base 10. Two etching processes may form a first groove and a second groove within the bending region B12. For example, the first mask (Etch Bending A MASK, EBA MASK) etches the first flat layer 105 and the passivation layer 104 of the bending region B12 to form a first groove and expose the surface of the interlayer insulating layer 103. The second mask (Etch Bending B MASK, EBB MASK) etches the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first groove in the bending region B12 to expose the surface of the base 10. Furthermore, for example, after forming the passivation layer 104, the passivation layer 104 in the bending region B12 is etched with a first mask, and then the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the bending region B12 are etched with a second mask. Then, the first flat layer 105 is filled into the groove formed in the bending region B12, and multiple bending connection lines in the bending region B12 may be located in the first flat layer 105. However, this is not limited in this embodiment. In this example, grooves can be carved in the bending region B12 using EBA MASK and EBB MASK, reducing the thickness of the inorganic insulating layer in the bending region B12 and enhancing the bending effect.

[0113] (8) A third source-drain metal layer is fabricated on the base. In some examples, a sixth insulating thin film is applied to the base on which the above structure is formed, and the sixth insulating thin film is patterned by a patterning process to form a second flat layer 106. Then, a fifth conductive thin film is deposited on the base on which the above structure is formed, and the fifth conductive thin film is patterned by a patterning process to form a third source-drain metal layer. Then, a seventh insulating thin film is applied, and the seventh insulating thin film is patterned by a patterning process to form a third flat layer 107.

[0114] In some examples, as shown in Figures 2, 5, 7, and 9, the third source-drain metal layer may include at least a second relay electrode 232 located in display area AA, a fourth pad metal layer 714 of the first pad 71 located in the first signal access area B131, a sixth pad metal layer 722 of the second pad 72 located in the second signal access area B132, and a touch relay line 272 in the signal access area B13. The second relay electrode 232 in display area AA may be electrically connected to the first relay electrode 231 via a fourth pixel via opened in the second flat layer 106.

[0115] In some examples, as shown in Figure 5, the second flat layer 106 may cover the edge of the third pad metal layer 713 in the first signal access region B131. The fourth pad metal layer 714 may be electrically connected to the third pad metal layer 713 located in the second source-drain metal layer via a third contact via opened in the second flat layer 106. A portion of the fourth pad metal layer 714 may extend to the surface of the second flat layer 106 on the side away from the base 10. For example, the orthographic projection of the fourth pad metal layer 714 on the base 10 may cover the orthographic projection of the third pad metal layer 713 on the base 10.

[0116] In some examples, as shown in Figures 7 and 9, the touch bend connection line 262 may extend into the signal access area B13 and be electrically connected to the touch relay line 272 located in the third source-drain metal layer via a fourth relay via V4 opened in the second flat layer 106. The touch relay line 272 may extend into the second signal access area B132 and be electrically connected to the second pad 72 in the second signal access area B132. The touch relay line 272 and the sixth pad metal layer 722 of the connecting second pad 72 may be an integrated structure.

[0117] To date, the manufacturing of the circuit structure layer of display area AA, the base of the first pad 71 of the first signal access area, and the base of the second pad 72 of the second signal access area has been completed. In this example, the first pad 71 includes four pad metal layers, and the second pad 72 also includes four pad metal layers. By forming the pads with multiple pad metal layers, it is possible to reduce the resistance of the pads and improve the signal transport performance of the pads.

[0118] In some examples, the first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, for example, one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single layers, multiple layers, or composite layers. The first flat layer 105, the second flat layer 106, and the third flat layer 107 may be organic insulating layers, for example, organic materials such as polyimide, acrylic, or polyethylene terephthalate may be used. The first gate metal layer and the second gate metal layer may be metallic materials, for example, one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and may be single-layer structures. For example, the first gate metal layer and the second gate metal layer may each include a Mo metal layer. The first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer may be made of one or more metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer or multi-layer composite structures, such as Ti / Al / Ti. For example, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer may be made of a three-layer stacked structure of Ti / Al / Ti. The semiconductor layer may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium-zinc-tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene. In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology. This is not limited to these embodiments.

[0119] (9) A light-emitting structure layer is manufactured on the base. In some examples, a transparent conductive thin film is deposited on the base 10 on which the above structure is formed, and the transparent conductive thin film is patterned by a patterning process to form a pattern for the first electrode 301 of the light-emitting element. A pixel definition thin film is applied to the base 10 on which the above structure is formed, and a pattern for the pixel definition layer (PDL) 304 is formed by a masking, exposure and development process. As shown in Figure 2, a pixel aperture is opened in the pixel definition layer 304 of the display area AA, and the pixel definition thin film within the pixel aperture is removed by development to expose at least a portion of the surface of the first electrode 301. For example, the pixel definition layer 304 may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate.

[0120] Then, an organic light-emitting layer 302 and a second electrode 303 are sequentially formed on the base 10 on which the above pattern is formed. As shown in Figure 2, the organic light-emitting layer 302 may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed within the pixel aperture of the display area AA, realizing a connection between the organic light-emitting layer 302 and the first electrode 301. Since the first electrode 301 is connected to the drain electrode 212 of the thin-film transistor 21, light emission control of the organic light-emitting layer 302 is realized. A part of the second electrode 303 may be formed on the organic light-emitting layer 302. After the light-emitting structure layer 30 is formed on the display area AA, the film layer structure of the first pad 71 of the first signal access area and the second pad 72 of the second signal access area is not changed.

[0121] (10) A sealing structure layer is manufactured. In some examples, a sealing structure layer 40 is formed on the base 10 on which the above pattern is formed. As shown in Figure 2, the sealing structure layer 40 may be formed in the display area AA, or a laminated structure of inorganic material / organic material / inorganic material may be adopted. The organic material layer may be placed between two inorganic material layers. After forming the sealing structure layer 40, the film layer structure of the first pad 71 of the first signal access area and the second pad 72 of the second signal access area is not changed.

[0122] (11) A touch structure layer is manufactured. In some examples, a first inorganic insulating thin film 701' is deposited on the base 10 on which the above structure is formed. In some examples, the first inorganic insulating thin film 701' may be an inorganic insulating material, for example, one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layer. In some examples, the thickness of the first inorganic insulating thin film 701' may be 1500 to 3000 angstroms, for example, about 2000 angstroms. The first inorganic insulating thin film 701' may form a touch buffer layer 501 in the display area, or it may form a first inorganic insulating layer 701 in the first bezel area. In this example, the touch buffer layer and the first inorganic insulating layer have the same layer structure. However, this embodiment is not limited to this. In other examples, the first inorganic insulating layer may be located on the side closer to the base of the touch buffer layer, or on the side further away from the base of the touch buffer layer.

[0123] Figure 10A is a schematic local cross-sectional view of a first signal access region after the formation of a first inorganic insulating thin film according to at least one embodiment of the present disclosure. Figure 10B is a schematic local cross-sectional view of a second signal access region after the formation of a first inorganic insulating thin film according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 10A and 10B, the first inorganic insulating thin film 701' may cover the fourth pad metal layer 714 of the first pad 71 of the first signal access region, and may cover the sixth pad metal layer 722 of the second pad 72 of the second signal access region. In this example, by using the first inorganic insulating thin film 701' during the manufacturing process to cover the surfaces of the first pad 71 and the second pad 72 away from the base, the first pad 71 and the second pad 72 can be protected in subsequent manufacturing processes, and the corrosion of the pads in subsequent manufacturing processes can be improved.

[0124] Then, a first touch conductive thin film is deposited, and the first touch conductive thin film is patterned by a patterning process to form a first touch conductive layer 511 on the touch buffer layer 501. For example, the first touch conductive layer 511 may include at least a first touch electrode, a second touch electrode, and a first connection portion located in the display area AA.

[0125] Then, a touch interlayer insulating thin film is applied, and the touch interlayer insulating thin film is patterned by a patterning process to form a touch interlayer insulating layer 502 that covers the first touch conductive layer. In some examples, the touch interlayer insulating layer 502 may be an organic insulating layer, and organic materials such as polyimide, acrylic, or polyethylene terephthalate may be used.

[0126] Then, a second touch conductive thin film is deposited and patterned by a patterning process to form a second touch conductive layer 512 on the intertouch insulating layer 502. For example, the second touch conductive layer 512 may include at least a second connection located in the display area AA. In some examples, the touch electrode and connection may be in the form of a metal mesh. In some examples, the first touch conductive layer 511 and the second touch conductive layer 512 may be made of one or more metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and may be in a single-layer or multi-layer structure.

[0127] In some examples, the first touch conductive layer, the second touch conductive layer, and the intertouch insulating layer of the first signal access region B131 and the second signal access region B132 may be removed. For example, after manufacturing the touch structure layer, the first signal access region B131 may include a first pad 71 placed on the base 10 and a first inorganic insulating thin film 701' covering the first pad 71, and the second signal access region B132 may include a second pad 72 placed on the base 10 and a first inorganic insulating thin film 701' covering the second pad 72.

[0128] (12) A color filter layer is manufactured. In some examples, a color film buffer thin film is applied to the base 10 on which the above structure is formed, and the color film buffer thin film is patterned by a patterning process to form a color film buffer layer 601. To avoid affecting subsequent processes, the color film buffer layer 601 in the first signal access region and the second signal access region may be removed. In some examples, the color film buffer layer 601 may be an organic insulating layer, and organic materials such as polyimide, acrylic, or polyethylene terephthalate may be used.

[0129] Then, a black pigment is applied, or a black chromium (Cr) thin film is deposited, and the black pigment or black chromium thin film is patterned by a patterning process to form a pattern of the black matrix 610 in the display area AA. Then, multiple filter units 611 of different colors are sequentially formed in the display area AA. For example, the multiple filter units may include multiple red filter units, multiple blue filter units, and multiple green filter units. Taking the formation of a red filter unit as an example, first, a red resin is applied to the structure in which the black matrix is ​​formed, and after baking and solidification, the red filter unit is formed by masking, exposure, and development. The formation processes for the green filter unit and the blue filter unit are similar and will not be described again here. The color film buffer layer 601 of the color filter layer, the black matrix 610, and the filter units are not installed in the first signal access area B131 and the second signal access area B132. In other words, the orthographic projection of the color film buffer layer 601, the black matrix 610, and the filter units on the base does not have to overlap with the first signal access area B131 and the second signal access area B132.

[0130] Then, a protective thin film is applied, and the protective thin film is patterned by a patterning process to form a color film protective layer 602. The color film protective layer 602 in the first signal access region and the second signal access region may be removed to expose the surface of the first inorganic insulating thin film 701'. In some examples, the color film protective layer 602 may be an organic insulating layer, and an organic material such as polyimide (PI) may be used.

[0131] (13) Etching the first inorganic insulating thin film. In some examples, a patterning process is used to pattern the first inorganic insulating thin film 701' exposed by the color film protective layer 602 to form the first inorganic insulating layer 701 of the first bezel region. The first inorganic insulating thin film 701' of a portion of the first signal access region B131 and the second signal access region B132 may be etched to expose at least a portion of the surface of the fourth pad metal layer 714 of the first pad 71 of the first signal access region B131 and at least a portion of the surface of the sixth pad metal layer 722 of the second pad 72 of the second signal access region B132.

[0132] In some examples, as shown in Figure 5, the first inorganic insulating layer 701 may be located in the gap between adjacent fourth pad metal layers 714 of the first pad 71. The first inorganic insulating layer 701 may be in direct contact with the surface of the fourth pad metal layer 714 of the first pad 71 that is away from the base 10, and the edge of the fourth pad metal layer 714 of the first pad 71 may be covered by the first inorganic insulating layer 701. The overlap length between one side edge of the fourth pad metal layer 714 of the first pad 71 and the first inorganic insulating layer 701 may be greater than 0 and 10 microns or less, for example, 5 microns or more and 10 microns or less. In this example, the first pad 71 can be effectively protected by using the first inorganic insulating layer 701 to provide edge coverage for the first pad 71.

[0133] In some examples, as shown in Figure 7, the first inorganic insulating layer 701 may be located in the gap between the sixth pad metal layers 722 of the adjacent second pad 72. The first inorganic insulating layer 701 may be in direct contact with the surface of the sixth pad metal layer 722 of the second pad 72 that is away from the base 10, and a portion of the edge of the sixth pad metal layer 722 of the second pad 72 may be covered by the first inorganic insulating layer 701. The overlap length between one side edge of the sixth pad metal layer 722 of the second pad 72 and the first inorganic insulating layer 701 may be greater than 0 and 10 microns or less, for example, 5 microns or more and 10 microns or less. In this example, the second pad 72 can be effectively protected by using the first inorganic insulating layer 701 to provide edge coverage for the second pad 72.

[0134] In this example, both the touch insulating layer 502 of the touch structure layer and the color film buffer layer 601 of the color filter layer can be manufactured using organic materials, contributing to improved bending resistance of the display panel. For example, the bending radius can be increased by more than 60%, contributing to the improvement of crack problems in reliability testing of the display panel.

[0135] In the manufacturing process of the display panel in this example, since all of the multiple film layers of the color filter layer are organic film layers, multiple development processes are required during the manufacturing process. If the surfaces of the first and second pads that are separated from the base are not protected, there is a risk that the surfaces of the first and second pads that are separated from the base will be corroded during the manufacturing process. For example, if the metal layers of the first and second pads employ a Ti / Al / Ti three-layer laminated structure, after the Al film layer is corroded during the manufacturing process, the Ti film layer is pushed and stretched by conductive ions during the binding process, causing the Ti film layers of adjacent pads to connect and form binding lines, or, due to voids caused by the corrosion of the Al film layer, the conductive ions are not broken down, causing defects such as dark lines and binding misalignment. In this example, by protecting the first and second pads using a first inorganic insulating thin film made of inorganic material during the manufacturing process, corrosion of the metal layers of the first and second pads during the manufacturing process of the touch structure layer and color filter layer can be prevented. For subsequent binding connections, after the color filter layer is manufactured, the first inorganic insulating thin film is etched to expose the surfaces of the first and second pads that are separated from the base. Since the organic film layer cannot be etched through by dry etching, only the first inorganic insulating thin film is used in the manufacturing process to cover the first and second pads. By removing both the organic film layers that are separated from the first and second pads in the first and second signal access areas, etching of the first inorganic insulating thin film covering the first and second pads is reduced, simplifying the process and improving the yield rate of the display panel. Furthermore, the wiring in the signal access area in this example may be installed on the same layer as one or more display area metal layers in the circuit structure layer, and it is not necessary to install wiring in the signal access area on the same layer as the first and second touch conductive layers. By reducing the wiring film layer in the signal access area, short circuits due to gaps, foreign matter, or metal residue (remain) between adjacent wirings in the signal access area can be avoided.

[0136] After the manufacturing of the above-mentioned film layer structure is completed, the display panel can be peeled off from the glass carrier plate by a peeling process.

[0137] The manufacturing process in this example can be implemented using currently mature manufacturing equipment, requires minimal changes from conventional processes, is highly compatible with conventional manufacturing processes, is easy to implement, is easy to carry out, has high production efficiency, low production costs, and a high yield rate.

[0138] The structure and manufacturing process of the display panel in this example are merely illustrative. In some examples, the corresponding structure can be modified or the patterning process can be increased or decreased according to actual demand. For example, the passivation layer on the side away from the base of the first source-drain metal layer may be omitted, and the edge of the second pad metal layer located on the first source-drain metal layer of the first pad may be covered by the first flat layer. Also, for example, the first inorganic insulating layer of the first bezel region and the first or third sealing layer made of inorganic material of the sealing structure layer of the display region may have the same layer structure. However, this embodiment is not limited to this.

[0139] Figure 11A is a schematic local section of a first signal access area according to at least one embodiment of the present disclosure. Figure 11A may be a schematic local section along the P-P' direction in Figure 4. Figure 11B is a schematic local section of a second signal access area according to at least one embodiment of the present disclosure. Figure 11B may be a schematic local section along the R-R' direction in Figure 6. In some examples, as shown in Figure 11A, the first pad 71 may include four pad metal layers that are stacked, for example, a first pad metal layer 711, a second pad metal layer 712, a third pad metal layer 713, and a fourth pad metal layer 714. The fourth pad metal layer 714 may be located in the third source-drain metal layer. The edges of the fourth pad metal layer 714 are not covered by the first inorganic insulating layer 701. The first inorganic insulating layer 701 may be located in the gap between adjacent first pads 71. The first inorganic insulating layer 701 and the orthographic projection of the fourth pad metal layer 714 of the first pad 71 on the base 10 do not have to overlap. The third flat layer 107 may be in contact with the edge of the fourth pad metal layer 714, or the edge of the fourth pad metal layer 714 may be covered by the third flat layer 107. In this example, an organic film layer (e.g., the third flat layer 107) may be used to protect the pad metal layer on the side of the first pad furthest from the base (in this example, the fourth pad metal layer 714).

[0140] In some examples, as shown in Figure 11B, the second pad 72 may include two laminated pad metal layers, for example, a fifth pad metal layer 721 and a sixth pad metal layer 722. The sixth pad metal layer 722 may be located on the third source-drain metal layer. The edge of the sixth pad metal layer 722 is not covered by the first inorganic insulating layer 701. The first inorganic insulating layer 701 may be located in the gap between adjacent second pads 72. The first inorganic insulating layer 701 and the orthographic projection of the sixth pad metal layer 722 on the base 10 of the second pad 72 do not have to overlap. The third flat layer 107 may cover the edge of the sixth pad metal layer 722. In this example, the second pad may be protected by using an organic film layer (e.g., the third flat layer 107) to cover the edge of the pad metal layer furthest from the base of the second pad (in this example, the sixth pad metal layer 722). In other examples, the first inorganic insulating layer 701 and the third flat layer 107 do not necessarily overlap with the orthographic projection of the surface of the sixth pad metal layer 722 exposed by the first inorganic insulating layer 701 and the third flat layer 107 on the base 10. The first inorganic insulating layer 701 may partially overlap with the orthographic projection of the sixth pad metal layer 722 covered by the third flat layer 107 on the base 10.

[0141] The remaining structure of the display panel in this example can be found in the description of the above embodiment, so it will not be explained again here.

[0142] Figure 12 is another schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 12 shows a schematic plan view of the display panel before the bending process is performed. Figure 13 is a schematic local plan view of the wiring in the first bezel region in Figure 12. Figure 14 is a schematic local cross-sectional view along the U-U' direction in Figure 13.

[0143] In some examples, as shown in Figure 12, the display panel may include a display area AA and a peripheral area BB surrounding the display area AA. The first bezel area B1 may include a fan-out wiring area B11, a bend area B12, and a signal access area B13, which are sequentially installed along the direction away from the display area AA. In this example, the multiple display area metal layers of the display structure layer of the display area AA may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer.

[0144] In some examples, as shown in Figures 12 to 14, the touch lead wire 252 in the fan-out wiring area B11 of the first bezel region may be located in the first or second touch conductive layer. The touch lead wire 252 may be electrically connected to a touch bending connection wire 262 located in the second source-drain metal layer via a third relay via V3 near the bending area B12 of the fan-out wiring area B11. The touch bending connection wire 262 may extend into the signal access area B13 and be electrically connected to a touch relay wire 272. In this example, the touch bending connection wire 262 and the touch relay wire 272 may be an integrated structure and located in the second source-drain metal layer. The touch relay wire 272 may extend into the second signal access area B132 and be electrically connected to the second pad 72 of the second signal access area B132. For example, the touch relay wire 272 and the fifth pad metal layer 721 of the second pad 72 may be an integrated structure. The sixth pad metal layer 722 of the second pad 72 is located in the third source-drain metal layer and may be in contact with the fifth pad metal layer 721 via contact vias opened in the second flat layer 106.

[0145] In this example, the touch bend connection line 262 and the touch relay line 272 do not need to be electrically connected via a fourth relay via in the signal access area, and the installation of the fourth relay via can be omitted, saving the hole-making process and simplifying the manufacturing process.

[0146] The structure of the display area in this example, and the film layer structure of the first and second pads, can be found in the description of the above embodiment, so they will not be explained again here.

[0147] Figure 15 is a schematic diagram of another local cross-section along the U-U' direction in Figure 13. In some examples, as shown in Figures 12, 13, and 15, the multiple display area metal layers of the display structure layer in display area AA may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. The multiple bending connection lines of the bending area B12 in this example may all be located in the third source-drain metal layer, but this is not limited to this embodiment. In other examples, the multiple bending connection lines of the bending area may all be located in the first source-drain metal layer.

[0148] In some examples, as shown in Figures 13 and 15, the touch lead wire 252 in the fan-out wiring area B11 of the first bezel region may be located in the first or second touch conductive layer. The touch lead wire 252 may be electrically connected to a touch bending connection wire 262 located in the third source-drain metal layer via a third relay via V3 near the bending area B12 of the fan-out wiring area B11. The touch bending connection wire 262 may extend into the signal access area B13 and be electrically connected to a touch relay wire 272. In this example, the touch bending connection wire 262 and the touch relay wire 272 may be an integrated structure and located in the third source-drain metal layer. The touch relay wire 272 may extend into the second signal access area B132 and be electrically connected to the second pad 72 of the second signal access area B132. For example, the touch relay wire 272 and the sixth pad metal layer 722 of the second pad 72 may be an integrated structure. The sixth pad metal layer 722 of the second pad 72 is located on the third source-drain metal layer and may be in contact with the fifth pad metal layer 721 via contact vias opened in the second flat layer 106. The fifth pad metal layer 721 may be located on the second source-drain metal layer.

[0149] The structure of the display area in this example, and the film layer structure of the first and second pads, can be found in the description of the above embodiment, so they will not be explained again here.

[0150] Figure 16 is a schematic local cross-section of another display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 16 shows the structure of one subpixel of the display area as an example. In some examples, as shown in Figure 16, the display area of ​​the display panel may include a base 10 and, in a direction perpendicular to the display panel, circuit structure layers 20, light-emitting structure layer 30, sealing structure layer 40, touch structure layer 50 and color filter layer 60 sequentially installed on the base 10. The circuit structure layers 20 of the display area may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer installed on the base 10. A first gate insulating layer 101 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be provided between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first flat layer 105 may be provided between the first source-drain metal layer and the second source-drain metal layer, and a second flat layer 106 may be provided on the side of the second source-drain metal layer away from the base 10. In this example, the drain electrode 212 of the thin-film transistor 21 of the pixel circuit may be electrically connected to the first electrode 301 of the light-emitting element via a first relay electrode 231 located in the second source-drain metal layer. The multiple display area metal layers of the display structure layer in this example may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. The remaining film layers of the display panel in this example will not be described again here, as they can be found in the description of the above embodiment.

[0151] In some examples, as shown in Figures 12 and 13, the touch lead wire 252 may be electrically connected to a touch bend connection wire 262 located in the second source-drain metal layer via a third relay via V3 near the bend area B12 of the fan-out wiring area B11. The touch bend connection wire 262 may extend into the signal access area B13 and be electrically connected to a touch relay wire 272. In this example, the touch bend connection wire 262 and the touch relay wire 272 may be an integrated structure and may be located, for example, in the second source-drain metal layer.

[0152] Figure 17 is a schematic local section of a signal access area according to at least one embodiment of the present disclosure. Figure 17 may be a schematic local section along the U-U' direction in Figure 13. In some examples, as shown in Figure 17, the touch bend connection line 262 and the touch relay line 272 may be an integrated structure and may be located in the second source-drain metal layer. The touch relay line 272 and the sixth pad metal layer 722 of the second pad 72 of the second signal access area may be an integrated structure. The fifth pad metal layer 721 of the second pad 72 may be located in the first source-drain metal layer. The sixth pad metal layer 722 of the second pad 72 may be electrically connected to the fifth pad metal layer 722 via contact vias opened in the passivation layer 104 and the first flat layer 105. For example, the orthographic projection of the sixth pad metal layer 722 of the second pad 72 on the base 10 may cover the orthographic projection of the fifth pad metal layer 721 on the base 10.

[0153] Figure 18A is a schematic local section of a first signal access area according to at least one embodiment of the present disclosure. Figure 18A may be a schematic local section of a first pad along the P-P' direction in Figure 4. Figure 18B is a schematic local section of a second signal access area according to at least one embodiment of the present disclosure. Figure 18B may be a schematic local section of a second pad along the R-R' direction in Figure 6.

[0154] In some examples, as shown in Figure 18A, the first pad 71 of the first signal access region may include three stacked pad metal layers, for example, a first pad metal layer 711, a second pad metal layer 712, and a third pad metal layer 713. The third pad metal layer 713 may be located on the second source-drain metal layer, the second pad metal layer 712 may be located on the first source-drain metal layer, and the first pad metal layer 711 may be located on the first gate metal layer. The first inorganic insulating layer 701 may be located in the gap between adjacent first pads, and the first inorganic insulating layer 701 may cover the edge of the third pad metal layer 713. In other examples, the first pad metal layer 711 may be located on the second gate metal layer. This embodiment is not limited thereto.

[0155] In some examples, as shown in Figure 18B, the second pad 72 of the second signal access region may include two stacked pad metal layers, for example, a fifth pad metal layer 721 and a sixth pad metal layer 722. The first inorganic insulating layer 701 may be located in the gap between adjacent second pads, and the first inorganic insulating layer 701 may cover the edge of the sixth pad metal layer 722. For example, the first inorganic insulating layer 701 may cover the edge of the sixth pad metal layer 722 that is exposed by the second flat layer 106. In this example, the sixth pad metal layer 722 may be located on the second source-drain metal layer, and the fifth pad metal layer 721 may be located on the first source-drain metal layer.

[0156] The remaining structure of the display panel in this example can be found in the description of the above embodiment, so it will not be explained again here.

[0157] Figure 19A is a schematic local section of a first signal access area according to at least one embodiment of the present disclosure. Figure 19A may be a schematic local section of a first pad along the P-P' direction in Figure 4. Figure 19B is a schematic local section of a second signal access area according to at least one embodiment of the present disclosure. Figure 19B may be a schematic local section of a second pad along the R-R' direction in Figure 6.

[0158] In some examples, as shown in Figure 19A, the first pad 71 of the first signal access region may include three stacked pad metal layers, for example, a first pad metal layer 711, a second pad metal layer 712, and a third pad metal layer 713. The first inorganic insulating layer 701 may be located in the gap between adjacent first pads 71. The orthographic projection of the first inorganic insulating layer 701 and the third pad metal layer 713 on the base does not have to overlap. The third pad metal layer 713 may be located in the second source-drain metal layer, the second pad metal layer 712 may be located in the first source-drain metal layer, and the first pad metal layer 711 may be located in the first gate metal layer. In other examples, the first pad metal layer 711 may be located in the second gate metal layer. This embodiment is not limited thereto.

[0159] In some examples, as shown in Figure 19B, the second pad 72 of the second signal access region may include two stacked pad metal layers, for example, a fifth pad metal layer 721 and a sixth pad metal layer 722. The first inorganic insulating layer 701 may be located in the gap between adjacent second pads 72. The orthographic projection of the first inorganic insulating layer 701 and the sixth pad metal layer 722 on the base does not have to overlap. The sixth pad metal layer 722 may be located on the second source-drain metal layer, and the fifth pad metal layer 721 may be located on the first source-drain metal layer. In other examples, the orthographic projection of the surface of the sixth pad metal layer 722 exposed by the first inorganic insulating layer 701 and the second flat layer 106 on the base 10 does not have to overlap. The first inorganic insulating layer 701 may partially overlap with the orthographic projection of the sixth pad metal layer 722 on the base 10 covered by the second flat layer 106.

[0160] The remaining structure of the display panel in this example can be found in the description of the above embodiment, so it will not be explained again here.

[0161] Figure 20 is a schematic cross-sectional view of a signal access area according to at least one embodiment of the present disclosure. Figure 20 may be a schematic cross-sectional view of another area along the U-U' direction in Figure 13. Figure 21 is a schematic cross-sectional view of another area of ​​a second signal access area according to at least one embodiment of the present disclosure. Figure 21 may be a schematic cross-sectional view of a second pad along the R-R' direction in Figure 6. Figure 22 is a schematic cross-sectional view of another area of ​​a second signal access area according to at least one embodiment of the present disclosure. Figure 22 may be a schematic cross-sectional view of a second pad along the R-R' direction in Figure 6. The multiple display area metal layers of the display structure layer in this example may include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer.

[0162] In some examples, as shown in Figures 20 and 21, the touch bending connection line 262 and the touch relay line 272 may be an integrated structure and may be located in the second source-drain metal layer. The touch relay line 272 and the fifth pad metal layer 721 of the second pad 72 of the second signal access area may be an integrated structure. The second pad 72 of the second signal access area may include one pad metal layer, for example, the fifth pad metal layer 721. As shown in Figure 21, the first inorganic insulating layer 701 may be located in the gap between adjacent second pads 72 and may cover the edge of the fifth pad metal layer 721. As shown in Figure 22, the first inorganic insulating layer 701 may be located in the gap between adjacent second pads 72 and may not overlap with the orthographic projection at the base of the fifth pad metal layer 721.

[0163] The remaining structure of the display panel in this example and the structure of the first pad in the first signal access area can be found in the description of the embodiment above, so they will not be explained again here. You may also refer to the descriptions in Figures 18A and 19A for the structure of the first pad in the first signal access area.

[0164] Figure 23 is a schematic local cross-sectional view of another display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 23 shows the structure of one subpixel of the display area as an example. In some examples, as shown in Figure 23, the display area of ​​the display panel may include a base 10 and, in a direction perpendicular to the display panel, circuit structure layers 20, light-emitting structure layers 30, sealing structure layers 40, touch structure layers 50 and color filter layers 60 sequentially installed on the base 10. The circuit structure layers 20 of the display area may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer installed on the base 10. The touch structure layers 50 may include a stacked touch buffer layer 501 and a first touch conductive layer 511. A self-capacitive touch structure can be integrated into the display panel of this example to form an FSLOC structure. The structure of the first pad in the first signal access area and the structure of the second pad in the second signal access area of ​​the display panel in which the FSLOC structure is integrated in this example may be substantially the same as the structure of the first and second pads of the display panel in which the FMLOC structure is integrated, so they will not be explained again here.

[0165] This embodiment further provides a display panel comprising a base, a display structure layer, a touch structure layer, a color filter layer, and a plurality of pads. The base includes a display area and a first bezel area located on one side of the display area. The display structure layer is located at the base of the display area, the touch structure layer is located on the side of the display structure layer away from the base, and the color filter layer is located on the side of the touch structure layer away from the base. The plurality of pads are located in the first bezel area. The orthographic projections of the touch structure layer and the color filter layer on the base do not overlap with the orthographic projections of the plurality of pads on the base.

[0166] In some exemplary embodiments, the display panel further comprises a first inorganic insulating layer located in the first bezel region, the first inorganic insulating layer located on the side of the plurality of pads away from the base, and the first inorganic insulating layer exposing at least a portion of the surface of the plurality of pads away from the base. The touch structure layer includes a touch buffer layer, a first touch conductive layer, an inter-touch insulating layer, and a second touch conductive layer, which are sequentially laminated on the side away from the base. The first inorganic insulating layer and the touch buffer layer have the same layer structure.

[0167] In some exemplary embodiments, at least one of the plurality of pads includes at least one pad metal layer. The first bezel region includes a first signal access region and a second signal access region, the second signal access region being located on the side of the first signal access region away from the display region. The plurality of pads includes a plurality of first pads located in the first signal access region and a plurality of second pads located in the second signal access region. The number of pad metal layers of at least one first pad among the plurality of first pads is greater than the number of pad metal layers of at least one second pad among the plurality of second pads.

[0168] The details of the display panel in this example can be found in the description of the above embodiment, so they will not be explained again here.

[0169] Embodiments of this disclosure further provide a method for manufacturing a display panel, comprising: providing a base, the base including a display area and a first bezel area located on one side of the display area; forming a display structure layer in the display area; forming a plurality of pads in the first bezel area, the display structure layer including a plurality of display area metal layers, at least one of the plurality of pads including at least one pad metal layer; forming a touch structure layer on the side of the display structure layer away from the base; and forming a first inorganic insulating layer in the first bezel area. The first inorganic insulating layer is located on the side of the plurality of pads away from the base and exposes at least a portion of the surface of the pad metal layers that are separated from the base of the plurality of pads. The pad metal layer exposed by the first inorganic insulating layer of at least one pad and the display area metal layer of one of the plurality of display area metal layers of the display structure layer have the same layer structure.

[0170] In some exemplary embodiments, forming a first inorganic insulating layer in the first bezel region includes, after forming a display structure layer, depositing a first inorganic insulating thin film covering a plurality of pads in the first bezel region, and, after forming a touch structure layer, etching the first inorganic insulating thin film to form the first inorganic insulating layer.

[0171] In some exemplary embodiments, the manufacturing method further comprises forming a color filter layer on the side away from the base of the touch structure layer after forming the touch structure layer and before etching the first inorganic insulating thin film, wherein the color filter layer comprises a color film buffer layer, a black matrix, a plurality of filter units and a color film protective layer, which are sequentially installed on the side away from the base, and both the color film buffer layer and the color film protective layer are organic insulating layers.

[0172] The method for manufacturing the display panel according to this embodiment can be found in the description of the embodiment above, so it will not be explained again here.

[0173] Figure 24 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 24, this embodiment provides a display device 91 comprising a display panel 910 of the above embodiment. In some examples, the display panel 910 may be an OLED display panel with an integrated touch structure. The display device 91 may be a product or component with display and touch functions such as a mobile phone, tablet, television, monitor, laptop, digital frame, or navigator.

[0174] The drawings in this disclosure relate only to the structures relating to this disclosure; for other structures, conventional designs may be referenced. Where there is no conflict, new embodiments can be obtained by combining the embodiments and features of the embodiments in this disclosure. Modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, as can be understood by those skilled in the art. Any such modifications or equivalent substitutions should be included within the scope of the claims of this disclosure. [Explanation of Symbols]

[0175] AA display area BB surrounding area B1 First bezel area B2 Second bezel area B3 Third bezel area B4 4th bezel area 10 base 20 circuit structure layers 30. Luminescent structural layer 40 Sealing structure layer 50 Touch Structure Layers 60 color filter layers 71, 72 pads 701 First Inorganic Insulating Layer 711 First pad metal layer 712 Second pad metal layer 713 Third pad metal layer 714 Fourth pad metal layer

Claims

1. A display panel comprising a base, a display structure layer, a touch structure layer, a plurality of pads, and a first inorganic insulating layer, The base includes a display area and a first bezel area located on one side of the display area. The display structure layer is located at the base of the display area and includes a plurality of display area metal layers. The touch structure layer is located on the side away from the base of the display structure layer. The plurality of pads are located in the first bezel region, and at least one of the plurality of pads includes at least one pad metal layer. The first inorganic insulating layer is located in the first bezel region and on the side of the plurality of pads away from the base, and the first inorganic insulating layer exposes at least a portion of the surface of the pad metal layer of the plurality of pads that is separated from the base. The display panel wherein the pad metal layer exposed by the first inorganic insulating layer of at least one pad and one of the display area metal layers of the display structure layer have the same layer structure.

2. The display panel according to claim 1, wherein the pad metal layer exposed by the first inorganic insulating layer of at least one pad comprises a laminated structure of at least two types of metal materials.

3. The display panel according to claim 2, wherein the pad metal layer exposed by the first inorganic insulating layer of at least one pad includes a titanium-aluminum-titanium triple-layer structure.

4. The display panel according to any one of claims 1 to 3, wherein the first inorganic insulating layer covers the edge of the pad metal layer exposed by the first inorganic insulating layer of at least one pad.

5. The display panel according to claim 4, wherein the overlap length between the first inorganic insulating layer and one side edge of the exposed pad metal layer is 10 microns or less.

6. The display panel according to any one of claims 1 to 3, wherein the first inorganic insulating layer does not overlap with the edge of the pad metal layer exposed by the first inorganic insulating layer of at least one pad.

7. The display panel according to any one of claims 1 to 6, wherein the display structure layer includes a plurality of subpixels, at least one of the plurality of subpixels includes a pixel circuit and a light-emitting element, the pixel circuit is electrically connected to the light-emitting element via a first relay electrode and a second relay electrode, the second relay electrode is located on the side of the first relay electrode away from the base, and the pad metal layer exposed by the first inorganic insulating layer of at least one pad and the second relay electrode have the same layer structure.

8. The first bezel region includes a signal access region, the signal access region includes a first signal access region and a second signal access region, the second signal access region is located on the side of the first signal access region away from the display region, and the plurality of pads include a plurality of first pads located in the first signal access region and a plurality of second pads located in the second signal access region. The display panel according to claim 7, wherein the number of pad metal layers of at least one first pad among the plurality of first pads is greater than the number of pad metal layers of at least one second pad among the plurality of second pads.

9. The display panel according to claim 8, wherein the at least one first pad includes a first pad metal layer, a second pad metal layer, a third pad metal layer, and a fourth pad metal layer that are sequentially stacked along a direction away from the base.

10. The display panel according to claim 9, wherein the pixel circuit includes at least one thin-film transistor and at least one capacitor, the first pad metal layer of the at least one first pad and the first or second plate of the at least one capacitor have the same layer structure, the second pad metal layer and the source and drain electrodes of the at least one thin-film transistor have the same layer structure, the third pad metal layer and the first relay electrode have the same layer structure, and the fourth pad metal layer and the second relay electrode have the same layer structure.

11. The display panel according to any one of claims 8 to 10, wherein the at least one second pad includes a fifth pad metal layer and a sixth pad metal layer that are sequentially stacked along a direction away from the base.

12. The display panel according to claim 11, wherein the fifth pad metal layer of at least one second pad and the first relay electrode have the same layer structure, and the sixth pad metal layer and the second relay electrode have the same layer structure.

13. The first bezel region further includes a folding region and a fan-out wiring region located on the side of the signal access region closer to the display region, the fan-out wiring region being located on the side of the folding region closer to the display region, At least several touch lead wires are installed in the aforementioned fan-out wiring area. At least several touch bending connection lines are provided in the aforementioned bending region. At least several touch relay lines are installed in the aforementioned signal access area. The display panel according to any one of claims 8 to 12, wherein the touch bending connection wire electrically connects the touch lead wire and the touch relay wire, and the touch relay wire and one of the pad metal layers of the connecting first pad are integrated into a single structure.

14. The display panel according to claim 13, wherein the touch bending connection line and the connecting touch relay line are integrated into a single structure.

15. The display panel according to claim 13, wherein the touch bending connection line and the first relay electrode have the same layer structure, and the touch relay line and the second relay electrode have the same layer structure.

16. The display panel according to any one of claims 1 to 6, wherein the display structure layer includes a plurality of subpixels, at least one of the plurality of subpixels includes a pixel circuit and a light-emitting element, the pixel circuit is electrically connected to the light-emitting element via a first relay electrode, and the pad metal layer exposed by the first inorganic insulating layer of at least one pad and the first relay electrode have the same layer structure.

17. The display panel according to any one of claims 1 to 16, wherein the touch structure layer includes a touch buffer layer, a first touch conductive layer, an inter-touch insulating layer, and a second touch conductive layer, which are sequentially stacked on the side away from the base, the first inorganic insulating layer and the touch buffer layer having the same layer structure, and the inter-touch insulating layer is an organic insulating layer.

18. The display panel according to any one of claims 1 to 17, further comprising a color filter layer located on the side of the touch structure layer away from the base, wherein the color filter layer includes a color film buffer layer, a black matrix, a plurality of filter units, and a color film protective layer, which are sequentially installed on the side away from the base, and both the color film buffer layer and the color film protective layer are organic insulating layers.

19. A display device comprising a display panel according to any one of claims 1 to 18.

20. A method for manufacturing a display panel, A base is provided, the base includes a display area and a first bezel area located on one side of the display area, A display structure layer is formed in the display area, a plurality of pads are formed in the first bezel area, the display structure layer includes a plurality of display area metal layers, and at least one of the plurality of pads includes at least one pad metal layer. A touch structure layer is formed on the side of the display structure layer that is away from the base, The manufacturing method, comprising: forming a first inorganic insulating layer in the first bezel region; the first inorganic insulating layer is located on the side of the plurality of pads away from the base and exposes the surface of at least a portion of the pad metal layer of the plurality of pads away from the base; and the pad metal layer exposed by the first inorganic insulating layer of at least one pad and one of the display area metal layers of the plurality of display area metal layers of the display structure layer having the same layer structure.

21. Forming the first inorganic insulating layer in the first bezel region means After forming the display structure layer, a first inorganic insulating thin film covering the plurality of pads is deposited on the first bezel region. The manufacturing method according to claim 20, comprising etching the first inorganic insulating thin film after forming the touch structure layer to form a first inorganic insulating layer.

22. The manufacturing method according to claim 21, further comprising forming a color filter layer on the side of the touch structure layer away from the base after forming the touch structure layer and before etching the first inorganic insulating thin film, wherein the color filter layer comprises a color film buffer layer, a black matrix, a plurality of filter units and a color film protective layer, which are sequentially installed on the side away from the base, and both the color film buffer layer and the color film protective layer are organic insulating layers.

23. It is a display panel, A base including a display area and a first bezel area located on one side of the display area, A display structure layer located at the base of the aforementioned display area, A touch structure layer located on the side of the display structure layer away from the base, A color filter layer located on the side of the touch structure layer away from the base, The bezel area comprises a plurality of pads located in the first bezel area, The display panel wherein the orthographic projection of the touch structure layer and the color filter layer on the base does not overlap with the orthographic projection of the plurality of pads on the base.

24. The first inorganic insulating layer is located in the first bezel region, the first inorganic insulating layer is located on the side of the plurality of pads away from the base, and the first inorganic insulating layer exposes at least a portion of the surface of the plurality of pads that is separated from the base. The touch structure layer includes a touch buffer layer, a first touch conductive layer, an inter-touch insulating layer, and a second touch conductive layer, which are sequentially stacked on the side away from the base. The display panel according to claim 23, wherein the first inorganic insulating layer and the touch buffer layer have the same layer structure.

25. At least one of the plurality of pads includes at least one pad metal layer, The first bezel region includes a first signal access region and a second signal access region, the second signal access region being located on the side of the first signal access region away from the display region, The plurality of pads include a plurality of first pads located in the first signal access area and a plurality of second pads located in the second signal access area. The display panel according to claim 23, wherein the number of pad metal layers of at least one first pad among the plurality of first pads is greater than the number of pad metal layers of at least one second pad among the plurality of second pads.

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