Battery device, battery management system, and low-power mode control method

Abstract

In the battery management system, if a communication failure occurs in the battery monitoring circuit that monitors the battery module, an interrupt is generated in the bridge circuit that transmits signals between the processor and the battery monitoring circuit. The power circuit wakes up in response to the interrupt input to the enable pin and generates the power supply voltage. The processor operates based on the power supply voltage and disables the enable pin if an error flag is set due to the communication failure in the battery monitoring circuit.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims the benefit of priority based on Korean Patent Application No. 10 - 2024 - 0041794, filed on March 27, 2024, and all the contents disclosed in the document of the Korean Patent Application are included as part of this specification.

[0002] This disclosure relates to a battery device, a battery management system, and a low - power mode control method.

Background Art

[0003] An electric vehicle or a hybrid vehicle is a vehicle that mainly obtains power by driving a motor using a battery as a power source, and is actively studied in terms of being an alternative that can solve the pollution and energy problems of internal combustion engine vehicles. Also, batteries are used in various external devices other than vehicles.

[0004] When power from the battery is not required in an external device, for example, when the vehicle is parked, the battery can shift to a low - power mode. When the battery is in the low - power mode state, there may be a problem that the battery management system cannot return to the low - power mode again after waking up from the low - power mode due to an unintended operation of the battery management system.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment can provide a battery device, a battery management system, and a low - power mode control method that can return to the low - power mode even after waking up due to an unintended operation.

Means for Solving the Problems

[0006] According to one embodiment, a battery management system for managing a battery module may be provided. The battery management system may include a battery monitoring circuit for monitoring the battery module, a power circuit that wakes up in response to an interrupt input to a first enable pin and generates a power supply voltage, a processor that operates based on the power supply voltage and disables the first enable pin if an error flag is set in the battery monitoring circuit due to a communication failure, and a bridge circuit that transmits a signal between the processor and the battery monitoring circuit and generates the interrupt if the communication failure occurs in the battery monitoring circuit.

[0007] According to one embodiment, the battery device may include a battery module and a battery management system. The battery management system may include a battery monitoring circuit for monitoring the battery module, a power circuit having a first enable pin, a processor, and a bridge circuit for transmitting signals between the processor and the battery monitoring circuit. If a communication failure occurs in the battery monitoring circuit while the battery management system is in low-power mode, the bridge circuit may generate an interrupt, the power circuit may wake up in response to the interrupt input to the first enable pin and generate a power supply voltage, the processor may wake up based on the power supply voltage, recognize the communication failure, set an error flag indicating the communication failure, and request the battery management system to switch to low-power mode.

[0008] According to one embodiment, a low-power mode control method for a battery management system that manages a battery module can be provided. The low-power mode control method may include the steps of: generating an interrupt in response to a communication failure that occurs when the battery management system is in low-power mode; generating a power supply voltage in response to the interrupt; setting an error flag indicating the communication failure; and requesting the battery management system to transition to the low-power mode. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing an example of a battery device according to one embodiment. [Figure 2] This flowchart shows an example of a low-power mode control method for a battery management system according to one embodiment. [Figure 3] This is a block diagram showing an example of a battery device according to one embodiment. [Figure 4] This is a block diagram showing an example of a battery device according to one embodiment. [Figure 5] This flowchart shows an example of a low-power mode control method for a battery management system according to one embodiment. [Figure 6] This is a block diagram showing an example of a battery device according to one embodiment. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, so that those with ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention can be implemented in a variety of different forms and is not limited to the embodiments described herein. In the drawings, parts unrelated to the description have been omitted in order to clearly illustrate the present invention, and similar parts throughout the specification are denoted by similar reference numerals.

[0011] When one component is described as being "linked" to another, it should be understood that it may be directly linked to the other component, or there may be other components in between. On the other hand, when one component is described as being "directly linked" to another, it should be understood that there are no other components in between.

[0012] In the following explanation, expressions written in the singular may be interpreted as singular or plural unless explicitly stated otherwise, such as "one" or "single."

[0013] In the flowchart explained with reference to the diagram, the order of operations can be changed, some operations can be merged, some operations can be split, and certain operations may not be performed.

[0014] Figure 1 is a block diagram showing an example of a battery device according to one embodiment.

[0015] Referring to Figure 1, the battery device 100 may include a battery module 110 and a battery management system (BMS) 120. The battery device 100 may be connected to an external device. The external device may be, for example, a means of transport, an energy storage system (ESS), or an electronic device, and the means of transport may be, for example, an electric vehicle, a hybrid vehicle, or a smart mobility vehicle. For the sake of explanation, the external device will be described as a vehicle below.

[0016] In one embodiment, the battery device 100 may include a plurality of battery modules 110. The plurality of battery modules 110 may be connected in series or in parallel. The battery module 110 may include a plurality of battery cells. The plurality of battery cells may be connected in series, for example.

[0017] The battery management system 120 is connected to the battery module 110 and can monitor and manage the battery module 110. The battery management system 120 may include a battery monitoring circuit 121, a bridge circuit 122, a processor 123, and a power circuit 124.

[0018] The battery monitoring circuit 121 is connected to the battery module 110 and can monitor the state of the battery cells (e.g., cell voltage) contained in the battery module 110. In one embodiment, the battery monitoring circuit 121 may include multiple battery monitoring circuits 121, each corresponding to a plurality of battery modules 110. In one embodiment, one battery monitoring circuit 121 may correspond to two or more battery modules 110, or two or more battery monitoring circuits 121 may correspond to one battery module 110. For convenience, Figure 1 shows three battery modules 110 and three battery monitoring circuits 121. In one embodiment, the battery monitoring circuit 121 is provided as an integrated circuit (IC), and the battery monitoring circuit 121 provided as an integrated circuit is referred to as a battery monitoring IC (BMIC).

[0019] In one embodiment, multiple battery monitoring circuits 121 can be connected in series and communicate with each other. In one embodiment, multiple battery monitoring circuits 121 may be connected to a serial peripheral interface (SPI) bus, providing bidirectional communication between two battery monitoring circuits 121. In one embodiment, the SPI bus may be an ISO-SPI (isolated SPI) bus.

[0020] The bridge circuit 122 can translate signals transmitted from the processor 123 and transmit them to the battery monitoring circuit 121, or translate signals transmitted from the battery monitoring circuit 121 and transmit them to the processor 123. In one embodiment, the bridge circuit 122 may be connected to the battery monitoring circuit 121, for example, the first of a plurality of battery monitoring circuits 121, via an SPI bus. In one embodiment, the SPI bus may be an ISO-SPI (isolated SPI) bus. In one embodiment, the bridge circuit 122 may be provided to an IC. The bridge circuit 122 provided to an IC is referred to as the bridge IC. When the battery management system 120 is in sleep mode, if a loss of communication (LOC) occurs in the battery monitoring circuit 121, the bridge circuit 122 may recognize the communication failure and generate an interrupt INTR (for example, an interrupt INTR with a high level).

[0021] Processor 123 can control the overall operation of the battery management system 120. Processor 123 is connected to bridge circuit 122, transmits signals for controlling battery monitoring circuit 121 to bridge circuit 122, receives monitoring information provided from battery monitoring circuit 121 via bridge circuit 122, and can manage the state of battery module 110 or the state of the battery cells of battery module 110. A non-volatile memory (NMV) 123a can be attached to processor 123. In one embodiment, non-volatile memory 123a may be built into processor 123. In one embodiment, non-volatile memory 123a may be installed outside processor 123 and connected to processor 123 and a bus. In one embodiment, processor 123 and bridge circuit 122 may be connected to an SPI bus. In one embodiment, processor 123 is a processing circuitry, for example, it may be a microcontroller unit (MCU).

[0022] Power circuit 124 can supply a power supply voltage (e.g., 5V) VDD to processor 123. Power circuit 124 can convert the voltage supplied from external battery 10, for example, the auxiliary battery 10 of an external device, into power supply voltage VDD. Power circuit 124 can enter a low power mode when battery management system 120 shifts to the sleep mode. Power circuit 124 in the low power mode may wake up in response to an interrupt INTR from bridge circuit 122. Also, power circuit 124 can also wake up in response to a signal (e.g., a vehicle start signal) IG for operating an external device. In one embodiment, processor 123 and power circuit 124 may be connected to an SPI bus.

[0023] In one embodiment, the power circuit 124 can include a power management IC (PMIC). The PMIC 124 can include a power pin VSUP that receives a power supply voltage from the auxiliary battery 10 and enable pins EN1 and EN2. In one embodiment, the voltage of the auxiliary battery 10 may be supplied to the power pin VSUP via the diode D1. A start signal IG may be input to the enable pin EN1, and an interrupt INTR may be input to the enable pin EN2. Therefore, the PMIC 124 in the low power mode can wake up in response to the start signal IG input to the enable pin EN1 (for example, the start signal IG having a high level) or the interrupt INTR input to the enable pin EN2 (for example, the interrupt INTR having a high level), and convert the voltage input to the power pin VSUP into the power supply voltage VDD of the processor 123. By operating with the power supply voltage VDD as a power source by the processor 123, the battery management system 120 can wake up from the sleep mode.

[0024] In one embodiment, the voltage Vs supplied from the auxiliary battery 10 (for example, the voltage supplied from the auxiliary battery 10 passing through the diode D1) may be provided as the power supply voltage Vs of the bridge circuit 122.

[0025] In one embodiment, the unit 120a including the battery monitoring circuit 121 may be referred to as a cell monitoring unit (CMU) or a high voltage (HV) unit, and the unit 120b including the bridge circuit 122, the processor 123, and the power circuit 124 may be referred to as a battery monitoring unit (BMU) or a low voltage (LV) unit.

[0026] FIG. 2 is a flowchart showing an example of a low power mode control method of a battery management system according to one embodiment.

[0027] Referring to Figures 1 and 2, if a communication failure occurs in the battery monitoring circuit 121 (S210), the bridge circuit 122 can recognize the communication failure (S215). The bridge circuit 122 can generate an interrupt INTR in response to the communication failure (S220). The power circuit 124, for example, the PMIC 124, can wake up in response to the interrupt INTR and convert the voltage of the auxiliary battery 10 to the power supply voltage VDD (S225).

[0028] The processor 123 wakes up when the power supply voltage VDD is input from the PMIC 124 and can operate using the power supply voltage VDD as a power source (S230). Therefore, the processor 123 can recognize a communication failure in the battery monitoring circuit 121 and refer to the non-volatile memory 123a installed in the processor 123 (S235). If an error flag indicating a communication failure in the battery monitoring circuit 121 is not set in the non-volatile memory 123a, the processor 123 can set (i.e., save) the error flag in the non-volatile memory 123a (S240). Because the battery management system 120 has woken up due to the communication failure, the processor 123 can request the battery management system 120 to transition to sleep mode (S245). Therefore, the PMIC 124 transitions to low-power mode, and since the power supply voltage VDD is not supplied from the PMIC 124, the processor 123 can also transition to low-power mode (S250).

[0029] On the other hand, if the battery monitoring circuit 121 continues to experience communication problems even after the battery management system 120 has entered sleep mode (i.e., low power mode), the bridge circuit 122 may generate an interrupt INTR. As a result, the PMIC 124, which has entered low power mode again, wakes up in response to the interrupt INTR (S255), and the power supply voltage VDD is supplied to the PMIC 124, allowing the processor 123 to wake up as well (S260).

[0030] After waking up, the processor 123 can refer to the non-volatile memory 123a, and if an error flag is set in the non-volatile memory 123a, it can disable the enable pin EN2 of the PMIC 124 (S265). That is, if the error flag is set, the processor 123 can disable the reception of the interrupt INTR of the PMIC 124 (S265). In one embodiment, the processor 123 can disable the enable pin EN2 of the PMIC 124 via SPI communication. Because the battery management system 120 has woken up due to a communication failure, the processor 123 can request the battery management system 120 to switch to sleep mode (S270). Therefore, the PMIC 124 switches to low-power mode, and since the PMIC 124 does not supply the power supply voltage VDD, the processor 123 can also switch to low-power mode (S275). On the other hand, even if the battery monitoring circuit 121 experiences a communication failure after the battery management system 120 has entered sleep mode, the PMIC 124 can maintain low-power mode without being woken up by the interrupt INTR because the enable pin EN2 of the PMIC 124 is disabled (S275).

[0031] As explained above, without the error flag set in the non-volatile memory 123a, the battery management system may not be able to maintain low power mode due to unintended malfunctions such as communication failures. However, according to one embodiment, when the error flag is set in the non-volatile memory 123a, the interrupt INTR reception of the power circuit 124 is disabled, allowing the battery management system to maintain low power mode.

[0032] Figure 3 is a block diagram showing an example of a battery device according to one embodiment.

[0033] Referring to Figure 3, the battery management system 320 of the battery device 300 may further include a transformer 125 that connects the HV unit (i.e., the initial battery monitoring circuit 121) 320b and the LV unit (i.e., the bridge circuit 122) 320a, compared to the battery management system 120 described with reference to Figure 1. Thus, the bridge circuit 122 can receive monitoring information from the battery monitoring circuit 121 via the transformer 125.

[0034] Figure 4 is a block diagram showing an example of a battery device according to one embodiment.

[0035] Referring to Figure 4, the battery device 400 may include a battery module 410 and a battery management system 420. The battery device 400 is connected to an external device. In one embodiment, the battery device 400 may include a plurality of battery modules 410.

[0036] The battery management system 420 is connected to the battery module 410 and can monitor and manage the battery module 410. The battery management system 420 may include a battery monitoring circuit 421, a bridge circuit 422, a processor 423, and a power circuit 424.

[0037] The battery module 410, battery monitoring circuit 421, bridge circuit 422, and processor 423 perform the same or similar operations as the battery module 110, battery monitoring circuit 121, bridge circuit 122, and processor 123 described with reference to Figure 1, and therefore a detailed explanation is omitted.

[0038] The power circuit 424 can supply the power supply voltage VDD to the processor 423. The power circuit 424 can convert the voltage supplied from an external battery 40, for example, an auxiliary battery 40 of an external device, into the power supply voltage VDD. The power circuit 424 can transition to a low-power mode when the battery management system 420 enters sleep mode.

[0039] In one embodiment, the power circuit 424 may include a direct current (DC) / DC converter 424a and a PMIC 424b. The DC / DC converter 424a receives a voltage supply from the auxiliary battery 40 and can convert the voltage of the auxiliary battery 40 to a predetermined voltage (e.g., 12V). The DC / DC converter 424a may be, for example, a buck / boost converter. The PMIC 424b receives a predetermined voltage supply from the DC / DC converter 424a and can convert the predetermined voltage to a power supply voltage (e.g., 5V) VDD.

[0040] The power circuit 424 in low-power mode may wake up in response to an interrupt INTR from the bridge circuit 422. Alternatively, the power circuit 424 may wake up in response to a signal IG that activates an external device (e.g., a vehicle start signal). In one embodiment, the processor 423 and the power circuit 424, for example, the PMIC 424b, may be connected to an SPI bus.

[0041] In one embodiment, the DC / DC converter 424a may include a power supply pin VN for receiving the voltage of the auxiliary battery 40 and an enable pin EN for enabling the DC / DC converter 424a. In one embodiment, the power circuit 424 may further include a transistor TR2 that turns on in response to a start signal IG, a transistor TR3 that turns on in response to an interrupt INTR, and a transistor TR1 that transmits the voltage of the auxiliary battery 40 to the power supply pin VN and enable pin EN of the DC / DC converter 424a in response to the turn-on of transistor TR2 or transistor TR3.

[0042] For example, transistors TR1, TR2, and TR3 may be n-channel FETs (field-effect transistors). In this case, the drains of transistors TR2 and TR3 may be connected to node N1, and the sources of transistors TR2 and TR3 may be connected to the ground terminal. Resistors R1 and R2 may be connected in series between the input terminal to which the start signal IG is input and the ground terminal, and the connection point of resistors R1 and R2 may be connected to the gate of transistor TR2. That is, the voltage of the start signal IG may be divided by resistors R1 and R2 and input to the gate of transistor TR2. An interrupt INTR may be input to the gate of transistor TR3. Resistors R3 and R4 may be connected in series between the drain of transistor TR1 and node N1, and the connection point of resistors R3 and R4 may be connected to the gate of transistor TR1. The voltage of the auxiliary battery 40 may be supplied to the drain of transistor TR1, and the source of transistor TR1 may be connected to the power supply pin VN and the enable pin EN. The source of transistor TR1 may be connected to the enable pin EN via resistor R5. Alternatively, the voltage from the auxiliary battery 40 may be supplied to the drain of transistor TR1 via diode D1.

[0043] Therefore, when the start signal IG is input, transistor TR1 is turned on, and the voltage obtained by dividing the voltage of the auxiliary battery 40 by resistors R3 and R4 is applied to the gate of transistor TR3, which may turn on transistor TR3. Similarly, when the interrupt INTR is input, transistor TR1 is turned on, and the voltage obtained by dividing the voltage of the auxiliary battery 40 by resistors R3 and R4 is applied to the gate of transistor TR3, which may turn on transistor TR3. When transistor TR3 is turned on, the voltage of the auxiliary battery 40 is input to the enable pin EN, the DC / DC converter 424a is woken up, and the voltage of the auxiliary battery 40 supplied to the power pin VN can be converted to a predetermined voltage.

[0044] In one embodiment, the PMIC424b may include a power supply pin VSUP and enable pins EN1 and EN2 that receive a predetermined voltage from the DC / DC converter 424a. A start signal IG may be input to the enable pin EN1, and an interrupt signal INTR may be input to the enable pin EN2. Thus, the PMIC424 in low-power mode can wake up in response to the start signal IG input to the enable pin EN1 or the interrupt signal INTR input to the enable pin EN2, and convert the voltage input to the power supply pin VSUP into the power supply voltage VDD of the processor 423. The battery management system 420 can wake up from sleep mode as the processor 423 operates using the power supply voltage VDD as a power source.

[0045] Figure 5 is a flowchart showing an example of a low-power mode control method for a battery management system according to one embodiment.

[0046] Referring to Figures 4 and 5, if a communication failure occurs in the battery monitoring circuit 421 (S510), the bridge circuit 422 can recognize the communication failure (S515). The bridge circuit 422 may generate an interrupt INTR in response to the communication failure (S520). Of the power circuits 424, the DC / DC converter 424a wakes up in response to the interrupt INTR and can convert the voltage of the auxiliary battery 40 to a predetermined voltage (S525). The PMIC 424b wakes up in response to the interrupt INTR and can convert the predetermined voltage supplied by the DC / DC converter 424a to the power supply voltage VDD (S530).

[0047] The processor 423 wakes up when the power supply voltage VDD is input from the PMIC 424b and can operate using the power supply voltage VDD as a power source (S535). Therefore, the processor 423 recognizes the communication failure of the battery monitoring circuit 421 and can refer to the non-volatile memory 423a installed in the processor 423 (S540). If an error flag indicating a communication failure of the battery monitoring circuit 421 is not set in the non-volatile memory 423a, the processor 423 can set (i.e., save) the error flag in the non-volatile memory 423a (S545). Because the battery management system 420 has woken up due to the communication failure, the processor 423 can request the battery management system 420 to transition to sleep mode (S550). Therefore, the PMIC 424b transitions to low-power mode, and since the power supply voltage VDD is not supplied from the PMIC 424b, the processor 423 can also transition to low-power mode (S555). In one embodiment, the DC / DC converter 424a can also be switched to low-power mode (S555).

[0048] On the other hand, if the battery monitoring circuit 421 continues to experience communication failures even after the battery management system 420 has entered sleep mode (i.e., low power mode), the bridge circuit 422 may generate an interrupt INTR. Thus, the PMIC 424b, which has entered low power mode again, wakes up in response to the interrupt INTR (S560), and the processor 423 can also be woken up by the supply of power voltage VDD from the PMIC 424b (S565). In one embodiment, the DC / DC converter 424a, which has entered low power mode, can also wake up in response to the interrupt INTR (S560).

[0049] After waking up, the processor 423 can refer to the non-volatile memory 423a, and if an error flag is set in the non-volatile memory 423a, it can disable the enable pin EN2 of the PMIC 424b (S570). That is, if an error flag is set, the processor 423 can disable the reception of the interrupt INTR of the PMIC 424b (S570). In one embodiment, the processor 423 can disable the enable pin EN2 of the PMIC 424b via SPI communication. Because the battery management system 420 has woken up due to a communication failure, the processor 423 can request the battery management system 420 to transition to sleep mode (S575). Therefore, the PMIC 424b transitions to low-power mode, and since the PMIC 424b does not supply the power supply voltage VDD, the processor 423 can also transition to low-power mode (S580). On the other hand, even if the battery monitoring circuit 421 continues to experience communication failure after the battery management system 420 has entered sleep mode, the PMIC 424b can maintain low-power mode without being woken up by the interrupt INTR because the enable pin EN2 of the PMIC 424b is disabled (S580).

[0050] As explained above, without the error flag set in the non-volatile memory 423a, the battery management system may not be able to maintain low power mode due to unintended malfunctions such as communication failures. However, according to one embodiment, when the error flag is set in the non-volatile memory 423a, the interrupt INTR reception of the power circuit 424 is disabled, allowing the battery management system to maintain low power mode.

[0051] Figure 6 is a block diagram showing an example of a battery device according to one embodiment.

[0052] Referring to Figure 6, the battery management system 620 of the battery device 600 may further include a transformer 625 that connects the HV unit (i.e., the first battery monitoring circuit 621) and the LV unit (i.e., the bridge circuit 622), compared to the battery management system 420 described with reference to Figure 4. Thus, the bridge circuit 622 can receive monitoring information from the battery monitoring circuit 121 via the transformer 425.

[0053] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

1. A battery management system that manages battery modules, A battery monitoring circuit for monitoring the aforementioned battery module, A power circuit that wakes up in response to an interrupt input to the first enable pin and generates a power supply voltage, A processor that operates based on the aforementioned power supply voltage, and disables the first enable pin when an error flag is set in the battery monitoring circuit due to a communication failure, A bridge circuit that transmits signals between the processor and the battery monitoring circuit, and generates the interrupt when the communication failure occurs in the battery monitoring circuit. A battery management system, including...

2. The battery management system according to claim 1, wherein the processor sets the error flag if the error flag was not set when the communication failure occurred.

3. The battery management system according to claim 1, wherein the processor includes a non-volatile memory and stores the error flag in the non-volatile memory.

4. The aforementioned battery management system further includes non-volatile memory, The processor stores the error flag in the non-volatile memory. The battery management system according to claim 1.

5. The aforementioned processor It wakes up in response to the aforementioned power supply voltage and recognizes the communication failure. If the error flag is not set, after setting the error flag, the system requests the battery management system to switch to low power mode. The power circuit switches to the low-power mode in response to a request to switch to the low-power mode. The battery management system according to claim 1.

6. If the power circuit wakes up again in response to the interrupt, The aforementioned processor, It wakes up in response to the aforementioned power supply voltage and recognizes the communication failure. In response to the error flag, the first enable pin is disabled. The system requests the aforementioned battery management system to switch to low-power mode. The power circuit switches to the low-power mode in response to a request to switch to the low-power mode. The battery management system according to claim 5.

7. The power circuit includes a power management integrated circuit that generates the power supply voltage based on the voltage from an external battery, The aforementioned power management integrated circuit is The power pin to which the voltage from the external battery is input, The first enable pin and, Includes a second enable pin to which a start signal is input in response to the start of an external device, A battery management system according to any one of claims 1 to 6.

8. The aforementioned power circuit is A DC / DC converter that converts a first voltage from an external battery to a second voltage, Includes a power management integrated circuit that generates the power supply voltage based on the second voltage, The aforementioned power management integrated circuit is The first power supply pin to which the second voltage is input, The first enable pin and, Includes a second enable pin to which a start signal is input in response to the start of an external device, A battery management system according to any one of claims 1 to 6.

9. The power circuit further includes a first transistor that is turned on in response to the start signal or interrupt and transmits the first voltage from the external battery, The aforementioned DC / DC converter is The second power supply pin to which the first voltage is input, Including an enable pin to which the first voltage is input, The battery management system according to claim 8.

10. The aforementioned power circuit is A second transistor that turns on in response to the aforementioned start signal, The system further includes a third transistor that turns on in response to the interrupt, The first transistor turns on in response to the turn-on of the second transistor or the turn-on of the third transistor. The battery management system according to claim 9.

11. Battery module and Includes a battery management system, The aforementioned battery management system is A battery monitoring circuit for monitoring the aforementioned battery module, A power circuit having a first enable pin, Processor and The processor and the battery monitoring circuit include a bridge circuit that transmits signals between the processor and the battery monitoring circuit, If a communication failure occurs in the battery monitoring circuit while the battery management system is in low-power mode, the bridge circuit generates an interrupt. The power circuit wakes up in response to the interrupt input to the first enable pin and generates a power supply voltage. The processor wakes up based on the power supply voltage, recognizes the communication failure, sets an error flag indicating the communication failure, and requests the battery management system to switch to low power mode. Battery device.

12. If the battery monitoring circuit continues to experience the communication failure after the battery management system has transitioned to the low-power mode, the bridge circuit generates the interrupt. The power circuit wakes up in response to the interrupt input to the first enable pin and generates the power supply voltage. The processor wakes up based on the power supply voltage, recognizes the communication failure, and if the error flag is set, disables the first enable pin and requests the battery management system to switch to low power mode. The battery device according to claim 11.

13. The battery device according to claim 11, wherein the processor includes a non-volatile memory and stores the error flag in the non-volatile memory.

14. The aforementioned battery management system further includes non-volatile memory, The processor stores the error flag in the non-volatile memory. The battery device according to claim 11.

15. The power circuit includes a power management integrated circuit that generates the power supply voltage based on the voltage from an external battery, The aforementioned power management integrated circuit is The power pin to which the voltage from the external battery is input, The first enable pin and, Includes a second enable pin to which a start signal is input in response to the start of an external device, The battery device according to any one of claims 11 to 14.

16. The aforementioned power circuit is A DC / DC converter that converts a first voltage from an external battery to a second voltage, Includes a power management integrated circuit that generates the power supply voltage based on the second voltage, The aforementioned power management integrated circuit is The first power supply pin to which the first voltage is input, The first enable pin and, Includes a second enable pin to which a start signal is input in response to the start of an external device, The battery device according to any one of claims 11 to 14.

17. A low-power mode control method for a battery management system that manages battery modules, The steps include: generating an interrupt in response to a communication failure that occurs when the battery management system is in low-power mode; The steps include generating a power supply voltage in response to the interrupt, The steps include setting an error flag indicating the aforementioned communication failure, A step of requesting the battery management system to switch to the low-power mode, A low-power mode control method, including the following:

18. If the communication failure persists after the battery management system has entered the low-power mode, the step of generating the interrupt, The steps include generating the power supply voltage in response to the interrupt, If the aforementioned error flag is set, the step of disabling the reception of the interrupt, A step of requesting the battery management system to switch to the low-power mode, The low-power mode control method according to claim 17, further comprising:

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