Oscillator device and control method

Abstract

The apparatus includes a first inverter having input terminals and output terminals, a first capacitive device connected between the input terminals and output terminals of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as an inverting amplifier, and the first capacitive device and the resistor network are configured to determine the frequency of an oscillator.

Description

Technical Field

[0001]

[0001] Cross - reference to Related Applications This patent application claims priority to U.S. Patent Application No. 18 / 626,280, entitled "Oscillator Device and Control Method," filed on April 3, 2024, which is incorporated herein by reference in its entirety, and specifically, this is a continuation application thereof.

[0002]

[0002] Embodiments of the present invention relate to an oscillator, and in certain embodiments, to a resistor - capacitor oscillator having a capacitor with an extended effective capacitance.

Background Art

[0003]

[0003] As semiconductor technology evolves, oscillators are widely used in various electronic devices. For example, oscillators are commonly used in processors (e.g., microcontrollers), mobile devices (e.g., mobile phones), audio devices (e.g., wireless headphones), computers (e.g., laptop computers), telecommunication devices (e.g., base stations), etc.

[0004]

[0004] FIG. 1 shows an oscillator. The oscillator includes a first inverter 101, a second inverter 102, a third inverter 103, a fourth inverter 104, a capacitor C1, a resistor network 100, a first NAND gate 201, a second NAND gate 202, and a third NAND gate 203. The resistor network 100 includes a plurality of switch - resistor networks (e.g., S1 - R1, S2 - R2, S3 - R3, and S4 - R4) connected in series between a first terminal and a second terminal of the resistor network 100. Each first switch - resistor network includes a resistor (e.g., R1) and a switch (e.g., S1) connected in parallel.

[0005]

[0005] As shown in Figure 1, the input terminal of the second inverter 102 is connected to the input terminal of the first inverter 101, and further connected to the first terminal of the resistor network 100 and the first terminal of the capacitor C1. The second terminal of the capacitor C1 is grounded. The output terminal of the second inverter 102 is connected to the input terminal of the third inverter 103. The output terminal of the third inverter 103 is connected to the first input terminal of the second NAND gate 202. The output terminal of the first inverter 101 is connected to the second input terminal of the first NAND gate 201. The first input terminal of the first NAND gate 201 is connected to the output terminal of the second NAND gate 202. The second input terminal of the second NAND gate 202 is connected to the output terminal of the first NAND gate 201. The output terminal of the first NAND gate 201 is connected to the first input terminal of the third NAND gate 203. The second input terminal of the third NAND gate 203 is configured to receive an enable signal EN. The output terminal of the third NAND gate 203 is connected to the second terminal of the resistor network 100. The input terminal of the fourth inverter 104 is connected to the output terminal of the first NAND gate 201. The output terminal OSCOUT of the fourth inverter 104 is configured to generate a periodic AC signal.

[0006]

[0006] The oscillator shown in Figure 1 is an RC oscillator. The periodic AC signal generated by the oscillator can be used as a clock signal, timing signal, etc. In addition, an RC oscillator can generate a variable frequency by changing the resistance value of the resistor network 100 and / or the capacitance value of the capacitor C1. To realize a low operating frequency oscillator, a high RC value is required. However, in an integrated circuit, a larger size is required to realize a large RC. Therefore, since a lower operating frequency is desired, a larger RC is essential, and the cost increases.

[0007]

[0007] The semiconductor industry has developed manufacturing techniques aimed at producing high-density capacitors with values ​​several times greater than those of standard capacitors, resulting in smaller capacitor sizes. However, these new manufacturing techniques require specific mask layouts and complex manufacturing procedures, making them more expensive compared to standard semiconductor manufacturing processes.

[0008]

[0008] It is desirable to have capacitive devices for use in low-frequency oscillator applications that exhibit good characteristics such as a large capacitance value with a smaller capacitor size. This disclosure addresses this need. [Overview of the project]

[0009]

[0009] These and other problems are generally solved or avoided by preferred embodiments of the present disclosure that provide a resistor-capacitor oscillator with a capacitor having an extended effective capacitance, and the technical advantages are generally achieved.

[0010]

[0010] According to one embodiment, the apparatus comprises a first inverter having input terminals and output terminals, a first capacitive device connected between the input terminals and output terminals of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as an inverting amplifier, and the first capacitive device and the resistor network are configured to determine the frequency of an oscillator.

[0011]

[0011] According to another embodiment, the method provides an oscillator comprising a first inverter, a first capacitive device connected between the input and output terminals of the first inverter, and a resistor network coupled to the first capacitive device, and includes configuring the first inverter as an inverting amplifier for increasing the effective capacitance of the first capacitive device, and adjusting the frequency of the oscillator by adjusting at least one of the effective capacitance of the first capacitive device and the resistance of the resistor network.

[0012]

[0012] In yet another embodiment, the system comprises a first inverter having input terminals and output terminals, a first capacitive device connected between the input terminals and output terminals of the first inverter, a second inverter having input terminals and output terminals, a second capacitive device connected between the input terminals and output terminals of the second inverter, and a resistor network connected to the input terminals of the first inverter and the input terminals of the second inverter, wherein the first capacitive device, the second capacitive device and the resistor network are configured to determine the frequency of an oscillator.

[0013]

[0013] The above has provided a fairly broad overview of the features and technical advantages of the Disclosure so that the detailed description of the Disclosure below may be better understood. Further features and advantages of the Disclosure that form the subject matter of the claims of the Disclosure are described below. It should be understood by those skilled in the art that the disclosed concepts and particular embodiments can be readily used as a basis for modifying or designing other structures or processes to accomplish the same objectives of the Disclosure. Furthermore, it should be understood that such equivalent structures do not deviate from the spirit and scope of the Disclosure as set forth in the appended claims.

[0014]

[0014] For a more complete understanding of the present disclosure and its advantages, refer hereto to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0015] [Figure 1] This is a diagram of an oscillator. [Figure 2] This is a block diagram of a resistor-capacitor oscillator with a capacitor having an enlarged effective capacitance, according to various embodiments of the present disclosure. [Figure 3] Figure 2 is a schematic diagram of an oscillator according to various embodiments of the present disclosure. [Figure 4] Figure 3 is a schematic diagram of an inverter according to various embodiments of the present disclosure. [Figure 5]This figure shows different embodiments of the capacitor shown in Figure 3, according to various embodiments of the present disclosure. [Figure 6] Figure 3 is a schematic diagram of a resistor network according to various embodiments of the present disclosure. [Figure 7] This is a schematic diagram of a first embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. [Figure 8] This is a schematic diagram of a second embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. [Figure 9] This is a schematic diagram of a third embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. [Figure 10] This is a schematic diagram of a fourth embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. [Figure 11] This is a flowchart of a method for controlling the oscillator shown in Figure 2 according to various embodiments of the present disclosure. [Modes for carrying out the invention]

[0016]

[0026] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise specified. The drawings are drawn to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale.

[0017]

[0027] The fabrication and use of currently preferred embodiments are described in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific situations. The specific embodiments described are merely illustrative of specific methods of fabrication and use of the disclosed invention and do not limit the scope of this disclosure.

[0018]

[0028] The present disclosure is described with respect to a preferred embodiment in a specific situation, namely, a resistor-capacitor oscillator having a capacitor with an enlarged effective capacitance. However, the present disclosure may be applied to various oscillators. Various embodiments will be described in detail below with reference to the accompanying drawings.

[0019]

[0029] FIG. 2 shows a block diagram of a resistor-capacitor (RC) oscillator having a capacitor with an enlarged effective capacitance according to various embodiments of the present disclosure. The oscillator includes an inverter 200, a capacitive device, and a resistor network 220. In some embodiments, the capacitive device is implemented as capacitor C1 as shown in FIG. 2. The inverter 200 has an input terminal and an output terminal. The capacitor C1 is connected between the input terminal and the output terminal of the inverter 200. The resistor network 220 is coupled to the input terminals of the capacitor C1 and the inverter 200.

[0020]

[0030] During operation, the inverter 200 is configured as an inverting amplifier. According to the mirror effect of the inverting amplifier, the capacitance value of the capacitor on the input node of the inverting amplifier can be expressed as follows. Cin = C1×(1 + A) (1)

[0021]

[0031] In Equation (1), A is the voltage gain of the inverting amplifier. The capacitance value of the capacitor on the output node of the inverting amplifier can be expressed as follows.

Equation

[0022]

[0032] Considering that the value of A is large, the capacitance value of the capacitor on the output node of the inverting amplifier is approximately equal to the capacitance value of C1. Therefore, the total capacitance provided by C1 and the inverting amplifier can be expressed as follows. Ctotal = C1 × (2 + A) (3)

[0023]

[0033] In some embodiments, the voltage gain A of the inverting amplifier is in the range of about 8 to about 20. For example, if the voltage gain A is equal to 8, the total capacitance is equal to 10 times the capacitance of capacitor C1. In other words, a capacitor with 10% capacitance can achieve equivalent performance when determining the oscillator frequency. The capacitor size is significantly smaller compared to conventional RC oscillators (e.g., the RC oscillator shown in Figure 1), less than 90% of their size.

[0024]

[0034] One advantage of connecting capacitor C1 between the input and output terminals of inverter 200 is that the capacitance increase technology shown in Figure 2 does not increase power consumption. In addition, the capacitance increase technology shown in Figure 2 does not require a special semiconductor manufacturing process.

[0025]

[0035] During operation, capacitor C1 and the resistor network are configured to determine the oscillator frequency. In particular, the oscillator may include a second capacitive device and a second inverter. In some embodiments, the second capacitive device is implemented as a second capacitor C2. The second capacitor C2 is connected between the input and output terminals of the second inverter. The resistor network 220 includes a plurality of switch-resistor networks connected in series. Capacitors C1, C2 and the plurality of switch-resistor networks are configured to set the oscillator frequency. The detailed structure of the oscillator is described below with reference to Figures 3 to 6.

[0026]

[0036] Figure 3 shows schematic diagrams of the oscillator shown in Figure 2 according to various embodiments of the present disclosure. The oscillator comprises a first capacitive device, a first inverter 302, a second capacitive device, a second inverter 304, a third inverter 306, a fourth inverter 308, a first NAND gate 312, a second NAND gate 314, a third NAND gate 316, and a resistor network 320.

[0027]

[0037] In some embodiments, the first capacitive device is implemented as a first capacitor C1. The second capacitive device is implemented as a second capacitor C2, as shown in Figure 3. The first capacitor C1 is connected between the input and output terminals of the first inverter 302. The second capacitor C2 is connected between the input and output terminals of the second inverter 304.

[0028]

[0038] The input terminal of the second inverter 304 is connected to the input terminal of the first inverter 302, and further connected to the first terminal of the resistor network 320. The output terminal of the second inverter 304 is connected to the input terminal of the third inverter 306. The output terminal of the third inverter 306 is connected to the first input terminal of the second NAND gate 314. The output terminal of the first inverter 302 is connected to the second input terminal of the first NAND gate 312. The first input terminal of the first NAND gate 312 is connected to the output terminal of the second NAND gate 314. The second input terminal of the second NAND gate 314 is connected to the output terminal of the first NAND gate 312. The output terminal of the first NAND gate 312 is connected to the first input terminal of the third NAND gate 316. The second input terminal of the third NAND gate 316 is configured to receive the enable signal EN. The output terminal of the third NAND gate 316 is connected to the second terminal of the resistor network 320. The input terminal of the fourth inverter 308 is connected to the output terminal of the first NAND gate 312. The output terminal of the fourth inverter 308 is configured to generate a periodic AC signal.

[0029]

[0039] During operation, the resistor network 320 and capacitors C1 and C2 form a loop. Capacitors C1 and C2 charge and discharge through the resistor network 320, generating an oscillating waveform OSCOUT at the output. An enable signal EN is provided to enable and disable the oscillator. In particular, when the enable signal is logically high level, it allows the oscillator to operate normally. In other words, the oscillator is enabled, and the output signal oscillates at a frequency determined by the resistor network 320 and capacitors C1 and C2. When the enable signal EN is logically low level, it prevents the capacitors from charging or discharging, thereby stopping the oscillation. This effectively disables the oscillator.

[0030]

[0040] Figure 4 shows schematic diagrams of the inverters shown in Figure 3 according to various embodiments of the present disclosure. The inverters shown in Figure 3 share a common structure. As an example, Figure 4 shows a typical structure of the first inverter 302. The first inverter 302 comprises a p-type transistor M1 and an n-type transistor M2 connected in series between a bias voltage bus VDD and ground. The gates of the p-type transistor M1 and the n-type transistor M2 are connected to each other and further connected to the input terminal VIN of the first inverter 302. The drains of the p-type transistor M1 and the n-type transistor M2 are connected to each other and further connected to the output terminal VOUT of the first inverter 302. A capacitor C1 is connected between the input terminal VIN and the output terminal VOUT of the first inverter 302.

[0031]

[0041] During operation, the first inverter 302 is configured as an inverting amplifier. This inverting amplifier can increase the capacitance at the input node of the first inverter 302. The rationale behind the increase in capacitance at the input node of the first inverter can be explained as follows: During operation, VIN is rising. In response to the change in VIN, VOUT, which is the output of the inverter, is falling. Since the voltage across capacitor C1 cannot change instantaneously, the voltage at VIN is falling. More power is used to overcome the force from the inverting amplifier and maintain and increase the voltage at VIN. This configuration of the first capacitor C1 and the first inverter 302 increases the effective capacitance at the input node of the first inverter 302. The effective capacitance value of the capacitor on the input node of the inverting amplifier can be expressed as follows: Cin = C1 × (1 + A) (4)

[0032]

[0042] Referring back to equation (3), the total capacitance provided by the first capacitor C1 and the inverting amplifier is equal to (A+2) times the capacitance of the first capacitor C1.

[0033]

[0043] Figure 5 shows different embodiments of the capacitor shown in Figure 3 according to various embodiments of the present disclosure. The capacitive device shown in Figure 3 may be replaced by a plurality of switch-capacitor networks connected in parallel (e.g., S1-C1 and S2-C2). As shown in Figure 5, each switch-capacitor network includes a capacitor (e.g., C1) and a switch (e.g., S1) connected in series.

[0034]

[0044] During operation, the oscillator frequency can be adjusted by turning on a predetermined number of switches in a multi-switch-capacitor network.

[0035]

[0045] Figure 6 shows schematic diagrams of the resistor network shown in Figure 3 according to various embodiments of the present disclosure. The resistor network 320 includes a plurality of switch-resistor networks (e.g., S1-R1, S2-R2, S3-R3, and S4-R4) connected in series between a first terminal of the resistor network 320 and a second terminal of the resistor network 320. As shown in Figure 6, each switch-resistor network includes a resistor (e.g., R1) and a switch (e.g., S1) connected in parallel.

[0036]

[0046] During operation, the oscillator frequency can be adjusted by turning on a predetermined number of switches in a multi-switch-resistor network.

[0037]

[0047] A resistor-capacitor (RC) ring oscillator is an oscillator circuit that produces a continuous square wave output. An RC ring oscillator comprises an odd number of inverter stages connected in a ring configuration, each stage containing an RC network and an inverter. The RC network acts as a delay element, and the capacitors charge and discharge through resistors, resulting in time delays. The output of each inverter stage is fed back to the input of the next stage, forming a loop. As the signal propagates through the loop, multiple delays occur, causing oscillations in the output. The oscillation frequency is determined by the time constant of the RC network and the propagation delay of the inverters.

[0038]

[0048] The advantageous feature of having a capacitor with increased effective capacitance, as shown in Figure 2, is also applicable to RC ring oscillators. Figures 7 to 10 show four different embodiments of RC ring oscillators featuring increased effective capacitance.

[0039]

[0049] Figure 7 shows a schematic diagram of a first embodiment of an RC ring oscillator featuring increased effective capacitance, according to various embodiments of the present disclosure. The RC ring oscillator comprises a first inverter 702, a first resistor R1, a first capacitor C1, a second inverter 704, a second resistor R2, a second capacitor C2, a NAND gate 706, a third resistor R3, and a third capacitor C3.

[0040]

[0050] As shown in Figure 7, the first resistor R1 is connected between the output of the NAND gate 706 and the input terminal of the first inverter 702. The first capacitor C1 is connected between the input terminal and the output terminal of the first inverter 702. The second resistor R2 is connected between the output terminal of the first inverter 702 and the input terminal of the second inverter 704. The second capacitor C2 is connected between the input terminal of the second inverter 704 and ground. The third resistor R3 is connected between the output terminal of the second inverter 704 and the first input terminal of the NAND gate 706. The third capacitor C3 is connected between the first input terminal of the NAND gate 706 and ground. The second input terminal of the NAND gate is configured to receive the enable signal EN.

[0041]

[0051] Referring back to equation (3), the total capacitance provided by C1 and the first inverter 702 is equal to C1 × (2 + A). That is, the effective capacitance is equal to (2 + A) times the capacitance of the first capacitor C1. By using the capacitor and inverter configuration shown in Figure 7, the capacitor size is significantly reduced compared to a conventional RC ring oscillator in order to achieve a large RC time constant.

[0042]

[0052] It should be noted that other variations of the capacitive devices and resistor networks described above are also applicable to the RC ring oscillator shown in Figure 7. For example, the resistor shown in Figure 7 (e.g., R1) may be replaced with a series-connected switch-resistor network (e.g., the resistor network shown in Figure 6). Similarly, the capacitor shown in Figure 7 (e.g., C1) may be replaced with a parallel-connected switch-capacitor network (e.g., the switch-capacitor network shown in Figure 5).

[0043]

[0053] Figure 8 shows a schematic diagram of a second embodiment of an RC ring oscillator featuring increased effective capacitance, according to various embodiments of the present disclosure. The RC ring oscillator comprises a first inverter 802, a first resistor R1, a first capacitor C1, a second inverter 804, and a NAND gate 806.

[0044]

[0054] As shown in Figure 8, the first resistor R1 is connected between the output of the NAND gate 806 and the input terminal of the first inverter 802. The first capacitor C1 is connected between the input terminal and the output terminal of the first inverter 802. The input terminal of the second inverter 804 is connected to the output terminal of the first inverter 802. The output terminal of the second inverter 804 is connected to the first input terminal of the NAND gate 806. The second input terminal of the NAND gate 806 is configured to receive the enable signal EN.

[0045]

[0055] Referring back to equation (3), the total capacitance provided by C1 and the first inverter 802 is equal to C1 × (2 + A). That is, the effective capacitance is equal to (2 + A) times the capacitance of the first capacitor C1. By using the capacitor and inverter configuration shown in Figure 8, the capacitor size is significantly reduced compared to a conventional RC ring oscillator in order to achieve a large RC time constant.

[0046]

[0056] It should be noted that other variations of the capacitive devices and resistor networks described above are also applicable to the RC ring oscillator shown in Figure 8. For example, the resistor shown in Figure 8 (e.g., R1) may be replaced with a series-connected switch-resistor network (e.g., the resistor network shown in Figure 6). Similarly, the capacitor shown in Figure 8 (e.g., C1) may be replaced with a parallel-connected switch-capacitor network (e.g., the switch-capacitor network shown in Figure 5).

[0047]

[0057] Figure 9 shows a schematic diagram of a third embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. The RC ring oscillator comprises a first inverter 902, a first resistor R1, a first capacitor C1, a second inverter 904, and a third inverter 906.

[0048]

[0058] As shown in Figure 9, the first capacitor C1 is connected between the input terminal and output terminal of the first inverter 902. The input terminal of the second inverter 904 is connected to the output terminal of the first inverter 902. The input terminal of the third inverter 906 is connected to the output terminal of the second inverter 904. The first resistor R1 is connected between the output terminal of the third inverter 906 and the input terminal of the first inverter 902.

[0049]

[0059] Referring back to equation (3), the total capacitance provided by C1 and the first inverter 902 is equal to C1 × (2 + A). That is, the effective capacitance is equal to (2 + A) times the capacitance of the first capacitor C1. By using the capacitor and inverter configuration shown in Figure 9, the capacitor size is significantly reduced compared to a conventional RC ring oscillator in order to achieve a large RC time constant.

[0050]

[0060] It should be noted that other variations of the capacitive devices and resistor networks described above are also applicable to the RC ring oscillator shown in Figure 9. For example, the resistor shown in Figure 9 (e.g., R1) may be replaced with a series-connected switch-resistor network (e.g., the resistor network shown in Figure 6). Similarly, the capacitor shown in Figure 9 (e.g., C1) may be replaced with a parallel-connected switch-capacitor network (e.g., the switch-capacitor network shown in Figure 5).

[0051]

[0061] Figure 10 shows a schematic diagram of a fourth embodiment of an RC ring oscillator characterized by increased effective capacitance, according to various embodiments of the present disclosure. The RC ring oscillator comprises a first inverter 1002, a first resistor R1, a first capacitor C1, a second inverter 1004, a second resistor R2, a second capacitor C2, a third resistor R3, a third capacitor C3, a third inverter 1006, a fourth resistor R4, a fourth inverter 1008, a fifth resistor R5, and a NAND gate 1010.

[0052]

[0062] As shown in Figure 10, the first resistor R1 is connected between the output of the NAND gate 1010 and the input terminal of the first inverter 1002. The first capacitor C1 is connected between the input terminal and the output terminal of the first inverter 1002. The second resistor is connected between the output terminal of the first inverter 1002 and the input terminal of the second inverter 1004. The third resistor R3 is connected between the output terminal of the second inverter 1004 and the input terminal of the third inverter 1006. The second capacitor C2 is connected between the input terminal and the output terminal of the second inverter 1006. The fourth resistor R4 is connected between the output terminal of the third inverter 1006 and the input terminal of the fourth inverter 1008. The fifth resistor R5 is connected between the output terminal of the fourth inverter 1008 and the first input of the NAND gate 1010. The third capacitor C3 is connected between the first input of the NAND gate 1010 and ground. The second input terminal of the NAND gate 1010 is configured to receive the enable signal EN.

[0053]

[0063] Referring back to equation (3), the total capacitance provided by C1 and the first inverter 1002 is equal to C1 × (2 + A). The effective capacitance of the first capacitor C1 is equal to (2 + A) times the capacitance of the first capacitor C1. Similarly, the total capacitance provided by C2 and the third inverter 1006 is equal to C2 × (2 + A). The effective capacitance of the second capacitor C2 is equal to (2 + A) times the capacitance of the second capacitor C2. By using the capacitor and inverter configuration shown in Figure 10, the capacitor size is significantly reduced compared to a conventional RC ring oscillator in order to achieve a large RC time constant.

[0054]

[0064] It should be noted that other variations of the capacitive devices and resistor networks described above are also applicable to the RC ring oscillator shown in Figure 10. For example, the resistor shown in Figure 10 (e.g., R1) may be replaced with a series-connected switch-resistor network (e.g., the resistor network shown in Figure 6). Similarly, the capacitor shown in Figure 10 (e.g., C1) may be replaced with a parallel-connected switch-capacitor network (e.g., the switch-capacitor network shown in Figure 5).

[0055]

[0065] Figure 11 shows a flowchart of a method for controlling the oscillator shown in Figure 2, according to various embodiments of the present disclosure. The flowchart shown in Figure 11 is merely an example and does not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the various steps shown in Figure 11 may be added, deleted, replaced, rearranged, and repeated.

[0056]

[0066] In step 1102, an oscillator is provided. The oscillator comprises a first inverter, a first capacitive device connected between the input terminal and output terminal of the first inverter, and a resistor network coupled to the first capacitive device.

[0057]

[0067] In step 1104, the first inverter is configured as an inverting amplifier to increase the effective capacitance of the first capacitive device.

[0058]

[0068] In step 1106, the oscillator frequency is adjusted by adjusting at least one of the effective capacitance of the first capacitive device and the resistance of the resistor network.

[0059]

[0069] The effective capacitance of the first capacitive device is equal to (A+2) times the capacitance of the first capacitive device, where A is the voltage gain of the inverting amplifier.

[0060]

[0070] The oscillator further comprises a second inverter and a second capacitive device connected between the input and output terminals of the second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, and a third NAND gate, wherein the input terminal of the second inverter is connected to the input terminal of the first inverter and further connected to the first terminal of a resistor network, the output terminal of the second inverter is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the second NAND gate, the output terminal of the first inverter is connected to the second input terminal of the first NAND gate, the first input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, and the second The second input terminal of the NAND gate is connected to the output terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate, the second input terminal of the third NAND gate is configured to receive an enable signal, the output terminal of the third NAND gate is connected to the second terminal of a resistor network, the input terminal of the fourth inverter is connected to the output terminal of the first NAND gate, the output terminal of the fourth inverter is configured to generate a periodic AC signal, the resistor network includes a plurality of switch-resistor networks connected in series between the first terminal of the resistor network and the second terminal of the resistor network, each switch-resistor network includes resistors and switches connected in parallel.

[0061]

[0071] This method further includes turning on a predetermined number of switches in a plurality of switch-resistor circuits in order to determine the frequency of the oscillator.

[0062]

[0072] The first capacitive device includes a plurality of switch-capacitor networks connected in parallel, each switch-capacitor network including a capacitor and a switch connected in series.

[0063]

[0073] This method further includes turning on a predetermined number of switches in a plurality of switch-capacitor circuits in order to determine the frequency of the oscillator.

[0064]

[0074] While embodiments and their advantages of this disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0065]

[0075] Furthermore, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, manufactures, compositions, means, methods, and steps described herein. As will be readily apparent to those skilled in the art from the disclosure, existing or future-developed processes, machines, manufactures, compositions, means, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized in accordance with this disclosure. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions, means, methods, or steps within their scope.

Claims

1. A first inverter having input terminals and output terminals, A first capacitive device connected between the input terminal and the output terminal of the first inverter, A resistor network coupled to the first capacitive device, wherein the first inverter is configured as an inverting amplifier, and the first capacitive device and the resistor network are configured to determine the frequency of an oscillator. A device equipped with the following features.

2. The aforementioned device A second inverter having input terminals and output terminals, A second capacitive device connected between the input terminal and the output terminal of the second inverter, A third inverter having input terminals and output terminals, A fourth inverter having input terminals and output terminals, A first NAND gate, a second NAND gate, and a third NAND gate, Furthermore, The input terminal of the second inverter is connected to the input terminal of the first inverter, and further connected to the first terminal of the resistor network. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the first input terminal of the second NAND gate. The output terminal of the first inverter is connected to the second input terminal of the first NAND gate. The first input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate. The second input terminal of the third NAND gate is configured to receive an enable signal. The output terminal of the third NAND gate is connected to the second terminal of the resistor network. The input terminal of the fourth inverter is connected to the output terminal of the first NAND gate. The output terminal of the fourth inverter is configured to generate a periodic AC signal. The apparatus according to claim 1.

3. The first capacitive device comprises a first capacitor, The second capacitive device comprises a second capacitor, The resistor network includes a plurality of switch-resistor networks connected in series between the first terminal and the second terminal of the resistor network, and each switch-resistor network includes resistors and switches connected in parallel. The apparatus according to claim 2.

4. At least one of the first capacitive device and the second capacitive device includes a plurality of switch-capacitor networks connected in parallel, and each switch-capacitor network includes a capacitor and a switch connected in series. The apparatus according to claim 2 or 3.

5. The first inverter comprises a p-type transistor and an n-type transistor connected in series between a bias voltage bus and ground. The gates of the p-type transistor and the n-type transistor are connected to each other and further connected to the input terminal of the first inverter. The drain of the p-type transistor and the drain of the n-type transistor are connected to each other and further connected to the output terminal of the first inverter. The apparatus according to any one of claims 1 to 4.

6. The aforementioned device A second inverter having input terminals and output terminals, A second resistor, a third resistor, a second capacitor, a third capacitor, and a NAND gate, Furthermore, The first capacitive device comprises a first capacitor, The resistor network comprises a first resistor, The first resistor is connected between the output of the NAND gate and the input terminal of the first inverter. The second resistor is connected between the output terminal of the first inverter and the input terminal of the second inverter. The second capacitor is connected between the input terminal and ground of the second inverter. The third resistor is connected between the output terminal of the second inverter and the first input terminal of the NAND gate. The third capacitor is connected between the first input terminal of the NAND gate and ground. The second input terminal of the NAND gate is configured to receive an enable signal. The apparatus according to claim 1.

7. The aforementioned device A second inverter having input terminals and output terminals, NAND gate and Furthermore, The first capacitive device comprises a first capacitor, The resistor network comprises a first resistor, The first resistor is connected between the output of the NAND gate and the input terminal of the first inverter. The input terminal of the second inverter is connected to the output terminal of the first inverter. The output terminal of the second inverter is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is configured to receive an enable signal. The apparatus according to claim 1.

8. The aforementioned device A second inverter having input terminals and output terminals, A third inverter having input terminals and output terminals, Furthermore, The first capacitive device comprises a first capacitor, The resistor network comprises a first resistor, The input terminal of the second inverter is connected to the output terminal of the first inverter. The input terminal of the third inverter is connected to the output terminal of the second inverter. The first resistor is connected between the output terminal of the third inverter and the input terminal of the first inverter. The apparatus according to claim 1.

9. The aforementioned device A second inverter having input terminals and output terminals, A third inverter having input terminals and output terminals, A second capacitive device connected between the input terminal and the output terminal of the third inverter, A fourth inverter having input terminals and output terminals, A second resistor, a third resistor, a fourth resistor, a fifth resistor, a third capacitor, and a NAND gate, Furthermore, The first capacitive device comprises a first capacitor, The second capacitive device comprises a second capacitor, The resistor network comprises a first resistor, The first resistor is connected between the output of the NAND gate and the input terminal of the first inverter. The first capacitor is connected between the input terminal and the output terminal of the first inverter. The second resistor is connected between the output terminal of the first inverter and the input terminal of the second inverter. The third resistor is connected between the output terminal of the second inverter and the input terminal of the third inverter. The second capacitor is connected between the input terminal and the output terminal of the third inverter. The fourth resistor is connected between the output terminal of the third inverter and the input terminal of the fourth inverter. The fifth resistor is connected between the output terminal of the fourth inverter and the first input of the NAND gate. The third capacitor is connected between the first input of the NAND gate and ground. The second input terminal of the NAND gate is configured to receive an enable signal. The apparatus according to claim 1.

10. The inverting amplifier is configured such that the effective capacitance of the first capacitive device is equal to (A + 2) times the capacitance of the first capacitive device, where A is the voltage gain of the inverting amplifier. The apparatus according to any one of claims 1 to 9.

11. To provide an oscillator comprising a first inverter, a first capacitive device connected between the input terminal and output terminal of the first inverter, and a resistor network coupled to the first capacitive device, The first inverter is configured as an inverting amplifier for increasing the effective capacitance of the first capacitive device, The frequency of the oscillator is adjusted by adjusting at least one of the effective capacitance of the first capacitive device and the resistance of the resistor network. Methods that include...

12. The effective capacitance of the first capacitive device is equal to (A + 2) times the capacitance of the first capacitive device, where A is the voltage gain of the inverting amplifier. The method according to claim 11.

13. The oscillator, A second inverter and a second capacitive device connected between the input terminal and output terminal of the second inverter, A third inverter, a fourth inverter, a first NAND gate, a second NAND gate, and a third NAND gate, Furthermore, The input terminal of the second inverter is connected to the input terminal of the first inverter, and further connected to the first terminal of the resistor network. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the first input terminal of the second NAND gate. The output terminal of the first inverter is connected to the second input terminal of the first NAND gate. The first input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate. The second input terminal of the third NAND gate is configured to receive an enable signal. The output terminal of the third NAND gate is connected to the second terminal of the resistor network. The input terminal of the fourth inverter is connected to the output terminal of the first NAND gate. The output terminal of the fourth inverter is configured to generate a periodic AC signal. The resistor network includes a plurality of switch-resistor networks connected in series between the first terminal and the second terminal of the resistor network, and each switch-resistor network includes resistors and switches connected in parallel. The method according to claim 11 or 12.

14. To determine the frequency of the oscillator, a predetermined number of switches in the plurality of switch-resistor circuits are turned on. The method according to claim 13, further comprising:

15. The first capacitive device includes a plurality of switch-capacitor networks connected in parallel, and each switch-capacitor network includes a capacitor and a switch connected in series. The method according to any one of claims 11 to 14.

16. To determine the frequency of the oscillator, a predetermined number of switches in the plurality of switch-capacitor circuits are turned on. The method according to claim 15, further comprising:

17. A first inverter having input terminals and output terminals, A first capacitive device connected between the input terminal and the output terminal of the first inverter, A second inverter having input terminals and output terminals, A second capacitive device connected between the input terminal and the output terminal of the second inverter, A resistor network connected to the input terminals of the first inverter and the input terminals of the second inverter, wherein the first capacitive device, the second capacitive device and the resistor network are configured to determine the frequency of the oscillator. A system that includes these features.

18. The aforementioned system A third inverter having input terminals and output terminals, A fourth inverter having input terminals and output terminals, A first NAND gate, a second NAND gate, and a third NAND gate, Furthermore, The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the first input terminal of the second NAND gate. The output terminal of the first inverter is connected to the second input terminal of the first NAND gate. The first input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate. The second input terminal of the third NAND gate is configured to receive an enable signal. The output terminal of the third NAND gate is connected to the resistor network, The input terminal of the fourth inverter is connected to the output terminal of the first NAND gate. The output terminal of the fourth inverter is configured to generate a periodic AC signal. The system according to claim 17.

19. The first capacitive device comprises a first capacitor, The second capacitive device comprises a second capacitor. The system according to claim 17 or 18.

20. The resistor network includes a plurality of switch-resistor networks connected in series between the first terminal and the second terminal of the resistor network, and each switch-resistor network includes resistors and switches connected in parallel. The system according to any one of claims 17 to 19.

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