Voltage range for training physical memory

Abstract

The voltage range for training physical memory is described. The device can be configured to include a PHY having an interface for supporting communication of command signals and data to physical memory. The PHY performs a training mode for training the interface over the training voltage range to communicate command signals or data, and an operating mode for communicating command signals or data over an operating voltage range smaller than the training voltage range using the trained interface.

Description

Technical Field

[0001] (Related Application) This application claims the priority of U.S. Patent Application No. 18 / 305,080, filed on April 21, 2023, entitled "Voltage Range for Training Physical Memory", the entire disclosure of which is hereby incorporated by reference in its entirety.

Background Art

[0002] The amount of data and the speed at which data can be accessed from physical memory by a computing device are driving factors for overall device operation. Due to this operational impact, techniques for increasing this speed, accuracy, and memory capacity of physical memory have been continuously developed, and as an example, dynamic random access memory (DRAM) can be mentioned. However, this continuous development faces further issues that affect the case where data can be accessed from physical memory, issues arising from the environmental conditions (e.g., heat) of the operation of physical memory, and the like.

[0003] A detailed description will be given with reference to the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] It is a block diagram of a non-limiting exemplary system configured to employ the training and operation mode techniques described herein. [Figure 2] It is a block diagram of a non-limiting exemplary system that more specifically shows the configuration of the PHY of FIG. 1 when communicatively coupled via an interface to a physical memory implemented using a plurality of dynamic random access memory (DRAM) devices. [Figure 3] It is a block diagram of a non-limiting exemplary system showing the training voltage range in the training mode and the operation voltage range in the operation mode. [Figure 4] This is a non-limiting, exemplary system block diagram demonstrating the individualized programmability of a dynamic random access memory (DRAM) device for implementing the training voltage range in training mode and the operating voltage range in operation mode. [Figure 5] This figure shows the procedure in an exemplary embodiment of the training and operating mode voltage range for an interface that enables communication between the PHY and physical memory. [Modes for carrying out the invention]

[0005] (overview) The PHY, also known as the physical layer, is typically implemented as an integrated circuit to provide a physical interface in hardware between a processing unit (e.g., a central processing unit) and physical memory (e.g., dynamic random access memory). The PHY is responsible for converting digital data from the processing unit into analog electrical signals that are transmitted to physical memory via the physical interface. Similarly, the PHY is also responsible for converting analog electrical signals received via the physical interface into digital data used by the processing unit.

[0006] As part of implementing the physical interface, the PHY performs training (e.g., adjustable at startup and during operation) to configure the parameters of the physical interface in order to optimize communication. This training is available to the PHY to address differences in processing unit and physical memory design, changes in operating conditions (e.g., temperature), etc. An example of a parameter configured as part of the training is impedance calibration, which is configured by adjusting the termination resistance values ​​in the PHY and physical memory. Impedance calibration is used to match the impedances of the transmitter and receiver, which are utilized by the physical interface between the PHY and physical memory to reduce signal reflections and maintain signal quality. Voltage and timing reference parameters are also configured as part of the training by adjusting voltage levels and clock phases to establish common voltage and timing references for signals communicated between the PHY and physical memory. Read and write leveling is configured as part of the training by adjusting the relative timing of clock and data signals via the physical interface to adjust data sampling. The data strobe signal (DQS) aligns with the data signal (DQ) during a read operation, for example, and defines "when" the data signal is sampled based on the data strobe signal.

[0007] However, conventional techniques used to perform training with PHYs are inefficient, time-consuming to execute, and lead to increased power consumption. Examples of conventional training techniques include brute-force approaches or reliance on prior knowledge of the device. In conventional brute-force approaches, for each parameter, such as impedance, voltage and timing criteria, equalization settings, clock phase, etc., as mentioned above, the PHY tests the range of possible values. As a result, the PHY is tasked with comparing and evaluating each combination of parameters to identify the optimal combination that yields the best result, such as the fastest communication speed while also supporting reliable communication. Therefore, conventional brute-force approaches can consume considerable resources when evaluating a potentially large number of parameter combinations.

[0008] The a priori approach relies on careful measurement and characterization of components to set parameters. In the a priori approach, for example, impedance and data throughput are measured and characterized for the physical connection between the PHY and physical memory. However, such measurements and resulting characterizations are difficult to achieve accurately in real-world scenarios due to process variations in manufacturing the components and may vary due to changes in environmental conditions faced in the typical operation of the components.

[0009] To address these technical challenges, the PHY implements a training mode to train parameters as part of the physical interface that supports the communication of data and command signals between the PHY and physical memory. Once the physical interface parameters are set by the training mode, the operation mode is used to support increasing the signaling speed of data and command signals.

[0010] In training mode, a first range of voltages is used by the PHY to determine the parameter values ​​as described above. For example, the voltage reference (Vref) parameter has a value learned as part of the training. The voltage reference parameter defines a stable reference voltage that can be used as part of differential signaling, as an intermediate reference voltage to distinguish between high logic levels and low logic levels, for example, 1 and 0, based on whether the detected voltage level is above or below the reference voltage. Therefore, training the voltage reference parameter by the PHY involves determining the reference voltage to be set as the voltage reference parameter.

[0011] To determine the value of the voltage reference (Vref) parameter, the PHY sets a first range of voltages as part of the training mode. This first range is set by the PHY by modifying weakly terminated termination conditions in physical memory (e.g., the use of termination resistors to electrically terminate transmission lines) and output impedance to support, for example, a "rail-to-rail" voltage amplitude of 0.1 volts to 1.1 volts. The initial value of the voltage reference (Vref) parameter is set within this first range, which is "known to be good," and is optimized along with training other parameters of the physical interface, as described above.

[0012] During training mode, once the values ​​of the voltage reference (Vref) parameter and other parameters are set, the PHY initiates an operating mode with a reduced signal range to support, for example, an increased signal velocity from 0.85 volts to 1.1 volts. Voltage level changes across the increased voltage range in training mode take longer to execute than, for example, voltage level changes across the reduced voltage range in operating mode. However, during training performed in training mode, a larger voltage range acts to improve the efficiency of training the physical interface (e.g., through the use of Vref, which is known to be good), because the signal velocity at that point is a lower priority than realizing the entire trained interface. Once training is complete, the reduced voltage range is used in operating mode to increase the signal velocity. Further explanations of these and other examples are included in the following sections and shown in the corresponding figures.

[0013] In some embodiments, the technology described herein relates to a device including a physical layer (PHY) having an interface for supporting communication of command signals and data to physical memory, wherein the PHY performs a training mode for training the interface over a training voltage range for communicating command signals or data, and an operating mode for communicating command signals or data over an operating voltage range smaller than the training voltage range using the trained interface.

[0014] In some embodiments, the technology described herein relates to a device that implements an interface protocol in which the interface employs parameters used to control communication of command signals and data to physical memory.

[0015] In some embodiments, the techniques described herein relate to a device in which the training mode detects the values ​​of parameters of an interface protocol, and the operation mode uses the detected parameters.

[0016] In some embodiments, the techniques described herein relate to devices, and the parameters relate to signals or timing.

[0017] In some embodiments, the techniques described herein relate to devices, and the parameters relate to voltage reference (Vref) training, command training, clock-to-straw leveling, write leveling training, or strobe-to-DQ training of interface protocols.

[0018] In some embodiments, the techniques described herein relate to devices, and the parameters relate to how signals propagate from one physical memory component of physical memory to another physical memory component of physical memory.

[0019] In some embodiments, the techniques described herein relate to a device in which the training mode is configured to modify the termination state or output impedance of the PHY in order to implement the training voltage range of the training mode.

[0020] In some embodiments, the techniques described herein relate to a device, and the training mode is further configured to modify the termination state or output impedance of the physical memory in order to implement a training voltage range as part of the training mode.

[0021] In some embodiments, the techniques described herein relate to devices in which the training mode operates at a frequency lower than that of the operating mode.

[0022] In some aspects, the techniques described herein relate to a device, where the PHY includes another interface for transmitting command signals and data using a memory controller.

[0023] In some aspects, the techniques described herein relate to a device, where the PHY is implemented in hardware as part of an integrated circuit, the interface is bidirectional, and the physical memory is a dynamic random access memory (DRAM).

[0024] In some aspects, the techniques described herein relate to a system that includes a memory controller, a dynamic random access memory (DRAM), and a physical layer (PHY) that provides a communication link between the memory controller and the DRAM. The PHY implements a training mode for detecting values of parameters as part of training an interface between the PHY and the DRAM, the training mode operating over a training voltage range, and an operating mode for implementing the interface between the PHY and the DRAM using the detected values of the parameters, the operating mode operating over an operating voltage range smaller than the training voltage range.

[0025] In some aspects, the techniques described herein relate to a system, where the training mode is configured to modify the termination state and output impedance of the PHY to implement the training voltage range of the training mode.

[0026] In some aspects, the techniques described herein relate to a system, where the training mode is further configured to modify the termination state and output impedance of the dynamic random access memory (DRAM) to implement the training voltage range as part of the training mode.

[0027] In some embodiments, the techniques described herein relate to systems, and the parameters include signals or timings.

[0028] In some embodiments, the techniques described herein relate to systems, and the parameters include voltage reference (Vref) training.

[0029] In some embodiments, the techniques described herein relate to systems, and the parameters include command training, clock versus straw leveling, or straw versus DQ training.

[0030] In some embodiments, the techniques described herein are methods, and include setting a training mode for training an interface between a physical layer (PHY) and physical memory for communicating command signals or data, the training mode employing a training voltage range, and setting an operating mode for operating the trained interface between the PHY and physical memory for communicating command signals or data, the operating mode employing an operating voltage range smaller than the training voltage range.

[0031] In some embodiments, the techniques described herein relate to methods, and the training mode is configured to modify the termination state and output impedance of the PHY in order to implement the training voltage range of the training mode.

[0032] In some embodiments, the techniques described herein relate to systems, and interface training is voltage reference (Vref) training.

[0033] Figure 1 is a block diagram of a non-limiting exemplary system 100 configured to employ the training and operating mode techniques described herein. These techniques are available through a wide range of device configurations 102. Examples of such devices include, but are not limited to, computing devices, servers, mobile devices (e.g., wearables, mobile phones, tablets, laptops), processors (e.g., graphics processing units, central processing units, and accelerators), digital signal processors, interference accelerators, disk array controllers, hard disk drive host adapters, memory cards, solid-state drives, wireless communication hardware connections, Ethernet® hardware connections, switches, bridges, network interface controllers, and other device configurations. Additional examples include artificial intelligence training accelerators, cryptographic and compression accelerators, network packet processors, and video coders and decoders. In various embodiments, it should be understood that the techniques described herein may be used with any one or more of the devices listed above and / or various other devices without departing from the spirit or scope of the described techniques.

[0034] An example of device 102 includes a processing unit 104 having a core 106 that is communicably coupled (e.g., via a bus) to a memory controller 108, which is communicably coupled (e.g., via a bus) to a physical memory 110. The processing unit 104 is configured in hardware to execute instructions as arithmetic and logical operations, to control input / output devices, and to manage data storage and retrieval. The processing unit can be configured as a central processing unit, a graphics processing unit, and other processing units including digital signal processing, tensor processing units, and field-programmable gate arrays. The core 106 as part of the processing unit 104 can be configured in various ways to execute instructions as part of the processing unit 104 to perform operations in hardware, for example, as one or more integrated circuits for running an operating system 112, an application 114, etc. Other configurations are also possible, examples of which include parallel processors, graphics processing units, etc.

[0035] In one example, the memory controller 108 is configured for use as an I / O device, for example, as an input / output memory management unit (IOMMU) (in hardware such as an integrated circuit or a microcontroller configured to execute instructions). The memory controller 108 can be configured as part of the processing unit 104 itself (for example, as an on-die memory controller) or as a separate component on the motherboard of device 102. Although a single instance of physical memory 110 is illustrated, physical memory 110 can represent multiple physical memory components 116, for example, various types of physical memory that can be implemented together (for example, implemented in hardware) as volatile and non-volatile memory.

[0036] The memory controller 108 is configured to control access between the core 106 and the physical memory 110. The memory controller 108 can be configured in hardware, for example, using one or more integrated circuits, and supports instruction execution through configuration as a microcontroller, etc. In the example shown, the memory controller 108 supports the core 106 in using the virtual memory address 118 in the virtual address space together with the physical memory address 120 in the physical address space of the physical memory 110. Virtual memory is a technique for managing the use of shared physical memory 110 by, for example, multiple cores. Virtual memory supports a variety of different functions. Examples of these functions include expanding the amount of storage available to applications beyond the amount actually available in physical memory, offloading memory management from applications 114 and the operating system 112, using various different types of memory without the application's awareness, supporting memory optimization, address memory fragmentation, etc.

[0037] The physical layer (PHY) 122 is employed by the processing unit 104 and implements a physical interface 124 with the physical memory 110. The PHY 122 can be configured as hardware in an integrated circuit, for example, that is communicatively located between the processing unit 104 and the physical memory 110 (e.g., dedicated or included as part of the processing unit 104). The PHY 122 is configured to support interoperability between the processing unit 104 and the physical memory 110, even if developed by different manufacturers. To this end, the PHY 122 defines programmable signals, timings, and other parameters as part of training to define how command signals and data are transmitted via the physical interface 124.

[0038] Training is performed by PHY122 to set parameters of the physical interface 124 (e.g., adjustable at startup and during operation) to optimize communication. An example of a parameter set as part of the training is impedance calibration, which is set by adjusting the termination resistance values ​​in PHY122 and physical memory 110. Impedance calibration is used to match the transmitter and receiver impedances utilized by the physical interface 124 between PHY122 and physical memory 110 to reduce signal reflections and maintain signal quality. Voltage and timing reference parameters are also set as part of the training by adjusting voltage levels and clock phases to establish common voltage and timing references for signals communicated between PHY122 and physical memory 110. Read and write leveling is set as part of the training by adjusting the relative timing of the clock and data signals via the physical interface 124 to adjust data sampling. The data strobe signal (DQS) is aligned with the data signal (DQ) during read operations, for example, to define "when" the data signal is sampled based on the data strobe signal.

[0039] To maximize the speed of command signal and data communication via the physical interface 124, the PHY 122 supports training mode 126 and operation mode 128. Training mode 126 operates as a kind of handshake technique to determine the values ​​of programmable parameters used to implement the protocol.

[0040] Traditional techniques for performing training are carried out in one of two ways, as described above. The first, brute-force example faces a considerable amount of trial and error, as different values ​​are set and tested for parameters. This example faces operational inefficiencies, delays, increased power consumption, etc., due to the large number of parameters being tested and the large number of values ​​that can be used for those parameters. The second example employs an a priori approach, relying on careful measurement and characterization of processing units, physical memory, and the interfaces between them, which are difficult to achieve in real-world scenarios. This challenge is further exacerbated when faced with changing environmental conditions.

[0041] To overcome these challenges, a training mode 126 is employed that uses a training voltage range 130 that is larger than the operating voltage range 132 used as part of the operating mode 128. In this way, as will be further explained below, a reduction in training time and an improvement in accuracy are achieved in training mode 126 while maintaining the faster communication speed supported by the operating mode 128.

[0042] In the initial stages of training performed by training mode 126, for example, the voltage reference (Vref) setting value is not set. Therefore, asynchronous techniques are employed in the initial training stages where Vref is not used until its value is determined. To reduce the time spent on training, the training voltage range 130 is initially employed by PHY 122 as part of the training to support "rail-to-rail" voltage amplitudes. This voltage amplitude is used to define the minimum voltage that defines logic 1 (VIHmin) and the maximum voltage that defines logic 0 (VILmax). This is done by modifying the termination state and output impedance of the physical interface 124 between PHY 122 and physical memory 110 to support this increasing range, for example, so that it is weakly terminated in physical memory 110.

[0043] Once the asynchronous feedback portion of training mode 126 is complete and the value of Vref is determined, the termination state and output impedance are returned to the operating voltage range 132 by the PHY 122. Thus, once trained, the physical interface 124 operates with increased signal velocity and improved efficiency using the parameters learned during training mode 126. As a result, the time required to execute the asynchronous portion of training to determine the value of Vref is reduced, the operating mode is achieved in a shorter time, and thereby improves device operation.

[0044] Figure 2 is a block diagram of a non-limiting exemplary system 200 that shows in more detail the configuration of PHY 122 when it is communicably coupled via a physical interface 124 to a physical memory 110 implemented using multiple dynamic random access memory (DRAM) devices 202(1), ..., 202(N). The exemplary PHY 122 includes multiple bidirectional transceivers implementing DQ lanes 204, DM lanes 206, DQS lanes 208, command / address lanes 210, and a clock 212. The DQ lanes 204 carry data signal transmission via their respective wires, illustrated, for example, using bidirectional arrows. The DM lanes 206 carry data mask signals. The data mask signals are used to selectively enable or disable writing data from the DQ lanes 204 to memory. When the data mask signals are asserted (activated), the corresponding data bits are masked or ignored during the write operation, thereby allowing the memory controller to selectively write data to a specific memory location without affecting adjacent locations. DQS lane 208 implements a data strobe that transmits clock signals for DQ lane 204 and DM lane 206. The data strobe is used to control sampling of DQ lane 204 and DM lane 206, for example, based on the rising and falling edges of the signal. For example, the data strobe of DQS lane 208 is used to control the timing at which a data signal is sampled from DQ lane 206 to define a logical 1 or 0.

[0045] The command / address lane 210 supports the communication of command signals to the DRAM device 202(1), for example, to each transceiver. Various types of command signals and associated addresses are sent from the PHY 122 using the command / address lane 210, examples of which include maintenance signals, setup signals, and data retention command signals such as "read" and "write". In the case of "read" and "write", the command signal is sent via the command / address lane, and data is transmitted from the PHY 122 to the DRAM device 202(1) via the DQ lane 204 in the case of writes, and these are sampled based on data strobe signals from the DQS lane 208. Conversely, in read commands, data is transmitted from the DRAM device 202(1) to the PHY 122 via the DQ lane 204, and this is also sampled based on data strobe signals from the DQS lane 208.

[0046] In some examples, multiple DRAM devices are coupled together in a communicative manner via the physical interface 124 of the PHY122. This is implemented, in one example, via a bidirectional multidrop bus to support communication with DRAM devices 202(1), ..., DRAM device 202(N). However, the use of a bidirectional multidrop bus introduces challenges such as signal discontinuities and reflections caused by the load on both sides of DRAM device 202(1). For example, writing from the PHY122 to DRAM device 202(N) involves recognition of DRAM device 202(1) on the multidrop bus placed between the PHY122 and DRAM device 202(N), for example, to terminate the bus to prevent unwanted signal reflections.

[0047] However, training the physical interface 124 presents a "chicken and the egg" problem. For example, training one type of parameter may depend on another type of parameter. As a result, training actually faces asynchronous feedback that defines levels with unknown timing relationships, rather than poorly formed feedback (i.e., not formed as data packets with strobes and data bits). Furthermore, training typically relies on ordering, such as training the command / address lane 210 before training the DQ lane 204.

[0048] As a result, initial training is performed by PHY122 without knowledge of the precise timing of the command / address lane 210, and without precise voltage or time references for the transceiver implementing the physical interface 124. However, training by PHY122 still relies on feedback received from the DRAM device and the interpretation of that feedback. Conventional techniques to address this involve brute-force methods involving many different input voltage levels, reference levels, etc., to determine "what works," as described above. On the other hand, a priori knowledge involves careful measurement of the hardware, the accuracy of which is limited by manufacturing precision, dispersion, and environmental conditions (e.g., heat).

[0049] Therefore, in this example, PHY122 utilizes the training voltage range 130 during training mode 126 to provide a larger voltage amplitude, and thus increased detectability. PHY122 does this by modifying the termination state and output impedance of the physical memory 110, as well as for PHY122 itself. The termination state and output impedance are set, for example, using values ​​in the corresponding transistors. Setting the values ​​in the corresponding transistors compels the signal to have a wider amplitude (e.g., between rails) in the training voltage range 130. Once training (e.g., a portion of training with asynchronous feedback) is complete, PHY122 returns to the operating voltage range 132 using the parameters detected during training mode 126, which have a smaller voltage amplitude to support higher data transmission rates.

[0050] Figure 3 is a block diagram of a non-limiting, exemplary system 300 showing the training voltage range 130 for training mode 126 and the operating voltage range 132 for operating mode 128. In the example shown, the voltage range is 0 volts to 1.1 volts for the physical interface 124 between the physical memory 110 and the PHY 122.

[0051] In operating mode 128, the operating voltage range 132 is defined as 0.85 volts to 1.1 volts. This is used to support higher communication frequencies (in the gigahertz range) by minimizing the detected voltage amplitude, for example, the minimum voltage defining logic 1 (VIHmin) and the maximum voltage defining logic 0 (VILmax). This is because shorter voltage amplitudes can be performed in a shorter time to change the voltage on the wires implementing the physical interface 124, and therefore support these higher frequencies.

[0052] On the other hand, in training mode 126, the communication speed is not a driving factor and is therefore feasible at reduced frequencies, for example, in the megahertz range. Based on this insight, the training voltage range 130 is set by PHY 122 to 0.1 volts to 1.1 volts. This is done, for example, by modifying the termination strength and output impedance parameters of DRAM devices 202(1) to 202(N) and PHY 122, which are set via their respective bits using associated transistors.

[0053] Using the larger amplitude of the training voltage range 130 in training mode 126, for example, the "assured operation" value of the voltage reference (Vref) can be set for use as part of training regardless of process fluctuations and environmental conditions, which is not possible with conventional techniques. Furthermore, these techniques support interleaving between training mode 126 and operating mode 128 to deal with changes in environmental conditions, for example.

[0054] Figure 4 is a block diagram of a non-limiting, exemplary system 400 showing the individualized programmability of DRAM devices 202(1) to 202(N) for implementing the training voltage range 130 of training mode 126 and the operating voltage range 132 of operation mode 128. Each of the PHY 122 and DRAM devices 202(1) to 202(N) can be configured to include, for example, independently programmable terminations 402, 404(1), 404(N) and registers 406, 408(1) to 408(N) for different voltage ranges. The independent programmability provided by the PHY 122 supports individualized training.

[0055] DRAM devices 202(1)–202(N) include, for example, registers 408(1)–408(N) that can be programmed to different values. Examples of these registers and their corresponding functions include a default mode register (e.g., RTT_Park), a register specifying the resistor to which the signal sending write commands to physical memory 110 terminates (e.g., RTT_WR), and so on. Each DRAM device 202(1)–202(N) that shares a communication coupling (e.g., via wires) is generally referred to as a "rank." Therefore, training a particular rank involves individually changing the terminations between these various states to control which "which" rank is being trained along its communication coupling. Various other examples are also contemplated.

[0056] Figure 5 shows step 500 in an exemplary embodiment of a stepwise algorithm that provides a structure for training and operating mode voltage ranges to a physical interface that connects the physical layer (PHY) to the physical memory in a communicative manner.

[0057] The training mode is configured to train the interface between the PHY and physical memory for communicating command signals or data. The training mode uses a training voltage range (block 502). For example, PHY122 sets the training voltage range 130 in PHY122 and / or individual DRAM devices 202(1) to 202(N) by setting the termination state or output impedance using the corresponding transistor.

[0058] The operating mode is configured to operate a trained interface between the PHY and physical memory for communicating command signals or data. The operating mode employs an operating voltage range smaller than the training voltage range (block 504). For example, operating mode 128 uses parameters trained as part of training mode 126. Operating mode 128 then uses these parameters in an operating voltage range 132 smaller than the training voltage range 130 of training mode 126, which is also set by the corresponding transistor. In this way, higher frequencies are supported as part of operating mode 128, which benefits from the reduced training time of training mode 126 operating at lower frequencies. Various other examples are also considered.

[0059] It should be understood that many variations are possible based on the disclosures herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0060] The various functional units shown in the figures and / or described herein (including device 102 where appropriate) are implemented in any of a variety of different forms, such as hardware circuitry, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The methods provided are implemented in any of a variety of devices, such as general-purpose computers, processors, or processor cores. Suitable processors include, by example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), graphics processing units (GPUs), parallel accelerators, multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines.

[0061] In one or more embodiments, the methods and procedures provided herein can be implemented in computer programs, software, or firmware incorporated into a non-temporary computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-temporary computer-readable storage media include magnetic media such as read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, internal hard disks, and removable disks, as well as magnetic-optical media such as CD-ROM disks and digital versatile disks (DVDs).

[0062] While systems and technologies have been described in language specific to their structural features and / or methodological actions, it should be understood that the systems and technologies defined in the attached claims are not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as exemplary forms of carrying out the claimed invention.

Claims

1. It is a device, It includes a physical layer (PHY) with an interface that supports communication of command signals and data with physical memory, The aforementioned PHY is, A training mode for training the interface over a training voltage range in order to communicate the command signals or data, An operating mode for communicating the command signal or data over an operating voltage range smaller than the training voltage range using a trained interface, To implement device.

2. The interface implements an interface protocol that employs parameters used to control the communication of the command signal and the data with the physical memory. The device according to claim 1.

3. The training mode detects the values ​​of the parameters of the interface protocol, and the operation mode uses the detected parameters. The device according to claim 2.

4. The aforementioned parameters relate to signals or timing. The device according to claim 2.

5. The parameters relating to the voltage reference (Vref) training, command training, clock-to-straw leveling, write leveling training, or strobe-to-DQ training of the interface protocol, The device according to claim 2.

6. The aforementioned parameters relate to how signals propagate from one physical memory component of the physical memory to another physical memory component of the physical memory. The device according to claim 2.

7. The training mode is configured to modify the termination state or output impedance of the PHY in order to implement the training voltage range of the training mode. The device according to claim 1.

8. The training mode is configured to modify the termination state or output impedance of the physical memory in order to implement the training voltage range as part of the training mode. The device according to claim 1.

9. The aforementioned training mode operates at a frequency lower than the frequency of the aforementioned operating mode. The device according to claim 1.

10. The PHY includes another interface for transmitting command signals and data to and from the memory controller. The device according to claim 1.

11. The PHY is implemented in hardware as part of an integrated circuit, the interface is bidirectional, and the physical memory is dynamic random access memory (DRAM). The device according to claim 1.

12. It is a system, Memory controller and Dynamic Random Access Memory (DRAM), The system comprises a physical layer (PHY) that provides communication connectivity between the memory controller and the DRAM, The aforementioned PHY is, A training mode for detecting parameter values ​​as part of training the interface between the PHY and the DRAM, the training mode operating over a training voltage range, An operating mode for implementing the interface between the PHY and the DRAM using the detected parameter values, the operating mode operating over an operating voltage range smaller than the training voltage range, To implement system.

13. The training mode is configured to modify the termination state and output impedance of the PHY in order to implement the training voltage range of the training mode. The system according to claim 12.

14. The training mode is configured to modify the termination state and output impedance of the dynamic random access memory (DRAM) in order to implement the training voltage range as part of the training mode. The system according to claim 13.

15. The aforementioned parameters include signals or timings. The system according to claim 12.

16. The aforementioned parameters include voltage reference (Vref) training, The system according to claim 12.

17. The aforementioned parameters include command training, clock vs. straw leveling, or straw vs. DQ training. The system according to claim 12.

18. It is a method, A training mode for training the interface between the physical layer (PHY) and physical memory for communicating command signals or data, comprising setting a training mode that employs a training voltage range, An operating mode for operating a trained interface between the PHY and the physical memory to communicate command signals or data, including setting an operating mode that employs an operating voltage range smaller than the training voltage range, method.

19. The training mode is configured to modify the termination state and output impedance of the PHY in order to implement the training voltage range of the training mode. The method of claim 18.

20. The training of the interface is voltage-referenced (Vref) training. The method of claim 18.

Images