Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes the steps of: forming a structure to be wired, comprising a first chip and a resin encapsulation layer, wherein a plurality of pads are provided on the front surface of the first chip, and at least the chip sides of the first chip are sealed by the resin encapsulation layer; forming a rewiring layer, wherein the rewiring layer is located on the front surface of the chip and is electrically connected to the pads, and the rewiring layer is provided with at least one stepped structure facing the resin encapsulation layer; forming at least one through-hole in the resin encapsulation layer that penetrates the resin encapsulation layer, wherein each through-hole corresponds to one stepped structure, and the orthographic projection of the through-hole onto the plane on which the front surface of the chip is located is entirely within the orthographic projection of the rewiring layer onto the said plane, and at least partially overlaps with the orthographic projection onto the said plane of the portion of the corresponding stepped structure that is not in contact with the resin encapsulation layer; and filling the through-hole with a fluid conductive material, forming a conductive portion after the conductive material has solidified, providing an electrical element on the back surface of the chip, and joining at least one electrical element to the conductive portion.

Description

Technical Field

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[0001] The present invention relates to the technical field of semiconductors, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. <Cross-reference to related applications> This application claims the priority of a Chinese patent application with an application number of 2023106322309 and a filing date of May 30, 2023, and all of its contents are incorporated herein by reference.

Background Art

[0002] In conventional semiconductor packaging technology, usually, a lead frame or a conductive copper pillar is used to realize the electrical connection between the front and back surfaces of a chip. The chip packaging technology may include a process of attaching the chip and the lead frame or the conductive copper pillar to a carrier substrate and sealing them with a hot press resin.

[0003] However, in the process of sealing the chip and the lead frame or the conductive copper pillar with a hot press resin, deformation and displacement of the lead frame and the conductive copper pillar are likely to occur, thereby causing problems such as short circuits and open circuits between the redistribution layer located on the front surface of the chip and the lead frame or the conductive copper pillar, which affects the yield of the product.

Summary of the Invention

[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] The first aspect of the embodiments of the present invention is a step of forming a structure to be wired, wherein the structure to be wired includes a first chip and a resin encapsulation layer. The first chip includes a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface. A plurality of pads are provided on the chip front surface, and at least the chip side surfaces are encapsulated by the resin encapsulation layer. A step of forming a redistribution layer, wherein the redistribution layer is located on the front of the chip and electrically connected to the pad, and the redistribution layer is provided with at least one stepped structure toward the resin encapsulation layer, A step of forming at least one through-hole in the resin encapsulation layer, wherein each through-hole corresponds to one of the stepped structures, the orthographic projection of the through-hole onto the plane on which the front surface of the chip is located is entirely within the orthographic projection of the redistribution layer onto the plane, and the orthographic projection of the through-hole onto the plane at least partially overlaps with the orthographic projection of the portion of the corresponding stepped structure that is not in contact with the resin encapsulation layer onto the plane. The present invention provides a method for manufacturing a semiconductor structure, which includes the steps of: filling the through-hole with a fluid conductive material; forming a conductive portion after the conductive material has solidified; providing an electrical element on the back side of the chip; and joining at least one of the electrical elements to the conductive portion.

[0006] In one embodiment, the step of forming the redistribution layer is: The step of forming a first trace layer and a second trace layer located on the structure to be routed, on the side of the first trace layer away from the structure to be routed, thereby obtaining a rerouting layer including the first trace layer and the second trace layer, The first trace layer comprises a plurality of first trace structures, each of which is electrically connected to the pad; the second trace layer comprises a second trace structure located on the side of each of the first trace structures away from the structure to be routed, wherein at least one side of at least one of the second trace structures protrudes from the corresponding first trace structure to form a stepped structure.

[0007] In one embodiment, the orthographic projection onto the plane of the portion of the edge of the through hole that is not in contact with the rewiring layer lies inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin sealing layer, and / or The distance between the surface of the stepped structure that faces the resin sealing layer and is not in contact with the resin sealing layer and the resin sealing layer is in the range of 10 μm to 60 μm.

[0008] In one embodiment, after forming the redistribution layer, a semiconductor intermediate structure is obtained, the resin encapsulation layer includes a cut line, the redistribution layer is in contact with a region of the resin encapsulation layer located outside the cut line, and before forming a plurality of through holes penetrating the resin encapsulation layer, the method for manufacturing the semiconductor structure is as follows: The step further includes arranging the semiconductor intermediate structure on a support member, The support member includes a plate portion and a support portion formed extending from one side of the plate portion, the support portion being in contact with the cut line, and the rewiring layer facing the plate portion with a gap between it and the plate portion. After providing an electrical element on the back surface of the chip and joining at least one of the electrical elements to the conductive portion, the method for manufacturing the semiconductor structure is as follows: The process further includes the step of cutting the obtained structure along the aforementioned cut line.

[0009] In one embodiment, the through-hole is filled with a fluid conductive material, and after the conductive material solidifies, the conductive portion is formed. The method for manufacturing the semiconductor structure is as follows: A step of filling a filler between the surface of the stepped structure facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer to form a filled portion, or The method further includes the step of forming a resin-sealing film layer, the resin-sealing film layer covering the redistribution layer and filling the gap between the surface of the stepped structure facing the resin-sealing layer and not in contact with the resin-sealing layer and the resin-sealing layer.

[0010] In one embodiment, the electrical element includes a second chip, the electrical element is provided on the back side of the chip, and after joining at least one of the electrical elements to the conductive portion, the method for manufacturing the semiconductor structure is as follows: The method further includes the step of filling a filler between the second chip and the resin sealing layer to form a filled structure.

[0011] In one embodiment, the surface of the conductive portion that is away from the rewiring layer protrudes more than the surface of the resin encapsulating layer that is away from the rewiring layer.

[0012] In one embodiment, the manufacturing method further includes the step of forming a heat dissipation layer, the heat dissipation layer being formed simultaneously with the conductive portion.

[0013] In one embodiment, the electrical element includes at least one of a second chip, an inductor, a resistor, and a capacitor, and / or The conductive material includes at least one of solder and silver paste.

[0014] A second embodiment of the present invention is: A first chip comprising a chip front, a chip back facing the chip front, and a plurality of chip sides connecting the chip front and the chip back, wherein a plurality of pads are provided on the chip front, A resin sealing layer covering the side surface of the chip, wherein the resin sealing layer is provided with at least one through hole, A conductive part located at least partially within the through hole, wherein the material of the conductive part includes at least one of solder and silver paste, A redistribution layer disposed on the side of the resin encapsulation layer closest to the front surface of the chip, electrically connected to the pad and electrically connected to the conductive portion, wherein the redistribution layer is provided with at least one stepped structure toward the resin encapsulation layer, each of the through holes corresponds to one of the stepped structures, the orthographic projection of the through holes onto the plane on which the front surface of the chip is located is entirely within the orthographic projection of the redistribution layer onto the plane, and the orthographic projection of the portion of the stepped structure not in contact with the resin encapsulation layer onto the plane at least partially overlaps with the orthographic projection of the corresponding through hole onto the plane, The present invention provides a semiconductor structure comprising an electrical element located on the side of the resin encapsulation layer away from the front surface of the chip, wherein at least one of the electrical elements is joined to the conductive portion.

[0015] In one embodiment, the redistribution layer includes a first trace layer and a second trace layer located on the side of the first trace layer away from the first chip, the first trace layer includes a plurality of first trace structures, the first trace structures are electrically connected to the pads, and the second trace layer includes second trace structures located on the side of each of the first trace structures away from the first chip, with at least one side of at least one of the second trace structures protruding from the corresponding first trace structure to form a stepped structure.

[0016] In one embodiment, the conductive portion is in contact with both the first trace structure and the second trace structure, or the conductive portion is in contact with only the second trace structure.

[0017] In one embodiment, the orthographic projection onto the plane of the portion of the edge of the through hole that is not in contact with the rewiring layer lies inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin sealing layer, and / or The distance between the surface of the stepped structure that faces the resin sealing layer and is not in contact with the resin sealing layer and the resin sealing layer is in the range of 10 μm to 60 μm.

[0018] In one embodiment, the semiconductor structure further includes a filling portion located between the surface of the stepped structure facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer, and / or The electrical element includes a second chip, and the semiconductor structure further includes a filling structure located between the second chip and the resin encapsulation layer.

[0019] The main technical effects achieved by the embodiments of the present invention are as follows.

[0020] The method for manufacturing a semiconductor structure and the semiconductor structure according to an embodiment of the present invention are such that a redistribution layer electrically connected to pads is provided on the front side of a first chip, an electrical element is provided on the back side of the first chip, and at least one electrical element is joined to a conductive portion, so that the electrical element can be electrically connected to the redistribution layer through the conductive portion located in the through-hole of the resin encapsulation layer, that is, an electrical connection between the front side and the back side of the chip is realized, and it is not necessary to provide a lead frame or a conductive pillar in the manufacturing process of the semiconductor structure, avoiding problems such as short circuits or open circuits between the redistribution layer located on the front side of the chip and the first chip due to deformation or misalignment of the lead frame and the conductive pillar, and being helpful for improving the yield of the product. By forming the conductive portion in a manner that a conductive material with fluidity is filled in the through-hole of the resin encapsulation layer, the conductive material can basically fill the through-hole, ensuring that the electrical connection effect between the conductive portion obtained after the conductive material is solidified, the electrical element, and the redistribution layer is good. Compared with the method of forming the conductive portion in the through-hole in an electroplating process, problems such as the conductive material not being plated on the hole wall of the through-hole in the electroplating process and short circuits between the electrical element and the redistribution layer due to misalignment in the alignment in the electroplating process can be improved, and it is helpful for improving the yield of the product. By providing a step structure on the redistribution layer facing the resin encapsulation layer, the orthographic projection of the plane where the front side of the chip located in the portion not in contact with the resin encapsulation layer of the step structure is located at least partially overlaps with the orthographic projection of the corresponding through-hole on the plane. In the process of joining the conductive portion and the electrical element, the gas in the through-hole can be discharged through the passage between the portion not in contact with the resin encapsulation layer of the step structure and the resin encapsulation layer, so that it can be prevented that the presence of gas in the through-hole causes cavities in the conductive portion and affects the quality of the semiconductor structure.

Brief Description of the Drawings

[0021] [Figure 1] It is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention. [Figure 2] It is a partial cross-sectional view of a wafer according to an exemplary embodiment of the present invention. [Figure 3]This is a cross-sectional view of a first chip according to one exemplary embodiment of the present invention. [Figure 4] This is a partial cross-sectional view of a first intermediate structure according to one exemplary embodiment of the present invention. [Figure 5] This is a partial cross-sectional view of a second intermediate structure according to one exemplary embodiment of the present invention. [Figure 6] This is a partial cross-sectional view of a third intermediate structure according to one exemplary embodiment of the present invention. [Figure 7] This is a partial cross-sectional view of a fourth intermediate structure according to one exemplary embodiment of the present invention. [Figure 8] This is a partial cross-sectional view of a fifth intermediate structure according to one exemplary embodiment of the present invention. [Figure 9] This is a partial cross-sectional view of a sixth intermediate structure according to one exemplary embodiment of the present invention. [Figure 10] This is a partial cross-sectional view of a seventh intermediate structure according to one exemplary embodiment of the present invention. [Figure 11] This is a partial cross-sectional view of an eighth intermediate structure according to one exemplary embodiment of the present invention. [Figure 12] This is a partial cross-sectional view of a ninth intermediate structure according to one exemplary embodiment of the present invention. [Figure 13] This is a partial cross-sectional view of a 10th intermediate structure according to one exemplary embodiment of the present invention. [Figure 14] This is a partial cross-sectional view of the 11th intermediate structure according to one exemplary embodiment of the present invention. [Figure 15] This is a partial cross-sectional view of a 12th intermediate structure according to one exemplary embodiment of the present invention. [Figure 16] This is a partial cross-sectional view of the 13th intermediate structure according to one exemplary embodiment of the present invention. [Figure 17] This is a partial cross-sectional view of a 13th intermediate structure according to another exemplary embodiment of the present invention. [Figure 18] This is a partial cross-sectional view of the 14th intermediate structure according to one exemplary embodiment of the present invention. [Figure 19] This is a cross-sectional view of a semiconductor structure according to one exemplary embodiment of the present invention. [Figure 20] This is a cross-sectional view of a semiconductor structure according to another exemplary embodiment of the present invention. [Figure 21] This is a cross-sectional view of a semiconductor structure according to yet another exemplary embodiment of the present invention. [Modes for carrying out the invention]

[0022] Exemplary embodiments are described in detail here, and examples are shown in the accompanying drawings. Where the following description relates to the drawings, unless otherwise noted, the same numbers in different drawings indicate the same or similar elements. Notwithstanding that the embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of apparatus and methods consistent with some aspects of the present invention detailed in the accompanying claims.

[0023] The terminology used in this invention is for the purpose of describing specific embodiments and is not intended to limit the invention. The singular forms “one kind,” “the said,” and “the” used in this invention and the claims are also intended to include the plural form unless the context clearly indicates otherwise. Furthermore, the term “and / or” used in this invention should be understood to include any or all possible combinations of one or more related enumerated items.

[0024] This invention may use terms such as first, second, third, etc., to describe various types of information, but it should be understood that this information is not limited to these terms. These terms are used solely to distinguish the same type of information. For example, without departing from the scope of this invention, first information may be called second information, and similarly, second information may be called first information. Depending on the context, the word "…case" used herein may be interpreted as "…and," "…when," or "in response to a decision."

[0025] Hereinafter, several embodiments of the present invention will be described in detail with reference to the drawings. To the extent that they do not contradict each other, the embodiments and features described below can be combined with each other.

[0026] An embodiment of the present invention provides a method for manufacturing a semiconductor structure. As shown in Figure 1, the method for manufacturing the semiconductor structure includes the following steps 110 to 140.

[0027] In step 110, a structure to be wired is formed, the structure to be wired includes a first chip and a resin sealing layer, the first chip includes a chip front, a chip back facing the chip front, and a plurality of chip sides connecting the chip front and the chip back, a plurality of pads are provided on the chip front, and at least the chip sides are sealed by the resin sealing layer.

[0028] In step 120, a redistribution layer is formed, the redistribution layer is located on the front of the chip and electrically connected to the pad, and the redistribution layer is provided with at least one stepped structure toward the resin encapsulation layer.

[0029] In step 130, at least one through-hole is formed in the resin encapsulation layer, each through-hole corresponding to one of the stepped structures, the orthogonal projection of the through-hole onto the plane on which the front surface of the chip is located is entirely within the orthogonal projection of the redistribution layer onto the plane, and the orthogonal projection of the through-hole onto the plane at least partially overlaps with the orthogonal projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin encapsulation layer.

[0030] In step 140, the through-hole is filled with a fluid conductive material, a conductive portion is formed after the conductive material solidifies, an electrical element is provided on the back side of the chip, and at least one of the electrical elements is joined to the conductive portion.

[0031] In the manufacturing method of a semiconductor structure according to an embodiment of the present invention, a redistribution layer electrically connected to pads is provided on the front surface of the first chip, an electrical element is provided on the back surface of the first chip, and at least one electrical element is joined to a conductive portion, so that the electrical element can be electrically connected to the redistribution layer via a conductive portion located in a through-hole in the resin encapsulation layer. That is, an electrical connection is achieved between the front surface and the back surface of the chip, eliminating the need to provide a lead frame or conductive pillar in the semiconductor structure manufacturing process, thus avoiding problems such as short circuits or open circuits between the redistribution layer located on the front surface of the chip and the first chip due to deformation or misalignment of the lead frame and conductive pillar, and contributing to an improvement in product yield. By forming the conductive portion by filling the through-holes of the resin encapsulation layer with a fluid conductive material, the conductive material can essentially fill the through-holes, ensuring good electrical connection between the conductive portion obtained after the conductive material has solidified and the electrical element and the redistribution layer. Compared to forming the conductive portion in the through-holes using an electroplating process, this method improves upon the problems of the conductive material not being plated on the holes in the through-holes during the electroplating process, and short circuits between the electrical element and the redistribution layer due to misalignment during the electroplating process, thus contributing to improved product yield. By providing a stepped structure in the redistribution layer toward the resin encapsulation layer, the orthographic projection of the portion of the stepped structure not in contact with the resin encapsulation layer onto the plane where the front surface of the chip is located at least partially overlaps with the orthographic projection of the corresponding through-hole onto the same plane. In the process of joining the conductive portion and the electrical element, gas in the through-hole can be discharged through the passage between the portion of the stepped structure not in contact with the resin encapsulation layer and the resin encapsulation layer. This prevents voids from forming in the conductive portion due to the presence of gas in the through-hole, thus preventing the quality of the semiconductor structure from being affected.

[0032] The following describes in detail each step of the method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0033] In step 110, a structure to be wired is formed, the structure to be wired includes a first chip and a resin sealing layer, the first chip includes a chip front, a chip back facing the chip front, and a plurality of chip sides connecting the chip front and the chip back, a plurality of pads are provided on the chip front, and at least the chip sides are sealed by the resin sealing layer.

[0034] In one embodiment, the first chip may be manufactured by the following process.

[0035] First, a wafer is provided. The wafer has a specific function. Referring to Figure 2, the wafer 14 has an active surface, and an insulating film layer 12 and pads are provided on the active surface of the wafer 14. An opening 121 is provided in the insulating film layer 12, and the pads are exposed through the opening 121. The pads are used to electrically connect to an external element.

[0036] Next, the wafer 14 is cut. The wafer 14 may be cut at the positions indicated by the dashed lines in Figure 2. The wafer 14 may be mechanically cut or laser cut. Optionally, before cutting the wafer 14, the back surface opposite the active surface of the wafer may be polished using a polishing device to bring the thickness of the wafer 14 to a predetermined thickness. This step yields the first chip 10 shown in Figure 3.

[0037] In one embodiment, the step of forming the structure to be wired may include the following process.

[0038] First, the first chip is mounted on the carrier substrate so that the front surface of the first chip faces the carrier substrate.

[0039] This step yields the first intermediate structure shown in Figure 4. As shown in Figure 4, the first chip 10 is attached to the carrier substrate 20 via an adhesive layer 21. The adhesive layer 21 may be made of a material that is easy to peel off later to remove the carrier substrate; for example, a thermally separable material that loses its tackiness when heated may be used as the adhesive layer 21. Although Figure 4 shows only one first chip attached to the carrier substrate, in practice, multiple first chips may be attached to the carrier substrate.

[0040] In one embodiment, the shape of the carrier substrate 20 may be circular, rectangular, or other shapes. The carrier substrate 20 may be a small-sized wafer substrate, or a larger-sized carrier substrate, such as a stainless steel plate substrate or a polymer substrate.

[0041] Next, a resin sealing layer is formed to cover the chip side surface of the first chip.

[0042] This step yields the second intermediate structure shown in Figure 5. As shown in Figure 5, the resin encapsulation layer 30 is formed on the first chip 10 and the exposed carrier substrate 20, covering the chip side surface of the first chip 10 to form a flat structure. After peeling off the carrier substrate 20, rewiring and packaging can be performed on the formed flat structure.

[0043] In one embodiment, before forming the resin encapsulation layer 30, pretreatment steps such as chemical cleaning or plasma cleaning may be performed to remove impurities from the surface of the first chip 10 and the carrier substrate 20, thereby ensuring that the resin encapsulation layer 30 comes into closer contact with the first chip 10 and the carrier substrate 20, and preventing delamination or cracking.

[0044] In one embodiment, the material of the resin encapsulation layer 30 may be a polymer resin, a resin composite material, or a polymer composite material. For example, the resin encapsulation layer 30 may be a resin having fillers such as inorganic particles. The resin encapsulation layer 30 may be formed by methods such as injection molding, comparison molding, or transfer molding.

[0045] Next, the carrier substrate is peeled off.

[0046] This step yields the third intermediate structure shown in Figure 6, i.e., the structure to be wired. Referring to Figure 6, in the third intermediate structure, the front surface of the first chip 10 is not covered by the resin sealing layer 30, and the pads on the front surface of the first chip 10 are exposed.

[0047] In step 120, a redistribution layer is formed, the redistribution layer is located on the front of the chip and electrically connected to the pad, and the redistribution layer is provided with at least one stepped structure toward the resin encapsulation layer.

[0048] In one embodiment, before step 120, the third intermediate structure may be attached to the carrier substrate such that the front surface of the first chip is separated from the carrier substrate.

[0049] In one embodiment, the step of forming a redistribution layer includes forming a first trace layer and a second trace layer located on the side of the first trace layer away from the structure to be routed, thereby obtaining a redistribution layer comprising the first trace layer and the second trace layer, wherein the first trace layer comprises a plurality of first trace structures, the first trace structures are electrically connected to the pads, and the second trace layer comprises second trace structures located on the side of each of the first trace structures away from the structure to be routed, with at least one side of at least one of the second trace structures protruding from the corresponding first trace structure to form a stepped structure.

[0050] This step yields the fourth intermediate structure shown in Figure 7. As shown in Figure 7, the resin encapsulation layer 30 and the first chip 10 are attached to the carrier substrate 22 via an adhesive layer 23, and the redistribution layer 40 includes a first trace layer 41 and a second trace layer 43, the first trace layer 41 includes a plurality of first trace structures 42, the first trace structures 42 are electrically connected to the pads via conductive pillars 50 located in openings 121 in the insulating film layer 12, and the second trace layer 43 includes a plurality of second trace structures 44, the portions of the second trace structures 44 protruding from the corresponding first trace structures 42 form a stepped structure 401 with the first trace structures 42.

[0051] In one embodiment, as shown in Figure 7, the distance d between the surface of the stepped structure 401 facing the resin encapsulation layer 30 and not in contact with the resin encapsulation layer 30 and the resin encapsulation layer 30 is in the range of 10 μm to 60 μm. This configuration avoids the disadvantage of gas discharge from the through-holes in the resin encapsulation layer in later steps due to a distance d that is too small between the surface of the stepped structure 401 facing the resin encapsulation layer 30 and not in contact with the resin encapsulation layer 30, and the difficulty of the redistribution layer manufacturing process due to a distance that is too large. In some embodiments, the distance d between the surface of the stepped structure 401 facing the resin encapsulation layer 30 and not in contact with the resin encapsulation layer 30 and the resin encapsulation layer 30 may be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, etc.

[0052] In one embodiment, the step of forming a first trace layer and a second trace layer located on the side of the first trace layer away from the structure to be routed on the structure to be routed may include the following process.

[0053] First, a seed layer is formed on the front side of the first chip of the structure to be wired. The seed layer may be formed by sputtering.

[0054] Next, a first insulating layer is provided on the side of the seed layer away from the first chip. The first insulating layer may be provided by laminating a dry film to the side of the seed layer away from the first chip.

[0055] Next, the first insulating layer is exposed and developed to form a plurality of first openings.

[0056] Next, electroplating is performed to form a subtrace structure within each first opening.

[0057] Next, a second insulating layer is provided on the side of the subtrace structure that is away from the resin sealing layer. The second insulating layer may be provided by a method of laminating a dry film.

[0058] Next, the second insulating layer is exposed and developed to form a plurality of second openings, where the second openings correspond one-to-one with the first openings, and the size of at least one of the second openings is larger than the size of the first opening.

[0059] Next, electroplating is performed to form a second trace structure in each second opening, thereby obtaining a second trace layer.

[0060] Next, the first and second insulating layers are removed. These layers may be removed by reacting the chemical with the first and second insulating layers. Since a portion of the first insulating layer is located below the second trace layer, the chemical may be reacted with the first and second insulating layers under ultrasonic conditions to remove the entire first insulating layer.

[0061] Next, the portion of the seed layer not covered by the subtrace structure is etched away, and the portion of the remaining seed layer that is in contact with each subtrace structure and the subtrace structure itself constitute the first trace structure, resulting in a first trace layer containing multiple first trace structures.

[0062] In one embodiment, the first trace structure 42 and the conductive pillar 50 may be formed simultaneously in the same process.

[0063] In step 130, at least one through-hole is formed in the resin encapsulation layer, each through-hole corresponding to one of the stepped structures, the orthogonal projection of the through-hole onto the plane on which the front surface of the chip is located is entirely within the orthogonal projection of the redistribution layer onto the plane, and the orthogonal projection of the through-hole onto the plane at least partially overlaps with the orthogonal projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin encapsulation layer.

[0064] In one embodiment, the resin encapsulation layer includes a cut line, and the redistribution layer is in contact with a region of the resin encapsulation layer located outside the cut line. Prior to step 130, the method for manufacturing the semiconductor structure further includes the steps of peeling off a carrier substrate to obtain a semiconductor intermediate structure, and arranging the semiconductor intermediate structure on a support member, the support member including a plate portion and a support portion formed extending from one side of the plate portion, the support portion being in contact with the cut line, and the redistribution layer facing the plate portion and having a gap between it and the plate portion.

[0065] The above steps result in the fifth intermediate structure shown in Figure 8. As shown in Figure 8, the support portion 242 of the support member 24 is in contact with the cut line 32 of the resin sealing layer 30, and there is a gap between the plate portion 241 of the support member 24 and the rewiring layer 40. The support member 24 may include a plurality of support portions 242, and two adjacent support portions 242 are provided facing each other. The cut line 32 of the resin sealing layer 30 is the position where the resin sealing layer will be cut later.

[0066] By providing the support member 24, the intermediate structure can be supported, which is convenient for subsequent processes. Since the support portion 242 is in contact with the cut line 32 of the resin encapsulation layer 30, it is possible to avoid the support portion 242 contacting other areas, causing those areas to be subjected to force and deform, thereby affecting the quality of the semiconductor structure. Furthermore, since a stepped structure is provided in the redistribution layer 40, the strength of the redistribution layer 40 is low. By installing it so that there is a gap between the plate portion 241 and the redistribution layer 40, it is possible to avoid the redistribution layer 40 contacting the support member 24 and being subjected to force and deformed.

[0067] Step 130 yields the sixth intermediate structure shown in Figure 9. As shown in Figure 9, the resin encapsulation layer 30 has a plurality of through holes 31 that penetrate the resin encapsulation layer 30, and the orthographic projection of each through hole 31 onto the plane where the front surface of the chip is located is all within the orthographic projection of the redistribution layer 40 onto the same plane, the through holes 31 correspond one-to-one with the stepped structure 401, and the orthographic projection of each through hole 31 onto the same plane partially overlaps with the orthographic projection of the portion of the corresponding stepped structure 401 that is not in contact with the resin encapsulation layer 30 onto the same plane. In other embodiments, the orthographic projection of each through hole 31 onto the same plane may all be within the orthographic projection of the portion of the corresponding stepped structure 401 that is not in contact with the resin encapsulation layer 30 onto the same plane.

[0068] In step 140, since the conductive part is formed by filling the through-hole 31 with a fluid conductive material, some gas remains in the through-hole 31 when filling the through-hole with the conductive material. By positioning the structure so that the orthographic projection of the portion of the stepped structure 401 that is not in contact with the resin sealing layer 30 onto the plane and the corresponding orthographic projection of the through-hole 31 onto the plane overlap at least partially, the gas in the through-hole 31 can be discharged through the passage between the portion of the stepped structure 401 that is not in contact with the resin sealing layer 30 and the resin sealing layer 30 during the subsequent process of joining the conductive part in the through-hole 31 to the electrical element.

[0069] In one embodiment, the orthographic projection onto the plane of the portion of the edge of the through-hole 31 that is not in contact with the redistribution layer 40 lies inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure 401 that is not in contact with the resin encapsulation layer 30. When installed in this manner, in a direction parallel to the plane on which the front of the chip is located, the stepped structure 401 extends beyond the portion of the edge of the corresponding through-hole 31 that is not in contact with the redistribution layer 40. When the through-hole 31 is later filled with a fluid conductive material, the fluid conductive material flows out from the portion of the through-hole 31 not sealed by the stepped structure 401 and flows onto the surface of the portion of the stepped structure 401 that is not in contact with the resin encapsulation layer 30. This prevents the conductive material from flowing onto the surface of the resin encapsulation layer 30, which would electrically connect two adjacent first trace structures 42 and affect the performance of the semiconductor structure.

[0070] In one embodiment, the distance between the orthographic projection onto the plane of the portion of the edge of the through-hole 31 that is not in contact with the rewiring layer 40 and the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure 401 that is not in contact with the resin sealing layer 30 is greater than 50 μm. When installed in this manner, it is possible to effectively prevent the conductive material from flowing onto the surface of the resin sealing layer 30.

[0071] In one embodiment, as shown in Figure 9, a portion of the edge of the through-hole 31 is in contact with the corresponding first trace structure 42, and the edge of the second trace structure 44 protrudes more than the portion of the edge of the corresponding through-hole 31 that is not in contact with the first trace structure 42. In other embodiments, the entire edge of the through-hole 31 does not need to be in contact with the first trace structure 42.

[0072] In one embodiment, a vacuum passage may be provided in the support portion 242 of the support member 24, and gas may be extracted between the support portion 242 and the cut line 32 of the resin sealing layer 30 via the vacuum passage, thereby vacuum adsorption between the support portion 242 and the cut line 32. This facilitates the subsequent separation of the support member 24 and the resin sealing layer 30. In another embodiment, the support portion 242 and the cut line 32 of the resin sealing layer 30 may be bonded via an adhesive layer, and the adhesive layer may be made of a material that is easily peeled off in order to later peel off the carrier substrate, for example, a thermally separable material that loses its tackiness when heated may be used as the adhesive layer.

[0073] In step 140, the through-hole is filled with a fluid conductive material, a conductive portion is formed after the conductive material solidifies, an electrical element is provided on the back side of the chip, and at least one of the electrical elements is joined to the conductive portion.

[0074] In one embodiment, the conductive material comprises at least one of solder and silver paste. The solder may be, for example, solder paste. The solder paste and silver paste have good fluidity at room temperature, making it easier to fill through-holes in the resin encapsulation layer and ensuring a better effect of electrical connection between the conductive parts formed in the through-holes of the resin encapsulation layer and the rewiring layer. The solder paste is a paste-like mixture formed by mixing solder powder, flux and other surfactants, thixotropes, etc., while the silver paste is prepared from silver or a compound thereof, flux, binder and diluent. In a later step, during the process of joining the conductive parts and the electrical elements, the flux in the solder volatilizes and is discharged through the passage between the portion of the stepped structure 401 that is not in contact with the resin encapsulation layer 30 and the resin encapsulation layer 30.

[0075] In one embodiment, if the conductive material is solder paste, silver paste, or a mixture of both, the conductive material may be heated to melt it and then cooled to solidify it.

[0076] In one embodiment, the step of filling the through-hole with the fluid conductive material includes a process of filling the through-hole with the fluid conductive material in a screen printing process.

[0077] In the screen printing process, the screen is first positioned on the side of the sixth intermediate structure away from the carrier substrate, and then the conductive material is printed into the through-holes 31 through the mesh of the screen, forming a conductive portion after the conductive material solidifies. Because the screen has a certain thickness, during the process of printing the conductive material, some of the conductive material is filled into the mesh of the screen, and the surface of the finally formed conductive portion away from the redistribution layer 40 protrudes more than the surface of the resin encapsulation layer 30 away from the redistribution layer 40, i.e., the conductive portion protrudes beyond the through-holes 31. This facilitates bonding between the conductive portion and the electrical element in a later step. In the screen printing process, the printing pressure and printing speed may be controlled so that the conductive material almost completely fills the through-holes 31. In some embodiments, the printing pressure range may be 4 kg to 10 kg, and the printing speed range may be 20 mm / s to 100 mm / s.

[0078] In another embodiment, the step of filling the through-hole with the fluid conductive material includes a process of filling the through-hole with the fluid conductive material in a dispensing process.

[0079] In this embodiment, a fluid conductive material is injected into the through-hole 31 in a dispensing process, and the finally formed conductive portion may or may not protrude from the resin sealing layer 30.

[0080] In one embodiment, the electrical element includes at least one of a second chip and a passive element, the passive element including at least one of an inductor, a resistor, and a capacitor. The functions of the second chip and the first chip may be the same or different.

[0081] In one embodiment, the manufacturing method further includes the step of forming a heat dissipation layer, which is formed simultaneously with the conductive portion. This helps to simplify the manufacturing method of the semiconductor structure. Step 140 yields the seventh intermediate structure shown in Figure 10. As shown in Figure 10, a conductive portion 70 is formed in each through-hole 31, and the heat dissipation layer 80 covers the back surface of the first chip 10. The surface of the conductive portion 70 away from the redistribution layer 40 protrudes more than the surface of the resin encapsulation layer 30 away from the redistribution layer 40. The conductive portion 70 is in contact with both the corresponding first trace structure 42 and the second trace structure 44. In other embodiments, the conductive portion 70 may be in contact only with the corresponding second trace structure 44. In other embodiments, the heat dissipation layer may be formed after the conductive portion is formed. By providing a heat dissipation layer covering the back surface of the chip, the heat dissipation layer can dissipate heat from the back surface of the first chip, which helps to lower the temperature of the first chip and improve the performance of the first chip.

[0082] In one embodiment, as shown in Figure 10, the heat dissipation layer 80 is in contact with the conductive part 70. The heat dissipation layer 80 is electrically connected to the redistribution layer 40 via the conductive part 70. As a result, the heat generated in the redistribution layer 40 is conducted to the heat dissipation layer 80 via the conductive part 70, and the heat can be dissipated through the heat dissipation layer 80, further lowering the temperature of the semiconductor structure and helping to improve the performance of the semiconductor structure.

[0083] In one embodiment, if the electrical element further includes a passive element and a second chip, after the seventh intermediate structure is obtained, step 140 further includes providing at least one passive element and a second chip on the side of the seventh intermediate structure away from the support member.

[0084] This step yields the eighth intermediate structure shown in Figure 11. As shown in Figure 11, the second chip 81 is in contact with a plurality of conductive parts 70, and the passive element 82 is in contact with a plurality of conductive parts 70.

[0085] In one embodiment, after the eighth intermediate structure is obtained, step 140 further includes the step of joining the second chip 81 and the passive element 82 to the conductive portion 70, respectively. This step yields the ninth intermediate structure shown in Figure 12. The second chip 81 and the passive element 82 may be joined to the conductive portion 70 by a reflow process.

[0086] In one embodiment, after step 140, the method for manufacturing the semiconductor structure further includes the step of filling a filler between the second chip and the resin encapsulation layer to form a filled structure.

[0087] This step yields the tenth intermediate structure shown in Figure 13. As shown in Figure 13, the surface of the filling structure 91 away from the redistribution layer 40 abuts against the second chip 81, and the surface of the filling structure 91 facing the redistribution layer 40 abuts against the resin encapsulation layer 30. In this way, by first filling the space between the second chip 81 and the resin encapsulation layer 30 with a filler to form the filling structure 91, and then forming an encapsulation layer (described later) to encapsulate the electrical element, the probability of a cavity existing at the bottom after the electrical element is encapsulated can be reduced. That is, it is possible to achieve either a small cavity at the bottom or no cavity at all after the electrical element is encapsulated, resulting in a good filling effect at the bottom of the electrical element and further reducing the risk of short circuits between adjacent solder bumps of the electrical element.

[0088] The filler and sealing layer materials forming the filling structure 91 may both contain filler particles. The size of the filler particles in the filling structure 91 is smaller than the size of the filler particles in the sealing layer. This further reduces the probability of a cavity existing at the bottom of the electrical element, improves the filling effect at the bottom of the electrical element, and is advantageous in reducing the risk of short circuits between adjacent solder bumps of the electrical element.

[0089] In one embodiment, after step 140, the method for manufacturing the semiconductor structure further includes the step of forming a sealing layer that covers the electrical element.

[0090] After this step, removing the support member 24 yields the 11th intermediate structure shown in Figure 14. As shown in Figure 14, the sealing layer 92 covers the second chip 81, the heat dissipation layer 80, and the passive element 82. The sealing layer 92 can protect the second chip 81, the heat dissipation layer 80, and the passive element 82.

[0091] In one embodiment, as shown in Figure 14, the surface of the heat dissipation layer 80 that is separated from the rewiring layer 40 is exposed from the sealing layer 92. This ensures that the heat dissipation effect of the heat dissipation layer 80 is better.

[0092] In one embodiment, the thickness of the initially formed sealing layer 92 is greater than the thickness of the heat dissipation layer 80. By thinning the side of the sealing layer 92 away from the first chip 10, the thickness of the sealing layer 92 can be made approximately the same as the thickness of the heat dissipation layer 80, so that the surface of the heat dissipation layer 80 away from the redistribution layer 40 is exposed from the sealing layer 92. The surface of the sealing layer 92 away from the redistribution layer 40 may be thinned by polishing.

[0093] In one embodiment, before forming the sealing layer 92, pretreatment steps such as chemical cleaning and plasma cleaning may be performed to remove impurities from the surface of the electrical element that is separated from the first tip 10 and impurities from the surface of the resin sealing layer 30 that is separated from the first tip 10, thereby allowing the sealing layer 92 to come into closer contact with the electrical element and the resin sealing layer 30, and preventing delamination and cracking.

[0094] In one embodiment, the material of the sealing layer 92 may be a polymer resin, a resin composite material, or a polymer composite material. For example, the sealing layer 92 may be a resin having fillers such as inorganic particles. The sealing layer 92 may be formed by methods such as injection molding, comparison molding, or transfer molding.

[0095] In one embodiment, after the step of filling the through-hole with the fluid conductive material and forming a conductive portion after the conductive material has solidified, the method for manufacturing the semiconductor structure further includes the step of filling a filler between the surface of the stepped structure facing the resin encapsulation layer and not in contact with the resin encapsulation layer and the resin encapsulation layer to form a filled portion. This step may be performed after the step of forming the encapsulation layer. After or before the step of forming the encapsulation layer, the method for manufacturing the semiconductor structure further includes the step of peeling off the support member and attaching the obtained structure to the carrier substrate such that the redistribution layer is located on the side away from the carrier substrate of the first chip.

[0096] This step yields the 12th intermediate structure shown in Figure 15. As shown in Figure 15, the encapsulation layer 92 is attached to the carrier substrate 26 via the adhesive layer 25. The surface of the filling portion 93 away from the redistribution layer 40 is in contact with the portion of the stepped structure 401 that is not in contact with the resin encapsulation layer 30, specifically the surface of the second trace structure 44 facing the resin encapsulation layer 30, while the surface of the filling portion 93 facing the resin encapsulation layer 30 is in contact with the resin encapsulation layer 30. In this way, by first filling the space between the electrical element and the resin encapsulation layer with a filler to form the filling portion 93, and then forming a dielectric layer (described later) to cover the redistribution layer, the probability of a cavity existing at the bottom of the redistribution layer can be reduced. That is, after the dielectric layer covers the redistribution layer, there may be a small cavity or no cavity at the bottom of the redistribution layer, resulting in a good filling effect at the bottom of the redistribution layer and improving the quality of the semiconductor structure.

[0097] The filler material forming the filled portion 93 and the dielectric layer material may both contain filler particles. The size of the filler particles in the filled portion 93 is smaller than the size of the filler particles in the dielectric layer, which is advantageous in reducing the probability of a cavity existing at the bottom of the redistribution layer and improving the filling effect at the bottom of the redistribution layer.

[0098] After the step of filling a filler between the surface of the stepped structure facing the resin encapsulation layer and not in contact with the resin encapsulation layer and the resin encapsulation layer to form a filled portion, the method for manufacturing the semiconductor structure may further include the step of forming a dielectric layer, wherein the dielectric layer covers the second trace structure and the second trace structure is not exposed from the dielectric layer.

[0099] This step yields the 13th intermediate structure shown in Figure 16. As shown in Figure 16, the dielectric layer 94 covers each second trace structure 44, the exposed resin encapsulation layer 30, and the exposed insulating film layer 12.

[0100] In another embodiment, after the step of filling the through-hole with the fluid conductive material and forming a conductive portion after the conductive material has solidified, the method for manufacturing the semiconductor structure further includes the step of forming a resin encapsulation film layer, the resin encapsulation film layer covering the redistribution layer and filling the gap between the surface of the stepped structure facing the resin encapsulation layer and not in contact with the resin encapsulation layer and the resin encapsulation layer. This step may be performed after the step of forming the encapsulation layer. After or before the step of forming the encapsulation layer, the method for manufacturing the semiconductor structure further includes the step of peeling off the support member and attaching the resulting structure to a carrier substrate such that the redistribution layer is located on the side away from the carrier substrate of the first chip.

[0101] This step yields the 13th intermediate structure shown in Figure 17. As shown in Figure 17, the sealing layer 92 is attached to the carrier substrate 26 via the adhesive layer 25, and the resin sealing film layer 99 covers the redistribution layer 40 and fills the gap between the surface of the stepped structure 401 facing the resin sealing layer 30 and not in contact with the resin sealing layer 30 and the resin sealing layer 30. This allows for the formation of a resin sealing film layer 99 that covers the redistribution layer 40 and fills the gap between the second trace structure and the resin sealing layer 30 in a single resin sealing process, which helps to simplify the manufacturing process. The material of the resin sealing film layer 99 may have filler particles, which is advantageous in reducing the probability of voids existing at the bottom of the redistribution layer and improving the filling effect at the bottom of the redistribution layer.

[0102] In one embodiment, after a 13th intermediate structure is obtained, the method for manufacturing the semiconductor structure further includes the step of forming a redistribution structure on the side of the redistribution layer away from the first chip, wherein the redistribution structure includes a third trace structure electrically connected to the redistribution layer and conductive convex pillars located on the side of the third trace structure away from the redistribution layer.

[0103] If the 13th intermediate structure is as shown in Figure 16, the above steps yield the 14th intermediate structure shown in Figure 18. As shown in Figure 18, the redistribution structure 95 is located on the side of the dielectric layer 94 away from the first chip 10 and includes a plurality of third trace structures 951 and a plurality of conductive protrusions 952, where one third trace structure 951 may be electrically connected to one or more second trace structures 44, and one third trace structure 951 may be provided with one or more conductive protrusions 952. The dielectric layer 94 may be provided with openings 941 that correspond one-to-one with the second trace structures 44, with each opening 941 exposing a portion of the corresponding second trace structure 44. The third trace structures 951 are electrically connected to the second trace structures 44 via conductive structures 96 located within the openings 941.

[0104] In the above embodiment, the third trace structure includes conductive convex pillars, which is advantageous for electrical connection between the external structure and the semiconductor structure. In other embodiments, a rewiring structure may not be formed, and only conductive convex pillars may be formed within the openings of the dielectric layer.

[0105] In one embodiment, after the 14th intermediate structure is obtained, the method for manufacturing the semiconductor structure further includes the step of forming a dielectric film layer, the dielectric film layer covering the redistribution structure, and the surface of the conductive convex column away from the first tip being exposed from the dielectric film layer.

[0106] After removing the carrier substrate following this step, the semiconductor structure shown in Figure 19 is obtained. As shown in Figure 19, the dielectric film layer 97 covers the redistribution structure 95 and the exposed dielectric layer 94.

[0107] In one embodiment, the method for manufacturing the semiconductor structure further includes the step of forming a plurality of conductive balls on the side of the redistribution structure away from the first chip in a ball planting process. After the carrier substrate 26 is removed, the surface of the conductive convex column of the redistribution structure away from the first chip is exposed, so ball planting can be performed on the surface of the conductive convex column away from the first chip.

[0108] This step yields the semiconductor structure shown in Figure 20. As shown in Figure 20, one conductive ball 98 is formed on the surface of each conductive convex column 952 of the redistribution structure 95 that is away from the first chip 10. The redistribution structure 95 of the semiconductor structure can be bonded to a circuit board via the conductive balls 98, facilitating the connection between the semiconductor structure and the circuit board. The material of the conductive balls 98 may be solder paste, metallic tin, or a tin alloy.

[0109] In one embodiment, if the 13th intermediate structure is as shown in Figure 17, a semiconductor structure as shown in Figure 21 is obtained after forming a plurality of conductive balls on the side of the rewiring structure away from the first chip in a ball plant process.

[0110] In one embodiment, if in step 110 there are multiple first chips included in the structure to be wired, the method for manufacturing the semiconductor structure further includes, after step 140, the step of cutting the structure obtained along the cut line to obtain multiple semiconductor structures. The semiconductor structures obtained after cutting may each include at least one first chip, as shown in Figure 19, Figure 20, or Figure 21.

[0111] Embodiments of the present invention further provide a semiconductor structure. As shown in Figures 19 to 21, the semiconductor structure includes a first chip 10, a resin encapsulation layer 30, a conductive portion 70, a redistribution layer 40, and an electrical element.

[0112] The first chip 10 includes a chip front, a chip back facing the chip front, and a plurality of chip sides connecting the chip front and the chip back, with a plurality of pads provided on the chip front. The resin encapsulation layer 30 covers the chip sides, and the resin encapsulation layer 30 has at least one through hole 31. The conductive portion 70 is at least partially located within the through hole 31. The material of the conductive portion 70 includes at least one of solder and silver paste. The redistribution layer 40 is located on the side of the resin encapsulation layer 30 closer to the chip front, and the redistribution layer 40 is electrically connected to the pads and electrically connected to the conductive portion 70. The redistribution layer 40 is provided with at least one stepped structure 401 facing the resin encapsulation layer 30, each of the through holes 31 corresponds to one of the stepped structures 401, the orthographic projection of the through holes 31 onto the plane where the front surface of the chip is located is entirely within the orthographic projection of the redistribution layer 40 onto the plane, and the orthographic projection of the portion of the stepped structure 401 that is not in contact with the resin encapsulation layer 30 onto the plane at least partially overlaps with the orthographic projection of the corresponding through hole 31 onto the plane. The electrical elements are located on the side of the resin encapsulation layer 30 away from the front surface of the chip, and at least one of the electrical elements is joined to the conductive portion 70.

[0113] In the semiconductor structure according to the embodiment of the present invention, the conductive material of the conductive part includes at least one of solder and silver paste. The conductive part is obtained by filling the through-hole with a fluid conductive material and solidifying it. The conductive material can fill the through-hole, and after the conductive material has solidified, it is guaranteed that the electrical connection effect between the conductive part obtained and the electrical element and the redistribution layer is good. Compared to the method of forming the conductive part in the through-hole by the electroplating process, it is possible to improve the problem of the conductive material not being plated on the hole wall of the through-hole in the electroplating process, and the problem of short circuits between the electrical element and the redistribution layer due to misalignment in the electroplating process. There is no need to provide a lead frame or conductive pillar in the semiconductor structure, and problems such as short circuits and open circuits between the redistribution layer located on the front of the chip and the chip due to deformation or misalignment of the lead frame and conductive pillar are avoided, which helps to improve the yield of the product. By providing a stepped structure in the redistribution layer toward the resin encapsulation layer, the orthographic projection of the portion of the stepped structure not in contact with the resin encapsulation layer onto the plane where the front surface of the chip is located will at least partially overlap with the orthographic projection of the corresponding through-hole onto the same plane. In the process of joining the conductive portion and the electrical element, the gas in the through-hole and the flux in the solder can be discharged through the passage between the portion of the stepped structure not in contact with the resin encapsulation layer and the resin encapsulation layer. This prevents the presence of gas and flux in the through-hole from creating cavities in the conductive portion and affecting the quality of the semiconductor structure.

[0114] In one embodiment, as shown in Figures 19 to 21, the redistribution layer 40 includes a first trace layer 41 and a second trace layer 43 located on the side of the first trace layer 41 away from the first chip 10, wherein the first trace layer 41 includes a plurality of first trace structures 42, the first trace structures 42 being electrically connected to the pads, and the second trace layer 43 includes a second trace structure 44 located on the side of each of the first trace structures 42 away from the first chip, with at least one side of at least one of the second trace structures 44 protruding from the corresponding first trace structure 42 to form a stepped structure 401.

[0115] In one embodiment, as shown in Figures 19 to 21, the orthographic projection onto the plane of the portion of the edge of the through hole 31 that is not in contact with the rewiring layer 40 lies inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure 401 that is not in contact with the resin sealing layer 30.

[0116] In one embodiment, as shown in Figures 19 to 21, the conductive portion 70 is in contact with both the first trace structure 42 and the second trace structure 44, or the conductive portion 70 is in contact only with the second trace structure 44.

[0117] In one embodiment, as shown in Figures 19 to 21, the distance d between the surface of the stepped structure 401 facing the resin sealing layer 30 and not in contact with the resin sealing layer 30 and the resin sealing layer 30 is in the range of 10 μm to 60 μm.

[0118] In one embodiment, as shown in Figures 19 to 21, the semiconductor structure further includes a heat dissipation layer 80 formed simultaneously with the conductive portion 70.

[0119] In one embodiment, the electrical element includes at least one of a second chip, an inductor, a resistor, and a capacitor.

[0120] In one embodiment, as shown in Figures 19 and 20, the semiconductor structure further includes a filling portion 93 located between the surface of the stepped structure 401 facing the resin sealing layer 30 and not in contact with the resin sealing layer 30 and the resin sealing layer 30.

[0121] In one embodiment, as shown in Figures 19 to 21, when the electrical element includes a second chip, the semiconductor structure further includes a filling structure 91 located between the second chip and the resin encapsulation layer.

[0122] In one embodiment, as shown in Figures 20 and 21, the semiconductor structure further includes a plurality of conductive balls 98 located on the side of the redistribution layer 40 away from the first chip 10.

[0123] The embodiments of the method for manufacturing a semiconductor structure according to the embodiments of the present invention belong to the same inventive concept as the embodiments of the semiconductor structure, and the relevant details and descriptions of beneficial effects can be referred to from each other, so the explanation is omitted here.

[0124] Note that in the drawings, the sizes of layers and regions may be exaggerated for clarity. Also, when an element or layer is described as being "on top" of another element or layer, it may be directly above the other element, or there may be an intermediate layer. Also, when an element or layer is described as being "below" another element or layer, it may be directly below the other element, or there may be one or more intermediate layers or elements. Also, when a layer or element is described as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may be one or more intermediate layers or elements. Throughout the text, similar reference symbols indicate similar elements.

[0125] Those skilled in the art will readily conceive of other embodiments of the invention after considering the specification and implementing what is disclosed herein. The invention is intended to cover any variations, uses, or adaptive changes of the invention, which will conform to the general principles of the invention and include common or conventional technical means in the art not disclosed herein. The specification and examples are illustrative only, and the actual scope and spirit of the invention are shown by the following claims.

[0126] It should be noted that the present invention is not limited to the exact structure shown in the above description and drawings, and various modifications and changes are possible without departing from its scope. The scope of the present invention is limited only by the appended claims.

Claims

1. A step of forming a structure to be wired, wherein the structure to be wired includes a first chip and a resin sealing layer, the first chip includes a chip front, a chip back facing the chip front, and a plurality of chip sides connecting the chip front and the chip back, a plurality of pads are provided on the chip front, and at least the chip sides are sealed by the resin sealing layer, A step of forming a redistribution layer, wherein the redistribution layer is located on the front of the chip and electrically connected to the pad, and the redistribution layer is provided with at least one stepped structure toward the resin sealing layer, A step of forming at least one through-hole in the resin sealing layer, wherein each of the through-holes corresponds to one of the stepped structures, the orthographic projection of the through-hole onto the plane on which the front surface of the chip is located is entirely within the orthographic projection of the redistribution layer onto the plane, and the orthographic projection of the through-hole onto the plane at least partially overlaps with the orthographic projection of the portion of the corresponding stepped structure that is not in contact with the resin sealing layer onto the plane. The process includes the steps of filling the through-hole with a fluid conductive material, forming a conductive portion after the conductive material has solidified, providing an electrical element on the back side of the chip, and joining at least one of the electrical elements to the conductive portion. A method for manufacturing a semiconductor structure characterized by the following:

2. The step of forming the redistribution layer is, The step of forming a first trace layer and a second trace layer located on the structure to be wired, on the side of the first trace layer away from the structure to be wired, thereby obtaining a rewiring layer including the first trace layer and the second trace layer, The first trace layer comprises a plurality of first trace structures, each of which is electrically connected to the pad; the second trace layer comprises a second trace structure located on the side of each first trace structure away from the structure to be routed, wherein at least one side of at least one of the second trace structures protrudes from the corresponding first trace structure to form the stepped structure. A method for manufacturing a semiconductor structure according to claim 1.

3. The orthographic projection onto the plane of the portion of the edge of the through hole that is not in contact with the rewiring layer is located inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin sealing layer. A method for manufacturing a semiconductor structure according to claim 1.

4. The distance between the surface of the stepped structure facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer is in the range of 10 μm to 60 μm. A method for manufacturing a semiconductor structure according to claim 1.

5. After forming the redistribution layer, a semiconductor intermediate structure is obtained, the resin encapsulation layer includes a cut line, the redistribution layer is in contact with a region of the resin encapsulation layer located outside the cut line, and before forming a plurality of through holes penetrating the resin encapsulation layer, The step further includes arranging the semiconductor intermediate structure on a support member, The support member includes a plate portion and a support portion formed extending from one side of the plate portion, the support portion being in contact with the cut line, and the rewiring layer facing the plate portion with a gap between it and the plate portion. An electrical element is provided on the back side of the chip, and at least one of the electrical elements is joined to the conductive part, The step further includes cutting the obtained structure along the aforementioned cut line. A method for manufacturing a semiconductor structure according to claim 1.

6. The through-hole is filled with a fluid conductive material, and after the conductive material has solidified, the conductive part is formed. The step further includes filling a filler between the surface of the stepped structure that faces the resin sealing layer and is not in contact with the resin sealing layer and the resin sealing layer to form a filled portion. A method for manufacturing a semiconductor structure according to claim 1.

7. The through-hole is filled with a fluid conductive material, and after the conductive material has solidified, the conductive part is formed. The process further includes the step of forming a resin-sealed film layer, The resin sealing film layer covers the rewiring layer and fills the gap between the surface of the stepped structure facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer. A method for manufacturing a semiconductor structure according to claim 1.

8. The electrical element includes a second chip, and the electrical element is provided on the back side of the chip, and at least one of the electrical elements is joined to the conductive portion. The process further includes the step of filling a filler between the second chip and the resin sealing layer to form a filled structure. A method for manufacturing a semiconductor structure according to claim 1.

9. The surface of the conductive portion that is away from the rewiring layer protrudes more than the surface of the resin encapsulating layer that is away from the rewiring layer. A method for manufacturing a semiconductor structure according to claim 1.

10. The process further includes the step of forming a heat dissipation layer, wherein the heat dissipation layer is formed simultaneously with the conductive portion. A method for manufacturing a semiconductor structure according to claim 1.

11. The aforementioned electrical element includes at least one of the second chip, inductor, resistor, and capacitor, and / or The conductive material includes at least one of solder and silver paste. A method for manufacturing a semiconductor structure according to claim 1.

12. A first chip comprising a front surface, a back surface facing the front surface, and a plurality of side surfaces connecting the front surface and the back surface, wherein a plurality of pads are provided on the front surface of the first chip, A resin sealing layer covering the side surface of the chip, wherein the resin sealing layer is provided with at least one through hole, A conductive part located at least partially within the through hole, wherein the material of the conductive part includes at least one of solder and silver paste, A redistribution layer located on the side of the resin encapsulation layer closest to the front surface of the chip, electrically connected to the pad and electrically connected to the conductive portion, wherein the redistribution layer is provided with at least one stepped structure toward the resin encapsulation layer, each of the through holes corresponds to one of the stepped structures, the orthographic projection of all of the through holes onto the plane on which the front surface of the chip is located lies within the orthographic projection of the redistribution layer onto the plane, and the orthographic projection of the portion of the stepped structure not in contact with the resin encapsulation layer onto the plane at least partially overlaps with the orthographic projection of the corresponding through hole onto the plane, An electrical element located on the side of the resin encapsulation layer away from the front of the chip, wherein at least one of the electrical elements is joined to the conductive portion, including an electrical element A semiconductor structure characterized by the following features.

13. The redistribution layer includes a first trace layer and a second trace layer located on the side of the first trace layer away from the first chip, the first trace layer includes a plurality of first trace structures, the first trace structures are electrically connected to the pads, and the second trace layer includes a second trace structure located on the side of each first trace structure away from the first chip, with at least one side of at least one of the second trace structures protruding from the corresponding first trace structure to form a stepped structure. The semiconductor structure according to feature 12.

14. The conductive portion either contacts both the first trace structure and the second trace structure, or the conductive portion contacts only the second trace structure. The semiconductor structure according to feature 13.

15. The orthographic projection onto the plane of the portion of the edge of the through hole that is not in contact with the rewiring layer is located inside the edge of the orthographic projection onto the plane of the portion of the corresponding stepped structure that is not in contact with the resin sealing layer. The semiconductor structure according to feature 12.

16. The distance between the surface of the stepped structure facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer is in the range of 10 μm to 60 μm. The semiconductor structure according to feature 12.

17. The step structure further includes a filling portion located between the surface facing the resin sealing layer and not in contact with the resin sealing layer and the resin sealing layer, The semiconductor structure according to feature 12.

18. The aforementioned electrical element includes a second chip, The semiconductor structure further includes a filling structure located between the second chip and the resin encapsulation layer. The semiconductor structure according to feature 12.

19. The present invention further comprises a resin-sealing film layer, the resin-sealing film layer covering the redistribution layer and filling the gap between the surface of the stepped structure facing the resin-sealing layer and not in contact with the resin-sealing layer and the resin-sealing layer. The semiconductor structure according to feature 12.

20. The surface of the conductive portion that is away from the rewiring layer protrudes more than the surface of the resin encapsulating layer that is away from the rewiring layer. The semiconductor structure according to feature 12.

Images