To indicate the presence of a portion of data corresponding to a predetermined pattern in the physical layer's received data path.

Abstract

One or more embodiments relate to a method comprising: applying oversampling to data on a physical layer's receiving data path; generating a first signal indicating a relationship between a pattern revealed by a portion of the oversampled data and a predetermined pattern; generating a second signal, which is an observed feature of the first signal indicating the highest relationship between the pattern revealed by each portion of the oversampled data and the predetermined pattern; and providing the second signal to indicate the presence of a portion of data corresponding to a predetermined pattern in a coupling portion of the physical layer's receiving data path.

Description

Technical Field

[0001] (Claim of Priority) This application claims the benefit of the filing date of Chinese Patent Application No. 202310566068.5, filed on May 18, 2023, which is "indicating the existence of a portion of data corresponding to a predetermined pattern in the reception data path of the physical layer".

Background Art

[0002] Interconnections are widely used to facilitate communication between network devices, subsystems, and systems. Generally speaking, electrical signals are transmitted over a physical medium (e.g., without limitation, a bus, coaxial cable, or twisted pair - generally simply referred to as a "line" or "bus") by devices coupled to that physical medium.

[0003] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transmit data packets and ultimately messages communicated between network devices. According to the OSI model, special circuits called physical layer (PHY) devices are used to interface between the analog domain of the circuit and the digital domain of the data link layer (also referred to herein simply as the “link layer”), which operates according to packet signaling. While the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides control abstractions for the physical layer. As a non-limiting example, when transmitting data to another device on the network, the MAC controller may prepare messages for the physical media, add error correction elements, and implement collision avoidance. Furthermore, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare messages for higher layers.

[0004] Various network topologies exist that implement the physical layer and the link layer (and may include other layers without limitation). The Peripheral Component Interconnect (PCI) standard and Parallel Advanced Technology Attachment (Parallel ATA), which have been used together since the early 1990s, can implement multidrop bus topologies. The trend since the early 2000s has been to use point-to-point bus topologies; for example, the PCI Express standard (PCIe) and Serial ATA (SATA) standards implement point-to-point topologies.

[0005] A typical point-to-point bus topology can implement lines between devices (e.g., dedicated point-to-point, without limitation) or lines between devices and switches (e.g., switched point-to-point, without limitation). In a multidrop bus topology, the physical transmission medium is a shared bus, and each network device is coupled to the shared bus via a circuit selected based on the type of physical medium (e.g., coaxial or twisted pair, without limitation).

[0006] Point-to-point bus topologies, such as dedicated point-to-point topologies or switched point-to-point topologies, require more wires and more expensive materials than multidrop topologies, partly due to the increased number of links between devices. In certain applications, such as automobiles, physical constraints may exist that make it difficult to connect devices directly. Therefore, topologies that do not require direct connections, or require fewer direct connections, within a network or subnetwork (e.g., multidrop topologies, to the extent that they do not) may be less affected by, or even hindered by, such constraints.

[0007] Devices in a baseband network (and, but not limited to, a multidrop network) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, at a given moment, only one device in the baseband network can transmit. Therefore, media access control methods are sometimes used to handle competition for such shared transmission medium. [Brief explanation of the drawing]

[0008] To facilitate identification of any particular element or function, the most significant digit of the reference number refers to the figure number in which that element is first introduced. [Figure 1] This is a block diagram showing a device, according to one or more embodiments, that demonstrates the presence of a portion of data corresponding to a predetermined pattern in the coupling portion of the physical layer's received data path. [Figure 2] This is a block diagram showing a portion of the apparatus in Figure 1, according to one or more embodiments. [Figure 3] This graph shows lines representing exemplary correlation signals with noise and lines representing exemplary correlation signals without noise, based on one or more embodiments. [Figure 4] This flowchart illustrates a process, using one or more embodiments, for generating signals that suggest a portion of data corresponding to a predetermined pattern that reveals a predetermined pattern. [Figure 5] This flowchart illustrates a process, using one or more embodiments, for generating signals that suggest a relationship between a pattern revealed by a portion of oversampled data and a predetermined pattern. [Figure 6] This flowchart illustrates the process of determining the feature that suggests the highest relationship between the pattern revealing each portion of the oversampled data and a given pattern, using one or more examples. [Figure 7] This block diagram shows a system for adjusting signal timing to indicate the presence of a portion of data corresponding to a predetermined pattern in the coupling portion of the physical layer's received data path, in one or more embodiments. [Figure 8] This flowchart illustrates a process for adjusting signal timing to indicate the presence of a portion of data corresponding to a predetermined pattern in the coupling portion of the physical layer's received data path, in one or more embodiments. [Figure 9] This block diagram shows a system for illustrating patterns revealed by data of a predetermined message type on the physical layer's receiving data path, according to one or more embodiments. [Figure 10]In one or more embodiments, a block diagram of a circuit that may be used to implement the various functions, operations, actions, processes, and / or methods disclosed by one or more embodiments. [Modes for carrying out the invention]

[0009] The following detailed description refers to the accompanying drawings, which form part of this specification and illustrate specific examples of embodiments that may carry out the disclosure. These embodiments are described in sufficient detail to enable those skilled in the art to carry out the disclosure. However, other embodiments made possible herein may be utilized without departing from the scope of the disclosure, with variations in structure, materials, and processes.

[0010] The illustrative diagrams presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the disclosure. In some cases, similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristics.

[0011] The following description may include examples to help enable those skilled in the art to carry out the disclosed examples. The use of the terms “exemplary,” “as an example,” and “for example” means that the relevant description is explanatory, and the scope of this disclosure is intended to include examples and legal equivalents, but the use of such terms is not intended to limit the scope of the examples of this disclosure to specified components, steps, features, functions, etc.

[0012] It will be readily apparent that the components of the embodiments described in this specification and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following descriptions of various embodiments are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Various aspects of the embodiments may be presented in the drawings, which are not necessarily drawn to scale unless specifically indicated.

[0013] Furthermore, the specific implementations illustrated and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Conversely, the specific implementations illustrated and described are merely illustrative and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic between various blocks are examples of specific implementations. It will be readily apparent to those skilled in the art that this disclosure can be implemented by numerous other partitioning solutions. For the most part, details such as timing considerations are omitted, as such details are not necessary for a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0014] Those skilled in the art will understand that information and signals can be represented using any of the various different techniques and methods. Some drawings may illustrate a signal as a single signal for clarity in presentation and explanation. Those skilled in the art will understand that a signal can represent a bus of signals, which can have various bit widths, and that this disclosure can be implemented with any number of data signals, including a single data signal.

[0015] The various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, dedicated processors, digital signal processors (DSPs), integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein, all of which are encompassed by the use of the term “processor.” A general-purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration. A general-purpose computer containing a processor is considered a dedicated computer, while a general-purpose computer is configured to execute computing instructions (e.g., software code, but not limited to) related to the embodiments of this disclosure.

[0016] Examples may be described in relation to processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe actions as sequential processes, many of these actions can be performed in different sequences, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes may correspond to methods, threads, functions, procedures, subroutines, subprograms, other structures, or combinations thereof. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or codes in a computer-readable medium. Computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of computer programs from one location to another.

[0017] Any reference to elements in this specification using notations such as "first," "second," etc., does not limit the number or order of those elements unless such limitation is expressly stated. Rather, these notations may be used in this specification as a convenient way to distinguish two or more elements or examples of elements. Thus, references to the first and second elements do not mean that only two elements may be used, or that the first element must precede the second element in any way. In addition, unless otherwise specified, a set of elements may contain one or more elements.

[0018] As used herein, the term “substantially” when referring to a given parameter, characteristic, or condition means and includes the extent to which a person skilled in the art would understand that the given parameter, characteristic, or condition satisfies small variations, such as within acceptable manufacturing tolerances. For example, depending on the particular parameter, characteristic, or condition that is substantially satisfied, the parameter, characteristic, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0019] As used herein, any relative terms such as "over", "under", "on", "underlying", "upper", "lower", etc. are used for clarity and convenience in understanding the disclosure and the accompanying drawings and do not include or depend on any specific preference, orientation, or order, unless the context clearly indicates otherwise.

[0020] In this description, the term "coupled" and its derivatives can be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the element can be in direct physical or electrical contact, or there can be intervening elements or layers present. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers. The term "connected" can be used interchangeably herein with the term "coupled" and has the same meaning unless expressly indicated otherwise or the context indicates otherwise to those skilled in the art.

[0021] Vehicles such as automobiles, trucks, buses, ships, and / or aircraft may include a vehicle communication network. The complexity of the vehicle communication network can vary depending on the number of electronic devices within the network. For example, a high-level vehicle communication network can include various control modules for, by way of non-limiting example, engine control, transmission control, safety control (e.g., anti-lock brakes), and emission control. To support these modules, the automotive industry relies on various communication protocols.

[0022] 10SPE (i.e., 10 Mbps single-pair Ethernet, also known as "10BASE-T1S") is a network technology defined in IEEE 802.3cg (trademark). 10SPE can be used, among other things, for example, on a multi-drop network or shared transmission media to provide deterministic transmission without collisions.

[0023] The 1588 high-precision time protocol (PTP) is a network technology used to synchronize clocks in a computer network defined by IEEE 1588 (“1588 PTP”). In 10BASE-T1S, the 1588 PTP media access controller (MAC) generates a timestamp when the frame start delimiter (SFD) crosses the media independent interface (MII) between the MAC and the physical layer (PHY) device, and adds a value to or subtracts a value from the timestamp to obtain a timestamp representing when the SFD crosses the media dependent interface (MDI). The added or subtracted value represents, in some cases, the known fixed latency between the media dependent interface (MDI), which is the interface between the PHY and the cable, and the MII between the MAC and the PHY. In this specification, the PHY device is also referred to as “PHY”.

[0024] The PHY may have variable latency, but it is desirable to know with relatively high accuracy when a packet is transmitted or received over the network. A PHY including a pattern matcher for observing frames on the internal MII between the PHY (e.g., between the physical coding sublayer (PCS) and the physical layer collision avoidance (PLCA) regulation sublayer (RS), i.e., “PLCA RS”) may be utilized.

[0025] The pattern matcher generates a pulse in response to detecting a symbol corresponding to the SFD in the internal MII between the PCS and the PLCA RS. The pulse is provided to the MAC via a further MII, which is the interface between the MAC and the PHY. However, in the PLCA PHY, the latency of the PLCA RS and the internal MII are not fixed or known.

[0026] Furthermore, if the MII clock between the MAC and the PHY has a lower resolution than the PHY clock, pulses generated by the pattern matcher may be transmitted to the MAC after waiting for the MII clock period. Since the MAC generates a timestamp using the time it receives the pulse, the difference between the timestamp value generated by the MAC in response to the pulse and the actual time the pulse was generated in the PHY may be equivalent to the clock period of the further MII clock.

[0027] The inventors of this disclosure understand that the latency of PLCA RS is variable (non-fixed), while the latency between the PCS and MDI is fixed. The inventors of this disclosure understand that it is desirable to perform pattern matching in a portion of the receive path between the MDI and PCS in order to reduce uncertainty regarding PHY latency. The PCS is responsible, in non-limiting examples, for encoding, decoding, scrambling, descrambling, alignment market insertion and removal, and block and symbol deskue. Prior to the PCS, noise and sampling phase may corrupt the data samples taken by the pattern matcher to such an extent that the detection of a given pattern of bitwise symbols is unreliable.

[0028] Furthermore, the inventors of this disclosure understand that, in order to reduce uncertainty regarding PHY latency, it is desirable to use a different path between PHY and MAC than the MII, which results in lower uncertainty than the MII.

[0029] One or more embodiments generally relate to the use of a correlator to detect a predetermined pattern revealed by data on the PHY's receiving data path. The correlator may be coupled to observe the data stream in a portion of the PHY's receiving data path located before the PCS block and to detect a predetermined pattern revealed by the data in the data stream.

[0030] As used herein, the term “data” should be understood to include data and symbols used to represent data, unless otherwise explicitly stated or the context in which it is used does not lead to a different interpretation by a person skilled in the art. The frame start delimiter, Ethernet preamble, and Ethernet stream start delimiter (SSD) are, in this specification, considered to be part of the data, respectively.

[0031] Figure 1 is a block diagram of a device 100 showing, in one or more embodiments, the presence of a portion of data corresponding to a predetermined pattern (also referred to herein simply as a “portion of data”) in the coupling portion of the physical layer’s received data path. The device 100 may include a data sampling circuit 102 and a logic circuit 110. The logic circuit 110 may include correlation logic 104 and feature observation logic 106. The device 100, more specifically the data sampling circuit 102, may be coupled to receive data 116 from a portion 112 of the PHY’s received data path 124. The depiction of the portion 112 of the PHY’s received data path 124 in Figure 1 is for the sake of facilitating discussion and is not intended in any way to limit the scope of this disclosure. Including a portion 112 of the received data path 124 in the device 100 is optional.

[0032] In one or more embodiments, the device 100, more specifically the logic circuit 110, can infer, through correlation calculations, one or more portions of data corresponding to various predetermined patterns. The device 100 can observe data 116 in the receiving data path 124 (for example, by sampling data 116 on the receiving data path 124, but not limited to) and generate a second signal 120 (which may be interchangeably referred to herein as the “feature identification signal 120” or the “second signal 120”) that suggests a portion of data 116 corresponding to a predetermined pattern 126 of bits or symbols (for example, a correlated portion, but not limited to), and by inference suggests the presence of a portion of data in a combined portion of the receiving data path 124 of the PHY (for example, a portion 112, but not limited to). In one or more embodiments, the combined portion of the receiving data path of the PHY may be a predetermined reference plane of the PHY.

[0033] In one or more embodiments, a data sampling circuit 102 oversamples data 116 in a received data path 124 and provides the oversampled portion of data 114 to a logic circuit 110. The data sampling circuit 102 may be coupled to a portion 112 of the received data path 124 (also referred to herein as the “coupled portion 112”) to oversample data 116. Oversampling of data includes, but is not limited to, sampling data at a sampling frequency higher than the Nyquist rate (e.g., twice the bandwidth of data 116). Any rate preferably higher than the Nyquist rate based on operating conditions may be selected for the sampling rate of the data sampling circuit 102. Oversampling can improve one or more of the resolution and signal-to-noise ratio and reduce aliasing and phase distortion. Recovering a signal from oversampled data 114 is easier than recovering a signal from data 116. In one or more embodiments, the location of the coupling portion 112 of the received data path 124 may be any location on the received data path 124, including, but not limited to, the location immediately preceding the PCS block of the PHY.

[0034] In one or more embodiments, the logic circuit 110 receives a portion of oversampled data 114 from the data sampling circuit 102 and generates a second signal 120 that indicates a portion of data 116 corresponding to a predetermined pattern 126. The portion of oversampled data 114 may be, or include, an oversampled version of data 116. Instances of the portion of oversampled data 114 may reveal one or more patterns ("revealed patterns 128"), including, but not limited to, substantially revealing a predetermined pattern 126.

[0035] In one or more embodiments, the correlation logic 104 of the logic circuit 110 generates a signal 118 (also referred to herein as the “first signal 118” or “correlation signal 118”) that indicates a relationship between a revealed pattern 128 of a portion of the oversampled data 114 and a predetermined pattern 126. The relationship between the revealed pattern 128 of a portion of the oversampled data 114 and the predetermined pattern 126 indicated by the correlation logic 104 may be the degree of identity or difference between the revealed pattern 128 and the predetermined pattern 126. In one or more embodiments, a given level of the first signal 118 may represent the magnitude of the relationship between the revealed pattern 128 and the predetermined pattern 126, as calculated by the correlation logic 104. Therefore, if the level of the first signal 118 in the first time is greater than the level of the first signal 118 in a different second time, it indicates that the relationship between a portion of the oversampled data 114 and the predetermined pattern 126 in the first time is stronger than the relationship between a further portion of the oversampled data 114 and the predetermined pattern 126 in the second time.

[0036] In one or more embodiments, the feature observation logic 106 of the logic circuit 110 generates a second signal 120 that suggests a detected feature of the first signal 118. In one or more embodiments, the detected feature suggests a predetermined relationship (e.g., a suitably strong relationship) between an exposed pattern 128 of a portion of the oversampled data 114 and a predetermined pattern 126. In one or more embodiments, a threshold may be used to observe whether the level of the first signal 118 shows a sufficient correlation with the predetermined pattern 126, and thus the feature may be a level of the first signal 118 that exceeds such a threshold.

[0037] In some cases, there may be multiple instances of the first signal 118 level above the threshold, or the threshold may not be used at all. In either case, the highest relationship between the revealed pattern 128 of the oversampled portion of the data 114 and a given pattern 126 can be observed by the feature observation logic 106 that utilizes the first signal 118. Given that the signal level of the first signal 118 indicates the strength of the relationship, the detected feature may be the peak amplitude of the first signal 118 above the threshold (if the first signal 118 is a continuous waveform), as described herein.

[0038] Figure 2 is a block diagram showing a portion 200 (also referred to herein as “apparatus portion 200”) of apparatus 100 according to one or more embodiments. Apparatus portion 200 may include a data sampling circuit 102, a coupling portion 112 of a received data path 124, a predetermined reference plane of the PHY 202, an optional MDI 204, and an optional PCS block 210.

[0039] In the specific embodiment shown in Figure 2, the coupling portion 112 of the receiving data path 124 is located on or near a predetermined reference plane of the PHY 202. In one or more embodiments, the predetermined reference plane of the PHY 202 may be set at any location within the receiving data path 124, including, but not limited to, various interfaces between the processing blocks of the PHY. In the specific embodiment shown in Figure 2, the predetermined reference plane of the PHY 202 is located between the MDI 204 and the PCS block 210. Using other locations as the reference plane is particularly conceivable and is not beyond the scope of this disclosure.

[0040] A portion of the data 208 may reveal a pattern 206 ("revealed pattern 206"), which in various examples may be an Ethernet preamble, an Ethernet frame start delimiter (SFD), an Ethernet stream start delimiter (SSD), or other symbols, each of which is considered a portion of the data as described herein. 1588PTP specifies that the reference plane of the 1588 timestamp is when the SFD crosses the PHY cable interface. If the SSD preamble, or another known sequence of bits or symbols located at a known fixed number of bits prior to the SFD, is used as a predetermined pattern 126, the second signal 120 may be delayed by a predetermined number of bits representing the distance between the SSD preamble and the SFD to indicate the portion of the data 116 corresponding to the SFD, more generally, the desired reference plane.

[0041] Figure 3 is a graph 300 showing line 302 representing exemplary correlation signals (e.g., examples of correlation signal 118, but not limited to) generated with noise by apparatus 100 or apparatus part 200 in one or more embodiments. Line 314 represents exemplary correlation signals generated without noise by apparatus 100 or apparatus part 200 in one or more embodiments. Line 314 is shown as a visual reference because the disclosed correlation signals are typically observed with some noise.

[0042] In Graph 300, the horizontal axis 312 represents time increasing from left to right, and the vertical axis 310 represents the strength of the correlation, where "1" corresponds to 100% correlation, "0" corresponds to 0% direct or inverse correlation (i.e., 100% no correlation), and "-1" corresponds to 100% inverse correlation.

[0043] Line 302 (and line 314) includes multiple peaks, for example, peak 304, peak 306, and peak 308. Peaks are formed when the intensity of the correlation indicated by the correlation signal changes from generally increasing to generally decreasing.

[0044] The feature observation logic 106 compares the heights of various peaks, such as peaks 304, 306, and 308 (e.g., the values ​​of the correlation strength associated with such peaks), to observe that peak 304 is the highest peak on line 302 for the given period. A portion of the data associated with peak 304 can be inferred to correspond to a given pattern (e.g., a given pattern 126, but not limited to one). In one or more embodiments, a peak threshold can be used to observe that the peak shows sufficient correlation with the given pattern. Non-limiting examples of peak thresholds include at least 0.95, at least 0.9, at least 0.85, at least 0.8, at least 0.75, or at least 0.7. In some cases, corruption caused by the oversampling process may introduce noise into the first signal 118, and therefore a peak threshold of less than 1 may be selected that is still sufficiently reliable in detecting the given pattern.

[0045] The timing T corresponding to peak 304 can be captured by the feature observation logic 106 to indicate the timing of the portion of data 116 corresponding to peak 304, and therefore to indicate the timing of the portion of data 116 corresponding to a given pattern 126.

[0046] Figure 4 is a flowchart showing a process 400 that generates a signal suggesting a portion of data exhibiting a predetermined pattern, according to one or more embodiments. Part or all of the process 400 may be carried out by the apparatus 100 of Figure 1, as a non-limiting example.

[0047] In operation 402, process 400 applies oversampling (for example, via the data sampling circuit 102 in Figure 1) to the data received from the PHY's data reception path (for example, but not limited to, the reception data path 124 in Figure 1) (for example, but not limited to, data 116). In one or more embodiments, applying oversampling to the data may include applying oversampling to a copy of the data or a copy of a portion of the data.

[0048] In operation 404, process 400 generates a first signal (e.g., first signal 118) that shows the relationship between a pattern revealed by a portion of the oversampled data (e.g., revealed pattern 128, but not limited to, revealed by a portion of the oversampled data 114) and a predetermined pattern (e.g., predetermined pattern 126, but not limited to).

[0049] In operation 406, process 400 generates a second signal (e.g., a second signal 120) that exhibits observed features (e.g., peaks) of the first signal. The observed features suggest the highest relationship between the pattern revealed by each portion of the oversampled data and a given pattern, and by inference suggest the portion of data 116 corresponding to the given pattern.

[0050] In operation 408, process 400 provides a second signal (e.g., second signal 120) to indicate the observation of a pattern that most strongly correlates with a given pattern, which is used as an indicator of the presence of a portion of data (e.g., portion of data 116) corresponding to a given pattern in a coupling portion (e.g., coupling portion 112) of the PHY's received data path (e.g., received data path 124). In one or more embodiments, the indicator of presence may be an indicator of presence in a given reference plane of the PHY, such as an SFD across the MDI, e.g., a given reference plane of PHY 202.

[0051] Figure 5 is a flowchart illustrating a process 500 in which, according to one or more embodiments, signals are generated that suggest a relationship between a pattern revealed by a portion of oversampled data and a predetermined pattern.

[0052] In operation 502, process 500 observes the difference or similarity between the pattern revealed by the portion of the oversampled data and a predetermined pattern. In operation 504, process 500 determines the relationship between the pattern revealed by the portion of the oversampled data (e.g., a portion of the oversampled data 114, but not limited to) and the predetermined pattern (e.g., a predetermined pattern 126, but not limited to) at least in part in response to the observed difference or similarity between the pattern revealed by the portion of the oversampled data and the predetermined pattern.

[0053] In operation 506, the level of the first signal (e.g., the first signal 118, but not limited to it) is set to correspond to a determined relationship between the pattern revealed by the oversampled portion of the data and a predetermined pattern. As an unrestricted example, setting the value of the first signal to "1" may indicate 100% correlation, "0" may indicate no direct or indirect correlation (i.e., 100% uncorrelated), and "-1" may indicate 100% negative correlation, with the levels between them indicating varying degrees of correlation.

[0054] Figure 6 is a flowchart illustrating a process 600 in which, in one or more embodiments, a feature is determined that suggests the highest relationship between a pattern revealing each portion of the oversampled data and a predetermined pattern.

[0055] In operation 602, process 600 observes one or more peaks in the first signal. As described above, a peak is formed when the intensity of the correlation indicated by the correlation signal changes from generally increasing to generally decreasing. In one or more embodiments, various peaks may be observed by observing a change in the value of the first signal from generally increasing to generally decreasing and capturing the value of the first signal when the change occurs. In one or more embodiments, multiple such changes in the value of the first signal may be observed during a given duration, and the correlation level of the first signal may be captured.

[0056] In operation 604, process 600 selects the highest peak from among one or more observed peaks of the first signal with respect to the feature that suggests the highest relationship between the pattern revealed by each portion of the oversampled data and a given pattern.

[0057] In one or more embodiments, operations 602 and 604 may be performed individually or collectively. When performed individually, multiple levels of the first signal may be captured during operation 602, and then in operation 604, the captured levels of the first signal may be compared to select the highest captured value of the first signal. When performed collectively, when a new peak is detected and a new associated value of the first signal is captured, the new associated value of the first signal is compared to the previous highest associated value of the first signal. If the new associated value of the first signal is higher, it is stored as the new highest associated value of the first signal for a given duration; if it is lower than the previous highest associated value of the first signal, the previous highest associated value of the first signal is retained and the new associated level of the previous highest associated value of the first signal is discarded.

[0058] As described above, the SSD is positioned at a fixed bit distance before the SFD in the Ethernet frame. In various examples where a sequence of other known bits or symbols located a known fixed number of bits from the SSD or SFD is used as a predetermined pattern 126, the timing of the second signal 120 may be adjusted to indicate the SFD instead of the SSD.

[0059] Figure 7 is a block diagram of a device 700 that, in one or more embodiments, adjusts the timing of a signal indicating the presence of a portion of data corresponding to a predetermined pattern in the coupling portion of the PHY's received data path, more specifically, the device 700 that adjusts the timing of a feature identification signal 120 to indicate an SFD instead of an SSD preamble, or a sequence of another known bit or symbol located at a known fixed number of bits from the SFD. Since device 700 includes certain elements of device 100 in Figure 1, those elements of device 100 are not described below in order to avoid unnecessary repetition of the description herein. A logic circuit 704 is provided in place of logic circuit 110, and the logic circuit 704 includes correlation logic 104 and feature observation logic 106, as described with respect to logic circuit 110. Logic circuit 704 includes synchronization logic 702 that delays the feature identification signal 120 output by the feature observation logic 106 by a predetermined number of bits to generate a modified feature identification signal 706 (which may also be referred to herein as the “third signal 706”). The predetermined number of bits represents the distance between the SSD and the SFD in bits. Generally speaking, the modified feature identification signal 706 is suitable for indicating a portion of the data corresponding to the SFD.

[0060] Figure 8 is a flowchart illustrating a process 800 for adjusting signal timing to indicate the presence of a portion of data corresponding to a predetermined pattern in the coupling portion of the PHY's received data path, in one or more embodiments.

[0061] In operation 802, process 800 generates a feature identification signal (e.g., feature identification signal 120) that indicates a first portion of the data (e.g., a portion of the data 116) corresponding to an observed feature (e.g., a peak) of a correlation signal (e.g., feature identification signal 120) that shows the relationship between a revealed pattern (e.g., revealed pattern 128) and a predetermined pattern (e.g., predetermined pattern 126).

[0062] In one or more embodiments, a predetermined pattern 126 may correspond to a sequence of other known bits or symbols located in a known fixed number of bits from the SSD or the SFD of an Ethernet frame.

[0063] In operation 804, process 800 generates a further signal (e.g., a modified feature identification signal 706) having a predetermined timing relationship with the feature identification signal. In one or more embodiments, the further signal may be generated by adding or subtracting a value representing a known fixed latency (e.g., represented by the number of bits or bit time, but not limited to) to the feature identification signal, and thus the predetermined timing relationship may be represented by such a value. Such a known fixed latency may correlate the feature identification signal (e.g., a feature identification signal 120, but not limited to) to the timing of another part of the data corresponding to a different pattern (e.g., a different single or multiple symbols, but not limited to). As an unspecified example, the second part of the data may include symbols of an SFD. By adding or subtracting a known fixed value, the indicated timing is effectively changed. In one or more embodiments, further signals (e.g., modified feature identification signals 706, but not limited to) may be generated by delaying the feature identification signal by a predetermined number of bits corresponding to the number of bits between the SFD and the SSD, or a sequence of other known bits or symbols located at a fixed number of bits in the SFD of the Ethernet frame.

[0064] In operation 806, process 800 utilizes a further signal (e.g., a modified feature identification signal 706) as a signal provided to indicate the presence of a portion of the data at the joining portion of the PHY's received data path. In one or more embodiments, the presence indicator may be, but is not limited to, an indicator of presence at a predetermined reference plane of the PHY, such as an SFD across the MDI.

[0065] The disclosed device for displaying patterns revealed by data on the physical layer's received data path is not necessarily required for all types of messages. False positives may occur if a given pattern can exist in multiple message types.

[0066] Figure 9 is a block diagram of a system 900 for showing a pattern revealed by data of a predetermined message type on the physical layer's received data path, according to one or more embodiments. The system 900 includes a device 916, a packet pattern matcher 902, and a pulse generator 908. Device 916 may, in non-limiting examples, be or include device 100 or device 700. Device 916 indicates that the pattern revealed by data 904 matches a predetermined pattern 126 (Figure 1) by asserting a timing signal 906, which may be a second signal 120 in Figure 1 or a third signal 706 in Figure 7. The packet pattern matcher 902 indicates that the pattern revealed by data 904 matches a predetermined pattern of a particular packet type by asserting a packet type signal 910. The pulse generator 908 generates a pulse 912 in at least partially in response to both the timing signal 906 and the packet type signal 910 being asserted.

[0067] The pulses may optionally be communicated via connector 914, which may be, or include, unassociated (i.e., not associated with the MII) pins, such as general-purpose input / output pins of a microcontroller having shorter clock periods than the MII, as an example without limitation.

[0068] Those skilled in the art will understand that the functional elements (e.g., functions, operations, behaviors, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 10 illustrates a non-limiting example of an implementation of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein may be implemented by hardware specifically configured to perform the functional elements.

[0069] Figure 10 is a block diagram of circuit 1000, which in some embodiments may be used to implement various functions, operations, actions, processes, and / or methods disclosed herein. Circuit 1000 includes one or more processors 1002 (which may be referred to herein as “processor 1002”) operably coupled to one or more data storage devices (which may be referred to herein as “storage device 1006”). The storage device 1006 includes machine-executable code 1008 stored therein, and the processors 1002 include logic circuits 1004. The machine-executable code 1008 includes information describing functional elements that can be implemented (e.g., executed) by the logic circuits 1004. The logic circuits 1004 are adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1008. When the circuit 1000 executes the functional elements described by the machine-executable code 1008, it should be considered dedicated hardware for executing the functional elements disclosed herein. In some embodiments, the processor logic circuit 1004 may execute the functional elements described by the machine-executable code 1008 sequentially, simultaneously (for example, on one or more different hardware platforms), or in one or more parallel processing streams.

[0070] When implemented by the logic circuit 1004 of processor 1002, machine executable code 1008 adapts processor logic circuit 1004 to perform the operations of the embodiments disclosed herein. In a non-limiting embodiment, machine executable code 1008 may adapt processor 1002 to perform some or all of the operations of one or more of the devices 100, device portion 200 represented by graph 300, device 700, and system 900. In a further non-limiting embodiment, machine executable code 1008 may adapt processor 1002 to perform the operations of process 400, process 500, process 600, or process 800 disclosed herein.

[0071] The processor 1002 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer, but at the same time, the general-purpose computer is configured to execute functional elements corresponding to machine-executable code 1008 (e.g., software code, firmware code, hardware description) relating to embodiments of this disclosure. The general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but it should be noted that the processor 1002 may instead include any conventional processor, controller, microcontroller, or state machine. The processor 1002 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration.

[0072] In some embodiments, the storage device 1006 includes volatile data storage devices (e.g., random-access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), etc.). In some embodiments, the processor 1002 and the storage device 1006 may be implemented in a single device (e.g., a semiconductor device product, a system-on-a-chip (SOC), etc.). In some embodiments, the processor 1002 and the storage device 1006 may be implemented in separate devices.

[0073] In some embodiments, the machine-executable code 1008 may include computer-readable instructions (e.g., software code, firmware code). In a non-limiting example, the computer-readable instructions may be stored in the memory device 1006, directly accessed by the processor 1002, and executed by the processor 1002 using at least the logic circuit 1004. Also, in a non-limiting example, the computer-readable instructions may be stored in the memory device 1006, transferred to a memory device (not shown) for execution, and executed by the processor 1002 using at least the logic circuit 1004. Thus, in some embodiments, the logic circuit 1004 includes an electrically configurable logic circuit 1004.

[0074] In some embodiments, machine-executable code 1008 may describe hardware (e.g., circuits) implemented within logic circuits 1004 to execute functional elements. This hardware may be described at any of various levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, a hardware description language (HDL), such as the IEEE standard hardware description language (HDL), may be used. In non-limiting examples, VERILOG®, SYSTEMVERILOG®, or very large-scale integration (VLSI) hardware description language (VHDL®) may be used.

[0075] An HDL description can be translated into a description at any of several other levels of abstraction, as desired. As an unrestricted example, a high-level description can be translated into a logic-level description such as a register-transfer language (RTL), gate-level (GL) description, layout-level description, or mask-level description. As an unrestricted example, microoperations performed by the hardware logic circuits of logic circuit 1004 (e.g., gates, flip-flops, registers, but not limited to these) may be described in RTL and then translated into a GL description by a synthesis tool, which can then be translated into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, separate gate or transistor logic, separate hardware components, or combinations thereof. Therefore, in some embodiments, machine-executable code 1008 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0076] In embodiments where the machine-executable code 1008 includes a hardware description (at any level of abstraction), the system (including a storage device 1006, not shown) may implement the hardware description described by the machine-executable code 1008. In a non-limiting example, the processor 1002 may include a programmable logic device (e.g., an FPGA or PLC), and the logic circuit 1004 may be electrically controlled to implement circuits corresponding to the hardware description in the logic circuit 1004. Also in a non-limiting example, the logic circuit 1004 may include hardwired logic manufactured by a manufacturing system (including a storage device 1006, not shown) according to the hardware description of the machine-executable code 1008.

[0077] Regardless of whether the machine-executable code 1008 includes computer-readable instructions or hardware descriptions, the logic circuit 1004 is adapted to execute the functional elements described by the machine-executable code 1008 when implementing the functional elements of the machine-executable code 1008. Note that while hardware descriptions do not have to directly describe functional elements, they indirectly describe the functional elements that the hardware elements described by them can perform.

[0078] Where used in this disclosure, the terms “module” or “component” may refer to a specific hardware implementation configured to perform actions of a module or component and / or software object or software routine that are stored in and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing devices, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored and / or executed in general-purpose hardware), specific hardware implementations, or combinations of software and specific hardware implementations, are also possible and intended.

[0079] When used in this disclosure, the term “combination” referring to multiple elements may include any combination of all elements or any various different subcombinations of some elements. For example, the phrase “A, B, C, D, or any combination thereof” may refer to A, B, C, or D; any combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or any one of C and D.

[0080] The terms used in this disclosure, and in particular in the appended claims (e.g., the text of the appended claims), are generally intended to be "open" terms (for example, the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," and the term "includes" should be interpreted as "includes, but is not limited to," etc.).

[0081] Additionally, if a specific number of introduced claim enumerations is intended, such intent will be explicitly enumerated in the claims; if there is no such enumeration, such intent does not exist. For example, to aid understanding, the following attached claims may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim enumeration. However, the use of such phrases should not be interpreted as the introduction of a claim enumeration by the indefinite article “one (a)” or “one (an)” limiting any particular claim containing such introduced claim enumerations to embodiments containing only one such enumeration (for example, “one (a)” and / or “one (an)” should be interpreted as meaning “at least one” or “one or more”). The same applies to the use of definite articles used to introduce claim enumerations. The term "each" should be interpreted as meaning "some or all," while the term "each and every" should be interpreted as meaning "all."

[0082] In addition, even if a specific number of claims introduced is explicitly listed, a person skilled in the art will recognize that such a list should be interpreted as meaning at least the number listed (for example, the explicit listing of “two lists” without other modifiers means at least two lists or two or more lists). Furthermore, where conventions similar to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” are used, such structures are generally intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0083] Furthermore, any separating words or phrases that present two or more alternative terms should be understood, whether in the specification, claims, or drawings, as intended to include the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0084] While this disclosure is described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that this disclosure is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, together with their legal equivalents. In addition, features of one embodiment can be combined with features of another embodiment, but still remain within the scope of the invention.

[0085] Example 1: A method comprising: applying oversampling to data on a receiving data path of a physical layer device; generating a first signal indicating a relationship between a pattern revealed by a portion of the oversampled data and a predetermined pattern; generating a second signal, which is an observed feature of the first signal indicating an observed feature that suggests the highest relationship between a pattern revealed by each portion of the oversampled data and a predetermined pattern; and providing the second signal to indicate the presence of a portion of data corresponding to a predetermined pattern in a coupling portion of the receiving data path of the physical layer.

[0086] Example 2: The method according to Example 1, wherein the coupling portion of the receiving data path of the physical layer device corresponds to a predetermined reference plane of the physical layer device.

[0087] Example 3: A predetermined reference plane corresponds to a media-dependent interface, using the method according to Examples 1 and 2.

[0088] Example 4: A method according to Examples 1 to 3, comprising: observing the difference or similarity between a pattern revealed by a portion of oversampled data and a predetermined pattern; determining the relationship between the pattern revealed by a portion of oversampled data and a predetermined pattern in at least a partial response to the observed difference or similarity; and setting the value of a first signal to correspond to the determined relationship between the pattern revealed by a portion of oversampled data and a predetermined pattern.

[0089] Example 5: A method according to Examples 1-4, comprising observing one or more peaks in the first signal and selecting the highest peak from among the observed peaks in the first signal with respect to a feature that suggests the highest relationship between the pattern revealed by each portion of the oversampled data and a predetermined pattern.

[0090] Example 6: A method according to Examples 1 to 5, comprising: generating a feature identification signal that indicates a first portion of oversampled data corresponding to an observed feature; generating a modified feature identification signal that has a predetermined relationship with the feature identification signal and indicates a second portion of data that is different from the first portion of the data and has a predetermined relationship with the related first portion; and using the modified feature identification signal as a second signal.

[0091] Example 7: The method according to Examples 1-6, wherein the predetermined relationship is a known fixed latency.

[0092] Example 8: A device comprising a data sampling circuit for oversampling data in the receiving data path of a physical layer device; a logic circuit comprising: correlation logic for generating a first signal, the first signal indicating a relationship between a pattern revealed by a portion of the oversampled data and a predetermined pattern; feature observation logic for generating a second signal, the second signal indicating an observed feature of the first signal, the feature indicating the highest relationship between a pattern revealed by each portion of the oversampled data and a predetermined pattern; and synchronization logic for generating a third signal, the third signal indicating a portion of the data corresponding to the observed feature.

[0093] Example 9: The apparatus according to Example 8, wherein the data sampling circuit is coupled to a portion of the data reception path corresponding to a predetermined reference plane of the physical layer device.

[0094] Example 10: The apparatus according to Examples 8 and 9, where a predetermined reference plane corresponds to a media-dependent interface.

[0095] Example 11: An apparatus according to Examples 8-10, comprising correlation logic, which includes logic for observing differences or similarities between a pattern revealed by a portion of oversampled data and a predetermined pattern, determining a relationship between the pattern revealed by a portion of oversampled data and a predetermined pattern in at least a partial response to the observed differences or similarities, and setting a value of a first signal to correspond to the determined relationship between the pattern revealed by a portion of oversampled data and a predetermined pattern.

[0096] Example 12: Apparatus according to Examples 8-11, wherein the observed features of the first signal include a peak.

[0097] Example 13: The data sampling circuit is an apparatus according to Examples 8-12, which oversamples data in a portion of the data reception path before the physical coding sublayer of the physical layer.

[0098] Example 14: The apparatus according to Examples 8-13, wherein the synchronization logic generates a third signal which has a predetermined relationship with the second signal and indicates a second part of data different from the first part.

[0099] Example 15: Apparatus according to Examples 8-14, wherein the predetermined relationship is a known fixed latency.

Claims

1. It is a method, The steps include applying oversampling to the data on the receiving data path of the physical layer device, A step of generating a first signal that shows the relationship between a pattern revealed by a portion of the oversampled data and a predetermined pattern, A step of generating a second signal that shows the observed features of the first signal, which indicate the highest relationship between the pattern revealed by each portion of the oversampled data and the predetermined pattern; A method comprising the step of providing the second signal to indicate the presence of a portion of data corresponding to the predetermined pattern in the coupling portion of the received data path of the physical layer.

2. The method according to claim 1, wherein the coupling portion of the receiving data path of the physical layer device corresponds to a predetermined reference plane of the physical layer device.

3. The method according to claim 2, wherein the predetermined reference surface corresponds to a media-dependent interface.

4. A step of observing the difference or similarity between the pattern revealed by a portion of the oversampled data and the predetermined pattern, A step of determining the relationship between the pattern revealed by the portion of the oversampled data and the predetermined pattern, in at least a partial response to the observed differences or similarities; The method according to claim 1, comprising the step of setting a value of the first signal to correspond to the determined relationship between the pattern revealed by the portion of the oversampled data and the predetermined pattern.

5. The steps include observing one or more peaks of the first signal, The method according to claim 1, comprising the step of selecting the highest peak from among the observed peaks of the first signal with respect to the feature that suggests the highest relationship between the pattern revealed by each portion of the oversampled data and the predetermined pattern.

6. The steps include generating a feature identification signal that represents a first portion of the oversampled data corresponding to the observed features, A step of generating a modified feature identification signal having a predetermined relationship with the feature identification signal, wherein the modified feature identification signal has a predetermined relationship with the related first part and indicates a second part of the data that is different from the first part of the data; The method according to claim 1, comprising the step of using the modified feature identification signal as the second signal.

7. The method according to claim 6, wherein the predetermined relationship is a known, fixed latency.

8. It is a device, A data sampling circuit that oversamples data in the receiving data path of a physical layer device, It is a logic circuit, A correlation logic that generates a first signal, wherein the first signal is a correlation logic that suggests a relationship between a pattern revealed by a portion of oversampled data and a predetermined pattern, A feature observation logic that generates a second signal, wherein the second signal suggests an observed feature of the first signal, and the feature suggests the highest relationship between the pattern revealed by each portion of the oversampled data and the predetermined pattern, A device including a logic circuit and a logic circuit, the logic including a synchronous logic that generates a third signal, wherein the third signal suggests a portion of the data corresponding to the observed feature.

9. The apparatus according to claim 8, wherein the data sampling circuit is coupled to a portion of the data reception path corresponding to a predetermined reference plane of the physical layer device.

10. The apparatus according to claim 9, wherein the predetermined reference surface corresponds to a media-dependent interface.

11. The aforementioned correlation logic is, Observe the difference or similarity between the pattern revealed by a portion of the oversampled data and the predetermined pattern, In response at least partially to the observed differences or similarities, the relationship between the pattern revealed by the portion of the oversampled data and the predetermined pattern is determined, and The apparatus according to claim 8, comprising logic for setting the value of the first signal to correspond to the determined relationship between the pattern revealed by the portion of the oversampled data and the predetermined pattern.

12. The apparatus according to claim 8, wherein the observed features of the first signal include a peak.

13. The apparatus according to claim 8, wherein the data sampling circuit oversamples the data in a portion of the data reception path before the physical coding sublayer of the physical layer.

14. The aforementioned synchronization logic is The apparatus according to claim 8, which generates a third signal having a predetermined relationship with the second signal, and which indicates a second portion of data different from the first portion.

15. The apparatus according to claim 14, wherein the predetermined relationship is a known, fixed latency.

Images