Apparatus, method, and computer readable medium for clock synchronization
By optimizing the time format conversion in the IEEE1588V2 protocol and employing a high-performance digital decimal divider, the problem of nanosecond carry processing in digital chip design was solved, achieving clock synchronization in low-cost and high-speed, high-bandwidth scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BELL SOFTWARE
- Filing Date
- 2023-09-18
- Publication Date
- 2026-06-02
Smart Images
Figure CN119652455B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure generally relate to the fields of communications and digital circuitry, and more specifically to an apparatus, method, and computer-readable medium for clock synchronization. Background Technology
[0002] In the IEEE 1588V2 protocol implementation system, the standard IEEE 1588V2 time information (IEEE 1588V2 timestamp) exchanged is 80 bits, with the high 48 bits representing seconds and the low 32 bits representing nanoseconds.
[0003] In digital chip design, when processing an 80-bit wide time counter, a carry is applied to the second field when the nanosecond field within the standard time reaches 1 second (i.e., 1000000000D = 3B9ACA00H). This can lead to frequent nanosecond carry operations in the design, such as asymmetric compensation additions and subtractions, for example, by adding a compensation delay value to the standard IEEE 1588V2 time or subtracting a compensation nanometer delay value from the standard time; or as part of the current ToD generation calibration operation, adding the time offset of the Precision Time Protocol (PTP) slave to the standard IEEE 1588V2 time counter. All these carry processes require more hardware logic resources in digital designs and also affect the timing characteristics of high-speed digital designs. Summary of the Invention
[0004] In general, the exemplary embodiments of this disclosure relate to a technical solution for communication. Specifically, it relates to a high-performance digital decimal divider for obtaining time information required during communication.
[0005] The technical solutions of the embodiments of this disclosure can be used in devices that output timestamps at the port of a Precision Time Protocol (PTP) system. By optimizing the corresponding calculation model, it satisfies the requirements of high-bandwidth network applications and low-cost design, and achieves higher maximum clock frequencies F. max A flexible balance is achieved between lower conversion latency and more.
[0006] In a first aspect of the disclosure, an apparatus for clock synchronization is provided. The apparatus includes at least one processor and at least one memory. The at least one memory stores instructions that, when executed by the at least one processor, cause the apparatus to at least: perform a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time in a first time unit; perform a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; and obtain a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first portion and a second portion, the first portion corresponding to the quotient and representing time in a second time unit, and the second portion corresponding to the remainder and representing time in a first time unit.
[0007] In a second aspect, a method for clock synchronization is provided. The method includes: performing a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time using a first time unit; performing a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; and generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponding to the quotient and representing time in a second time unit, and the second part corresponding to the remainder and representing time in a first time unit.
[0008] In a third aspect of the disclosure, an apparatus is provided. The apparatus includes: means for performing a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time using a first time unit; means for performing a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; and means for generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first portion and a second portion, the first portion corresponding to the quotient and representing time in a second time unit, and the second portion corresponding to the remainder and representing time in a first time unit.
[0009] In a fourth aspect of this disclosure, a non-transitory computer-readable medium is provided, including program instructions for causing an apparatus to perform at least the method of the second aspect.
[0010] In a fifth aspect of this disclosure, a computer program is provided that, when executed by a device, causes the device to perform at least the method of the second aspect.
[0011] In a sixth aspect of this disclosure, an apparatus is provided. The apparatus includes: a first execution circuit configured to perform a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time in a first time unit; a second execution circuit configured to perform a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; and an obtaining circuit configured to obtain a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first portion and a second portion, the first portion corresponding to the quotient and representing time in a second time unit, and the second portion corresponding to the remainder and representing time in a first time unit.
[0012] It should be understood that the description in the Summary of the Invention section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings, without exceeding the scope of protection claimed by this application.
[0014] Figure 1 A block diagram of an example PTP communication system in which embodiments of the present disclosure may be implemented is shown.
[0015] Figure 2 A schematic diagram illustrating the operation of a clock synchronization apparatus according to an embodiment of the present disclosure is shown.
[0016] Figure 3 A functional simulation timing diagram according to an embodiment of the present disclosure is shown.
[0017] Figure 4 A clock information interaction diagram of a PTP communication system according to an embodiment of the present disclosure is shown.
[0018] Figure 5 A block diagram of a component for time format conversion of a PTP system port according to an embodiment of the present disclosure is shown.
[0019] Figure 6 The functional simulation timing diagram of the direct hardware language programming implementation scheme is shown.
[0020] Figure 7 The timing diagram of the functional simulation of the frequency reduction method implementation scheme is shown.
[0021] Figure 8 The basic principle diagram of the implementation scheme based on the binary fast division calculation model is shown.
[0022] Figure 9 The functional simulation timing diagram of the implementation scheme based on the binary fast division calculation model is shown.
[0023] Figure 10A A logical diagram of the implementation scheme based on the binary fast division calculation model is shown.
[0024] Figure 10B A logical schematic diagram of a computational model according to an embodiment of the present disclosure is shown.
[0025] Figure 11 A simplified block diagram of an electronic device suitable for implementing embodiments of the present disclosure is shown.
[0026] Figure 12 A schematic diagram of a computer-readable medium suitable for implementing embodiments of the present disclosure is shown.
[0027] In all the accompanying drawings, the same or similar reference numerals denote the same or similar elements. Detailed Implementation
[0028] The principles and spirit of this disclosure will now be described with reference to several exemplary embodiments illustrated in the accompanying drawings. It should be understood that these specific embodiments are described only to enable those skilled in the art to better understand and implement this disclosure, and are not intended to limit the scope of this disclosure in any way.
[0029] As used herein, the term "comprising" and similar expressions should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0030] As used herein, the term “determine” encompasses a wide variety of actions. For example, “determine” can include calculation, computation, processing, derivation, investigation, searching (e.g., searching in a table, database, or other data structure), ascertainment, etc. Furthermore, “determine” can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Additionally, “determine” can include parsing, selecting, choosing, building, etc. As used herein, “at least one of the following: ” and “at least one of ” and similar wording, where a list of two or more elements is connected by “and” or “or”, means at least any one of these elements, or at least any two or more of these elements, or at least all of the elements.
[0031] As used herein, the term "circuit" means one or more of the following: (a) a hardware circuit implementation (such as an implementation of analog and / or digital circuits only); and (b) a combination of hardware circuits and software, such as (if applicable): (i) a combination of analog and / or digital hardware circuits with software / firmware; and (ii) any part of a hardware processor with software (including digital signal processors, software, and memory that work together to enable devices such as radio frequency devices or other computing devices to perform various functions); and (c) a hardware circuit and / or processor, such as a microprocessor or a part of a microprocessor, which requires software (e.g., firmware) for operation, but may be without software when it is not required for operation.
[0032] The definition of "circuit" applies to all uses of this term in this application (including any claim). As another example, the term "circuit" as used herein also covers a hardware circuit or processor (or processors), or a portion thereof, or an implementation thereof with accompanying software or firmware. For instance, if applicable to a particular claim symbol, the term "circuit" also covers a baseband integrated circuit or processor integrated circuit or similar integrated circuit in other computing devices.
[0033] Precision Time Protocol (PTP) is a time synchronization protocol, also known as the IEEE 1588 protocol, used to synchronize the time and frequency of standard Ethernet terminal devices. A PTP system typically includes a PTP domain and PTP ports. A PTP domain refers to a network that uses the PTP protocol; there is one and only one synchronization clock within the domain, and all devices within the domain maintain synchronization with this clock. A PTP port refers to the port on the corresponding device that runs the PTP protocol.
[0034] In a precision time protocol implementation system, the clock exchange standard is the IEEE 1588V2 standard format, which contains 80 bits of time information: the high 48 bits represent seconds and the low 32 bits represent nanoseconds. Its structure is shown below:
[0035] IEEE 1588V2 timestamp
[0036] {
[0037] UInt48 Second_Field;
[0038] UInt32 NanoSecond_Field;
[0039] }
[0040] Figure 1 A block diagram of an example PTP communication system is shown. In PTP communication system 100, the master device 110 (PTP Master) is the clock synchronization source, and the clocks of other devices are synchronized to the clock of the master device 110. Slave devices 120 (PTPSlaves) are devices that need to synchronize their clocks with the master device. The boundary device 130 (PTP Boundary) has multiple ports connected to the network clock. One slave port (S port) is connected to the PTP port of the upstream device (the M port of the master device 110), and the other ports (other M ports as shown in the figure) are connected as master ports to the slave ports of the downstream devices (the S ports of the slave device 120). The downstream slave ports are homogeneous with the PTP protocol and directly synchronized to the boundary clock. The transparent device 140 (PTPTC), such as a switch, does not require time synchronization but can forward and modify certain passing PTP packets, recording the time taken for the PTP packet to pass through the device (i.e., the forwarding time) and adding it to the correction field of the PTP packet. During the synchronization clock operation of the PTP protocol, the master device needs to output an IEEE 1588V2 standard timestamp at the output port because these timestamps are exchanged through the PTP system on the telecommunications network.
[0041] Currently, digital chip design typically employs a simple binary time counter approach. This means that both system time maintenance and calculation operations within the chip use an 80-bit binary counter format, eliminating the need for integer second carry-overs during time counter calculations. This significantly simplifies the design, reduces logic resource consumption, and increases the clock frequency required for logic implementation. Therefore, a time format conversion is necessary at the PTP system output port, transforming the 80-bit binary nanosecond counter format into the IEEE 1588V2 standard time format. This necessitates circuitry with specific computational logic for implementation.
[0042] Embodiments of this disclosure relate to an apparatus, method, and computer-readable medium for clock synchronization, specifically providing an apparatus for outputting a timestamp on a PTP port and its corresponding computational model. In the corresponding computational model, the current output is only related to the current input and is independent of the output results of the previous one or more clock cycles, thereby eliminating the corresponding feedback input circuit and reducing the number of clock cycles required to complete time format conversion (e.g., conversion from a binary nanosecond counter time format to the IEEE 1588V2 standard time format). Furthermore, based on the theory of fast binary multiplication, the number of binary addition or subtraction operations is reduced, thereby reducing the consumption of hardware logic resources corresponding to a large number of operations and significantly lowering the latency of implementing time format conversion.
[0043] For example, when converting an 80-bit binary counter time format to the IEEE 1588V2 standard time format on a PTP port, the calculation model is usually as follows: divide the nanosecond information output by the 80-bit binary counter time format by 1 second (hexadecimal 3B9ACA00). The quotient is the 48-bit second information in the IEEE 1588V2 standard time format, and the remainder is the 32-bit nanosecond information in the IEEE 1588V2 standard time format.
[0044] Figure 2 A schematic diagram illustrating the operation 200 of a clock synchronization apparatus according to some embodiments of the present disclosure is shown. In some embodiments of the present disclosure, reference is made to... Figure 1 For example, the device located on the main device 110 side is used in process 200.
[0045] exist Figure 2 In example flow 200, firstly, at 210, the device performs a first set of addition or subtraction operations on the first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time in a first time unit. The first bit value is, for example, Figure 1The timing information inside the main device side has a first time unit, for example, nanoseconds, and the internal timing information is, for example, time information in an 80-bit binary counter time format. Those skilled in the art will readily understand that the first bit value can also use other time formats and / or bit numbers suitable for a specific embodiment, and the first time unit can also be other time units such as milliseconds. The first set of addition or subtraction operations corresponds to the "division operation" in the calculation model on which the time format conversion is based, and in the calculation model corresponding to this embodiment, the "division operation" is converted into the first set of addition or subtraction operations, so that the converted division operation does not need to wait for the feedback of the calculation result. Theoretically, through the circuit implementation of the corresponding calculation model, the quotient of the first bit value relative to a predetermined divisor can be obtained within one clock cycle. Optionally, the predetermined divisor corresponds to the conversion value of the first bit value for time unit conversion. For example, if the first bit value expressed in nanoseconds is converted to expressed in seconds, then the predetermined divisor is 10. 9 The obtained quotient is an integer number of seconds after time unit conversion. Those skilled in the art will readily understand that the first bit value can also be converted to other types of time units; for example, converting the first bit value expressed in nanoseconds to milliseconds would result in a predetermined divisor of 10. 6 The obtained quotient is an integer millisecond information converted from time units.
[0046] Then, at 220, the device performs a second set of addition or subtraction operations based on the first bit value and the quotient to obtain the remainder obtained by dividing the first bit value by a predetermined divisor. The second set of addition or subtraction operations corresponds to the "remainder operation" in the calculation model upon which the time format conversion is based. In the calculation model corresponding to this embodiment, the "remainder operation" is converted into a second set of addition or subtraction operations performed on the quotient. Similarly, theoretically, through the circuit implementation of this corresponding calculation model, the remainder obtained by dividing the first bit value by the predetermined divisor can be obtained within one clock cycle. Optionally, the predetermined divisor corresponds to the conversion value for converting the first bit value to a time unit. For example, to convert the first bit value, expressed in nanoseconds, to a time unit, the predetermined divisor is 10. 9 The remainder obtained is the remaining nanosecond information after time unit conversion. Those skilled in the art will readily understand that the first bit value can also be converted to other types of time units; for example, converting the first bit value represented in nanoseconds to milliseconds would result in a predetermined divisor of 10. 6 The remainder obtained is the remaining nanosecond information after time unit conversion.
[0047] After obtaining the quotient and remainder, at position 230, the device obtains a second bit value representing time based on the quotient and remainder. The second bit value includes a first part and a second part. The first part corresponds to the quotient and represents time in a second time unit, and the second part corresponds to the remainder and represents time in a first time unit. Optionally, if the predetermined divisor is a conversion value between the first and second time units, the obtained quotient is integer time information in the second time unit, and the obtained remainder is remaining time information in the first time unit. Combining the obtained quotient and remainder can form a standard time format required by the PTP system, such as a timestamp format conforming to the Institute of Electrical and Electronics Engineers (IEEE) 1558 protocol version 2 (IEEE 1588V2 standard time format). In some embodiments, the first time unit is nanoseconds, the second time unit is seconds, the first part of the second bit value corresponds to 48 bits of integer second information corresponding to the obtained quotient, and the second part of the second bit value corresponds to the remaining 32 bits of nanosecond information corresponding to the obtained remainder. Those skilled in the art will readily understand that the first time unit and / or the second time unit can also be other time measurement units such as picosecond, nanosecond, microsecond, millisecond, second, minute, etc.
[0048] The clock synchronization apparatus provided in one or more embodiments of this disclosure, implemented through circuitry of a corresponding computational model, ensures that the output is only related to the current input and independent of the output after processing in the previous one or more clock cycles. This process requires no pipeline operation and, without considering hardware logic resource consumption and clock frequency, can complete the output of the quotient and remainder within two consecutive clock cycles, thereby outputting time information in the required time format without waiting for processing results through multiple clock cycles. The converted addition or subtraction operations can reduce the number of addition or subtraction operations, reduce the consumption of hardware logic resources, and significantly reduce implementation latency. Therefore, the clock synchronization apparatus provided in one or more embodiments of this disclosure can still achieve a high maximum clock frequency F on low-performance and medium-performance devices. max This is to meet the requirement of cost reduction. At the same time, it is also suitable for high-speed, high-bandwidth application scenarios.
[0049] The following is nanosecond time information in 80-bit binary counter time format with the first bit value, and the pre-defined divisor is 10. 9 Some embodiments are illustrated by way of example.
[0050] The first bit value, which is represented in nanoseconds, is converted to a value in seconds. In some embodiments of this disclosure, the corresponding computational model converts binary division into binary multiplication. This optimization of conversion greatly improves the conversion performance in circuit implementation.
[0051] First, convert "S = X / Y" to "S = X * (1 / Y)", that is, convert binary division into multiplication. Determine the predetermined divisor (10... 9 The binary reciprocal of 1 / 2, that is, the binary reciprocal of 1 second, calculated in nanoseconds. That is:
[0052] 1 / y = 1 / 3b9aca00(Hex) = 1 / 10 9 (Dec)=0.0000000000000000000000000000010001001011100000101111101000001001101101011010010101(Bin)
[0053] Secondly, minimize the number of adders used in binary multiplication operations, taking advantage of the following computational properties of binary:
[0054] 2 -p +2 -(p+1) +…+2 -q =2 -(p-1) -2 -q
[0055] For example, the binary decimal 0.0 0 1 1 1 1 1 1 1 can be simplified from 6 addition operations to 1 subtraction operation. The simplified result is: 1 2 3 4 5 6 7 8 9
[0057] 0.0 0 1 1 1 1 1 1 1 = 2 -2 -2 -9
[0058] For the binary decimal: 0.0 1 1 1 1 0 1 1, the five addition operations can be simplified to two subtraction operations, resulting in: 1 2 3 4 5 6 7 8 9
[0060] 0.0 0 1 1 1 1 0 1 1 = 2 -2 -2 -9 -2 -7
[0061] Based on the above simplification method, in the calculation model, the predetermined divisor (10) is... 9The binary reciprocal of the above is divided into multiple segments, and the multiple addition operations corresponding to at least one of the segments are converted into fewer subtraction operations.
[0062] To reduce the number of calculations, we utilize the characteristics of binary calculation and combine the calculations as follows:
[0063]
[0064] Next, in the computational model, based on the subtraction operation corresponding to at least one segment and the addition operation corresponding to the remaining segments among multiple segments, the first group of addition or subtraction operations is determined, that is:
[0065] s_q = x / y = x*(1 / y)
[0066] =x*{2 -30 +2 -34 +[2 -36 -2 -41 -2 -38 ]+[2 -46 -2 -53 -2 -48 +2 -55 +2 -61 +(2 -63 -2 -68 -2 -66 ]+[2 -69 -2 -73 -2 -71 +2 -75 +2 -78 +2 -80 +2 -82}, where x is the first bit value, y is the predetermined divisor, and the obtained value s_q is the quotient.
[0067] As can be seen from the calculation formula above, the initial 24 addition operations of binary multiplication are simplified to 19 addition or subtraction operations. Furthermore, all logical operations are simplified to addition or subtraction operations involving data shifting, eliminating the iterative calculation process of output feedback to input. In addition, simplified bit manipulation can be performed in the actual implementation, further reducing the consumption of hardware logic resources.
[0068] The computational models provided in some embodiments of this disclosure eliminate the need to feed back the output results of the input iterative model into the circuit design, simplifying the pipeline design of the computational model and optimizing the timing characteristics of the implementation. Furthermore, by utilizing the characteristics of binary arithmetic, the number of additions used in multiplication is reduced, thus reducing the logic resource consumption caused by addition and improving the timing characteristics of the design to achieve a higher maximum clock frequency F. max This shortened the conversion delay.
[0069] The nanosecond time information is still in 80-bit binary counter time format with the first bit value, and the predetermined divisor is 10. 9 Some embodiments are illustrated by way of example.
[0070] The first bit value, represented in nanoseconds, is converted to a time unit of seconds, and the remaining nanosecond information is displayed in the time format. In some embodiments of this disclosure, firstly, a predetermined divisor (10^6) is determined. 9 The binary number of ).
[0071] 10 9 (Dec)=00 1110111 00 1 1 0 101100 1 0 1 000000000(Bin)
[0072] The predetermined divisor (10) 9 The binary number is divided into multiple segments. Multiple addition operations corresponding to at least one of these segments are converted into fewer subtraction operations. The binary segmentation and merging method is still used:
[0073]
[0074] Based on the subtraction operation corresponding to at least one segment and the addition operation corresponding to the remaining segments among multiple segments, determine the second set of addition or subtraction operations. For the quotient s_q obtained from the first set of addition or subtraction operations, the second set of addition or subtraction operations can be:
[0075] s_q*10 9
[0076] =s_q*{[2 30 -2 23 -2 26 +2 20 +2 19 +[2 18 -2 14 -2 16 +2 11 +2 9}
[0077] The original binary multiplication, which involved 13 addition operations, was simplified to 11 addition or subtraction operations.
[0078] In some embodiments of this disclosure, the remainder is calculated by subtracting the result of the second set of addition or subtraction operations performed on the quotient from the first bit value. That is, the remainder is calculated by subtracting the result of the second set of addition or subtraction operations, s_q*10, from the first bit value. 9 The remainder obtained by dividing the first bit value by a predetermined divisor is the remaining nanosecond information displayed in the time information. That is:
[0079] s_r = x - s_q * 10 9
[0080] In some embodiments of this disclosure, a call register stores the quotient or remainder, wherein the number of bits in the register is determined by the number of bits in a first bit value and the number of bits in the binary reciprocal of a predetermined divisor.
[0081] Let's assume the register `tick_tod_count` stores an 80-bit binary value A. Then, we set register `s` to `A000…0` (with the tail of A extended by 82 bits of binary '0'). The bit width of `s` is 80 + 82 = 162. Here, 80 bits represent the number of bits in the output of the binary time counter `tick_tod_count`, and 82 bits represent the predetermined divisor 10. 9 The number of bits in the binary representation of the value is used to set register x for shift operations.
[0082] After performing the first set of binary addition or subtraction operations, the high 48 bits of the obtained result 's' are denoted as s_q and stored in std_tod_count[79:32], which is to obtain the 48-bit second information in the IEEE1588V2 standard format.
[0083] After performing the second set of binary addition or subtraction operations, the lower 32 bits of the obtained result 's' are denoted as s_r and stored in std_tod_count[31:0], thus obtaining 32-bit nanosecond information in the IEEE1588V2 standard format.
[0084] As shown in the following formula:
[0085] Std_tod_count[79:32] = tick_tod_count / 32'h3b9aca00; / / Get the whole quotient.
[0086] Std_tod_count[31:0] = tick_tod_count % 32'h3b9aca00; / / Get the remainder.
[0087] In some embodiments of this disclosure, a first set of addition or subtraction operations are performed on the first bit value during a first plurality of clock cycles, or a second set of addition or subtraction operations are performed on the quotient during a second plurality of clock cycles.
[0088] In theory, the device for time format conversion and its corresponding calculation model provided in this disclosure can obtain the quotient within one clock cycle and the remainder within the next clock cycle. Considering hardware logic resource consumption and hardware performance, the calculation operation can be split into multiple clock cycles, thereby increasing the clock frequency. Figure 3 As shown, in some embodiments of this disclosure, the total delay for time format conversion is 5 clock cycles. Specifically, after 3 clock cycles, the converted second information is obtained, and after another 2 clock cycles, the converted nanosecond information is obtained.
[0089] The apparatus provided in one or more embodiments of this disclosure performs addition and subtraction operations on the input entirely through pipeline circuits to obtain the calculation result. The pipeline addition and subtraction operations in the core algorithm can be broken down into arbitrary pipeline stages according to the project application scenario and hardware device characteristics, which is particularly beneficial for optimizing the timing characteristics of digital logic implementation and adapting to application scenarios with different speeds / bandwidths.
[0090] Some embodiments of this disclosure were verified on Intel's Stratix 10 1ST085EN2F43I2LG device, which consumes 267 ALM logic cells and has low hardware logic resource consumption. Meanwhile, its maximum clock frequency F... max Reaching up to 270.64MHz, it meets the needs of high-bandwidth, high-capacity (low-switching-latency) applications and exhibits excellent timing characteristics. At the same time, it retains significant timing optimization margins to reduce the cost of low-performance devices (design timing can be further optimized by designing more pipeline stages).
[0091] In some embodiments of this disclosure, a second bit value is inserted into a message in a communication network based on IEEE 1588 protocol version 2, wherein, optionally, the message includes a synchronization message and the first bit value corresponds to the start time of sending the synchronization message, and / or the message includes a delayed response message and the first bit value corresponds to the start time of receiving the delayed response message.
[0092] Figure 4 As shown Figure 1 The diagram illustrates the clock information interaction in an example PTP communication system. At time t1, the master device 110 sends a Sync message to the slave device 120, carrying its own clock t1. At time t2, the slave device 120 receives the Sync message and adds its own clock t2. At time t3, the slave device 120 sends a Delay Request (Delay_Req) message to the master device 110, carrying its own clock t3. At time t4, the master device 110 receives the Delay Request message, adds its own clock t4, and sends a Delay Request Response (Delay_Resp) message to the slave device 120, carrying the clock t4. Through this two-message interaction process between the master and slave devices, the slave device's clock can be calibrated, thus achieving clock synchronization. Figure 4 In the described scenario, the situations requiring the output of IEEE 1588V2 standard format timestamps include at least the following:
[0093] a) At time t1, when the master device 110 sends a SYNC message to the slave device 120 (when sending the SYNC message to the output port of the PTP network), a timestamp in IEEE 1588 V2 standard format needs to be inserted into the SYNC message.
[0094] b) At time t4, when the master device 110 receives the Delay_Req (delay request) message from the slave device 120 and sends a Delay_Resp (delay request response) message to the slave device 120, it needs to insert a timestamp in IEEE 1588V2 standard format into the Delay_Resp message to respond to the delayed request reception time.
[0095] In some embodiments of this disclosure, the following is performed: Figure 2 The apparatus for the illustrated workflow includes a field-programmable gate array (FPGA).
[0096] In some embodiments of this disclosure, the device converts the timing information internal to the master device side into time information in the IEEE 1588V2 standard format and outputs a standard format timestamp. For example... Figure 5 As shown, the system's internal timing component 410, for example, includes a binary counter timer within a chip. The device 420, for example, includes hardware resources such as an FPGA or ASIC, and is used to convert the time information output by the timing component 410 into standard format time information, such as the IEEE 1588V2 standard time format. At time t1, the device 420 adds a timestamp to the Sync message; at time t4, the device 420 adds a timestamp upon receiving the Delay_Req message.
[0097] The technical advantages of this disclosure over conventional solutions are illustrated below by comparison with other time format conversion methods, not by limitation.
[0098] For solutions that use hardware programming languages to directly implement time format conversion. For example... Figure 6 As shown, this scheme is simple to implement, requiring only a two-clock-cycle delay to obtain the conversion result. However, when this scheme is mapped to a digital programmable logic chip, it consumes a significant amount of logic resources. For bit-width division operations, such as those verified on Intel's Stratix10 1ST085EN2F43I2LG device, it was found to consume 1106 ALM logic units, indicating very high logic resource consumption. Furthermore, even on such a high-performance FPGA device, its maximum clock frequency F... maxIt can only reach 19.49MHz, which is far from the 125MHz PTP processing clock used in basic applications.
[0099] For a processing scheme that uses hardware language programming and reduces the clock frequency, the original time counter in the high-frequency system clock domain can be transferred to the 20MHz low-frequency clock domain. Then, a direct division can be performed in the low-frequency clock domain using a hardware description language, and the result can be sent back to the high-frequency system clock domain. Figure 7 The functional simulation timing diagram for switching between a system clock of 125MHz and a low-frequency clock of 20MHz is shown. The design of this method is relatively simple and can achieve the expected maximum clock frequency F. max While this solution is intended to be a high-speed, high-bandwidth application, it consumes a lot of hardware logic resources and has excessive conversion latency, requiring approximately 33 clock cycles, which cannot meet the needs of new application scenarios.
[0100] For the circuit implementation scheme of binary fast division as the computational model (Binary Pipeline partitioning method), the basic principle of this method is as follows: Figure 8 As shown, the binary time counter tick_tod_count to be converted is used as the dividend, and the value of 1 second (10) is used as the dividend. 9 The divisor is a unit in nanoseconds. The quotient and remainder obtained by the pipelined algorithm are the second and nanosecond portions of the IEEE 1588V2 standard format time counter, respectively. That is, std_tod_count[79:32] = quotient; Std_tod_count[31:0] = remainder.
[0101] Figure 9 The functional simulation timing diagram of a time-transformation implementation method based on binary fast division is shown. This method consumes minimal hardware resources and can meet the application scenarios of current low-rate PTP message processing. However, this method is based on the current input and the result of the previous operation, obtained through shifting and subtraction. The current result needs to be used as feedback input for the next operation. This model is not suitable for logic pipeline implementation. To optimize timing, the maximum clock frequency F of this method on low-performance chips is limited. max Optimization is very limited, making it difficult to implement on low-cost, low-performance devices. Furthermore, this method has excessive conversion latency; computation, including processing overhead, requires approximately 34 clock cycles to complete one conversion. It is unsuitable for high-bandwidth, high-throughput data processing scenarios.
[0102] Figure 10A and Figure 10BThis illustrates the logical implementation differences between the computational model based on binary fast division and the computational model used in one or more embodiments of this disclosure. For example... Figure 10A As shown, the computational model based on binary fast division requires the output of the previous clock cycle (t-1) to iterate to the current clock cycle (t), serving as the input to the logic shift subtractor 910; as... Figure 10B As shown, the computational model used in the embodiments of this disclosure employs pipeline adders or subtractors 920 for computation, requiring no iterative processing, and the output result of the current clock cycle (t) is only related to the current input.
[0103] As can be seen, compared to schemes implemented directly in hardware, schemes involving frequency reduction, and schemes involving direct binary division, the time format conversion apparatus provided in some embodiments of this disclosure has a very short conversion latency, making it suitable for the latest network synchronization applications with high speed and high bandwidth. The novel feedback-free mode of embodiments of this disclosure can achieve a higher maximum clock frequency F. max The optimized design facilitates implementation on low-performance logic devices, reducing implementation costs. Embodiments of this disclosure can be implemented using pure hardware logic resources, eliminating the need for specific hardware like digital signal processors (DSPs). The design is simple, low-cost, and easily portable.
[0104] Table 1 below compares the clock cycle count, clock frequency, and hardware resource consumption of the embodiments of this disclosure with those of conventional solutions. As shown in Table 1:
[0105]
[0106] Table 1
[0107] In some example embodiments, an apparatus capable of performing process 200 may include components for performing the various steps of method 200. These components may be implemented in any suitable form. For example, the components may be implemented in a circuit or software module.
[0108] In some example embodiments, the apparatus includes: means for performing a first set of addition or subtraction operations on a first bit value to obtain a quotient obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time using a first time unit; means for performing a second set of addition or subtraction operations on the first bit value and the quotient to obtain a remainder obtained by dividing the first bit value by the predetermined divisor; and means for generating a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first portion and a second portion, the first portion corresponding to the quotient and representing time in a second time unit, and the second portion corresponding to the remainder and representing time in a first time unit.
[0109] In some example embodiments, the first set of addition or subtraction operations is determined based on: determining the binary reciprocal of a predetermined divisor; dividing the binary reciprocal of the predetermined divisor into multiple segments; converting multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and determining the first set of addition or subtraction operations based on the subtraction operations corresponding to at least one segment and the addition operations corresponding to the remaining segments of the multiple segments.
[0110] In some example embodiments, the second set of addition or subtraction operations is determined based on: determining the binary number of the predetermined divisor; dividing the binary number of the predetermined divisor into multiple segments; converting multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and determining the second set of addition or subtraction operations based on the subtraction operations corresponding to at least one segment and the addition operations corresponding to the remaining segments of the multiple segments.
[0111] In some example embodiments, the component for obtaining the remainder obtained by dividing the first bit value by a predetermined divisor includes: a component for subtracting the result obtained after performing a second set of addition or subtraction operations on the quotient from the first bit value to calculate the remainder.
[0112] In some example embodiments, at least one of the following is true: the first time unit is nanoseconds; the second time unit is seconds; the predetermined divisor is a conversion value between the first time unit and the second time unit; or the second bit value conforms to the timestamp format specified in IEEE 1558 protocol version 2.
[0113] In some example embodiments, the predetermined divisor is 109, the first group of addition or subtraction operations includes 19 addition or subtraction operations, and the second group of addition or subtraction operations includes 11 addition or subtraction operations.
[0114] In some example embodiments, the apparatus further includes: means for performing a first set of addition or subtraction operations on a first bit value during a first plurality of clock cycles; or means for performing a second set of addition or subtraction operations on a quotient during a second plurality of clock cycles.
[0115] In some example embodiments, the apparatus further includes a component for inserting a second bit value into a message in a communication network based on IEEE 1588 protocol version 2.
[0116] In some example embodiments, the message includes a synchronization message, and the first bit value corresponds to the start time of sending the synchronization message.
[0117] In some example embodiments, the message includes a delayed response message, and the first bit value corresponds to the start time of receiving the delayed response message.
[0118] In some example embodiments, the apparatus further includes: a component for calling a register to store at least one of a quotient or a remainder, wherein the number of bits in the register is determined by the number of bits of a first bit value and the number of bits of the binary reciprocal of a predetermined divisor.
[0119] In some example embodiments, the device includes a field-programmable gate array (FPGA).
[0120] In some example embodiments, the apparatus further includes components for performing other steps in some embodiments of method 200. In some embodiments, the components include at least one processor and at least one memory storing computer program code. The at least one memory and the computer program code are configured, together with the at least one processor, to cause execution of the apparatus.
[0121] Figure 11 This is a simplified block diagram of an electronic device 1100 suitable for implementing embodiments of the present disclosure. Device 1100 may be provided to implement apparatus according to some embodiments of the present disclosure. As shown, device 1100 includes one or more processors 1110, one or more memories 1120 coupled to processor 1110, and one or more communication modules 1140 coupled to processor 1110.
[0122] The communication module 1140 is used for bidirectional communication. For example, the communication module 1140 may include a transmitter, receiver, or transceiver used in embodiments of this disclosure. The communication interface may represent any interface necessary for communication with other network elements.
[0123] Processor 1110 can be any type suitable for a local technology network and can include, but is not limited to, one or more of a general-purpose computer, a special-purpose computer, a microcontroller, a digital signal processor (DSP), and a controller-based multi-core controller architecture. Device 1100 can have multiple processors, such as application-specific integrated circuit chips, which are time-subordinate to a clock synchronized with the main processor.
[0124] Memory 1120 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 1024, erasable programmable read-only memory (EPROM), flash memory, hard disk, optical disc (CD), digital video disc (DVD), and other magnetic and / or optical storage. Examples of volatile memories include, but are not limited to, random access memory (RAM) 1122 and other volatile memories that do not persist during power-off periods.
[0125] Computer program 1130 includes computer-executable instructions that are executed by associated processor 1110. Program 1130 may be stored in ROM 1120. Processor 1110 may perform any suitable actions and processes by loading program 1130 into RAM 1122.
[0126] The embodiments of this disclosure can be implemented by means of program 1130, enabling device 1100 to perform as described in the reference. Figure 2 Any process discussed in this disclosure. Embodiments of this disclosure may also be implemented by hardware or by a combination of software and hardware.
[0127] In some embodiments, program 1130 may be tangibly contained in a computer-readable medium, which may include in device 1100 (such as in memory 1120) or other storage device accessible by device 1100. Program 1130 may be loaded from the computer-readable medium into RAM 1122 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc.
[0128] Figure 12 An example of a computer-readable medium 1200 in the form of a CD or DVD is shown. A program 1130 is stored on the computer-readable medium.
[0129] Generally, the various embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software, which can be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of this disclosure are shown and described as block diagrams, flowcharts, or represented using some other illustration, it should be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as, as in the non-limiting examples, hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.
[0130] This disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer-executable instructions, such as instructions included in a program module, which execute in a device on a real or virtual processor of a target to perform the method 1000 as described above with reference to FIG. 10. Typically, a program module includes routines, programs, libraries, objects, classes, components, data structures, etc., that perform a specific task or implement a specific abstract data type. In various embodiments, the functionality of program modules can be combined or divided among program modules as needed. The machine-executable instructions for the program module can execute within a local or distributed device. In a distributed device, the program module can reside in both local and remote storage media.
[0131] Computer program code used to implement the methods of this disclosure may be written in one or more programming languages. This computer program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the computer or other programmable data processing apparatus, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be performed. The program code may be executed entirely on a computer, partially on a computer, as a stand-alone software package, partially on a computer and partially on a remote computer, or entirely on a remote computer or server.
[0132] In the context of this disclosure, computer program code or related data may be carried on any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and so on. Examples of signals may include electrical, optical, radio, sound, or other forms of propagation signals, such as carrier waves, infrared signals, etc.
[0133] A computer-readable medium can be any tangible medium that contains or stores a program for or relating to an instruction execution system, apparatus, or device. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. More detailed examples of computer-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical storage devices, magnetic storage devices, or any suitable combination thereof. As used herein, the terms “non-transient” or “non-signal” are a limitation on the medium itself (i.e., tangible, not signaling), and not a limitation on the persistence of data storage (e.g., RAM and ROM).
[0134] Furthermore, although the operation of the methods of this disclosure is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. It should also be noted that the features and functions of two or more devices according to this disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided and embodied by multiple devices.
[0135] While this disclosure has been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the specific embodiments disclosed. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
[0136] Furthermore, although the operation of the methods of this disclosure is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. It should also be noted that the features and functions of two or more devices according to this disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided and embodied by multiple devices.
[0137] While this disclosure has been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the specific embodiments disclosed. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. A device for clock synchronization, comprising: At least one processor; as well as At least one memory, the at least one memory storing instructions, the instructions, when executed by the at least one processor, causing the device to at least: Based on performing a first set of addition or subtraction operations on the first bit value, a quotient is obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value represents time in a first time unit; Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, the remainder obtained by dividing the first bit value by the predetermined divisor is obtained; and A second bit value representing time is obtained based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponding to the quotient and representing time in a second time unit, and the second part corresponding to the remainder and representing time in the first time unit.
2. The apparatus of claim 1, wherein the first set of addition or subtraction operations is determined based on the following: Determine the binary reciprocal of the predetermined divisor; Divide the binary reciprocal of the predetermined divisor into multiple segments; Convert multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and The first group of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operation corresponding to the remaining segments among the plurality of segments.
3. The apparatus according to claim 1 or 2, wherein the second set of addition or subtraction operations is determined based on the following: Determine the binary number of the predetermined divisor; Divide the binary number of the predetermined divisor into multiple segments; Convert multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and The second group of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operation corresponding to the remaining segments among the plurality of segments.
4. The apparatus according to claim 1 or 2, wherein the apparatus is configured to obtain the remainder by: The remainder is calculated by subtracting the result obtained after performing a second set of addition or subtraction operations on the quotient from the first bit value.
5. The apparatus according to claim 1 or 2, wherein at least one of the following is true: The first time unit is nanosecond; The second time unit is seconds; The predetermined divisor is a conversion value between the first time unit and the second time unit; or The second bit value conforms to the timestamp format specified in IEEE 1558 protocol version 2.
6. The apparatus according to claim 1 or 2, wherein the predetermined divisor is 10. 9 The first group of addition or subtraction operations includes 19 addition or subtraction operations, and the second group of addition or subtraction operations includes 11 addition or subtraction operations.
7. The apparatus according to claim 1 or 2, wherein the apparatus is further comprising at least one of the following: Within the first plurality of clock cycles, the first set of addition or subtraction operations is performed on the first bit value; or During the second plurality of clock cycles, the second set of addition or subtraction operations are performed on the quotient.
8. The apparatus according to claim 1 or 2, wherein the apparatus is further configured to: The second bit value is inserted into the message of a communication network based on IEEE 1588 protocol version 2.
9. The apparatus of claim 8, wherein the message includes a synchronization message, and the first bit value corresponds to the start time of sending the synchronization message.
10. The apparatus of claim 8, wherein the message includes a delayed response message, and the first bit value corresponds to the start time of receiving the delayed response message.
11. The apparatus according to claim 1 or 2, wherein the apparatus is further configured to: The register stores at least one of the quotient or the remainder, wherein the number of bits in the register is determined by the number of bits in the first bit value and the number of bits in the binary reciprocal of the predetermined divisor.
12. The apparatus of claim 1 or 2, wherein the apparatus comprises a field-programmable gate array (FPGA).
13. A method for clock synchronization, comprising: Based on performing a first set of addition or subtraction operations on the first bit value, a quotient is obtained by dividing the first bit value by a predetermined divisor, wherein the first bit value uses a first time unit to represent time; Based on the first bit value and performing a second set of addition or subtraction operations on the quotient, the remainder obtained by dividing the first bit value by the predetermined divisor is obtained; and A second bit value representing time is generated based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponding to the quotient and representing time in a second time unit, and the second part corresponding to the remainder and representing time in the first time unit.
14. The method of claim 13, wherein the first set of addition or subtraction operations is determined based on: Determine the binary reciprocal of the predetermined divisor; Divide the binary reciprocal of the predetermined divisor into multiple segments; Convert multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and The first group of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operation corresponding to the remaining segments among the plurality of segments.
15. The method of claim 13 or 14, wherein the second set of addition or subtraction operations is determined based on: Determine the binary number of the predetermined divisor; Divide the binary number of the predetermined divisor into multiple segments; Convert multiple addition operations corresponding to at least one of the multiple segments into fewer subtraction operations; and The second group of addition or subtraction operations is determined based on the subtraction operation corresponding to the at least one segment and the addition operation corresponding to the remaining segments among the plurality of segments.
16. The method of claim 13 or 14, wherein obtaining the remainder obtained by dividing the first bit value by the predetermined divisor further comprises: The remainder is calculated by subtracting the result obtained after performing a second set of addition or subtraction operations on the quotient from the first bit value.
17. The method according to claim 13 or 14, wherein at least one of the following: The first time unit is nanosecond; The second time unit is seconds; The predetermined divisor is a conversion value between the first time unit and the second time unit; or The second bit value conforms to the timestamp format specified in IEEE 1558 protocol version 2.
18. The method according to claim 13 or 14, wherein the predetermined divisor is 10. 9 The first group of addition or subtraction operations includes 19 addition or subtraction operations, and the second group of addition or subtraction operations includes 11 addition or subtraction operations.
19. The method according to claim 13 or 14, further comprising: Within the first plurality of clock cycles, the first set of addition or subtraction operations are performed on the first bit value; or During the second plurality of clock cycles, the second set of addition or subtraction operations are performed on the quotient.
20. The method according to claim 13 or 14, further comprising: The second bit value is inserted into the message of a communication network based on IEEE 1588 protocol version 2.
21. The method of claim 20, wherein the message includes a synchronization message, and the first bit value corresponds to the start time of sending the synchronization message.
22. The method of claim 20, wherein the message includes a delayed response message, and the first bit value corresponds to the start time of receiving the delayed response message.
23. The method according to claim 13 or 14, further comprising: The register stores at least one of the quotient or the remainder, wherein the number of bits in the register is determined by the number of bits in the first bit value and the number of bits in the binary reciprocal of the predetermined divisor.
24. The method of claim 13 or 14, wherein the method is performed by a field-programmable gate array (FPGA).
25. A device for clock synchronization, comprising: A component for obtaining a quotient by dividing the first bit value by a predetermined divisor based on performing a first set of addition or subtraction operations on the first bit value, wherein the first bit value uses a first time unit to represent time; A component for performing a second set of addition or subtraction operations on the first bit value and the quotient to obtain the remainder obtained by dividing the first bit value by the predetermined divisor; as well as The component is used to generate a second bit value representing time based on the quotient and the remainder, wherein the second bit value includes a first part and a second part, the first part corresponding to the quotient and representing time in a second time unit, and the second part corresponding to the remainder and representing time in the first time unit.
26. A computer-readable medium storing instructions that, when executed by at least one processing unit, cause the at least one processing unit to perform the method according to any one of claims 13-24.