Laser annealing method and method for manufacturing semiconductor devices using the same

Abstract

Disclosed are a laser annealing method and a method for manufacturing a semiconductor device to which the same is applied. The disclosed laser annealing method is a laser annealing method for a semiconductor device portion including a transistor, and includes the steps of: providing a semiconductor device portion comprising a transistor including a semiconductor and a dielectric that forms a junction interface with the semiconductor; and performing laser annealing by irradiating the semiconductor device portion with a laser under conditions of a gas atmosphere of at least one of deuterium (D2), hydrogen (H2), and ammonia (NH3) and a pressure higher than 1 atmosphere, for passivating at least the interfacial charge between the semiconductor and the dielectric.

Description

Technical Field

[0001] The present invention relates to an annealing method for a workpiece and a method for manufacturing an element to which the same is applied, and more particularly, to a laser annealing method and a method for manufacturing a semiconductor element to which the same is applied.

Background Art

[0002] A MOSFET (metal-oxide-semiconductor field effect transistor) is an element that adjusts the amount of current flowing between a source and a drain through a voltage applied to a gate, and has played a pivotal role in technological development while being generally used in the industry since its development in the 1960s. The MOSFET is used as a core element of an integrated circuit, and currently, most semiconductor devices produced in large quantities are manufactured based on the MOSFET. Along with the development of semiconductor technology, the integration degree and performance of unit transistor elements such as MOSFETs have been continuously improved. In addition, development of new (or modified) structure FET elements capable of overcoming problems and performance limitations due to high integration (i.e., scaling down) of existing MOSFETs has also been carried out.

[0003] When manufacturing a transistor element such as a MOSFET, a heat treatment process is used that can deactivate interface charges present at the interface between a gate dielectric layer and a semiconductor channel and reduce the density of effective interface charges. Through such a heat treatment process, the film quality of the gate dielectric layer can be improved, and as a result, the performance and reliability of the transistor can be improved.

[0004] However, existing heat treatment processes involve heating the substrate in a forming gas atmosphere, which requires relatively long processing times and presents problems in terms of efficient process execution. Furthermore, even if dangling bonds present at the interface between the gate dielectric layer and the semiconductor channel are deactivated by existing heat treatment processes, defects can reappear due to reactivation phenomena. Such problems can occur not only at the interface but also within the gate dielectric layer itself.

[0005] Therefore, in the manufacturing of transistor elements such as MOSFETs, there is a need to develop technologies that can overcome the existing problems and limitations mentioned above, efficiently improve transistor performance, and ensure stability. Furthermore, as the integration density of transistors increases significantly, and their shape, structure, and scale change or evolve, there is a need to develop technologies and processes to ensure performance and reliability. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The technical problem that this invention aims to solve is to provide a process technology (laser annealing method) that can efficiently passivate interface charges between a semiconductor and a dielectric in the manufacturing of semiconductor devices including transistors, and that can significantly improve the performance, stability, and reliability of the transistor.

[0007] Furthermore, the technical problem that the present invention aims to solve is to provide a method for manufacturing semiconductor devices using the above-mentioned process technology (laser annealing method).

[0008] The problems that this invention aims to solve are not limited to those mentioned above, and other problems not mentioned can be understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] According to one embodiment of the present invention, a laser annealing method for a semiconductor element including a transistor is provided, comprising the steps of: providing a semiconductor element including a transistor comprising a semiconductor and a dielectric that forms a junction interface with the semiconductor; and performing laser annealing by irradiating the semiconductor element with a laser under conditions of a gas atmosphere of at least one of deuterium (D2), hydrogen (H2), and ammonia (NH3) and a pressure higher than 1 atmosphere, for passivating at least the interfacial charge between the semiconductor and the dielectric.

[0010] The aforementioned pressure conditions may be approximately 100 atmospheres or less.

[0011] The aforementioned pressure conditions may be between approximately 1 atmosphere and approximately 100 atmospheres.

[0012] The transistor can be formed on a substrate. Furthermore, the laser annealing can be performed while the temperature of the substrate is adjusted to a range of room temperature to approximately 550°C.

[0013] The laser annealing can be performed while the temperature of the substrate is adjusted to a range of room temperature to approximately 550°C.

[0014] The aforementioned laser annealing can be performed in a deuterium (D2) gas atmosphere.

[0015] The laser annealing can be performed such that the temperature of the surface portion of the semiconductor element rises to approximately 600°C to 2000°C.

[0016] The laser annealing can be performed for approximately 0.01 μs to 10 seconds.

[0017] The semiconductor may include the channel of the transistor, and the dielectric may include the gate dielectric layer of the transistor.

[0018] The step of providing the semiconductor element portion may include the step of forming a wiring member electrically connected to the transistor, and the laser annealing can be performed before or after the step of forming the wiring member.

[0019] The laser may include any one of ultraviolet rays, visible rays, infrared rays, and microwaves.

[0020] According to another embodiment of the present invention, a method for manufacturing a semiconductor device to which the laser annealing method described above is applied is provided. [Effects of the Invention]

[0021] According to each embodiment of the present invention, a process technology (laser annealing method) can be realized that can efficiently passivate interfacial charges between a semiconductor and a dielectric in the manufacturing of semiconductor devices including transistors, and that can significantly improve the performance, stability, and reliability of the transistor. According to one embodiment, by performing a high-speed annealing process using laser irradiation in a gas atmosphere such as deuterium (D2), which has a high binding energy to semiconductor elements (e.g., silicon), under pressurized conditions higher than 1 atmosphere, an efficient passivation process to remove interfacial charges can be performed, thereby significantly improving the performance, stability, and reliability of the semiconductor device. Furthermore, the process technology (laser annealing method) according to the embodiments of the present invention can be usefully utilized in the manufacturing of highly integrated semiconductor devices.

[0022] By applying the laser annealing method according to each embodiment of the present invention, it is possible to manufacture semiconductor devices that have high integration density while possessing excellent performance, stability, and reliability.

[0023] However, the effects of the present invention are not limited to the effects described above and can be extended in various ways without departing from the technical idea and scope of the present invention.

Brief Description of the Drawings

[0024] [Figure 1a-1c] It is a cross-sectional view for explaining a laser annealing method for a semiconductor element portion including a transistor according to an embodiment of the present invention.

[0025] [Figure 2a-2b] It is a cross-sectional view for explaining a laser annealing method for a semiconductor element portion including a transistor according to another embodiment of the present invention.

[0026] [Figures 3a-3d] It is a cross-sectional view for explaining a laser annealing method for a semiconductor element portion including a transistor according to another embodiment of the present invention.

[0027] [Figure 4] It is a plan view exemplarily showing a form of a pattern that a plurality of nanodots constituting a heating layer described in FIGS. 3a and 3b may have.

Modes for Carrying Out the Invention

[0028] Hereinafter, each embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0029] Each embodiment of the present invention described below is provided to more clearly explain the present invention to those having ordinary knowledge in the technical field, and the scope of the present invention is not limited by the following embodiments, and the following embodiments can be deformed into various other forms.

[0030] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the invention. A singular term used herein may include multiple forms unless the context clearly indicates otherwise. Furthermore, the term “including” as used herein identifies the presence of the shapes, stages, figures, actions, members, elements, and / or groups thereof mentioned, and does not exclude the presence or addition of one or more other shapes, stages, figures, actions, members, elements, and / or groups thereof. Furthermore, the term “connected” as used herein is a concept that includes not only direct connection of each member, but also indirect connection through further interposition of other members between them.

[0031] Furthermore, when one component is described as being "on top of" another component in this specification, this includes not only cases where one component is in contact with another component, but also cases where there are other components between the two components. The terms "and / or" as used herein include any one or more of the listed items and all combinations thereof. In addition, terms of degree such as "about" and "substantially" as used herein are used to mean a range of numerical values ​​or degrees or close to them, taking into account inherent manufacturing and material tolerances, and are used to prevent infringers from unfairly exploiting disclosures that refer to precise or absolute numerical values ​​provided to facilitate understanding of this application.

[0032] The embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes and thicknesses of the regions and parts shown in the attached drawings may be exaggerated to some extent for clarity and ease of explanation. The same reference numerals throughout the detailed description refer to the same components.

[0033] Figures 1a to 1c are cross-sectional views illustrating a laser annealing method for a semiconductor element including a transistor according to one embodiment of the present invention.

[0034] Referring to Figure 1a, a laser annealing method according to one embodiment of the present invention may include a step of providing a semiconductor element portion equipped with a transistor. The transistor may include a semiconductor and a dielectric that forms a junction interface with the semiconductor.

[0035] In one example, the semiconductor may include or correspond to the channel portion 110 of the transistor. The dielectric may include or correspond to the gate dielectric layer 120 of the transistor. In a specific embodiment, the transistor may include a channel portion 110 made of a semiconductor material and a gate dielectric layer 120 joined to the channel portion 110. The gate dielectric layer 120 may be arranged on the channel portion 110, and the gate electrode 130 may be arranged on the gate dielectric layer 120. A source 140A may be provided that is electrically connected to or in contact with a first region (e.g., a first end) of the channel portion 110, and a drain 140B may be provided that is electrically connected to or in contact with a second region (e.g., a second end) of the channel portion 110. The channel portion 110 can be called a channel member or channel region. The source 140A can be called a source member or source region, and similarly, the drain 140B can be called a drain member or drain region.

[0036] For example, the transistor may be formed on a predetermined substrate 100. The channel 110, source 140A, and drain 140B may be defined or formed within the surface of the substrate 100. The channel 110 may be defined between source 140A and drain 140B. Source 140A and drain 140B may be regions doped (ion-implanted) with high concentrations of conductive impurities.

[0037] The substrate 100 may, in non-limiting examples, be an inter-group IV compound substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon (Si)-germanium (Ge) substrate, or a group III-V or II-VI compound substrate, and may be a semiconductor substrate having a multilayer structure such as SOI (silicon-on-insulator) to suppress body effects, or a semiconductor layer obtained by epitaxial growth. The substrate 100 may be provided with insulating regions such as shallow trench isolation (STI) to define the active region, and may have well regions having a suitable conductivity type to embody an NMOS (n-type metal-oxide-semiconductor) transistor or a PMOS (p-type metal-oxide-semiconductor) transistor.

[0038] The channel portion 110 may, as a non-limiting example, contain intergroup IV compounds such as silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge), or may contain group III-V or group II-VI compounds.

[0039] The gate dielectric layer 120 may include, for example, silicon oxide (e.g., SiO2), silicon oxynitride (e.g., SiON), or silicon nitride (e.g., Si3N4), or it may include a high-dielectric (high-k) material having a higher dielectric constant than silicon nitride. The gate dielectric layer 120 may also include a laminated structure consisting of two or more layers of different dielectric materials. Materials that can be used as gate dielectric (insulating) materials in general transistor elements can be applied to the material of the gate dielectric layer 120. The gate dielectric layer 120 may be referred to as a gate insulating layer.

[0040] The gate electrode 130 may be formed from a predetermined conductive material such as impurity-doped conductive polysilicon, a metal, or a metal compound, and may be adjusted to have an appropriate work function. Although not shown, sidewall insulating layers may be further formed on both side walls of the gate laminate including the gate dielectric layer 120 and the gate electrode 130.

[0041] The semiconductor element portion may further include an insulating layer 150 formed on the substrate 100 so as to cover the gate electrode 130. The insulating layer 150 may be formed so as to cover the source 140A and drain 140B and the gate electrode 130. The insulating layer 150 can be formed by depositing a predetermined insulating material layer and then performing a planarization process on its upper surface. The insulating layer 150 may include, as non-limiting examples, silicon oxide (e.g., SiO2), silicon oxynitride (e.g., SiON), or silicon nitride (e.g., Si3N4), or other insulating materials, and may be composed of one or more insulating materials. The insulating layer 150 may be referred to as an interlayer insulating film.

[0042] Referring to Figure 1b, the laser annealing method according to an embodiment of the present invention may include the step of performing laser annealing (i.e., laser heat treatment) by irradiating the semiconductor element with a laser L10 under conditions of a gas atmosphere of at least one of deuterium (D2), hydrogen (H2), and ammonia (NH3) and a pressure higher than 1 atmosphere. The laser annealing can be performed by arranging the semiconductor element in a predetermined chamber and irradiating the semiconductor element with a laser L10 while a pressure higher than 1 atmosphere is formed in the chamber with the gas atmosphere. The laser annealing may be for passivating at least the interfacial charge between the semiconductor and the dielectric. In this embodiment, the semiconductor may be a channel portion 110, and the dielectric may be a gate dielectric layer 120.

[0043] The gas used to create the above-described gas atmosphere may include elements for passivating at least the interfacial charge between the semiconductor and the dielectric, i.e., the interfacial charge between the channel portion 110 and the gate dielectric layer 120. For example, the laser annealing heat treatment process described above can cause the elements in the gas to form Si-D bonds or Si-H bonds at or around the junction interface between the channel portion 110 and the gate dielectric layer 120, thereby deactivating (i.e., passivating) the interfacial charge generated by dangling bonds, etc. At this time, not only the interfacial charge but also fixed charges present around the interface can be deactivated (passivated) by a principle similar to that described above. As a result, the interfacial properties between the channel portion 110 and the gate dielectric layer 120 and the physical properties of the gate dielectric layer 120 are improved, and consequently, the performance, stability, and reliability of the transistor element can be improved.

[0044] In particular, when deuterium is used in the aforementioned gas atmosphere, its bonding energy with semiconductors such as silicon is higher than that of hydrogen, which can further significantly improve the stability and reliability of the transistor element. For example, since more energy is required to break Si-D bonds than Si-H bonds, the use of deuterium may be even more effective when lowering the trap level at the junction interface and performing a passivation process. In this respect, it may be preferable to perform the laser annealing in a deuterium (D2) gas atmosphere. The laser annealing can be performed in a 100% deuterium (D2) gas atmosphere, or in a gas atmosphere containing about 10% or more, or about 40% or more, deuterium (D2). However, depending on the circumstances, other gases other than deuterium (D2) gas, such as hydrogen (H2) gas or ammonia (NH3) gas, can also be used for passivation.

[0045] The pressure formed in the chamber during the laser annealing described above can be greater than 1 atmosphere (760 Torr). For example, the pressure may be greater than 1 atmosphere, less than 100 atmospheres, or equal to 100 atmospheres. More preferably, the pressure may be between 3 atmospheres and 100 atmospheres, or between 3 atmospheres and 50 atmospheres. By creating relatively high pressure conditions during the laser annealing described above, the elements of the gas (passivation gas) can be better bonded with semiconductor elements such as silicon. That is, by using relatively high pressure conditions, the elements of the gas (passivation gas) can be better bonded with semiconductor elements such as silicon at the interface between the channel portion 110 and the gate dielectric layer 120 and in the surrounding region. In particular, if the gas contains deuterium, the bonding-promoting effect (bonding-promoting effect between elements) due to high pressure can be further improved. Also, if the pressure is about 3 atmospheres or higher, the bonding-promoting effect between elements can be improved.

[0046] The laser L10 used in the laser annealing may be a laser (laser beam) generated from, for example, a YAG (yttrium aluminum garnet) laser generator, a CO2 laser generator, a diode laser generator, or a fiber laser generator. The laser L10 may include any one of ultraviolet light, visible light, infrared light, and microwaves. The laser L10 may have a wavelength of, for example, about 0.02 μm to 11 μm.

[0047] In the laser annealing described above, the laser L10 can be irradiated onto the surface of the insulating layer 150 from above the semiconductor element. The laser annealing can be performed so that the temperature of the surface of the semiconductor element rises to approximately 600°C to 2000°C. Because the laser L10 is used, the temperature of the surface of the semiconductor element can be raised to a considerably high temperature in a short time, and the heat treatment process for passivation described above can be performed efficiently and easily. In particular, the process of deactivating interfacial charges and fixed charges can be performed efficiently and effectively in a short time by promoting elemental penetration and bonding under instantaneous heating and pressurizing conditions due to laser irradiation.

[0048] The laser annealing can be performed for, for example, about 0.01 μs to 10 seconds. More preferably, the laser annealing can be performed for about 0.1 μs to 1 second. However, the time range of the laser annealing is not limited to those described above and can be adjusted in various ways depending on the circumstances.

[0049] According to one embodiment of the present invention, the laser annealing can be performed with the temperature of the substrate 100 adjusted to a range of room temperature (for example, about 25°C) to about 550°C. More specifically, the laser annealing can be performed with the temperature of the substrate 100 adjusted to a range of room temperature to about 550°C or a range of about 350°C to 450°C. When the laser annealing is performed with the substrate 100 heated to a predetermined temperature, the passivation of the interfacial charge can be performed more efficiently. However, if the temperature of the substrate 100 is high, such as about 550°C or higher or about 450°C or higher, an unintended reaction may occur in the substrate 100 portion that degrades the characteristics of the transistor. Therefore, it is preferable that the heating temperature of the substrate 100 be about 550°C or lower or about 450°C or lower.

[0050] Referring to Figure 1c, a wiring member 200 can be formed on the insulating layer 150. The wiring member 200 may be a member electrically connected to the transistor. For example, the wiring member 200 may be formed to be electrically connected to the gate electrode 130. Here, one wiring member 200 is shown, but multiple wiring members may be formed. A wiring member electrically connected to the source 140A may be further provided, and a wiring member electrically connected to the drain 140B may be further provided. The wiring member 200 can be considered a component included in the transistor.

[0051] The wiring member 200 may contain at least one of metals and metal compounds. Therefore, the process of forming the wiring member 200 can be described as a type of metallization process. Common materials used in semiconductor processes, such as electrodes, contact layers, and wiring, can be applied to the wiring member 200. The wiring member 200 does not necessarily have to be in a line form, and its form can be diverse. The wiring member 200 can be described as a metallic member or metallic wiring containing metals or metal compounds.

[0052] In the embodiments shown in Figures 1a to 1c, the laser annealing process was described in which the laser annealing process is performed before the metallization process. However, according to other embodiments of the present invention, the laser annealing process can also be performed after the metallization process. Such other embodiments will be described with reference to Figures 2a and 2b.

[0053] Figures 2a and 2b are cross-sectional views illustrating a laser annealing method for a semiconductor device including a transistor according to another embodiment of the present invention.

[0054] Referring to Figure 2a, the laser annealing method according to an embodiment of the present invention may include a step of providing a semiconductor element portion equipped with a transistor. The semiconductor element portion in Figure 2a may include the transistor configuration described in Figure 1a. That is, the semiconductor element portion in Figure 2a may include a substrate 101, a channel portion 111, a gate dielectric layer 121, a gate electrode 131, a source 141A, a drain 141B, and an insulating layer 151. The substrate 101, channel portion 111, gate dielectric layer 121, gate electrode 131, source 141A, drain 141B, and insulating layer 151 may correspond to the substrate 100, channel portion 110, gate dielectric layer 120, gate electrode 130, source 140A, drain 140B, and insulating layer 150 in Figure 1a, respectively.

[0055] In this embodiment, a wiring member 201 can be formed on the insulating layer 151 by a metallization process before laser annealing. The wiring member 201 may be the same as or similar to the wiring member 200 described in Figure 1c.

[0056] Referring to Figure 2b, the laser annealing method according to this embodiment may include the step of performing laser annealing (i.e., laser heat treatment) by irradiating the semiconductor element with a laser L11 under conditions of a gas atmosphere of at least one of deuterium (D2), hydrogen (H2), and ammonia (NH3) and a pressure higher than 1 atmosphere. The laser annealing can be performed by arranging the semiconductor element in a predetermined chamber and irradiating the semiconductor element with a laser L11 while a pressure higher than 1 atmosphere is formed in the chamber with the gas atmosphere. The laser annealing may be for passivating at least the interfacial charge between the semiconductor and the dielectric. The semiconductor may be a channel portion 111, and the dielectric may be a gate dielectric layer 121.

[0057] The specific conditions, characteristics, and effects of the laser annealing described above may be similar to those described with reference to Figure 1b. The pressure conditions may be about 100 atmospheres or less. More preferably, the pressure conditions may be about 1 atmosphere above 100 atmospheres or less, or about 3 atmospheres above 100 atmospheres or less. It may be preferable to perform the laser annealing in a gas atmosphere containing deuterium (D2). The laser annealing can be performed so that the temperature of the surface of the semiconductor element rises to about 600°C to 2000°C. The laser annealing can be performed, for example, for about 0.01 μs to 10 seconds. The laser can include any one of ultraviolet light, visible light, infrared light, and microwaves. The laser annealing can be performed with the temperature of the substrate 101 adjusted to a range of room temperature to 550°C. For example, the laser annealing can be performed with the temperature of the substrate 101 adjusted to a range of room temperature to 550°C. For further details regarding the specific conditions, characteristics, and effects of the aforementioned laser annealing, please refer to the explanation in Figure 1b.

[0058] For example, in this embodiment, the temperature at which the surface of the semiconductor element is heated by the laser annealing may be lower than the temperature at which the surface of the semiconductor element is heated by the laser annealing in the embodiment of Figure 1b. When the laser annealing is performed with the wiring member 201 formed, the heating temperature of the surface can be adjusted so that the wiring member 201 is not damaged by the laser annealing. Furthermore, it may be preferable to form the wiring member 201 with a metal or metal compound having a relatively high melting point.

[0059] In the embodiment described with reference to Figures 2a and 2b, the laser annealing is performed with the wiring member 201 already formed, and passivation is performed on the interface charge between the channel portion 111 and the gate dielectric layer 121. Therefore, after the passivation, the interface region between the channel portion 111 and the gate dielectric layer 121 may not be affected by the process for forming the wiring member 201.

[0060] Figures 3a to 3d are cross-sectional views illustrating a laser annealing method for a semiconductor element including a transistor according to another embodiment of the present invention.

[0061] Referring to Figure 3a, the laser annealing method according to an embodiment of the present invention may include a step of providing a semiconductor element portion equipped with a transistor. The semiconductor element portion in Figure 3a may include the transistor configuration described in Figure 1a. That is, the semiconductor element portion in Figure 3a may include a substrate 102, a channel portion 112, a gate dielectric layer 122, a gate electrode 132, a source 142A, a drain 142B, and an insulating layer 152. The substrate 102, channel portion 112, gate dielectric layer 122, gate electrode 132, source 142A, drain 142B, and insulating layer 152 may correspond to the substrate 100, channel portion 110, gate dielectric layer 120, gate electrode 130, source 140A, drain 140B, and insulating layer 150 in Figure 1a, respectively.

[0062] In this embodiment, a heating layer 162 can be formed on the insulating layer 152 before laser annealing. The heating layer 162 may contain at least one of metals and metal compounds. For example, the heating layer 162 may contain at least one of TiN, Ti, TiSi, Ta, TaN, Co, CoSi, Ni, NiSi, Ru, W, WSi, Cu, Re, Mo, Nb, and Cr. While a thickness of approximately 30 Å to 4000 Å may be preferable for improving the function of the heating layer 162, this embodiment is not limited thereto, and the appropriate thickness of the heating layer 162 can be varied as needed. The heating layer 162 may have a relatively high absorptive rate for lasers and can transfer or confine heat to the insulating layer 152. In this regard, the heating layer 162 may be referred to as a "laser absorption layer (high absorption layer)" or a "heat transfer layer".

[0063] According to one embodiment, the heating layer 162 may have a nano-pattern structure or a nano-dot array structure. For example, the heating layer 162 may include a nano-dot array containing a plurality of nano-dots 12. The plurality of nano-dots 12 may be formed from metallic materials such as metals or metallic compounds. When the heating layer 162 has a nano-dot array structure, in the subsequent laser annealing step, the heating layer 162 can effectively absorb the laser and transfer heat while effectively allowing gas transmission. However, depending on the case, the heating layer 162 may not have a nano-dot array structure and may have a continuous layer structure. When the heating layer 162 has a continuous layer structure, the gas transmission characteristics can be adjusted by appropriately controlling its thickness.

[0064] Referring to Figure 3b, the laser annealing method according to this embodiment may include the step of performing laser annealing (i.e., laser heat treatment) by irradiating the semiconductor element with a laser L12 under conditions of a gas atmosphere of at least one of deuterium (D2), hydrogen (H2), and ammonia (NH3) and a pressure higher than 1 atmosphere. The laser annealing can be performed by arranging the semiconductor element in a predetermined chamber and irradiating the semiconductor element with a laser L12 while a pressure higher than 1 atmosphere is formed in the gas atmosphere within the chamber. The laser annealing may be for passivating at least the interfacial charge between the semiconductor and the dielectric. The semiconductor may be a channel portion 112, and the dielectric may be a gate dielectric layer 122.

[0065] The specific conditions, characteristics, and effects of the laser annealing described above may be the same as or similar to those described with reference to Figure 1b. The pressure conditions may be about 100 atmospheres or less. More preferably, the pressure conditions may be about 1 atmosphere above 100 atmospheres or less, or about 3 atmospheres above 100 atmospheres or less. It may be preferable to perform the laser annealing in a gas atmosphere containing deuterium (D2). The laser annealing can be performed so that the temperature of the surface of the semiconductor element rises to about 600°C to 2000°C. The laser annealing can be performed, for example, for about 0.01 μs to 10 seconds. The laser can include any one of ultraviolet light, visible light, infrared light, and microwaves. The laser annealing can be performed with the temperature of the substrate 102 adjusted to a range of room temperature to about 550°C. For example, the laser annealing can be performed with the temperature of the substrate 102 adjusted to a range of room temperature to about 550°C. For further details regarding the specific conditions, characteristics, and effects of the aforementioned laser annealing, please refer to the explanation in Figure 1b.

[0066] After the step shown in Figure 3b, the heating layer 162 can be removed. The result is shown in Figure 3c.

[0067] Referring to Figure 3d, the wiring member 202 can be formed on the insulating layer 152 by a metallization process. The wiring member 202 may be the same as or similar to the wiring member 200 described in Figure 1c.

[0068] Figure 4 is a plan view illustrating the possible patterns of the multiple nanodots 12 that constitute the heating layer 162 described in Figures 3a and 3b.

[0069] Referring to Figure 4, by appropriately controlling the dimensions of the multiple nanodots 12 and the spacing between them, the heating layer 162 containing them can have a discontinuous layer structure while easily absorbing thermal energy from the laser and effectively allowing gas penetration. In this regard, the diameter of the multiple nanodots 12 is approximately 5 nm to 10 3 It may be preferable that the distance be on the order of nm, and the spacing between multiple nanodots 12 is about 5 nm to 10 2 It is sometimes preferable that the size be on the order of nanometers. However, the appropriate diameter and spacing range of the multiple nanodots 12 may vary depending on the wavelength of the laser used, etc. Furthermore, the arrangement of the multiple nanodots 12 is not limited to that shown in Figure 4 and can be varied in many ways. In addition, the heating layer 162 can have various nanopattern shapes other than a nanodot array structure, and in some cases, it can have a continuous layer shape.

[0070] The "transistors" described in each of the embodiments above may have a MOSFET structure, but can also have a variety of other transistor structures. For example, the transistors can have a variety of transistor structures such as a GAA (gate-all-around) FET structure, a fin FET structure, a tunneling FET structure, a spin FET structure, and a recess transistor structure. Furthermore, the "transistors" described in each of the embodiments above may be transistors as general switching elements or driving elements, and may also be memory transistors depending on the circumstances. When the transistor is a memory transistor, for example, a tunnel insulating layer (dielectric layer), a charge storage layer (charge trap layer), and a blocking insulating layer may be sequentially arranged between the semiconductor channel and the gate electrode (control gate electrode). In this case, the laser annealing process may be a process to improve the performance, stability, and reliability of the element by passivating at least the interfacial charge between the semiconductor channel and the tunnel insulating layer (dielectric layer). The term transistor as used herein may be interpreted broadly.

[0071] According to embodiments of the present invention, a method for manufacturing a semiconductor element using the laser annealing method described above is provided. Here, the semiconductor element may be a memory element or a non-memory element. The semiconductor element can encompass a variety of electronic elements.

[0072] According to the embodiments of the present invention described above, a process technology (laser annealing method) can be realized that can efficiently passivate interfacial charges between semiconductors and dielectrics in the manufacturing of semiconductor devices including transistors, and that can significantly improve the performance, stability, and reliability of transistors. According to one embodiment, by performing a high-speed annealing process using laser irradiation in a gas atmosphere such as deuterium (D2), which has a high binding energy to semiconductor elements (e.g., silicon), under pressurized conditions higher than 1 atmosphere, the passivation process to remove interfacial charges can be efficiently performed, and the performance, stability, and reliability of semiconductor devices can be significantly improved. Furthermore, the process technology (laser annealing method) according to the embodiments of the present invention can be usefully utilized in the manufacturing of highly integrated semiconductor devices. By applying the laser annealing method according to each embodiment of the present invention, it is possible to manufacture semiconductor devices that have high integration density while possessing excellent performance, stability, and reliability.

[0073] This specification discloses preferred embodiments of the present invention, and specific terms are used, but these are merely general terms used to facilitate the explanation of the invention and to promote understanding of the invention, and are not intended to limit the scope of the invention. It will be obvious to a person with ordinary skill in the art to which the present invention pertains that various modifications based on the technical idea of ​​the present invention are also possible, in addition to the embodiments disclosed herein. A person with ordinary skill in the art will see that the laser annealing method and the method for manufacturing a semiconductor device to which the same is applied according to the embodiments described with reference to Figures 1a to 4 can be substituted, modified, and transformed in various ways without departing from the technical idea of ​​the present invention. Therefore, the scope of the invention should not be defined by the embodiments described herein, but by the technical idea described in the claims. [Industrial applicability]

[0074] Each embodiment of the present invention can be applied to an annealing method for a workpiece and to the manufacture of an element to which this method is applied. Each embodiment of the present invention can be applied to a laser annealing method and to the manufacture of a semiconductor element to which this method is applied.

Claims

1. A laser annealing method for semiconductor elements including transistors, A step of providing a semiconductor element portion comprising a semiconductor and a transistor including a dielectric that forms a junction interface with the semiconductor; and At least for passivating the interface charge between the semiconductor and the dielectric, and comprising deuterium (D ２ ), hydrogen (H ２ ) and ammonia (NH ３ A laser annealing method for a semiconductor element, comprising the step of performing laser annealing by irradiating the semiconductor element with a laser under conditions of at least one of the following gas atmospheres and a pressure higher than 1 atmosphere.

2. The laser annealing method for a semiconductor element according to claim 1, wherein the pressure condition is 100 atmospheres or less.

3. The laser annealing method for a semiconductor element portion according to claim 1, wherein the pressure condition is greater than 1 atmosphere and less than or equal to 100 atmospheres.

4. The transistor is formed on a substrate, The laser annealing method for a semiconductor element portion according to claim 1, wherein the laser annealing is performed while the temperature of the substrate is adjusted to a range of room temperature to 550°C.

5. The aforementioned laser annealing uses deuterium (D ２ A laser annealing method for a semiconductor element portion according to claim 1, performed in a gas atmosphere.

6. The laser annealing method for a semiconductor element according to claim 1, wherein the laser annealing is performed such that the temperature of the surface portion of the semiconductor element portion is raised to 600°C to 2000°C.

7. The laser annealing method for a semiconductor element portion according to claim 1, wherein the laser annealing is performed for 0.01 μs to 10 seconds.

8. The semiconductor includes the channel of the transistor, The laser annealing method for a semiconductor element portion according to claim 1, wherein the dielectric includes the gate dielectric layer of the transistor.

9. The step of providing the semiconductor element portion includes the step of forming a wiring member electrically connected to the transistor, The laser annealing method for a semiconductor element portion according to claim 1, wherein the laser annealing is performed before or after the step of forming the wiring member.

10. The laser annealing method for a semiconductor element according to claim 1, wherein the laser includes one of ultraviolet light, visible light, infrared light, and microwaves.

11. A method for manufacturing a semiconductor device using the laser annealing method described in any one of claims 1 to 10.

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