Dual-gate structure for memory devices

Abstract

A memory device comprising at least one transistor having a dual-gate structure including a first gate metal and a second gate metal, wherein the first gate metal has a work function less than 4.55 eV and the second gate metal has a work function greater than 4.55 eV. A method for forming the memory device is also provided.

Claims

1. A memory device, The present invention comprises at least one transistor having a dual gate structure including a first gate metal and a second gate metal, wherein the first gate metal has a first work function and the second gate metal has a second work function that is higher than the first work function. Memory device.

2. The memory device according to claim 1, wherein the first work function is less than 4.55 eV and the second work function is greater than 4.55 eV.

3. The memory device according to claim 1, wherein the first gate metal comprises at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), titanium (Ti), or N+ polysilicon, and the second gate metal comprises at least one of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), or molybdenum (Mo).

4. The memory device according to claim 1, further comprising a bit line in contact with or near the second gate metal, and a storage node in contact with or near the first gate metal.

5. The memory device according to claim 1, wherein the first gate metal and the second gate metal are arranged on a spacer, the first gate metal extending over about 50% of the spacer, and the second gate metal extending over the remaining area of ​​the spacer.

6. The memory device according to claim 5, wherein the first gate metal and the second gate metal do not overlap.

7. The memory device according to claim 5, wherein the first gate metal and the second gate metal overlap by about 10% to about 20%.

8. The memory device according to claim 5, further comprising channels on each side of the spacer, wherein the channels have a thickness of about 5 nm to about 40 nm.

9. The memory device according to claim 1, wherein the memory device is a dynamic random access memory (DRAM).

10. A scaffold containing multiple interlayers of silicon (Si) and silicon germanium (SiGe), At least one nitride layer and The memory device according to claim 1, further comprising:

11. A method for manufacturing a memory device, Forming a first gate on a first portion of a gate oxide using a first metal, wherein the first metal has a work function less than 4.55 eV. Forming a second gate on a second portion of the gate oxide using a second metal, wherein the second metal has a work function greater than 4.55 eV. Methods that include...

12. The method according to claim 11, wherein the first metal comprises at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), titanium (Ti), or N+ polysilicon.

13. The method according to claim 11, wherein the second metal comprises at least one of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), or molybdenum (Mo).

14. The method according to claim 11, further comprising forming a bit line in contact with or near the second metal, and forming a storage node in contact with or near the first metal.

15. The method according to claim 11, further comprising forming the first gate and the second gate on a spacer.

16. The method according to claim 15, wherein the first gate extends over approximately 50% of the spacer, and the second gate extends over the remaining area of ​​the spacer.

17. The method according to claim 15, further comprising forming channels on each side of the spacer.

18. The method according to claim 17, wherein the channel has a thickness of about 5 nm to about 40 nm.

19. The method according to claim 11, wherein the memory device is a DRAM.

20. The method according to claim 11, wherein the gate oxide includes a dielectric layer.

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