Focus ring and semiconductor process chamber
The focus ring with an annular boss and positioning blocks addresses the issue of uneven etching rates by positioning the wafer away from the edge, enhancing uniformity and plasma distribution while being cost-effective.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
- Filing Date
- 2024-07-05
- Publication Date
- 2026-06-26
Smart Images
Figure 2026521188000001_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor manufacturing equipment, and specifically, to a focus ring and a semiconductor process chamber.
Background Art
[0002] Plasma etching realizes etching by ionizing a reaction gas through high-frequency glow discharge to generate plasma, and the plasma chemically reacts with the material at the site to be etched on the wafer to form volatile reactants. In the etching process, usually, by arranging a focus ring around the wafer, the plasma distribution across the entire wafer can be made more uniform. With the development of semiconductor devices towards smaller sizes, the number of transistors at the edge of the wafer gradually increases, and it becomes very important to ensure the uniformity of the etching rate from the center to the edge of the wafer.
[0003] FIG. 1 is a schematic configuration diagram of an assembly when a conventional focus ring is applied to a semiconductor process chamber. A chuck 10a is provided in the semiconductor process chamber, a focus ring 20a is fitted outside the chuck 10a, and during the process, a wafer 101a is fixed to the chuck 10a, and the inclined inner wall structure of the focus ring 20a guides the plasma to the wafer 101a to achieve the purpose of improving the uniformity of the etching rate at the edge of the wafer 101a. However, in the actual process, the semiconductor process chamber with this structure has a low uniformity of the etching rate at the edge of the wafer 101a during etching, that is, the effect of improving the uniformity of the etching rate at the edge is low, and thus the problem that the surface etching rate of the entire wafer 101a becomes non-uniform easily occurs.
Summary of the Invention
Problems to be Solved by the Invention
[0004] In response to the above technical challenges, this application provides a focus ring and a semiconductor process chamber that can improve upon the problem that arises when using conventional focus rings, where the uniformity of the etching rate at the wafer edges is low, resulting in an uneven surface etching rate across the entire wafer. [Means for solving the problem]
[0005] To solve the above technical problems, in the first embodiment, the focus ring according to the embodiment of the present application includes a ring body including a first inner annular surface and a first outer annular surface provided opposite to each other, and a first top surface and a bottom surface connecting the first inner annular surface and the first outer annular surface on the upper and lower sides, respectively; an annular boss provided on the first top surface and provided coaxially with the ring body, including a second inner annular surface and a second outer annular surface, and a second top surface connecting the second inner annular surface and the second outer annular surface at the top, wherein the radius of the second inner annular surface is greater than the radius of the first inner annular surface; and at least three positioning blocks provided on the first top surface, wherein at least three positioning blocks form positioning circles concentric with the ring body inside the at least three positioning blocks to position the wafer, wherein the radius of the positioning circle is greater than the radius of the first inner annular surface and smaller than the radius of the second inner annular surface.
[0006] In some embodiments, the difference between the radius of the second inner annular surface and the radius of the first inner annular surface is 10 mm or more.
[0007] In some embodiments, the positioning blocks are uniformly distributed along the circumferential direction of the positioning circle.
[0008] In some embodiments, the second apex is a horizontal plane connected to the second outer annular surface, The system includes a first inclined plane connected between the horizontal plane and the second inner annular plane.
[0009] In some embodiments, the focus ring is made of a ceramic material.
[0010] In some embodiments, the positioning block includes a third top surface, a positioning surface facing the center of the positioning circle, and a transition surface connecting the third top surface and the positioning surface.
[0011] In some embodiments, the transition surface includes a second bevel, a first chamfer connecting the second bevel and the third apex, and a second chamfer connecting the second bevel and the positioning surface.
[0012] In some embodiments, the angle between the second slope and the first apex is 65° or less and 25° or more.
[0013] In a second embodiment, the semiconductor process chamber according to the embodiment of the present application includes a chuck and the focus ring described in each of the above embodiments, wherein the chuck includes a chuck body and a columnar boss provided on the top surface of the chuck body for placing a wafer, the ring body is fitted to the outside of the columnar boss and supported on the top surface of the chuck body, and the first top surface is lower than the top surface of the columnar boss.
[0014] In some embodiments, the distance between the first top surface and the top surface of the columnar boss is 0.5 mm or less.
[0015] In some embodiments, the difference between the radius of the first inner annular surface and the radius of the columnar boss is greater than 0 and less than or equal to 0.5 mm. [Effects of the Invention]
[0016] As described above, the focus ring according to the embodiment of the present application includes a ring body, an annular boss, and at least three positioning blocks, the positioning blocks being located in a positioning circle concentric with the ring body, the positioning circle positioning the wafer, and the positioning blocks being positioned such that the second inner annular surface of the annular boss is away from the wafer edge, thereby reducing the influence of the focus ring's edge on the etching rate of the wafer edge. Furthermore, in the embodiment of the present application, the positioning blocks and the wafer are in point contact, which effectively reduces the influence of the focus ring on the etching rate of the wafer edge and improves the uniformity of the etching rate of the entire wafer. [Brief explanation of the drawing]
[0017] Herein, the drawings are incorporated into the specification and constitute part of this specification, illustrating embodiments conforming to the present application and are used together with the specification to interpret the principles of the present application. In order to more clearly explain the technical means of the embodiments of the present application, the drawings necessary for describing the embodiments are briefly described below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative work.
[0018] [Figure 1] This is a schematic diagram of the assembly when a conventional focus ring is applied to a semiconductor process chamber. [Figure 2] This is a schematic diagram of a part of another focus ring in related technology. [Figure 3] This is a schematic perspective view of a focus ring according to an embodiment of the present invention. [Figure 4] Figure 3 is a schematic front view of the focus ring. [Figure 5] This is a schematic cross-sectional view along line AA in Figure 3. [Figure 6] This is a schematic enlarged view of a part of the focus ring according to an embodiment of the present invention. [Figure 7] This is a schematic diagram of a semiconductor process chamber according to an embodiment of the present invention.
[0019] The achievement of the object of the present application, functional features, and advantages will be further described in combination with embodiments while referring to the drawings. Although clear embodiments of the present application are shown in the above drawings, they will be described in more detail below. These drawings and the written description do not limit the scope of the concept of the present application in any way, but explain the concept of the present application to those skilled in the art while referring to specific embodiments.
Embodiments for Carrying out the Invention
[0020] Hereinafter, exemplary embodiments will be described in detail, and examples thereof will be shown in the drawings. When the following description relates to the drawings, unless otherwise stated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that conform to the present application. On the contrary, they are merely examples of devices and methods that conform to some aspects of the present application described in detail in the appended claims.
[0021] In this specification, the terms "comprising", "containing", or any variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device containing a series of elements includes not only those elements but also other elements not expressly listed, or further includes the specific elements of such a process, method, article, or device. Without further limitation, the element limited by the phrase "comprising one..." does not exclude the further inclusion of other same elements in the process, method, article, or device containing the element. Also, members, features, and elements having the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by the interpretation in the specific embodiment or further combined with the context in the specific embodiment.
[0022] The terms "comprise", "comprising" are to be understood as indicating the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but not precluding the presence, occurrence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. Terms such as "or", "and / or", "including at least one of the following" used in this application are to be construed inclusively or as meaning any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A, B, C, A and B, A and C, B and C, A and B and C", and further for example, "A, B or C" or "A, B and / or C" means "any one of the following: A, B, C, A and B, A and C, B and C, A and B and C". An exception to this definition occurs only when combinations of elements, functions, steps or operations are inherently mutually exclusive in a specific way.
[0023] In this specification, various information is described using terms such as first, second, third, etc., but it should be understood that this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may be referred to as the second information, and similarly, the second information may be referred to as the first information. Depending on the context, the singular forms "a", "one" and "the" used in this specification are intended to include the plural form as well, unless the context indicates the contrary.
[0024] The orientation or positional relationship indicated by terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description and simplifying the description of this application, and is not to be construed as indicating or suggesting that the indicated device must have a specific orientation and be configured and operated in a specific orientation, and should not be understood as limiting this application.
[0025] For the sake of clarity, in each of the following embodiments, the orthogonal space formed by the horizontal and vertical directions is used as an example, and this premise should not be understood as limiting the present invention.
[0026] The method for calculating the uniformity of the etching rate of a wafer is: Uniformity of etching rate of wafer = (Maximum rate - Minimum rate) / (2 × Average rate). The inventor's research has shown that in conventional semiconductor process chambers, the uniformity of the etching rate at the edges of wafer 101a is low during etching, and the etching rate across the entire surface of wafer 101a tends to be uneven. This problem is mainly caused by the fact that the edges of the entire inner ring of the focus ring 20a are too close to the edges of wafer 101a, thus reducing the etching rate at the edges of wafer 101a.
[0027] To improve upon the above problem, as shown in Figure 2, Figure 2 is a schematic diagram of a part of another focus ring in the related technology, the focus ring 20b comprising a first part 21b made of a silicon-containing material and surrounding the wafer, and a second part 22b made of a yttrium-containing material and surrounding the outside of the first part 21b, the first part 21b and the second part 22b being connected by a third part 23b, the top surfaces 21b1 of the first part 21b and the top surfaces 22b1 of the second part 22b both being parallel to the horizontal plane, the top surface 21b1 of the first part 21b being lower than the top surface 22b1 of the second part 22b, the top surfaces 21b1 of the first part 21b and the top surfaces 22b1 of the second part 22b being connected by a transition slope 23b1 at the top of the third part 23b, the transition slope 23b1 being provided with a SiC coating 24b. The improvement means enhances the uniformity of the etching rate at the wafer edge by using different materials at different radial positions on the top of the focus ring 20b. However, this structure is manufactured by combining multiple materials, has a certain degree of difficulty in processing, is costly, does not have a positioning function for the wafer, and any misalignment of the wafer will affect the overall uniformity of the etching rate to some extent.
[0028] Based on this, the present application provides a focus ring and a semiconductor process chamber.
[0029] As shown in Figures 3 to 5, Figure 3 is a schematic perspective view of a focus ring according to an embodiment of the present application, Figure 4 is a schematic front view of the focus ring of Figure 3, and Figure 5 is a schematic cross-sectional view along line AA of Figure 3, wherein the focus ring 200 includes a ring body 10, an annular boss 20, and at least three positioning blocks 30.
[0030] As shown in Figure 5, the ring body 10 includes a first inner annular surface 11 and a first outer annular surface 12 that are provided opposite each other, and a first top surface 13 and a bottom surface 14 that connect the first inner annular surface 11 and the first outer annular surface 12 on the upper and lower sides, respectively. The annular boss 20 is provided on the first top surface 13 and is provided coaxially with the ring body 10, and includes a second inner annular surface 21 and a second outer annular surface 22, and a second top surface 23 that connects the second inner annular surface 21 and the second outer annular surface 22 at the top, with the radius of the second inner annular surface 21 being larger than the radius of the first inner annular surface 11. The ring body 10 and the annular boss 20 may be integrally molded structures, and for example, the entire focus ring 200 may be made of ceramic material and integrally sintered, but the material used for the focus ring 200 is not limited to this. Some examples of ceramic materials include Al2O3 ceramic, quartz, etc. The second inner annular surface 21 of the annular boss 20 extends outward relative to the first inner annular surface 11 of the ring body 10, thereby forming a stepped surface on the inner surface of the focus ring 200. The second outer annular surface 22 of the annular boss 20 and the first outer annular surface 12 of the ring body 10 may or may not be flush. Furthermore, the second outer annular surface 22 of the annular boss 20, the second top surface 23, the bottom surface 14 of the ring body 10, and the first outer annular surface 12 may be irregular planes such as flat surfaces, sloped surfaces, or stepped surfaces, and are not particularly limited in the embodiment of this application.
[0031] As shown in Figures 4 and 5, at least three positioning blocks 30 (12 are provided in the figures) are all provided on the first top surface 13 of the ring body 10, and a positioning circle C concentric with the ring body 10 is formed inside the at least three positioning blocks 30, and this inside is the side where the three positioning blocks 30 are close to the center of the ring body 10. The radius of the positioning circle C is greater than the radius of the first inner annular surface 11 and less than the radius of the second inner annular surface 21. Since the positioning circle C is for positioning the wafer, the radius of the positioning circle C only needs to be slightly larger than the radius of the wafer. In some embodiments, the ends of at least three positioning blocks 30 that are close to the center of the ring body 10 are connected in order to form a polygon, the center of the positioning circle C is located inside the polygon, and the positioning circle C is, for example, the circumscribed circle of the polygon. For example, if only three positioning blocks 30 are provided, the three vertex angles of the triangle formed by sequentially connecting the ends of the three positioning blocks 30 closest to the center of the ring body 10 are all acute angles, allowing the center of the positioning circle C to be located inside the triangle. This avoids the problem of the three positioning blocks 30 being too close together, making it impossible to position the wafer from three directions. Similarly, if four positioning blocks 30 are provided, the center of the positioning circle C can be located inside the rectangle formed by sequentially connecting the ends of the four positioning blocks 30 closest to the center of the ring body 10. Preferably, all positioning blocks 30 are uniformly distributed along the circumferential direction of the positioning circle C.
[0032] In conventional designs, as shown in Figure 1, the focus ring and wafer are in surface contact. The etching rate of the wafer edge is not only greatly affected by the focus ring, but because the focus ring is positioned very close to the wafer and is relatively too high, vortices tend to form above the wafer edge, and it is difficult for plasma to enter the gap between the focus ring and the wafer. Due to these two factors, the etching rate of the wafer edge is significantly reduced. In this embodiment, the focus ring 200 is positioned by forming a positioning circle C using a positioning block 30, and by positioning the wafer inside the positioning block 30, the second inner annular surface 21 of the annular boss 20 is separated from the wafer edge, thereby reducing the influence of the focus ring 200 edge on the etching rate of the wafer edge. Furthermore, in this embodiment, the positioning block 30 and the wafer are in point contact, which also effectively reduces the influence of the focus ring 200 on the etching rate of the wafer edge and improves the uniformity of the etching rate of the entire wafer. Furthermore, this embodiment improves the structure of the focus ring 200. The focus ring 200 can be made from the same material, for example, Al2O3 or a ceramic material such as quartz. Compared to the improved method in Figure 2, the manufacturing process of the focus ring 200 in this embodiment is more mature and less expensive.
[0033] In one embodiment, the difference between the radius of the second inner annular surface 21 of the annular boss 20 and the radius of the first inner annular surface 11 of the ring body 10 is 10 mm or more. In other words, the second inner annular surface 21 extends outward by 10 mm or more than the first inner annular surface 11. By comparing the results of electric field simulations and process results of different sizes, it is possible to effectively reduce the influence of the edge of the focus ring 200 on the etching rate of the wafer edge under these conditions, thereby having a high effect in improving the uniformity of the etching rate of the wafer edge.
[0034] In one embodiment, as shown in Figure 5, the second top surface 23 of the annular boss 20 may include a horizontal surface 231 and a first bevel surface 232. The horizontal surface 231 is connected to the second outer annular surface 22, and the first bevel surface 232 is connected between the horizontal surface 231 and the second inner annular surface 21. The first bevel surface 232 may be transitionally connected to the horizontal surface 231 and the second inner annular surface 21 by a rounded chamfer. In this embodiment, the first bevel surface 232, as a transition surface between the horizontal surface 231 and the second inner annular surface 21, can effectively adjust the electric field, control the plasma distribution, and improve the uniformity of the plasma distributed at the wafer edge, thereby improving the uniformity of the edge etching rate.
[0035] In one embodiment, as shown in Figure 6, Figure 6 is a schematic enlarged view of a part of the focus ring according to an embodiment of the present application. The positioning block 30 may include a third top surface 31, a positioning surface 32, and a transition surface 33. The positioning surface 32 faces the center of the positioning circle C and may be a vertical surface. The transition surface 33 connects the third top surface 31 and the positioning surface 32 and may be an inclined surface. The transition surface 33 can fine-tune the position of the wafer, for example, if the wafer deviates from the center of the positioning circle C when it falls, it can slide down along the transition surface 33 into the region where the positioning circle C is located.
[0036] In one embodiment, the transition surface 33 may include a second bevel 331, a first chamfer 332, and a second chamfer 333. The first chamfer 332 connects the second bevel 331 to the third top surface 31, and the second chamfer 333 connects the second bevel 331 to the positioning surface 32. That is, the second bevel 331 may be transitionally connected to the third top surface 31 via the first chamfer 332, or transitionally connected to the positioning surface 32 via the second chamfer 333, thereby preventing the wafer from being damaged by sharp corners while falling. For example, the angle between the second bevel 331 and the first top surface 13 may be 65° or less and 25° or more to ensure that the wafer slides gently into the positioning circle C if it is deviated from the center of the positioning circle C.
[0037] Embodiments of the present application further provide a semiconductor process chamber, as shown in Figure 7, which is a schematic diagram of a semiconductor process chamber according to an embodiment of the present application, and the semiconductor process chamber includes a chuck 100 and a focus ring 200 as described in each of the above embodiments. Here, the chamber body of the semiconductor process chamber is not shown.
[0038] The chuck 100 includes a chuck body 110 and a columnar boss 120 provided on the top surface of the chuck body 110 for supporting the wafer 101. The ring body 10 of the focus ring 200 is fitted outside the columnar boss 120 and supported on the top surface of the chuck body 110, with the first top surface 13 of the ring body 10 being lower than the top surface of the columnar boss 120, specifically, the diameter of the wafer 101 being greater than the diameter of the columnar boss 120, and the edge portion of the wafer 101 extending beyond the columnar boss 120 and floating above the first top surface 13 of the ring body 10. Positioning circles C formed inside at least three positioning blocks 30 of the focus ring 200 position the wafer 101.
[0039] For example, the distance between the first top surface 13 of the ring body 10 of the focus ring 200 and the top surface of the columnar boss 120 is 0.5 mm or less. That is, the height of the top surface of the columnar boss 120 higher than the first top surface 13 of the ring body 10 does not exceed 0.5 mm. This ensures that the edge portion of the wafer 101 floats above the ring body 10, preventing the gap between them from becoming too large, thus avoiding affecting the plasma density at the edge of the wafer 101 and preventing a decrease in the etching rate of the edge region of the wafer 101.
[0040] To facilitate the installation and fitting accuracy of the ring body 10 and the columnar boss 120, as an example, the difference between the radius of the first inner annular surface 11 of the ring body 10 and the radius of the columnar boss 120 is greater than 0 and 0.5 mm or less, so that the two are fitted together with a gap of 0.5 mm or less.
[0041] Other operating principles of the semiconductor process chamber in this embodiment will not be described in detail here, as they should be referred to in the description of the focus ring in the embodiment of this application described above.
[0042] The focus ring and semiconductor process chamber relating to this application have been described in detail above, and the principles and embodiments of this application have been explained using specific examples. In this application, emphasis has been placed on each example, and for parts that are not described in detail in one example, the relevant descriptions in other examples can be referenced.
[0043] The technical features of the technical means of this application can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments will be described. However, as long as there is no contradiction in these combinations of technical features, they should all be considered to fall within the scope described in this application.
Claims
1. A ring body including a first inner annular surface and a first outer annular surface provided opposite each other, and a first top surface and a bottom surface connecting the first inner annular surface and the first outer annular surface on both the upper and lower sides, An annular boss provided on the first top surface and coaxial with the ring body, comprising a second inner annular surface and a second outer annular surface, and a second top surface connecting the second inner annular surface and the second outer annular surface at an upper position, wherein the radius of the second inner annular surface is greater than the radius of the first inner annular surface, A focus ring characterized by comprising at least three positioning blocks provided on the first top surface, wherein at least three positioning blocks form positioning circles concentric with the ring body inside the at least three positioning blocks to position the wafer, and the radius of the positioning circles is greater than the radius of the first inner annular surface and smaller than the radius of the second inner annular surface.
2. The focus ring according to claim 1, characterized in that the difference between the radius of the second inner annular surface and the radius of the first inner annular surface is 10 mm or more.
3. The focus ring according to claim 1, characterized in that the positioning blocks are uniformly distributed along the circumferential direction of the positioning circle.
4. The second vertex is, A horizontal plane connected to the second outer annular surface, The focus ring according to claim 1, further comprising a first inclined surface connected between the horizontal surface and the second inner annular surface.
5. The focus ring according to claim 1, characterized in that the focus ring is made of a ceramic material.
6. The positioning block is The third vertex and, The positioning surface facing the center of the positioning circle, A focus ring according to any one of claims 1 to 5, characterized in that it includes a transition surface connecting the third top surface and the positioning surface.
7. The aforementioned transition surface is The second slope and, A first chamfer connecting the second slope and the third apex, The focus ring according to claim 6, further comprising a second chamfer connecting the second inclined surface and the positioning surface.
8. The focus ring according to claim 7, characterized in that the angle between the second slope and the first apex is 65° or less and 25° or more.
9. A chuck and a focus ring according to any one of claims 1 to 8, The chuck includes a chuck body and a columnar boss provided on the top surface of the chuck body for placing a wafer. A semiconductor process chamber characterized in that the ring body is fitted to the outside of the columnar boss and supported on the top surface of the chuck body, and the first top surface is lower than the top surface of the columnar boss.
10. The semiconductor process chamber according to claim 9, characterized in that the distance between the first top surface and the top surface of the columnar boss is 0.5 mm or less.
11. The semiconductor process chamber according to claim 9, characterized in that the difference between the radius of the first inner annular surface and the radius of the columnar boss is greater than 0 and 0.5 mm or less.