Optoelectronic devices, methods for manufacturing the same, and methods for using the same

Abstract

Various semiconductor structures comprising embedded tunnel junctions or aperture regions are described. Furthermore, methods for preparing and using such semiconductor structures are disclosed, and these structures can be used, for example, in optoelectronic devices such as vertical-cavity surface-emitting lasers (VCSELs) capable of emitting light at long wavelengths.

Description

[Technical Field]

[0001] [Cross-reference of related applications] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 509,683, filed on 22 June 2023, and the entire content of this application constitutes a part of this specification by reference.

[0002] The present invention relates to optoelectronic devices, such as vertical-cavity surface-emitting lasers that emit light at long wavelengths under room temperature (RT) and continuous-wave (CW) operation. [Background technology]

[0003] In the late 1990s and early 2000s, driven by the so-called "telecom bubble" and motivated by applications in high-bandwidth optical networks, considerable research and development and commercialization efforts were invested in long-wavelength (LW) vertical-cavity surface-emitting lasers (VCSELs), or LW-VCSELs. Unfortunately, these efforts did not yield the expected results, and further progress in this field stalled with the collapse of the overheated optical communications market in 2001. The wavelength range of 1200nm to 2400nm is important because it is the range conventionally used in silica fibers for long-distance single-mode telecommunications. There is growing renewed interest in LW-VCSELs that can function in this wavelength range due to several potential applications, including the following: 1) the need for low-power on-chip laser sources for photonic-electronic integrated circuits, 2) the growing market for eye-safe optical sensing systems based on VCSELs and VCSEL arrays, 3) the emerging market for low-cost optical links based on single-mode fiber for distances exceeding 1 km, 4) free-space (last-mile or indoor personal network) optical communications for 6G mobile and optical wireless networks, 5) the Internet of Things, 6) low-cost optical detection and ranging systems, and 7) devices and systems for biomedical sensing and diagnostics. In short, many applications in sensing and communications can be made possible by manufacturable VCSELs that emit light around 1550 nm.

[0004] However, one of the difficulties in developing NIR-MIR VCSELs is the need to combine a semiconductor active region that provides high optical gain in the 1200nm-2400nm range with a mirror that has high reflectivity, low light absorption, and high thermal conductivity. The selected semiconductor active region is, for example, an InAlGaAs quantum well prepared on an InP substrate, while the best mirror reported is the AlAs-GaAs DBR prepared on a GaAs substrate. However, InP-based and GaAs-based structures are generally incompatible in terms of epitaxial growth, which makes the realization of such VCSELs virtually impossible. There are different approaches to manufacturing NIR-MIR VCSELs, and some small-scale commercialization has taken place, but to date, none have reached the stage of cost-effective mass production. [Overview of the project] [Problems that the invention aims to solve]

[0005] Therefore, fabricating VCSELs capable of emitting light over long wavelength ranges remains extremely difficult. Consequently, there is still an inherently unmet need for long-wavelength emitting VCSELs.

[0006] Therefore, there is a need to develop various types of structures that can be used as mirrors and can be fabricated through simplified methods, and these structures can be used to fabricate VCSELs having a desired emission wavelength.

[0007] Therefore, the object of the present invention is to provide a structure that addresses and overcomes the problems known to date in the manufacturing of devices such as VCSELs.

[0008] Another object of the present invention is to provide a novel method for preparing such a structure.

[0009] A further object of the present invention is to provide a method for using the described structure, for example, for use in a VCSEL. [Means for solving the problem]

[0010] Various semiconductor structures comprising embedded tunnel junctions (BTJs) are described herein. Such semiconductor structures can be used in the fabrication of optoelectronic devices comprising vertical-cavity surface-emitting lasers (VCSELs). Details of such semiconductor structures comprising BTJs and the optoelectronic devices formed thereby are described herein.

[0011] In addition, various light-emitting structures having aperture regions formed by ion implantation are also described herein. Such light-emitting structures can be used in the fabrication of optoelectronic devices such as vertical-cavity surface-emitting lasers (VCSELs). Details of various light-emitting structures having aperture regions formed by ion implantation, and the optoelectronic devices formed thereby, are further described herein.

[0012] Various semiconductors and light-emitting structures, as well as their optoelectronic devices such as VCSELs, can be used in a wide range of applications, including but not limited to electronic, photonic, and optoelectronic applications. In particular, the VCSELs described may provide long-wavelength emission (i.e., emission at red, near-infrared, or infrared wavelengths from 900 nm to 3000 nm, as well as at subranges and individual wavelengths within that range). Furthermore, the VCSELs described may offer optical and electrical performance advantages compared to more common laser diodes, demonstrating, for example, superior beam quality, compact form factor, low operating power, cost-effective wafer-level testing, higher yield in manufacturing, and lower costs.

[0013] Non-limiting embodiments are described by reference to the accompanying drawings, which are schematic and not necessarily drawn to scale. In the drawings, each identical or substantially identical component shown is typically represented by a single reference numeral. For clarity, not all components are referenced in all drawings, nor are all components shown where it is not necessary for a person skilled in the art to understand the drawings. [Brief explanation of the drawing]

[0014] [Figure 1A] This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100, which, from bottom to top, is formed from (1) a stack 110 of 12 pairs of alternating layers of n+-indium phosphide (InP) and n--InP, (2) a layer 120 of thick n-InP layers, (3) an emissive structure 130 of InAlGaAs providing an active region having a target emission wavelength of 1550 nm, (4) a layer 140 of p-InP, (5) an embedded tunnel junction formed by a layer 150 of p++-InGaAs and a layer 160 of n++-InGaAs, (6) a current diffusion layer 170 enclosing the embedded tunnel junction, and optionally (7) a non-planar surface of the current diffusion layer, which forms a step feature 180 and can result in a photoconfinement effect. [Figure 1B] This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100', which is formed from, from bottom to top, an embedded tunnel junction formed by (1) a stack 110' of 12 pairs of alternating layers of n+-indium phosphide (InP) and n--InP, (2) a layer 120' of thick n-InP layers, (3) an emissive structure 130' of InAlGaAs providing an active region with a target emission wavelength of 1550 nm, (4) a layer 140' of p-InP, (5) a layer 150' of p++-InGaAs, and (6) a layer 160' of n++-InGaAs, and (7) a current diffusion layer 170' enclosing the embedded tunnel junction, optionally having non-planarity on the surface of the current diffusion layer (7), which can form a step feature 180' and result in a photoconfinement effect. [Figure 1C]This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100'' in which a p-doped second semiconductor layer 150'' is partially etched, and as a result of etching, the thickness of the layer 150'' beneath the n-doped second semiconductor layer 160'' is greater than that of the remaining layer 150''. Other layers and structures are not labeled for convenience. [Figure 1D] This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100''' in which a p-doped second semiconductor layer 150''' is partially and completely etched. As a result of the etching, the thickness of layer 150'' beneath the n-doped second semiconductor layer 160''' is greater than the thickness of the remaining layer 150'', and a portion of the original layer has been completely removed by etching. Other layers and structures are not labeled for convenience. [Figure 1E] This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100'''' in which a p-doped second semiconductor layer 150'''' has a uniform thickness and a portion of the original layer is completely removed by etching. It is also shown that an n-doped current diffusion layer 170'''' may include additional nonplanarity in which a portion of the layer is partially removed by etching. Other layers and structures are not denoted by reference numerals for convenience. [Figure 1F] This is a non-limiting cross-sectional view of an epitaxial semiconductor structure 100'''' in which a p-doped second semiconductor layer 150'''' has been etched to have a smaller area than the upper n-doped second semiconductor layer 160''''''. Other layers and structures are not denoted by reference numerals for convenience. [Figure 2] This figure shows a non-limiting fabrication process for creating a structure having an embedded tunnel junction (BTJ), such as semiconductor structure 100. [Figure 3]A non-limiting cross-sectional view of a light-emitting structure 200 having a distributed Bragg reflector (DBR) and an embedded tunnel junction (BTJ), showing from bottom to top: (1) a substructure 210 formed of a stack of 12 pairs of alternating layers of n+-InP and n--InP, wherein the n+-InP is selectively porous by electrochemical etching as indicated by dark bands; (2) a layer 220 of thick n-InP layers; (3) a BJT formed from bottom to top of a layer of InAlGaAs 230, a layer of p-InAlAs 240, a layer of p++-InAlAs 250 and a layer of n++-InP 260, and an upper current-diffusing layer 270 of n-InP, wherein the upper surface of the current-diffusing layer 270 includes a step feature 280. The shown Al2O3 layer 295 and additional SiO2 layer 290 are present due to the fabrication process. [Figure 4] This figure shows a non-limiting fabrication process for creating a light-emitting structure 200 that includes a distributed Bragg reflector (DBR) and a buried tunnel joint (BTJ). [Figure 5] This is a non-limiting cross-sectional view of a vertical-cavity surface-emitting laser (VCSEL) 300, which is formed by a light-emitting structure 200 having a lower DBR mirror, an upper dielectric DBR mirror 310 located on the upper part of the mesa structure of the light-emitting structure 200, and a metal contact 320. [Figure 6] This figure shows a non-restrictive fabrication process for creating a vertical-cavity surface-emitting laser (VCSEL) such as the VCSEL 300. [Figure 7] This graph shows the IV plots of a DBR device with a 10 μm diameter embedded tunnel junction (BTJ) (solid line) and a DBR device without a BTJ (dashed line). [Figure 8A] This is a graph showing the relationship between LI and LJ in NP-InP VCSELs with a 6 μm aperture region. [Figure 8B] This is a graph of the single-mode oscillation spectrum of an NP-InP VCSEL with a 6 μm aperture region. [Figure 9]This is a non-limiting cross-sectional view of an epitaxial structure 400 formed from, from bottom to top: (1) a stack 410 consisting of 12 pairs of alternating layers of n+-InP and n--InP; (2) a thick n-InP layer 420; (3) an InAlGaAs emissive structure 430 providing an active region having a target emission wavelength of 1550 nm; (4) a p-InAlAs layer 440; (5) a p++-InAlAs layer 450; (6) an n++-InP layer 460; and (7) an n-InP layer 470. [Figure 10] This figure shows a non-limiting fabrication process for creating a light-emitting structure 600 comprising a distributed Bragg reflector (DBR) and an aperture region. [Figure 11] This graph shows injection-induced defect profiles simulated using SRIM, with interlayer boundaries labeled by black dashed lines. [Figure 12]A non-limiting cross-sectional view of a distributed Bragg reflector (DBR) and an emission-emitting structure 600 having an aperture region inside, wherein from bottom to top there is a substructure 610 formed of a stack of 12 pairs of alternating layers of n+-InP and n--InP, wherein the n+-InP is selectively porous by electrochemical etching as indicated by dark bands; (2) a layer 620 of thick n-InP layers; and (3) a mesa structure from bottom to top, comprising an InAlGaAs layer 630, a p-InAlAs layer 640, a p++-InAlAs layer 650, an n++-InP layer 660, and an upper n-InP current-diffusing layer 670, providing an active region with a target emission wavelength of 1550 nm, the upper surface of the current-diffusing layer 670 includes a step feature 680. Within the mesa structure, there is an aperture region formed of p-InAlAs, p++-InAlAs, n++-InP, and n-InP portions, which is partially shown as regions 645, 655, and 665 below step feature 680. Here, the p-InAlAs, p++-InAlAs, n++-InP, and n-InP outside the aperture region were ion-implanted to reduce conductivity, and subsequent annealing restored conductivity, at least in the current diffusion layer of n-InP above the aperture region. In addition, a layer of SiO2 690 is shown, which is present due to the fabrication process. [Figure 13] This is a non-limiting cross-sectional view of a vertical-cavity surface-emitting laser (VCSEL) 700, which is formed by a light-emitting structure 600 having a lower DBR, an upper dielectric DBR mirror 710 located on the upper part of the mesa structure of the light-emitting structure 600, and a metal contact 720. [Figure 14] This figure shows a non-restrictive fabrication process for creating a vertical-cavity surface-emitting laser (VCSEL) such as the VCSEL 700. [Figure 15] This graph shows the IV plots of a light-emitting device having an aperture region with a diameter of 10 μm formed by ion implantation (solid line) and a light-emitting device without an aperture region (dashed line). [Figure 16A]This graph shows the relationship between LI and LJ for a 1380nm NP-InP VCSEL with a 7μm aperture region and a threshold current of 0.5mA. [Figure 16B] This is a graph of the single-mode oscillation spectrum of a 1380 nm NP-InP VCSEL with a 7 μm aperture region under an injection current of 8 mA, where the side-mode suppression ratio was greater than 30 dB. [Figure 17A] This graph shows the relationship between LI and LJ for a 1550nm NP-InP VCSEL with a 7μm aperture region and a threshold current of 0.67mA. [Figure 17B] This is a graph of the single-mode oscillation spectrum of a 1550 nm NP-InP VCSEL with a 7 μm aperture region under an injection current of 7 mA, where the side-mode suppression ratio was greater than 30 dB. [Modes for carrying out the invention]

[0015] Various semiconductor structures, as well as methods for manufacturing and using such semiconductor structures, are described herein. For example, the semiconductor structures can be used to fabricate light-emitting structures equipped with distributed Bragg reflector mirrors for high-performance VCSELs that emit light at long wavelengths.

[0016] I. Definition As used herein, "porosity" refers to the volume ratio of air present in a porous medium, such as a layer(s) of InP, GaAs, or GaSb, and is expressed as a percentage.

[0017] As used herein, “electropolishing” means that the n-doped indium phosphide or gallium arsenide is completely removed by etching, or substantially removed by etching (where “substantially removed by etching” means etching beyond 95%, 96%, 97%, 98%, or 99%), leaving voids where the n-doped material originally existed. These voids represent a low refractive index medium (i.e., air), which typically has a refractive index of about 1.

[0018] The terms "refractive index" and "index of refraction" are used interchangeably and refer to the ratio of the speed of light in a vacuum to the speed of light in a specified medium, such as a layer of InP, GaAs, or GaSb, according to the formula n = c / v (where c is the speed of light in a vacuum and v is the phase velocity of light in the medium).

[0019] As used herein, “refractive index contrast” refers to the relative difference in refractive index between two media having different refractive indices and coming into contact to form an interface.

[0020] Numerical ranges include ranges for thickness, doping concentration, ranges of integers, time, voltage, length, diameter, concentration, etc. These ranges disclose not only each possible numerical value that such a range can reasonably encompass, but also any subranges and combinations of subranges that are encompassed within that range. For example, a layer may have a thickness in the range of approximately 1 nm to 10 nm, where this range also discloses thicknesses that can be independently selected from approximately 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, and 9 nm, as well as any range between these numerical values ​​(e.g., 3 nm to 8 nm), and any possible combination of ranges between these values.

[0021] The use of the term "approximately" is intended to represent a value that is approximately ±10% above or below the stated value it modifies, and in other examples, the value may take a range of approximately ±5% above or below the stated value. When the term "approximately" is used before a range of numbers (i.e., approximately 1 to 5) or before a series of numbers (i.e., approximately 1, 2, 3, 4, etc.), it is intended to modify each number listed at both ends of the range and / or throughout the series, unless otherwise specified.

[0022] II. Semiconductor Structures and Devices Equipped with Embedded Tunnel Junctions (BTJs) Various semiconductor structures having embedded tunnel junctions are described herein. These semiconductor structures can be used to fabricate, or otherwise use to form a part thereof, light-emitting structures with distributed Bragg reflector (DBR) mirrors and other optoelectronic devices such as vertical-cavity surface-emitting lasers (VCSELs). Details of various semiconductor structures and optoelectronic devices having BTJs are described below.

[0023] a. Semiconductor structure with embedded tunnel junction (BTJ) In some examples, non-limiting semiconductor structures with embedded tunnel junctions (BTJs) are, A substructure comprising alternating layers of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers on a semiconductor substrate, A first n-doped semiconductor layer on top of the substructure, An emissive structure containing multiple quantum wells (MQWs) on a first n-doped semiconductor layer, A p-doped first semiconductor layer on top of an emissive structure, An embedded tunnel junction (BTJ) located on a p-doped first semiconductor layer, The embedded tunnel joint is Approximately 1×10 18 cm -3 A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10⁻¹⁶ layers on a second semiconductor layer doped with p. 18 cm -3 A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer. An embedded tunnel junction in which, optionally, a p-doped second semiconductor layer and an n-doped second semiconductor layer occupy equal or substantially equal areas on the p-doped first semiconductor layer, An n-doped current-diffusing layer enclosing at least a portion of an n-doped second semiconductor layer and at least a portion of an optionally p-doped second semiconductor layer, The current diffusion layer outside the portion having a layer of n-doped second semiconductor is in contact with a p-doped second semiconductor or a p-doped first semiconductor. An n-doped current-diffusing layer, wherein the surface of the current-diffusing layer optionally includes a region above the embedded tunnel junction, and the region is raised, forming a step feature that results in a photoconfinement effect. It is equipped with.

[0024] Exemplary and non-limiting semiconductor structures comprising a BTJ include those shown in Figures 1A to 1F. The BTJ is formed by a current diffusion layer and a region embedded within the current diffusion layer. For example, in semiconductor structure 100, the BTJ is defined by layers 150 and 160 encased by a current diffusion layer 170, which is in contact with layer 140. For example, in semiconductor structure 100', the BTJ is defined by layer 160' encased by a current diffusion layer 170', which is in contact with layer 150'. As described in Example 1, the BTJ defines a region that can provide a current confinement effect in a device comprising such a tunnel junction. Furthermore, as described above, the upper surface of the current diffusion layer of the structure may have a step-like feature (i.e., 180 in Figure 1B) that is above the BTJ and provides a photoconfinement effect.

[0025] For some specific semiconductor materials that form part of the semiconductor structure, such as layers of p-doped and n-doped second semiconductors, there is a minimum doping concentration as detailed above. For the remaining p-doped or n-doped layers mentioned, the concentration levels of p-doping or n-doping are not particularly restricted. In some examples, the different p-doped or n-doped layers, each independently, may have a high doping concentration level in the range of at least about 1×10 19 cm -3 or more, or about 0.1×10 19 cm -3 to 10×10 20 cm -3 . In some cases, the high doping concentration level is about 1×10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , or 10×10 19 cm -3 . In some other examples, the different p-doped or n-doped layers, each independently, are greater than about 1×10 18 cm -3 and less than 1×10 20 cm -3 , 2×10 18 cm -3 to 1×10 20 cm -3 , 3×10 18 cm -3 to 1×10 20 cm -3 , 4×10 18 cm -3 to 1×10 20 cm-3 less than, or 5×10 18 cm -3 ~1×10 20 cm -3 may have a medium doping concentration level of less than. In some examples, the moderately doped concentration level is 1×10 19 cm -3 ~1×10 20 cm -3 less than, or in the range of about 0.5×10 19 cm -3 ~10×10 19 cm -3 In some cases, the moderately doped concentration level is about 1×10 18 cm -3 , 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , or 10×10 18 cm -3 However, in still other examples, the differently p-doped or n-doped layers may each independently have a low doping concentration level in the range of less than about 20×10 17 cm -3 less than, or about 0.5×10 17 cm -3 ~10×10 17 cm -3 In some cases, the low doping concentration level is about 1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm-3 , 6 × 10 17 cm -3 , 7 × 10 17 cm -3 , 8 × 10 17 cm -3 , 9 × 10 17 cm -3 , or 10 × 10 17 cm -3 may also be.

[0026] As described above, the at least n-doped second semiconductor layer has a surface area smaller than the surface area of the p-doped first semiconductor layer. This is shown, for example, in FIGS. 1A-1F, where the n-doped second semiconductor layer occupies a smaller area or a smaller surface area compared to the surface area of the p-doped first semiconductor layer. In some non-limiting examples, the surface area occupied by the n-doped second semiconductor layer may be from about 1% to about 30% of the total surface area of the p-doped first semiconductor layer, as well as sub-ranges and individual values included in that range. In some examples, as in FIG. 1A, the p-doped second semiconductor layer and the n-doped second semiconductor layer occupy equal or substantially equal areas on the p-doped first semiconductor layer, as described below. In other examples, the p-doped second semiconductor layer and the n-doped second semiconductor layer occupy unequal areas on the p-doped first semiconductor layer. For example, as shown in FIG. 1B, the p-doped second semiconductor layer may have the same surface area as the p-doped first semiconductor layer, while the n-doped second semiconductor layer occupies a surface area smaller than the surface area of the p-doped first semiconductor layer.

[0027] In other examples, the p-doped second semiconductor layer can have any suitable area, exhibit variable thickness throughout the same layer, and / or be completely removed by etching in some specific parts / regions. As shown in Figure 1C, the epitaxial semiconductor structure 100'' may have a partially etched p-doped second semiconductor layer 150'', thereby making the thickness of the layer 150'' beneath the n-doped second semiconductor layer 160'' thicker than the remaining layer 150''. However, the thickness may vary in other ways and locations. As shown in Figure 1D, the epitaxial semiconductor structure 100''' may have a p-doped second semiconductor layer 150'''' that is partially and completely etched at different locations in the same layer, thereby making the thickness of the layer 150'' beneath the n-doped second semiconductor layer 160'' thicker than the remaining layer 150'' present, with a portion of the original layer completely removed by etching as shown. As shown in Figure 1E, the epitaxial semiconductor structure 100'''' may have a p-doped second semiconductor layer 150'''' which has a uniform thickness throughout and in which a portion of the original layer is completely removed by etching. Figure 1E also shows that the n-doped current diffusion layer 170'''' may include additional non-planar features in which some portions of the current diffusion layer are partially removed by etching. Finally, as shown in Figure 1F, the epitaxial semiconductor structure 100'''''' may have a p-doped second semiconductor layer 150'''' which is etched to have a smaller surface area than the surface area of ​​the upper n-doped second semiconductor layer 160''''''. Such an example can be considered a layer undercut.

[0028] In such an example, if the n-doped second semiconductor layer and the p-doped second semiconductor layer have equal or substantially equal areas, they are understood to overlap to form a bilayer stack on the p-doped first semiconductor layer. See Figure 1A. "Substantially equal," as used herein, means a comparison of the areas of two different layers where their respective areas differ by about 5%, 4%, 3%, 2%, 1%, or less.

[0029] Regarding the semiconductor structure, the semiconductor substrate can be manufactured from indium phosphide, gallium arsenide, or gallium antimonide. In some specific examples, the alternating layers of the substructure contain or are manufactured from a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which are lattice-matched to a selected semiconductor substrate manufactured from one of these materials. In other examples, the alternating layers of the substructure contain or are manufactured from a ternary semiconductor material which is lattice-matched to a selected semiconductor substrate manufactured from one of these materials. In yet another example, the alternating layers of the substructure contain or are manufactured from a quaternary semiconductor material which is lattice-matched to a selected semiconductor substrate manufactured from one of these materials.

[0030] In some examples, the described semiconductor structure may include, independently, a first n-doped semiconductor layer, an emissive structure, a first p-doped semiconductor layer, a second p-doped semiconductor layer, a second n-doped semiconductor layer, and a current diffusion layer, each of which may contain a semiconductor material selected to be lattice-matched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide.

[0031] Suitable semiconductor materials that can form part or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current diffusion layer may, independently, include: a semiconductor material lattice-matched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a semiconductor material lattice-matched to a gallium arsenide semiconductor substrate and selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a semiconductor material lattice-matched to a gallium antimonide semiconductor substrate and selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0032] In some examples, the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer can each independently include semiconductor materials that are lattice-mismatched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide. In such examples, the semiconductor material is lattice-mismatched to the indium phosphide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material is lattice-matched to the gallium arsenide semiconductor substrate and is selected from, but is not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor material is lattice-matched to the gallium antimonide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

[0033] In some cases, non-limiting examples of binary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in one or more layers named above is preferably based on the lattice matching of the semiconductor material of the layer of a given structure to a selected semiconductor substrate that can be manufactured from one of InP, GaAs, or GaSb. Those skilled in the art will be able to select appropriate semiconductor materials for each lattice-matched layer on the semiconductor substrate, as well as desired doping types and doping concentration levels, as detailed above.

[0034] The layers and structures described above may have any suitable dimensions, shapes, and thicknesses that are appropriate for their use. In some examples, different structures and layer thicknesses may be as follows:

[0035] [Table 1]

[0036] It is understood that the thicknesses of the layers and structures given above for a light-emitting structure having a DBR mirror inside, and a semiconductor structure that can be used to fabricate a VCSEL from such a light-emitting structure, may also specify the thicknesses of those layers and structures included in the light-emitting structure and the VCSEL.

[0037] In some examples, with respect to the substructure, the n-doped semiconductor layers within the alternating layers each have the same thickness, and / or the undoped (or low-doped) semiconductor layers within the alternating layers each have the same thickness. It is possible for the n-doped semiconductor layers and the undoped (or low-doped) semiconductor layers to have the same or different thicknesses. Non-limiting methods for manufacturing semiconductor structures with embedded tunnel junctions (BTJs) are: (i) A step of forming a substructure on a semiconductor substrate comprising alternating layers of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers, (ii) A step of depositing a first n-doped semiconductor layer on the substructure, (iii) A step of depositing or forming an emissive structure containing multiple quantum wells (MQWs) on a first semiconductor layer doped with n, (iv) A step of depositing a p-doped first semiconductor layer on the emissive structure, (v) On top of the first semiconductor layer doped with p, approximately 1 × 10 18 cm -3 A step of depositing a second layer of p-doped semiconductor having a higher p-doping level, (vi) Approximately 1 × 10⁻¹⁶ layers on top of the p-doped second semiconductor layer. 18 cm -3 A process of depositing a layer of n-doped semiconductor having a higher n-doping level, (vii)n A step of forming or patterning a masking material on the upper surface portion of a doped semiconductor layer, (viii) Etching and removing at least an n-doped semiconductor layer and optionally a p-doped second semiconductor outside the surface portion having the masking material on top, (ix) The process of removing the masking material, (x) A step of depositing an n-doped current diffusion layer enclosing at least a portion of a second n-doped semiconductor layer and optionally a portion of a second p-doped semiconductor layer, wherein the current diffusion layer outside the surface portion is in contact with the p-doped second semiconductor or the p-doped first semiconductor. It can include...

[0038] Details for manufacturing the substructure are provided in Section IV below. An exemplary scheme of the above method is shown in Figure 2, where the BTJ is formed by selectively etching layer 160 and optionally layer 150 to define the tunnel junction, which is subsequently filled by a current diffusion layer. Due to the non-planarity resulting from the etching of layer 160 and optionally layer 150, which are not protected by the masking material, the deposition of the current diffusion layer may produce a step-like feature on the upper surface of the current diffusion layer above the region of the BTJ.

[0039] The structures and layers formed or deposited by the above method can each be formed or deposited independently by known deposition methods, including metal-organic vapor deposition (MOCVD). The selection of precursors, p-dopants or n-dopants, and conditions for forming and doping such structures and layers to a specified thickness is known in the art.

[0040] Methods for depositing / forming emissive structures containing multiple quantum wells (MQWs) are known in the art.

[0041] In some examples, the masking material is selected from the group consisting of dielectrics (such as silicon dioxide, silicon nitride, and aluminum oxide) and / or photoresists, but is not limited to these. Such materials can be formed by various methods, such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

[0042] For the methods described, patterning, etching, or removal of any material may be carried out by any suitable technique, such as wet chemical etching, plasma etching, or inductively coupled plasma reactive ion etching (ICP-RIE), as needed.

[0043] For the methods described, the semiconductor substrate may be manufactured from indium phosphide, gallium arsenide, or gallium antimonide. In some specific examples, the alternating layers of the substructure contain or are manufactured from a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which are lattice-matched to a selected semiconductor substrate manufactured from one of indium phosphide, gallium arsenide, or gallium antimonide. In other examples, the alternating layers of the substructure contain or are manufactured from a ternary semiconductor material which is lattice-matched to a selected semiconductor substrate manufactured from one of indium phosphide, gallium arsenide, or gallium antimonide. In yet another example, the alternating layers of the substructure contain or are manufactured from a quaternary semiconductor material which is lattice-matched to a selected semiconductor substrate manufactured from one of indium phosphide, gallium arsenide, or gallium antimonide.

[0044] In some examples, the semiconductor structure formed according to this method may include, independently, a first n-doped semiconductor layer, an emissive structure, a first p-doped semiconductor layer, a second p-doped semiconductor layer, a second n-doped semiconductor layer, and a current diffusion layer, each of which may be selected to be lattice-matched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide.

[0045] Suitable semiconductor materials that can form part or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current diffusion layer may, independently, include: a semiconductor material lattice-matched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a semiconductor material lattice-matched to a gallium arsenide semiconductor substrate and selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a semiconductor material lattice-matched to a gallium antimonide semiconductor substrate and selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0046] In some examples of this method, the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer can each independently include a semiconductor material that is lattice-mismatched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide. In such examples, the semiconductor material is lattice-mismatched to the indium phosphide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material is lattice-matched to the gallium arsenide semiconductor substrate and is selected from, but is not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor material is lattice-matched to the gallium antimonide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

[0047] In some cases, non-limiting examples of binary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in one or more layers named above is preferably based on the lattice matching of the semiconductor material of the layer of a given structure to a selected semiconductor substrate that can be manufactured from one of InP, GaAs, or GaSb. Those skilled in the art will be able to select appropriate semiconductor materials for each lattice-matched layer on the semiconductor substrate, as well as desired doping types and doping concentration levels, as detailed above.

[0048] With respect to the method described, the layers, structures, and overall semiconductor structures formed according to this method may have any preferred dimensions, shapes, and thicknesses. Exemplary and non-limiting thicknesses of the overall semiconductor structure and layers are given in Table 1.

[0049] b. Light-emitting structure comprising a distributed Bragg reflector (DBR) mirror and a buried tunnel junction (BTJ) A semiconductor structure having a BTJ as described above can be used in the fabrication of a light-emitting structure that includes a distributed Bragg reflector and has an embedded tunnel junction (BTJ) inside.

[0050] In one example, such a light-emitting structure comprising a distributed Bragg reflector (DBR) mirror and an embedded tunnel junction (BTJ) inside, A substructure comprising alternating layers of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers on a semiconductor substrate, wherein the n-doped layers are porous and contain multiple pores, and the undoped (or low-doped) layers are non-porous or substantially non-porous; A first n-doped semiconductor layer on top of the substructure, An emissive structure containing multiple quantum wells (MQWs) on a first n-doped semiconductor layer, A p-doped first semiconductor layer on top of an emissive structure, An embedded tunnel junction located on a portion (or sub-region) of a p-doped first semiconductor layer, The embedded tunnel junction (BTJ) defines the aperture region. Approximately 1×10 18 cm -3 A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10⁻¹⁶ layers on a second semiconductor layer doped with p. 18 cm -3 A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer. An embedded tunnel junction in which, optionally, a p-doped second semiconductor layer and an n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, An n-doped current-diffusing layer enclosing at least a portion of an n-doped second semiconductor layer and at least a portion of an optionally p-doped second semiconductor layer, The current diffusion layer outside the portion having a layer of n-doped second semiconductor is in contact with a p-doped second semiconductor or a p-doped first semiconductor. The surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, and the region is raised, forming a step feature that results in a photoconfinement effect. It is equipped with.

[0051] A non-limiting example of a light-emitting structure equipped with a DBR mirror as described above is shown in Figure 3 as a light-emitting structure 200 equipped with a DBR and a BTJ inside.

[0052] In some examples, the porosity present in the n-doped layer of a porous substructure is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0053] Due to the presence of porosity in the n-doped layers of the substructure, air can fill multiple pores, thereby resulting in a refractive index lower than that of the unporous or substantially unporous undoped (or low-doped) layers. In some examples, a refractive index contrast (Δn) exists between the alternating layers after porosity, ranging from approximately 0.1 to approximately 2, or from approximately 0.1 to approximately 2.5.

[0054] Regarding the light-emitting structure, the semiconductor substrate can be made of indium phosphide, gallium arsenide, or gallium antimonide. In some specific examples, the alternating layers of the substructure contain or are made of a binary semiconductor material selected from indium phosphide, gallium arsenide, or gallium antimonide, which are lattice-matched to a selected semiconductor substrate made of one of these materials. In other examples, the alternating layers of the substructure contain or are made of a ternary semiconductor material which is lattice-matched to a selected semiconductor substrate made of one of these materials. In yet another example, the alternating layers of the substructure contain or are made of a quaternary semiconductor material which is lattice-matched to a selected semiconductor substrate made of one of these materials.

[0055] In some examples, the described light-emitting structure may include, independently, a first n-doped semiconductor layer, an emissive structure, a first p-doped semiconductor layer, a second p-doped semiconductor layer, a second n-doped semiconductor layer, and a current-diffusing layer, each of which may be selected to be lattice-matched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide.

[0056] Suitable semiconductor materials that can form part or all of the n-doped first semiconductor layer, the emissive structure, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current diffusion layer may, independently, include: a semiconductor material lattice-matched to an indium phosphide semiconductor substrate and selected from, but not limited to, the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb; or a semiconductor material lattice-matched to a gallium arsenide semiconductor substrate and selected from, but not limited to, the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP; or a semiconductor material lattice-matched to a gallium antimonide semiconductor substrate and selected from, but not limited to, the group consisting of GaSb, AlAsSb, and AlGaAsSb.

[0057] In some examples, the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer can each independently include semiconductor materials that are lattice-mismatched to a semiconductor substrate made of indium phosphide, gallium arsenide, or gallium antimonide. In such examples, the semiconductor material is lattice-mismatched to the indium phosphide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb; or the semiconductor material is lattice-matched to the gallium arsenide semiconductor substrate and is selected from, but is not limited to, the group consisting of InGaAs, AlGaAs, and In(Al)GaP; or the semiconductor material is lattice-matched to the gallium antimonide semiconductor substrate and is selected from, but is not limited to, the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

[0058] For certain semiconductor materials that form part of the light-emitting structure, such as the p-doped second semiconductor and the n-doped second semiconductor layers, there are minimum doping concentrations as detailed above. For the remaining p-doped or n-doped layers mentioned, the p-doping concentration levels or n-doping concentration levels are not particularly limited. In some examples, the different p-doped or n-doped layers each independently have a minimum doping concentration of at least about 1 × 10⁻⁶. 19 cm -3 The above, or approximately 0.1 × 10 19 cm -3 ~10×10 20 cm -3 It may have high doping concentration levels in the range of approximately 1 × 10⁻⁶. In some cases, high doping concentration levels may be approximately 1 × 10⁻⁶. 19 cm -3 , 2×10 19 cm -3 , 3 x 10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×1019 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , or 10 x 10 19 cm -3 This may also be the case. In some other examples, different p-doped or n-doped layers are each independently approximately 1 × 10⁻⁶ 18 cm -3 Larger 1 x 10 20 cm -3 Less than 2 × 10 18 cm -3 ~1 × 10 20 cm -3 Less than 3 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than 4 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than, or 5 × 10 18 cm -3 ~1 × 10 20 cm -3 It may have a moderate doping concentration level of less than 1 × 10⁻⁶. In some examples, a moderately doped concentration level is 1 × 10⁻⁶. 19 cm -3 ~1 × 10 20 cm -3 The range of less than, or approximately 0.5 × 10 19 cm -3 ~10×10 19 cm -3 This is within the range. In some cases, a moderate doping concentration level is approximately 1 × 10⁻⁶. 18 cm -3 , 2×10 18 cm -3 , 3 x 10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm-3 , 9×10 18 cm -3 , or 10 x 10 18 cm -3 This may also be the case. However, in yet another example, different p-doped or n-doped layers are each independently approximately 20 × 10 17 cm -3 Less than, or approximately 0.5 × 10 17 cm -3 ~10×10 17 cm -3 It may have low doping concentration levels in the range of . In some cases, low doping concentration levels are about 1 × 10 17 cm -3 , 2×10 17 cm -3 , 3 x 10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3 , 6×10 17 cm -3 , 7×10 17 cm -3 , 8×10 17 cm -3 , 9×10 17 cm -3 , or 10 x 10 17 cm -3 That's fine.

[0059] In some examples, non-limiting examples of binary semiconductor materials that can be p-doped or n-doped can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some examples, non-limiting examples of ternary semiconductor materials that can be p-doped or n-doped can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some examples, quaternary semiconductor materials that can be p-doped or n-doped can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary semiconductor material, ternary semiconductor material, or quaternary semiconductor material for use in one or more of the layers named above is preferably based on the lattice matching of the semiconductor material of the layer of a given structure to a selected semiconductor substrate that can be fabricated from any one of InP, GaAs, or GaSb. One of ordinary skill in the art will be able to select the appropriate semiconductor material for each layer that is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration levels, as detailed above.

[0060] Regarding the above light-emitting structure, the layers, structures, and the overall resulting light-emitting structure may have any suitable dimensions, shapes, and thicknesses. Exemplary and non-limiting thicknesses of the structures and layers of the overall resulting light-emitting structure are given in Table 1.

[0061] In some examples, the BTJ may form part of a mesa structure as shown in FIG. 3, and the dimensions of such a mesa structure can be selected to be larger than the dimensions of the BTJ. In other words, the mesa structure includes the BTJ within it.

[0062] A non-limiting method of manufacturing such a light-emitting structure comprising a DBR mirror and an embedded tunnel junction (BTJ) is (i’) providing or forming a semiconductor structure comprising an embedded tunnel junction (BTJ), wherein the semiconductor structure comprises a lower structure comprising alternating layers of an n-doped semiconductor layer and an undoped or lightly doped semiconductor layer on a semiconductor substrate, An n-doped first semiconductor layer on a lower structure, An emissive structure including a multiple quantum well (MQW) on the n-doped first semiconductor layer, A p-doped first semiconductor layer on the emissive structure, An embedded tunnel junction (BTJ) present on the p-doped first semiconductor layer, where the embedded tunnel junction, has a p-doped second semiconductor layer having a p-doping level greater than about 1×10 18 cm -3 and an n-doped second semiconductor layer having an n-doping level greater than about 1×10 cm 18 cm -3 on the p-doped second semiconductor layer, comprising, where at least the n-doped second semiconductor layer has a surface area smaller than the surface area of the p-doped first semiconductor layer, optionally, an embedded tunnel junction where the p-doped second semiconductor layer and the n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, an n-doped current diffusion layer encapsulating at least a portion of the n-doped second semiconductor layer and optionally at least a portion of the p-doped second semiconductor layer, where the current diffusion layer outside the portion having the n-doped second semiconductor layer on top is in contact with the p-doped second semiconductor or the p-doped first semiconductor, and the surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, the region being raised to form a step feature that provides an optical confinement effect, an n-doped current diffusion layer, comprising, (ii’) Forming a mesa structure by etching the current diffusion layer, the p-doped first semiconductor layer, optionally the p-doped second semiconductor layer, and a part of the light-emitting structure, (iii') A step of depositing a layer of silicon dioxide over a mesa structure, wherein at least a portion of the n-doped first semiconductor layer is not covered by the silicon dioxide layer, (iv') A step of etching the portion not covered by the silicon dioxide layer to form a trench that exposes the sidewall of the alternating layers of the substructure, (v') A step of selectively porousizing an n-doped semiconductor layer of a substructure, wherein multiple pores are formed and the undoped (or low-doped) semiconductor layer remains non-porous or substantially non-porous, (vi') A step of depositing one or more materials so as to cover the trench, sidewalls, and sidewalls of the mesa structure, (vii') If covered by one or more materials, a step of selectively removing one or more materials to expose at least a portion of the upper part of the mesa structure and optionally a portion of the n-doped first semiconductor layer, (viii') A step of forming a metal contact on a portion of the upper part of the mesa structure and on a portion of the n-doped first semiconductor layer, It can include...

[0063] A method for forming a structure with a BTJ is described above. A non-limiting exemplary scheme for forming a light-emitting structure with a DBR mirror and a BTJ is shown in Figure 4.

[0064] The structures and layers formed or deposited by the above method may each be independently formed or deposited by deposition methods known in the art, including metal-organic vapor deposition (MOCVD). The selection of precursors, p-dopants or n-dopants, and conditions for forming and doping such structures and layers to a specified thickness is known in the art.

[0065] For the described methods for preparing such light-emitting structures, patterning, etching, or removal can be carried out by any suitable technique, such as wet chemical etching, plasma etching, or inductively coupled plasma reactive ion etching (ICP-RIE).

[0066] In some examples of this method, one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, silicon nitride, and spin-on-glass, and / or one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist, or combinations thereof. Various types of photoresists are known in the art. For the methods described, the deposition of silicon dioxide and the layers of one or more materials can be formed by various methods, such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art. Other selections for the luminescent structure and the layers therein are given in Section IIb above.

[0067] In some examples of this method, the porosity formed in step (v') is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0068] In some examples of this method, step (v') is carried out by electrochemical etching in an electrolyte solution under an applied bias voltage. In some specific examples, the electrolyte solution may include halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (e.g., oxalic acid and citric acid), and mixtures thereof.

[0069] In some examples of this method, the metal contact formed during step (viii') is formed of or comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts are known to those skilled in the art.

[0070] With respect to the mesa structure formed in step (ii'), the dimensions of the mesa structure are selected to be larger than the dimensions of the BTJ. In other words, the mesa structure contains a BTJ inside. The mesa structure can be formed, for example, by wet etching or plasma etching (e.g., RIE etching).

[0071] c. Optoelectronic devices with embedded tunnel junctions (BTJs) The above-described light-emitting structure, which includes a DBR and a BTJ, can be used in the fabrication of optoelectronic devices having an embedded tunnel junction (BTJ) inside.

[0072] In some cases, optoelectronic devices are A light-emitting structure comprising a lower distributed Bragg reflector mirror and an internally embedded tunnel junction (BTJ), Upper distributed Bragg reflector mirror, Metal contacts and It can be equipped with.

[0073] Regarding optoelectronic devices, the light-emitting structure comprises a distributed Bragg reflector (DBR) and a back-to-junction (BTJ), as described above. Non-limiting examples of optoelectronic devices such as VCSELs are shown in Figure 5.

[0074] In some examples, the upper distributed Bragg reflector is formed of or comprises alternating layers of one or a combination thereof of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2.

[0075] In some examples, the metal contact is formed of or includes one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

[0076] In some examples, the optoelectronic device is a vertical-cavity surface-emitting laser (VCSEL). In some cases, the vertical-cavity surface-emitting laser operates at room temperature (about 25 °C) and in continuous-wave mode.

[0077] In some other cases, the vertical-cavity surface-emitting laser operates at a temperature below about 0 °C, above about 25 °C, or above about 85 °C. In still other examples, the vertical-cavity surface-emitting laser can operate in pulsed mode.

[0078] A vertical-cavity surface-emitting laser comprising a BTJ can emit light in the infrared wavelength region and / or the red wavelength region depending on the choice of the emissive structural material. In some cases, the vertical-cavity surface-emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

[0079] A non-limiting method of manufacturing an optoelectronic device comprising an embedded tunnel junction (BTJ) can (i'') providing or forming a lower distributed Bragg reflector mirror and a light-emitting structure comprising an embedded tunnel junction (BTJ) therein; (ii'') providing or forming an upper distributed Bragg reflector mirror on the light-emitting structure; (iii'') providing or forming a metal contact on the optoelectronic device; and can include.

[0080] For an optoelectronic device formed according to the above method, the light-emitting structure comprises a distributed Bragg reflector mirror (BDR) mirror and a BTJ as described above. A non-limiting scheme of a process for fabricating an optoelectronic device such as a VCSEL is shown in FIG. 6.

[0081] In such a method, the upper distributed Bragg reflector mirror of step (ii'') may comprise alternating layers of one or a combination thereof of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, and a-Si / CaF2. Methods for producing such a DBR having the aforementioned alternating layers are known in the art. The number of alternating layers in such a DBR may depend on the selected material. The upper DBR mirror may be deposited by means known in the art, and may include annealing to increase reflectivity. In some examples, the upper DBR mirror has a reflectivity of at least about 97% or more.

[0082] Regarding the above method, the metal contact in step (iii'') may be formed of or contain one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

[0083] It is understood that, in any of the methods described in Section II, the order of certain steps may be interchangeable, to the extent permitted and without adversely affecting the structure or device formed. For example, steps (ii'') and (iii'') of the method for manufacturing an optoelectronic device may be carried out in any preferred order.

[0084] III. Luminescent structure and device having an aperture region formed by ion implantation Various light-emitting structures and devices having aperture regions formed by ion implantation are described herein. These light-emitting structures can be used to fabricate, or otherwise form part of, other optoelectronic devices such as light-emitting structures with distributed Bragg reflector (DBR) mirrors and vertical-cavity surface-emitting lasers (VCSELs). Details of the various light-emitting structures and devices having aperture regions formed by ion implantation are described below.

[0085] a. A light-emitting structure comprising a distributed Bragg reflector (DBR) mirror and an aperture region formed by ion implantation. In one example, a light-emitting structure comprising a distributed Bragg reflector (DBR) mirror and an aperture region formed by ion implantation is: A substructure comprising alternating layers of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers on a semiconductor substrate, wherein the n-doped semiconductor layers are porous and contain multiple pores, and the undoped (or low-doped) layers are non-porous or substantially non-porous, and a sub-mirror structure, A first n-doped semiconductor layer on top of the substructure, Emissive structures containing multiple quantum wells (MQWs) on a semiconductor layer, A p-doped first semiconductor layer on top of an emissive structure, Approximately 1 × 10⁻¹⁶ layers on the first p-doped semiconductor layer. 18 cm -3 A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10⁻¹⁶ layers on a second semiconductor layer doped with p. 18 cm -3 A second n-doped semiconductor layer having a higher n-doping level, An n-doped current-diffusing layer on top of a second n-doped semiconductor layer, Equipped with, An aperture region exists, and the electrical conductivity of a portion of the p-doped first semiconductor layer within the aperture region is greater than the electrical conductivity of the p-doped first semiconductor layer outside the aperture region. A first p-doped semiconductor layer, an optionally p-doped second semiconductor, and an optionally n-doped second semiconductor have higher electrical resistance outside the aperture region compared to within the aperture region. The current diffusion layer is conductive both inside and outside the aperture region. The current diffusion layer optionally includes a region on the upper surface above the aperture region, which is raised and forms a step feature that results in a light confinement effect.

[0086] A non-limiting example of the light-emitting structure 600 having the DBR mirror described above is shown in Figure 12. The aperture region defines a part of the light-emitting structure formed by several parts of several specific layers, as discussed above and as shown in Figure 12. The aperture region is formed by ion implantation, where an ion implantation mask prevents the conductivity of the structural region beneath the mask from being impaired when exposed to and implanted with ions. The region protected by this mask defines the aperture region, which includes at least 645, 655, and 665 that have not been ion-implanted, as shown in Figure 12. For at least the n-doped current-diffusing layer, conductivity is restored by annealing following ion implantation outside the aperture region. The aperture region discussed provides a current-trapping effect when the light-emitting structure having the DBR mirror and aperture region is used in optoelectronic applications, because the implanted region of the p-doped first semiconductor remains resistive. Furthermore, an etching process using the same mask as ion implantation can create the presence of arbitrary step-like features 680 above the aperture region, which can result in a photoconfinement effect, causing the laser oscillation modes to overlap more with the aperture region.

[0087] For certain semiconductor materials that form part of the light-emitting structure, such as layers of p-doped and n-doped second semiconductors, there are minimum doping concentrations as detailed above. For the remaining p-doped or n-doped layers mentioned, the p-doping concentration levels or n-doping concentration levels are not particularly limited. In some examples, different p-doped or n-doped layers each independently have a minimum doping concentration of at least about 1 × 10⁻⁶. 19 cm -3 The above, or approximately 0.1 × 10 19 cm -3 ~10×10 20 cm -3 It may have high doping concentration levels in the range of approximately 1 × 10⁻⁶. In some cases, high doping concentration levels may be approximately 1 × 10⁻⁶. 19 cm -3 , 2×10 19cm -3 , 3 x 10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , or 10 x 10 19 cm -3 This may also be the case. In some other examples, different p-doped or n-doped layers are each independently approximately 1 × 10⁻⁶ 18 cm -3 Larger 1 x 10 20 cm -3 Less than 2 × 10 18 cm -3 ~1 × 10 20 cm -3 Less than 3 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than 4 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than, or 5 × 10 18 cm -3 ~1 × 10 20 cm -3 It may have a moderate doping concentration level of less than 1 × 10⁻⁶. In some examples, a moderately doped concentration level is 1 × 10⁻⁶. 19 cm -3 ~1 × 10 20 cm -3 The range of less than, or approximately 0.5 × 10 19 cm -3 ~10×10 19 cm -3 This is within the range. In some cases, a moderate doping concentration level is approximately 1 × 10⁻⁶. 18 cm -3 , 2×10 18 cm -3 , 3 x 10 18 cm -3 , 4×1018 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , or 10 x 10 18 cm -3 This may also be the case. However, in yet another example, different p-doped or n-doped layers are each independently approximately 20 × 10 17 cm -3 Less than, or approximately 0.5 × 10 17 cm -3 ~10×10 17 cm -3 It may have low doping concentration levels in the range of . In some cases, low doping concentration levels are about 1 × 10 17 cm -3 , 2×10 17 cm -3 , 3 x 10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3 , 6×10 17 cm -3 , 7×10 17 cm -3 , 8×10 17 cm -3 , 9×10 17 cm -3 , or 10 x 10 17 cm -3 That's fine.

[0088] In some examples, the semiconductor substrate is preferably made of indium phosphide, and the first p-doped semiconductor layer is made of p-doped InAlAs or p-doped InAlGaAs. In other examples, the semiconductor substrate may be made of other semiconductor materials such as GaAs or GaSb. The selection of the semiconductor material should be made to ensure that it is lattice-matched to the selection of the semiconductor substrate.

[0089] In some examples, the alternating layers of the substructure contain or are formed of a binary semiconductor material (such as indium phosphide) that is lattice-matched to the semiconductor substrate. In some other examples, the alternating layers of the substructure contain or are formed of a ternary semiconductor material that is lattice-matched to the semiconductor substrate. In yet another example, the alternating layers of the substructure contain or are formed of a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

[0090] In some examples, the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current diffusion layer each independently comprises or is formed of one or more materials lattice-matched to the semiconductor substrate. In some examples, the one or more materials are, for example, lattice-matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb, but are not limited to these.

[0091] In other examples, the emissive structure, the p-doped second semiconductor, and the n-doped second semiconductor each independently comprise one or more materials that are lattice mismatched to the indium phosphide semiconductor substrate. In such examples, one or more materials can be selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb.

[0092] In some cases, non-limiting examples of binary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in one or more layers named above is preferably based on the lattice matching of the semiconductor material of the layer of a given structure to a selected semiconductor substrate that can be manufactured from one of InP, GaAs, or GaSb. Those skilled in the art will be able to select appropriate semiconductor materials for each lattice-matched layer on the semiconductor substrate, as well as desired doping types and doping concentration levels, as detailed above.

[0093] In some examples, the layers of the p-doped first semiconductor, optionally a p-doped second semiconductor, and optionally an n-doped second semiconductor outside the aperture region have electrical conductivity about one to four orders of magnitude lower than that inside the aperture region. The selection of the material forming the layer of the p-doped first semiconductor should preferably be a material that, upon ion implantation, experiences a decrease in conductivity (becomes more resistive) compared to before ion implantation, and whose electrical conductivity does not recover or recovers only significantly when annealed at high temperatures. "Recovers significantly," as used herein, means a recovery of less than about 50%, less than about 40%, less than about 30%, less than about 20%, less than about 10%, less than about 5%, or less than 1% of the original electrical conductivity of the material before ion implantation.

[0094] In some examples, the porosity present in the n-doped layer of a porous substructure is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0095] The porous n-doped semiconductor layer of the underlying structure has multiple pores, and air can fill these pores, thereby lowering the refractive index of the porous semiconductor layer compared to the unporous or substantially unporous undoped semiconductor layer. In some examples, a refractive index contrast (Δn) exists between the alternating layers after porosity, which ranges from approximately 0.1 to approximately 2, or from approximately 0.1 to approximately 2.5.

[0096] The layers and structures of the light-emitting structures described above may have any suitable dimensions, shapes, and thicknesses that are appropriate for their use. In some examples, different structures and layer thicknesses may be as follows:

[0097] [Table 2]

[0098] It is understood that the thickness of the above structure, which can be used to fabricate a VCSEL from such a light-emitting structure that incorporates a DBR internally, can also specify the thickness of those layers.

[0099] In some examples, for light-emitting structures, the n-doped semiconductor layers within the alternating layers each have the same thickness, and / or the undoped (or low-doped) semiconductor layers within the alternating layers each have the same thickness. It is possible for the n-doped semiconductor layers and the undoped (or low-doped) semiconductor layers to have the same or different thicknesses.

[0100] In some examples, the aperture region is provided together with a mesa structure, as shown in Figure 12. In such examples, the dimensions of the mesa structure are selected to be larger than the dimensions of the aperture region.

[0101] A non-limiting method for manufacturing such a light-emitting structure comprising a DBR mirror and an aperture region formed by ion implantation is: (a) A step of providing or forming a light-emitting structure, wherein the light-emitting structure is A substructure comprising alternating layers of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers on a semiconductor substrate, A first n-doped semiconductor layer on top of the substructure, An emissive structure containing multiple quantum wells (MQWs) on a first semiconductor layer, A p-doped first semiconductor layer on top of an emissive structure, Approximately 1 × 10⁻¹⁶ layers on the first p-doped semiconductor layer. 18 cm -3 A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10⁻¹⁶ layers on a second semiconductor layer doped with p. 18 cm -3 A second n-doped semiconductor layer having a higher n-doping level, An n-doped current-diffusing layer on top of a second n-doped semiconductor layer, A process that includes, (b) A step of placing a masking material on the upper surface region of the current diffusion layer of the structure, (c) A step of performing ion implantation to reduce the conductivity of at least p-doped first semiconductor layers that are not covered by the masking material, (d) A step of etching a portion of the current diffusion layer, wherein the etching does not remove the current diffusion layer located beneath the masking material. (e) The process of removing the masking material, (f) A step of depositing a first layer of silicon dioxide on a portion of the current diffusion layer to cover at least the area where the masking material was present, (g) A step of annealing the structure to increase the electrical conductivity of the current diffusion layer, (h) A step of forming a mesa structure by etching a current diffusion layer, an n-doped second semiconductor, a p-doped second semiconductor, a p-doped first semiconductor, and a portion of the emissive structure that are not covered by the first silicon dioxide layer, (i) A step of depositing a second layer of silicon dioxide over a mesa structure, wherein at least a portion of the n-doped first semiconductor layer is not covered by the second layer of silicon dioxide. (j) A step of etching the structure not covered by the second layer of silicon dioxide to form a trench that exposes the side walls of the alternating layers of the substructure, (k) A step of selectively porousizing an n-doped semiconductor layer in an alternating layer of a substructure, wherein the formed pores contain air, and the undoped semiconductor layer remains non-porous or substantially non-porous. (l) A step of depositing one or more materials to cover the trench, sidewalls, and sidewalls of the mesa structure, (m) If covered by one or more materials, a step of selectively removing one or more materials to expose at least a portion of the upper part of the mesa structure and optionally a portion of the semiconductor layer, (n) A step of forming a metal contact on a part of the upper part of the mesa structure and optionally on a part of the semiconductor layer, It can include...

[0102] Details for fabricating the substructure are provided in Section IV below. An exemplary scheme of the above method is shown in Figure 10. The process in Figure 10 begins with a structure 400 as shown in Figure 9. Figure 10 shows the process in which a masking material is placed on the top layer to protect the area below from ion implantation 530. Annealing is used to selectively restore the conductivity of the top layer of at least n-doped material, as described in Example 2.

[0103] Methods for depositing / forming emissive structures containing multiple quantum wells (MQWs) are known in the art.

[0104] The structures and layers formed or deposited by the above method may each be independently formed or deposited by deposition methods known in the art, including metal-organic vapor deposition (MOCVD). The selection of precursors, p-dopants or n-dopants, and conditions for forming and doping such structures and layers to a specified thickness is known in the art.

[0105] With respect to annealing in step (g), annealing can be carried out at any suitable high temperature and duration necessary to increase the electrical conductivity of the ion-implanted current diffusion layer. In some examples, annealing restores the electrical conductivity of the ion-implanted current diffusion layer to at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or more compared to the electrical conductivity of the current diffusion layer before ion implantation. In some examples, the annealing temperature may be in the range of about 250°C to about 450°C, and a sub-range or individual temperature within that range. Annealing may be applied for a time in the range of about 1 minute to 1 hour or 1 minute to 30 minutes, and a sub-range or individual time within that range. In some examples, such as when an n-InP current diffusion layer is used, the annealing temperature may be 350°C and an annealing time of about 20 minutes is applied to restore conductivity to the current diffusion layer.

[0106] With respect to the mesa structure formed in process (h), the dimensions of the mesa structure are selected to be larger than the dimensions of the aperture region. In other words, the mesa structure has an aperture region inside it. The mesa structure can be formed, for example, by wet etching or plasma etching (e.g., RIE etching).

[0107] For certain semiconductor materials that form part of the light-emitting structure, such as the p-doped second semiconductor and the n-doped second semiconductor layers, there are minimum doping concentrations as detailed above. For the remaining p-doped or n-doped layers mentioned, the p-doping concentration levels or n-doping concentration levels are not particularly limited. In some examples, the different p-doped or n-doped layers each independently have a minimum doping concentration of at least about 1 × 10⁻⁶. 19 cm -3 The above, or approximately 0.1 × 10 19 cm -3 ~10×10 20 cm -3 It may have high doping concentration levels in the range of approximately 1 × 10⁻⁶. In some cases, high doping concentration levels may be approximately 1 × 10⁻⁶. 19 cm -3 , 2×10 19 cm -3 , 3 x 10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , or 10 x 10 19 cm -3 This may also be the case. In some other examples, different p-doped or n-doped layers are each independently approximately 1 × 10⁻⁶ 18 cm -3 Larger 1 x 10 20 cm -3 Less than 2 × 10 18 cm -3 ~1 × 10 20 cm -3 Less than 3 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than 4 x 10 18 cm -3 ~1 × 10 20 cm -3Less than, or 5 × 10 18 cm -3 ~1 × 10 20 cm -3 It may have a moderate doping concentration level of less than 1 × 10⁻⁶. In some examples, a moderately doped concentration level is 1 × 10⁻⁶. 19 cm -3 ~1 × 10 20 cm -3 The range of less than, or approximately 0.5 × 10 19 cm -3 ~10×10 19 cm -3 This is within the range. In some cases, a moderate doping concentration level is approximately 1 × 10⁻⁶. 18 cm -3 , 2×10 18 cm -3 , 3 x 10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , or 10 x 10 18 cm -3 This may also be the case. However, in yet another example, different p-doped or n-doped layers are each independently approximately 20 × 10 17 cm -3 Less than, or approximately 0.5 × 10 17 cm -3 ~10×10 17 cm -3 It may have low doping concentration levels in the range of . In some cases, low doping concentration levels are about 1 × 10 17 cm -3 , 2×10 17 cm -3 , 3 x 10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3, 6×10 17 cm -3 , 7×10 17 cm -3 , 8×10 17 cm -3 , 9×10 17 cm -3 , or 10 x 10 17 cm -3 That's fine.

[0108] In some examples, the masking material in step (b) is selected from the group consisting of, but not limited to, dielectrics (such as silicon dioxide, silicon nitride, and aluminum oxide), metals (such as nickel), and / or photoresists. Such materials may be formed by various methods such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

[0109] For the methods described, patterning, etching, or removal of any material may be carried out by any suitable technique, such as wet chemical etching, plasma etching, or inductively coupled plasma reactive ion etching (ICP-RIE), as needed.

[0110] In several examples, suitable semiconductor materials for the n-doped first semiconductor layer, the p-doped first semiconductor layer, the p-doped second semiconductor layer, the n-doped second semiconductor layer, and the current diffusion layer of the light-emitting structure are discussed in detail in Section IIIa above.

[0111] With respect to the method described, the layers, structures, and overall luminescent structures formed according to this method may have any preferred dimensions, shapes, and thicknesses. Exemplary and non-limiting thicknesses of the overall structure and layers are given in Table 2.

[0112] In some examples of this method, one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, silicon nitride, and spin-on glass, and / or one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist, or combinations thereof. With respect to the methods described, the deposition of the silicon dioxide and one or more material layers may be formed by various methods, such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

[0113] In some examples of this method, the porosity formed in step (k) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

[0114] In some examples of this method, step (k) is carried out by electrochemical etching in an electrolyte solution under an applied bias voltage. In some specific examples, the electrolyte solution may include halide ions, hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (e.g., oxalic acid and citric acid), and mixtures thereof.

[0115] In some examples of this method, the metal contact formed during step (n) is formed of or comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts are known to those skilled in the art.

[0116] i. Ion implantation Regarding ion implantation in step (c), this can be carried out based on the following details.

[0117] The masking material in step (b) can be formed from the material specified above. More specifically, the masking material can be described as an ion implantation masking material having any size, area, or shape for controllably selecting which surface area(s) to mask from ion implantation.

[0118] Such ion implantation masks can be formed using several methods. Some non-limiting examples include: (1) Photoresist method: A layer of photoresist is spin-coated onto a substrate. The photoresist mask layer can then be patterned into the desired shape using photolithography, electron beam lithography, or stamping techniques. Depending on the ion source and ion energy used, the mask layer can vary from less than approximately 1 μm to more than 10 μm, as needed. (2) Hard mask etching method: A hard mask layer of the material is deposited. This material may be a dielectric (e.g., silicon dioxide or silicon nitride) or a metal (e.g., titanium, aluminum). Depending on the material, various deposition techniques such as thermal deposition, electron beam deposition, sputtering, spin coating, chemical vapor deposition, and atomic layer deposition can be used. A layer of photoresist can then be spin-coated onto the deposited hard mask layer of the material and patterned. The hard mask layer of the material can then be removed by etching, either chemically or physically, to transfer the pattern from the photoresist to the layer of material beneath it. (3) Hard mask, lift-off method: Similar to the above technique (hard mask, etching method), but performed in the reverse order. First, a layer of photoresist is spin-coated and then patterned. Next, a hard mask layer is deposited on top of the photoresist using one of the techniques described in (2). Then, the photoresist is removed by etching, causing lift-off of the regions within the hard mask layer, thereby transferring the pattern to the hard mask layer.

[0119] In the ion implantation process, ion implantation is performed only in exposed areas of unmasked layers (which may be multiple). Ion implanted ions can originate from various ion sources. Many ion species and sources, such as aluminum, gold, nitrogen, hydrogen, helium, carbon, oxygen, titanium, and iron, can be used to modify (i.e., damage / reduce) the electrical conductivity of the ion-implanted area or region. In some examples, ions may be selected based on their higher atomic mass. For example, aluminum ions may be selected compared to hydrogen ions due to their larger atomic mass. The energy selected depends on the depth required for ion implantation. These energies can range from less than about 10 keV to more than about 1 MeV, controlling implantation at depths of less than about 10 nm to more than about 1 μm, about 10 nm to about 750 nm, about 10 nm to about 500 nm, about 10 nm to about 250 nm, about 10 nm to about 100 nm, or any preferred sub-range or individual depth range within those ranges disclosed herein. The ion dose can also be used to control the number of ions implanted and, consequently, the modification of electrical conductivity. A typical ion implantation dose is about 10, depending on the ion species and the desired depth. 12 cm -3 ~10 16 cm -3 The range may be, but is not limited to, these. The irradiation energy of the ion implantation source can be used to control the depth of ion implantation performed on the layer(s).

[0120] b. Optoelectronic device having an aperture region formed by ion implantation The above-described light-emitting structure, which includes a DBR and an aperture region, can be used in the fabrication of optoelectronic devices having an aperture region inside.

[0121] In some cases, optoelectronic devices are A light-emitting structure comprising a lower distributed Bragg reflector mirror and aperture region, Upper distributed Bragg reflector mirror, Metal contacts and It can be equipped with.

[0122] Regarding optoelectronic devices, the light-emitting structure comprises a lower distributed Bragg reflector (BDR) mirror and an aperture region, as described above. Non-limiting examples of optoelectronic devices such as VCSELs are shown in Figure 13.

[0123] In some examples, the upper distributed Bragg reflector is formed of or comprises alternating layers of one or a combination thereof of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, a-Si / CaF2.

[0124] In some examples, the metal contact is formed of or includes one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

[0125] In some cases, the optoelectronic device is a vertical-cavity surface-emitting laser (VCSEL). In some cases, a vertical-cavity surface-emitting laser operates at room temperature (approximately 25°C) and in continuous-wave mode.

[0126] In several other cases, vertical-cavity surface-emitting lasers operate at temperatures below approximately 0°C, above approximately 25°C, or above approximately 85°C. In yet another example, vertical-cavity surface-emitting lasers can operate in pulsed mode.

[0127] A vertical-cavity surface-emitting laser with an aperture region can emit light in the infrared and / or red wavelength regions, depending on the selection of the emissive structural material. In some cases, the vertical-cavity surface-emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

[0128] A non-limiting method for manufacturing optoelectronic devices having an aperture region is: (a') A step of providing or forming a light-emitting structure that includes a lower distributed Bragg reflector mirror and an aperture region, (b') A step of providing or forming an upper distributed Bragg reflector mirror on the light-emitting structure, (c') A step of providing or forming a metal contact on an optoelectronic device, It can include...

[0129] In the optoelectronic device formed according to the above method, the light-emitting structure comprises a lower distributed Bragg reflector (BDR) mirror and an aperture region, as described above. A non-limiting scheme for the process of fabricating optoelectronic devices such as VCSELs is shown in Figure 14.

[0130] In such a method, the upper distributed Bragg reflector mirror of step (b') may comprise alternating layers of one or a combination thereof of a-Si / SiO2, TiO2 / SiO2, Ta2O5 / SiO2, Nb2O5 / SiO2, ZnSe / SiO2, a-Si / Al2O3, a-Si / MgF, ZnS / MgF, and a-Si / CaF2. Methods for producing such a DBR having the aforementioned alternating layers are known in the art. The number of alternating layers in such a DBR may depend on the selected material. The upper DBR mirror may be deposited by means known in the art and may include annealing to increase reflectivity. In some examples, the upper DBR mirror has a reflectivity of at least about 97% or more.

[0131] Regarding the above method, the metal contact in step (c') may be formed of or contain one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

[0132] It is understood that, in any of the methods described in Section III, the order of certain steps may be interchangeable, to the extent permitted and without adversely affecting the structure or device formed. For example, steps (b') and (c') of the method for manufacturing an optoelectronic device may be carried out in any preferred order.

[0133] IV. Substructure and method for manufacturing and porous structure thereof The semiconductor structures and light-emitting structures described in Sections II and III, as well as the substructures of various structures such as optoelectronic devices, are described in detail below.

[0134] For the semiconductor structures 100, 100', 100''', 100'''', 100'''''', 10, and 400, each comprises a substructure having alternating layers of doped and undoped (or low-doped) semiconductor layers on a semiconductor substrate. The semiconductor substrate can be manufactured from, for example, indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb). In these particular structures, the n-doped semiconductor layer remains intact and has not yet undergone selective porosity treatment, such as by an electrochemical etching process.

[0135] In one example, a non-limiting exemplary substructure comprises a plurality of undoped or undoped (see below) semiconductor layers, which may be fabricated from layers of indium phosphide, gallium arsenide, or gallium antimonide, wherein at least one layer of n-doped semiconductor is located between at least two layers of undoped or undoped semiconductors, and which may be porousized by electrochemical etching (or electropolished).

[0136] The substructure comprises alternating layers of semiconductor layers on a semiconductor substrate. In some examples, a semiconductor substrate is selected, and a suitable semiconductor material lattice-matched to the substrate is selected, and alternating n-doped and undoped (or low-doped) semiconductor layers are formed. For example, the semiconductor substrate of the substructure may be manufactured from one of InP, GaAs, or GaSb. The semiconductor substrate and alternating layers of the substructure do not necessarily have to be manufactured from the same material, but preferably from lattice-matched materials, and it is understood that those skilled in the art can select this. The dimensions of the semiconductor substrate and the layers thereon (which may be more) (whether doped or undoped (or low-doped)) may be any dimensions, area, or shape suitable for a particular application. Typically, the semiconductor substrate and all layers thereon have equal dimensions, area, and shape. In some examples, the overall substructure has dimensions (i.e., length and width) of about 100 microns × 100 microns or less, and sub-ranges that fall within that range.

[0137] In some examples, the alternating layers of the substructure include or are manufactured from a binary semiconductor material selected from, but not limited to, indium phosphide, gallium arsenide, and gallium antimonide, and are lattice-matched to the semiconductor substrate. In some other examples, the alternating layers of the substructure include or are manufactured from a ternary semiconductor material that is lattice-matched to the semiconductor substrate. In yet another example, the alternating layers of the substructure include or are manufactured from a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

[0138] In some cases, non-limiting examples of binary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some cases, non-limiting examples of ternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some cases, quaternary semiconductor materials that can be p-doped or n-doped may be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in one or more layers named above is preferably based on the lattice matching of the semiconductor material of the layer of a given structure to a selected semiconductor substrate that can be manufactured from one of InP, GaAs, or GaSb. Those skilled in the art will be able to select appropriate semiconductor materials for each lattice-matched layer on the semiconductor substrate, as well as desired doping types and doping concentration levels, as detailed above.

[0139] In some examples, the substructure comprises at least 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or more pairs of n-doped semiconductor layers and undoped (or low-doped) semiconductor layers, which are in contact at least before electrochemical etching.

[0140] Those skilled in the art are familiar with methods for fabricating such substructures, for example, by methods known in the art, such as metal-organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE), to obtain epitaxial or homoepitaxial semiconductor layers doped with known reactants, dopants, and precursors, and undoped (or low-doped) semiconductor layers.

[0141] As shown in Figure 4, the substructure can be subjected to electrochemical (EC) etching conditions, in which the existing n-doped semiconductor layers are selectively porous, surrounded by undoped or low-n-doped semiconductor layers that remain non-porous or substantially non-porous under EC conditions, and multiple pores are formed within the adjacent n-doped semiconductor layers (where "substantially non-porous" means having a porosity of less than 25%, 20%, 15%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low-doped) layers). In some other examples, the multiple pores are aligned horizontally (i.e., parallel) to the planar direction of the n-doped semiconductor layers.

[0142] In some specific examples, the substructure is fabricated with a single type of doped semiconductor and an undoped (or low-doped) semiconductor. For example, the substructure can be fabricated with all indium phosphide layers, all gallium arsenide layers, or all gallium antimonide layers, which are doped alternately as described. However, it is also possible to mix different types of materials.

[0143] A well-doped n-doped semiconductor layer can be selectively electrochemically etched to selectively porous the doped semiconductor layer, or selectively electropolished (i.e., removed) the doped semiconductor layer or regions within it, as described below. Undoped or low-doped semiconductor layers are generally not electrochemically etched. Conditions for controlling the degree of porosity or enabling electropolishing are described in more detail below. Porosity and electropolishing do not require the removal of the entire n-doped semiconductor layer; only a portion or region of it may be porosified or electropolished in a given EC process. Porosity or electropolishing creates structures containing (air) pores or channels that may be formed horizontally as a result of selective lateral etching proceeding from one or more sidewalls of the underlying structure during EC etching.

[0144] Electrochemical etching requires that the n-doped semiconductor layer is doped with an n-type dopant. Therefore, the existing n-doped semiconductor layer is formed during deposition / formation. Exemplary dopants include, but are not limited to, n-type Ge dopants and Si dopants. Examples of such dopant sources include, for example, silane (SiH4), germane (GeH4), and isobutylgermane (IBGe). For an n-type doped layer, the n-type doping concentration may be uniform throughout the layer, or the doping concentration may form a gradient (i.e., a layer in which the dopant concentration gradients along the axis of the layer, such as the width direction). The doping concentration is at least about 1 × 10⁻⁶. 19 cm -3 The above, or approximately 0.1 × 10 19 cm -3 ~10×10 20 cm -3 A doping concentration level within this range is considered high. In some cases, a high doping concentration level is approximately 1 × 10⁻⁶. 19 cm -3 , 2×10 19 cm -3 , 3 x 10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , or 10 x 10 19 cm -3 It is possible. The doping concentration is approximately 1 × 10⁻⁶. 18 cm -3 Larger 1 x 10 20 cm -3 Less than 2 × 10 18 cm -3 ~1 × 10 20 cm -3 Less than 3 x 10 18 cm -3 ~1 × 1020 cm -3 Less than 4 x 10 18 cm -3 ~1 × 10 20 cm -3 Less than, or 5 × 10 18 cm -3 ~1 × 10 20 cm -3 A doping concentration level below 1 × 10⁻⁶ is considered moderate. In some cases, a moderately doped concentration level is 1 × 10⁻⁶. 19 cm -3 ~1 × 10 20 cm -3 The range of less than, or approximately 0.5 × 10 19 cm -3 ~10×10 19 cm -3 This is within the range. In some cases, a moderate doping concentration level is approximately 1 × 10⁻⁶. 18 cm -3 , 2×10 18 cm -3 , 3 x 10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , or 10 x 10 18 cm -3 It is possible. Moderate to high n-type doping is subject to electrochemical etching processes, which, depending on the conditions used during the electrochemical etching process, result in controlled porosity and / or electropolishing of the doped layer.

[0145] As described above, the substructure comprises an undoped semiconductor layer that is unaffected (porous or not etched) when the substructure is electrochemically etched. However, in some examples, the substructure may comprise a low-doped or low-doped semiconductor layer, where the doping concentration is approximately 20 × 10⁻⁶. 17 cm -3 Less than or approximately 0.5 × 10 17 cm -3 ~10×10 17 cm -3 A doping concentration level within this range is considered low. In some cases, a moderate doping concentration level is approximately 1 × 10⁻⁶. 17 cm -3 , 2×10 17 cm -3 , 3 x 10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3 , 6×10 17 cm -3 , 7×10 17 cm -3 , 8×10 17 cm -3 , 9×10 17 cm -3 , or 10 x 10 17 cm -3 It is possible.

[0146] The thickness of either an n-doped or undoped (low-doped) layer before electrochemical etching can independently range from approximately 50 nm to 500 nm (and any sub-range or individual thicknesses disclosed within that range). In some examples, the total thickness of the substructure before or after electrochemical etching can range from approximately 600 nm to approximately 8000 nm or from 600 nm to approximately 6000 nm, and any sub-range within that range. The dimensions and / or shape of the layers or semiconductor substrate can be any suitable shape / dimension required for the application. In some examples, with respect to the substructure, the n-doped semiconductor layers present in alternating layers are each identical or substantially identical in thickness to each other, and / or the undoped (or low-doped) semiconductor layers present in alternating layers are each identical or substantially identical in thickness to each other. "Substantially identical," as used herein, means that each particular layer differs in thickness from all other similar layers present by approximately 5%, 4%, 3%, 2%, 1%, or less, as described in the examples above. It is possible for the n-doped semiconductor layer and the undoped (or low-doped) semiconductor layer to have the same or different thicknesses.

[0147] Following electrochemical etching, undoped or low-doped semiconductor layers in the underlying structure are typically unaffected (i.e., non-porous or substantially non-porous, where "substantially non-porous" means having a porosity of less than 25%, 20%, 15%, 10%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low-doped) semiconductor layer). In some examples of this method, unintended porosity of the undoped (or low-doped) semiconductor layer may occur, in which case even low n-doped semiconductor layers may become porous during EC etching.

[0148] Following electrochemical etching, the n-doped semiconductor layer in the underlying structure becomes more porous compared to before electrochemical etching. High porosity can be considered to occur if the layer contains at least one portion with a porosity of approximately 10% to 90%, or more. In some examples, the porosity is at least approximately 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% or more. The incorporation of low refractive index materials such as air into the layer (or a portion thereof) through porosity has the effect of reducing the refractive index compared to the bulk semiconductor layer before porosity.

[0149] For n-doped semiconductor layers, electrochemical etching can yield different degrees of porosity and pore morphology by changing the type and concentration of the electrolyte, the n-doping concentration of the layer, and the applied bias voltage, as will be discussed in detail below.

[0150] Using electrochemical etching, lateral or horizontal pores can be selectively fabricated in the porous, n-doped semiconductor layer of the underlying structure. These are formed selectively from the side of the multilayer structure. Without limitation, the lateral or horizontal pores formed during the electrochemical etching process can have any suitable length. The porous semiconductor layer (or regions therein) contained within the multilayer structure is preferably nanoporous, but can be further defined as microporous, mesoporous, or macroporous, or any combination thereof. The porous layer or regions therein can be further classified as microporous (d < 2 nm), mesoporous (2 nm < d < 50 nm), or macroporous (d > 50 nm), where d is the average pore diameter. The morphology of the pores contained in the layer or regions therein can also be classified as circular, semi-circular, elliptical, or any combination thereof. The pores can have an average size (i.e., length) of about 5 nm to 100 nm, 5 nm to 75 nm, 5 nm to 50 nm, or 5 nm to 25 nm. In some examples, the average pore size is about 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or more. In some examples, based on the original doping concentration, the etchant used, and the applied voltage during the electrochemical porosification process, the average size of the pores can range from less than about 20 nm to greater than 50 nm. The spacing between any adjacent pores (which also defines the scale of the pore wall thickness) can range from about 1 nm to 50 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 25 nm, 5 nm to 20 nm, 5 nm to 15 nm, or 5 nm to 10 nm.

[0151] In a given substructure, all or part of the doped semiconductor layer may become porous during electrochemical etching. In some examples, the electrochemical etching proceeds from the sidewalls, and the degree of porosity of the layer is at least about 10%, 20%, 30%, 40%, 50%, 60%, 80%, or 90% of the longest planar dimension of the doped layer. In some other examples, if electropolishing occurs, the degree of electropolishing of the layer is at least about 10%, 20%, 30%, 40%, 50%, 60%, 80%, or 90% of the longest planar dimension of the doped layer. Porosity may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process. Electropolishing may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process.

[0152] As described above, in some examples, the n-doped semiconductor layer is removed (completely removed) by electropolishing, resulting in little to no material remaining between the undoped (or low-doped) layers where the doped semiconductor material previously existed. The dimensions of the void spaces formed by electropolishing depend on the dimensions of the doped semiconductor layer and the degree of material removed by electropolishing. In some examples, electropolishing can create lateral or horizontal (air) pores or channels between the undoped layers from which the doped material has been removed.

[0153] a. Optical properties of the substructure By selectively incorporating low-refractive-index materials such as air into selected regions or layers of the underlying structure through electrochemical etching, the refractive index can be reduced compared to the bulk semiconductor constituting the structure. Therefore, it is possible to selectively adjust the refractive index of porous regions within the underlying structure.

[0154] For example, in a substructure formed of InP before electrochemical etching, each layer has a refractive index of approximately 3.2. Electrochemical etching can selectively porousize or completely electropolish the n-doped InP layers, thus reducing the refractive index to less than 3.2. In some cases, the refractive index of the porous InP layer is approximately 1.5–2.7. If the InP layer is removed by electropolishing, the refractive index becomes approximately 1. As a result, the refractive index contrast (Δn) between InP layers after electrochemical etching can range from approximately 0.1 to approximately 2. In some cases, the refractive index contrast (Δn) is at least approximately 1.1, 1.2, 1.3, 1.4, or 1.5. In yet another case, the refractive index contrast ratio (Δn) is at least approximately 1.5.

[0155] Prior to electrochemical etching, each layer in the GaAs-formed substructure has a refractive index of approximately 3.95. Electrochemical etching can selectively porousize or completely electropolish the doped InP layer, thus reducing the refractive index to less than 3.95. In some examples, the refractive index of the porous GaAs layer is approximately 1.5–3.4. If the GaAs layer is removed by electropolishing, the refractive index becomes approximately 1. As a result, the refractive index contrast (Δn) between GaAs layers after electrochemical etching can range from approximately 0.1 to approximately 2.5. In some examples, the refractive index contrast (Δn) is at least approximately 1.1, 1.2, 1.3, 1.4, or 1.5. In yet another example, the refractive index contrast ratio (Δn) is at least approximately 1.5.

[0156] Prior to electrochemical etching, in the GaSb-formed substructure, each layer has a refractive index of approximately 3.85. Electrochemical etching can selectively porousize or completely electropolish the doped InP layer, thus reducing the refractive index to less than 3.85. In some examples, the refractive index of the porous GaAs layer is approximately 1.2–3.4. If the GaAs layer is removed by electropolishing, the refractive index becomes approximately 1. As a result, the refractive index contrast (Δn) between GaAs layers after electrochemical etching can range from approximately 0.1 to approximately 2. In some examples, the refractive index contrast (Δn) is at least approximately 1.1, 1.2, 1.3, 1.4, or 1.5. In yet another example, the refractive index contrast ratio (Δn) is at least approximately 1.5.

[0157] The substructure can function as a mirror and can demonstrate a reflectivity of at least approximately 99%, 99.1%, 99.2%, 99.3%, 99.4%, 99.5%, 99.6%, 99.7%, 99.8%, or 99.9%.

[0158] b. Method of electrochemical (EC) etching of the substructure As explained above, methods for forming alternating layers of doped semiconductor layers and undoped (or low-doped) semiconductor layers are known in the art. A non-limiting example of a method for forming the underlying structure is: (a) A step of forming a first layer of undoped or low-doped semiconductor on a semiconductor substrate, (b) A step of depositing a second layer of n-doped semiconductor on the first layer, (c) A step of depositing a third layer of undoped or low-doped semiconductor on the second layer, (d) A step of optionally repeating steps (b) and (c) to form additional alternating layers of n-doped semiconductor and undoped or low-doped semiconductor, It can include...

[0159] The formed substructures can be used to fabricate other structures, as shown in Figures 2, 4, and 10. In such processes, they can be subjected to electrochemical (EC) etching, as shown in Figures 4 and 10.

[0160] Electrochemical (EC) etching of an n-doped semiconductor layer, performed in the presence of an electrolyte and under an applied bias voltage, can selectively porous or electropolish at least a portion of the existing n-doped semiconductor.

[0161] Porosity formation and / or electropolishing that occur during electrochemical (EC) etching processes can be controlled based on the electrolyte concentration, doping concentration, and applied bias voltage (discussed below). The applied bias voltage is typically a positive voltage in the range of approximately 0.1V to 10V, 1.0V to 5V, or 1.0V to 2.5V. In some examples, based on the original doping concentration and the type of etchant used, the applied bias ranges from less than approximately 1V to at least approximately 10V. In some examples, when lower relative doping concentrations (sometimes multiple) are used, porosity can be selectively minimized, in one non-limiting example where the doping concentration in the sample is 5 × 10⁻⁶. 18 cm -3 If so, the doping concentration is 2 × 10 19 cm -3Compared to the case where both are etched under the same conditions, the porosity will be lower. This can be generally expected for all relative concentration differences. This is because, given all other electrochemical etching parameters constant, higher doping concentrations are expected to result in greater porosity compared to lower relative doping concentrations. In some examples, depending on the choice of electrolyte concentration, doping concentration, and applied bias voltage(s), electrochemical etching conditions can selectively and controllably result in either only porosity (introducing about 30% to 90% or more porosity) or complete electropolishing (i.e., total or near-total removal (i.e., removal of more than 95%, 96%, 97%, 98%, or 99% of the doped material)). The direction of the electric field during the EC etching process can be used to control the etching direction, thereby controlling the direction of the pores etched into the n-doped semiconductor layer. For example, the EC etching direction is dependent on the electric field direction and can be determined by the electric field direction. EC etching preferably results in a transverse etching direction. The etching rate in the lateral direction can be approximately 0.1 μm / min, 0.2 μm / min, 0.3 μm / min, 0.4 μm / min, 0.5 μm / min, 0.6 μm / min, 0.7 μm / min, 0.8 μm / min, 0.9 μm / min, 1 μm / min, 2 μm / min, 3 μm / min, 4 μm / min, 5 μm / min, 6 μm / min, 7 μm / min, 8 μm / min, 9 μm / min, 10 μm / min, 20 μm / min, 30 μm / min, 40 μm / min, or 50 μm / min.

[0162] EC etching can be performed under an applied bias voltage for approximately 1 minute to 24 hours, 1 minute to 12 hours, 1 minute to 6 hours, 1 minute to 4 hours, 1 minute to 2 hours, 1 minute to 1 hour, or 1 minute to 30 minutes. In some examples, EC etching is performed under an applied bias voltage for at least approximately 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 10 hours, 15 hours, 20 hours, 24 hours, or longer. EC etching can be performed under an applied bias voltage at room temperature or at temperatures in the range of approximately 10°C to approximately 50°C. EC etching can be performed under an applied bias voltage under ambient conditions or optionally in an inert atmosphere (such as nitrogen or argon).

[0163] EC etching can be carried out in different types and concentrations of highly conductive electrolytes (either salts or acids). Exemplary highly conductive electrolytes may include, but are not limited to, halide ions (fluorides, chlorides, bromides, iodides), hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (e.g., oxalic acid and citric acid), and mixtures thereof. The concentration of the electrolyte in a highly conductive electrolyte solution (typically aqueous) can range from about 0.1 M to 10 M. In some other examples, the concentration of the electrolyte in a highly conductive electrolyte solution (typically aqueous) can be defined as the percentage (volume / volume) of the electrolyte relative to the solvent (which may be multiple) (e.g., water) in which it is dissolved, and can range from about 0.1 vol% to 30 vol%. In further examples, the concentration of an electrolyte in a highly conductive electrolyte solution (typically aqueous) can be defined as the percentage (by weight / volume) of the electrolyte relative to the solvent in which it is dissolved (which may be multiple) (e.g., water), and can range from approximately 0.1% by weight to 30% by weight. The electrolytes listed above do not normally etch semiconductors such as InP, GaAs, or GaSb at room temperature, but can etch semiconductors such as InP, GaAs, or GaSb under applied electrochemical anodic conditions.

[0164] Electrochemical etching as described herein is thought to proceed, for example, laterally from the edges of exposed sidewalls (which may be multiple), preferentially forming horizontal pores. Lateral etching causes porosity, forming pores, typically nanopores, horizontally or primarily horizontally within the doped layer. The substructure has a vertical axis from bottom to top, with planar layers in which doped and undoped (or low-doped) semiconductors are alternately arranged. When EC etching is induced, porosity of the n-doped layer occurs perpendicular to the vertical axis or primarily perpendicular. "Primarily perpendicular," as used herein, refers to pores that, on average, are oriented within approximately 20, 15, 10, or 5 degrees from the perpendicular / horizontal plane relative to the vertical axis. In other words, porosity occurs along, or primarily along, a horizontal direction parallel or nearly parallel to the planar direction of the doped layer. For the substructure, after electrochemical etching, there may be very few, if any, pores aligned perpendicular to the vertical axis. The pores do not need to be aligned with the vertical axis of the substructure. In some examples, vertically aligned pores are not formed in the doped layer, and only horizontal pores are formed during electrochemical etching. In some examples, substantially non-porous undoped (or low-doped) InP, GaAs, or GaSb also have nanopores formed along the crystallographic direction, which are tilted at a 45-degree angle from the vertical and horizontal directions. In some other examples, it can be said that while macroscopically nanopores formed in n-doped semiconductors propagate laterally during porosification, microscopically nanopore generation can occur along specific crystallographic directions (e.g., tilts of +45° and -45° from the doped layer surface).

[0165] Electrochemical etching generally consists of the processes of oxide formation and removal (Quill, N., et al. (2013). ECS transactions, 58(8), 25-38). The presence of free holes at the semiconductor / electrolyte interface is important for oxidation, and the formed oxide is thought to be readily soluble in various electrolytes. Free holes are supplied by electric field-assisted tunneling, and their amount depends mainly on the anode bias and doping concentration. In some examples, electrochemical (EC) etching conditions do not result in EC etching at low anode bias and / or low doping concentrations (low doping as described above), but electropolishing (i.e., complete etching) is observed at high bias and / or high n-doping concentrations. Porosity is observed at intermediate bias and / or doping concentrations.

[0166] V. Structure and Method of Using Optoelectronic Devices Various structures and optoelectronic devices described herein, such as light-emitting structures with DBR mirrors and VCSELs, can be used in a variety of applications, including those in electronics, photon optics, and optoelectronics. Exemplary applications, though not limited to these, may include: low-power on-chip laser sources for photonic-electronic integrated circuits; eye-safe optical sensing systems based on VCSELs and VCSEL arrays; low-cost optical links based on single-mode fiber for distances exceeding 1 km; free-space (last-mile or indoor personal network) optical communications for 6G mobile and optical wireless networks; the Internet of Things; low-cost optical detection and ranging systems; and devices and systems for biomedical sensing and diagnostics.

[0167] In particular, the VCSELs described may provide long-wavelength emission (i.e., emission at red, near-infrared, or infrared wavelengths from 900 nm to 3000 nm, as well as at subranges and individual wavelengths within that range). In some specific examples, the VCSELs described may emit at specific wavelengths or wavelength ranges such as about 650 nm, about 850 nm to about 940 nm, about 1300 nm to about 1600 nm, or about 2000 nm to about 2400 nm. In some examples, the VCSELs may emit in the red wavelength range of the spectrum. VCSELs generally have important applications in a variety of fields, including information processing, microdisplays, picoprojection, laser headlamps, high-resolution printing, biophotonics, spectroscopic probing, and atomic clocks.

[0168] The various VCSELs described can offer optical and electrical performance that provides advantages over more commonly used end-emitting laser diodes (EELDs), such as superior beam quality, a compact form factor, lower operating power, cost-effective wafer-level testing, higher yield in manufacturing, and lower costs.

[0169] The present invention can be further understood by reference to the following non-limiting embodiments. [Examples]

[0170] Example 1: Nanoporous Vertical Cavity Surface Emitting Laser (VCSEL) with Embedded Tunnel Junction (BTJ) Materials and methods: A semiconductor structure 100 having an embedded tunnel junction (BTJ), as shown in Figure 1, was prepared starting from an epitaxially grown structure 10, as shown in Figure 2 (top row, far left). All layers were grown planar and continuously. From bottom to top, structure 10 consists of the following six parts: (1)n + - Indium phosphide (InP) (darker band, doping concentration: 5 × 10⁻¹⁶) 18 cm -3 )n --InP (brighter bandwidth, mild doping, doping concentration: 5 × 10⁻¹⁰) 18 cm -3 A stack of 12 pairs of alternating layers (less than n) + -InP can be porousized by electrochemical etching to form a nanoporous (NP)-InP layer having a low refractive index (lower than the refractive index of the layer before porosification), stack 110; (2) A thick n-InP layer of at least about 200 nm (light gray, doping concentration: 5 × 10⁻¹⁶) 17 cm -3 (3) Layer 120 of the InAlGaAs, which constitutes the majority of the volume of the structure; (4) Layer 140 of p-InP (doping concentration: 5 × 10) 17 cm -3 );(5)p ++ - InGaAs layer 150 (doping concentration 1 × 10) 19 cm -3 (6)n ++ - InGaAs layer 160 (black, doping concentration 1 × 10⁻¹⁶) 19 cm -3 (Super). Structure 10 was grown by metal-organic vapor deposition (MOCVD).

[0171] The semiconductor structure 100 shown in Figure 1 is arranged from bottom to top as follows: (1)n + - Indium phosphide (InP) and n - - A stack of 12 pairs of alternating layers with InP 110; (2) a layer of thick n-InP layers 120 nm thick; (3) an emissive structure of InAlGaAs 130 providing an active region having a target emission wavelength of 1550 nm; (4) a layer of p-InP 140; (5) p ++ - InGaAs layer 150 and n ++ -The embedded tunnel junction is formed with an InGaAs layer 160, (6) a current diffusion layer 170 encloses the embedded tunnel junction, and optionally (7) the surface of the current diffusion layer is nonplanar, which can form a step feature 180 and result in a light confinement effect.

[0172] Figure 2 shows a non-limiting schematic diagram of the process for fabricating the BTJ structure, starting from structure 10. The process was carried out by patterning a masking material on the top surface of structure 10 (Figure 2, top row, center). Next, wet etching with a mixture of citric acid and hydrogen peroxide was performed to remove the portions of layers 150 and 160 outside the masked area (Figure 2, top row, far right). After the mask was removed (Figure 2, bottom row, far left), a layer of n-InP (layer 170 in Figure 1) was regrown to embed the patterned tunnel junction underneath (Figure 2, bottom row, far right). At the end of the process, as shown in Figure 1, a small area was created, surrounded by layer 150 (p ++ -InGaAs) and layer 160(n ++ A tunnel junction with -InGaAs) is formed. The formed BTJ structure is thought to result in the following: 1) Current is injected mainly through the region containing the BTJ (this region may also be called the aperture region). In optoelectronic devices, only the region with carrier injection emits light and provides optical gain for laser oscillation. Therefore, the confined current injection is thought to lead to gain guidance for optical confinement. 2) After regrowth to form layer 170, the process results in the upper surface of the unplanarized semiconductor structure 100. In other words, the upper surface of the BTJ or aperture region is higher than the surrounding surface of the remaining layer 170 and can be considered a step feature 180 present on the structure that brings about the optical confinement effect in the optoelectronic device formed using the structure 100.

[0173] A light-emitting structure 200, which incorporates a distributed Bragg reflector (DBR) mirror as shown in Figure 3, was fabricated starting from the semiconductor structure 100 discussed above. The fabrication process for providing a light-emitting structure with an internal DBR is shown in Figure 3. A mesa structure was formed from the semiconductor structure 100 (Figure 4, top row, far left) through an etching process. The etching process could be either wet etching (dilute HCl, followed by citric acid and H2O2) or dry etching (Figure 4, top row, center), and the lower part of the mesa structure was located in layer 120. A layer 30 of SiO2 deposited by plasma-enhanced chemical vapor deposition (PECVD) was formed and patterned to cover most of the top surface except for the left portion (Figure 4, top row, far right). In other words, SiO230 was deposited on top of the entire mesa structure, with only the edges of the top surface on the side walls not covered by SiO230. The purpose of SiO230 was 1) to function as a dry etching mask for the next step in the process, and 2) to prevent the structure within the mesa from being attacked during the subsequent electrochemical (EC) etching process. Next, deep dry etching (8 sccm CH4, 4 sccm H2, 10 sccm Cl2, at 100 W HF power and 1200 W ICP power) was performed using SiO230 as a mask to form a trench reaching the bottom of stack 110 (Figure 4, middle, far left). Next, the structure (anode) and platinum (Pt) wire / plate (cathode) were immersed in the electrolyte and electrochemical (EC) etching was performed (Figure 4, middle, center). By applying a forward bias to the structure, EC etching was initiated from the trench sidewalls. The porous region (dark region) expanded laterally to cover the entire BTJ or aperture region above. Porousing occurred in the n of stack 110. + -Note that this was limited to the InP layer only, and the lightly doped InP layer remained intact (non-porous). Selectivity between porous and non-porous regions was achieved through differences in doping concentration. As a result of porosity, n +- The InP layer was filled with air, resulting in a lower refractive index compared to a lightly doped InP layer. The alternating structure with high and low refractive index layers forms mirrors in the DBR structure, which is used to form VCSELs.

[0174] Following the selective porosification of the stack, another layer 40 of PECVD SiO2 was deposited on the porous sample (Figure 4, middle, far right). The purpose of layer 40 was to cover and protect the entrance of the porous stack, which is nanoporous (NP)-InP. However, since PECVD SiO2 is known to cause leakage current, particularly through the mesa sidewalls (Jpn. J. Appl. Phys. 38 1195 (1999)), the SiO2 of layers 30 and 40 present on the mesa structure was removed with a buffered oxide etchant (Figure 4, bottom, far left), and a layer of Al2O350 was deposited thereon by atomic layer deposition (ALD) (Figure 4, bottom, center). Finally, a portion of the Al2O350 was removed to expose the top of the mesa structure and at least a portion of the top surface of layer 120 (Figure 4, bottom, far right), yielding a light-emitting structure with a DBR mirror inside.

[0175] The light-emitting structure 200, which has a DBR mirror inside, is shown in detail in Figure 3. From bottom to top, the light-emitting structure 200 consists of the following: (1)n + -InP and n - -A substructure 210 formed by a stack consisting of 12 pairs of alternating layers with InP, n + (1) Substructure 210, in which -InP is selectively porous by electrochemical etching as indicated by the dark band; (2) Layer 220 of a thick n-InP layer of at least about 200 nm; (3) From bottom to top, Layer 230 of InAlGaAs, Layer 240 of p-InAlAs, p ++ - Layer 250 and n of InAlAs ++A mesa structure comprising a BJT formed of an inP layer 260 and an upper n-inP current diffusion layer 270, wherein the upper surface of the current diffusion layer 270 includes a step feature 280. Additional layers, including the Al2O3 layer 295 and the SiO2 layer 290 shown in Figure 3, are present due to the fabrication process but are not necessary for the light-emitting structure or the DBR function provided therein.

[0176] A VCSEL 300, as shown in Figure 5, was formed using an emissive structure 200 equipped with an internal DBR mirror. The emissive structure 200 with DBR forms the lower DBR mirror of the VCSEL, and as shown in Figure 5, an upper dielectric DBR mirror 310 is located on top of the mesa structure, and metal contacts 320 are also present. The process for forming the VCSEL 300 is shown in Figure 6 and proceeds by forming the upper DBR 310 and metal contacts 320 on the emissive structure 200. The upper DBR mirror was formed by lifting off dielectric DBR deposited by sputtering (patterning a photoresist, depositing DBR across the entire surface, and using a solvent to lift off the DBR on the photoresist). As a result, the upper DBR remained only in the previous PR aperture region. The upper DBR mirror can also be formed by removing DBR outside the intended region by patterned dry etching, following full-surface sputtering deposition. The metal contacts 320 were formed through the lift-off of a metal stack deposited by electron beam deposition.

[0177] Characterization and discussion of luminescent structures and VCSELs with embedded tunnel junctions (BTJs): To confirm the current aperture effect of the BTJ structure, the current-voltage (IV) characteristics of an emissive structure with a DBR mirror having a BTJ (10 μm diameter) were compared with a control emissive structure with a DBR mirror without a BTJ. Both devices were measured before the deposition of the upper dielectric DBR. The structure outside the aperture region was simulated using the device without a BTJ. The IV curves of these two devices are summarized in Figure 7. This shows that the current at 2V in the device with a BTJ (solid line) was five times higher than the current in the device without a BTJ (dashed line). This indicates that in emissive structure 200 with a DBR mirror, the current was mainly confined to the BTJ or aperture region. It was also noted that the current in the device without a BTJ was much higher than the literature reported value (Jpn. J. Appl. Phys. Vol. 39 (2000)), which is likely due to punch-through of the p-InP layer. When a large forward bias (over 1.5V) was applied, the pn junction between layer 140 and layer 170 was reverse-biased, and the p-InP layer (layer 120) was completely depleted. Electrons from the n-InP layer (layer 120) were swept through the p-InP layer, resulting in a high current in the device without a back-to-back junction (BTJ).

[0178] Multiple VCSEL 300 devices (at least 10, and up to 10,000 to over 1 million, depending on wafer size) were fabricated and wafer-level tested on a probe station. All tests were performed under continuous wave (CW) operation. The current source used for characterization was a Keithley 2400, and the optical output was measured using a photodiode (Thorlab S122C) placed directly above the device under test. The photodiode was calibrated with a different commercially available 1550 nm EEL for the factory calibration, and mutual matching was found. Figure 8A shows the measured optical output power versus injection current or current density (LI or LJ) plot from a device with a 6 μm aperture (diameter). 2.37 kA / cm 2A clear laser oscillation threshold current density was measured. Figure 8B shows the emission spectrum exceeding the laser oscillation threshold for a single laser oscillation mode at approximately 1553 nm, collected using Thorlab OSA 203. The linewidth reached 63 pm above the threshold current density. The side-mode suppression ratio (SMSR) was greater than 30 dB. The output power was orders of magnitude lower than the literature-reported value at the SWIR wavelength. In addition to the large leakage current outside the aperture region, the fabricated VCSEL 300 device may have had 1) a highly reflective upper dielectric mirror (approximately 99.9%), which negatively affected the extraction of light from the resonator, and 2) an oxide layer may have formed at the interface between layers 260 and 270, which may have hindered effective current injection and increased device resistance and internal heating.

[0179] In summary, the fabricated VCSEL 300 device utilizes an NP-InP-based lower DBR mirror with a BTJ structure for current confinement. Single-mode VCSEL operation at approximately 1553 nm was demonstrated at room temperature with a current of 2.37 kA / cm². 2 CW operation at the threshold current density and a narrow linewidth of 63 pm were observed.

[0180] Example 2: Nanoporous vertical cavity surface-emitting laser (VCSEL) having an aperture region formed by ion implantation Materials and methods: In contrast to the BJT used in Example 1, the second VCSEL structure was fabricated using a nanoporous (NP)-InP-based luminescent structure comprising a lower DBR mirror and aperture region.

[0181] A light-emitting structure equipped with a distributed Bragg reflector (DBR) mirror was prepared starting from an epitaxially grown structure 400 as shown in Figure 9. All layers were grown planar and continuously. From bottom to top, structure 400 consists of the following seven parts: (1)n + -InP (darker bandwidth, doping concentration: 5 × 10⁻¹⁰) 18 cm -3 ) and n- -InP (brighter bandwidth, mild doping, doping concentration: 5 × 10⁻¹⁰) 18 cm -3 A stack 410 consisting of 12 pairs of alternating layers (less than n), where n + -InP can be porousized by electrochemical etching to form NP-InP having a low refractive index (lower than the refractive index of the layer before porosity); (2) a thick n-InP layer of at least about 200 nm (light gray, doping concentration: 5 × 10⁻⁶) 17 cm -3 (3) Layer 420 of p-InAlAs; (4) Emissive structure 430 of InAlGaAs providing an active region having a target emission wavelength of 1550 nm; (5) Layer 440 of p-InAlAs (doping concentration: 1 × 10⁻¹⁶) 18 cm -3 );(5)p ++ - InAlAs layer 450 (doping concentration 1 × 10) 19 cm -3 super);(6)n ++ - InP layer 460 (black, doping concentration 1 × 10⁻¹⁶) 19 cm -3 (7) Super); and (7) Layer 470 of the upper n-InP layer (light gray, doping concentration: 2 × 10 18 cm -3 Structure 400 was grown by metal-organic vapor deposition (MOCVD).

[0182] Figure 10 shows a non-limiting process for fabricating an NP InP VCSEL starting from epitaxial structure 400 (Figure 10, top row, far left), where SiO2510 was deposited and patterned on the top surface of structure 400 using photoresist 520 to define the aperture region (Figure 10, top row, center). Next, ion implantation (H + )530 was performed to damage the outer layer 440 of the aperture region / reduce its conductivity. Ion implantation was performed at energies of 38 keV to 45 keV and 6.4 × 10⁻¹⁰ 13 cm -2This was achieved with an ion implantation dose of . In other words, ion implantation does not occur under the regions covered by 510 and 520. Ion implantation typically occurs up to layer 430. For example, an implantation-induced defect profile simulated using Stopping and Range of Ions in Matter (SRIM) is shown in Figure 11, where the boundaries between different layers are marked with black dashed lines. It can be seen that the upper n-InP (layer 470) was damaged to some extent during ion implantation. According to the literature ("Ion implantation for isolation of III-V semiconductors", Materials Science Reports 4 (1990)), InAlAs requires a much higher annealing temperature compared to InP to restore its electrical conductivity. Based on this difference, it was possible to selectively restore the conductivity of the upper n-InP layer through annealing while maintaining the resistance of the InAlAs layer 440.

[0183] Using a self-aligning process, the patterned mask formed in 510 and 520 also served as a mask during dry etching, which removed a portion of layer 470, making the area beneath the patterned mask higher than the surrounding surface of the remaining layer 470. This can be seen as a structurally present step feature 540 that gives the optoelectronic device a photoconfinement effect, and an ion implantation zone 535 is also shown (Figure 10, second row, far left). The area outside the aperture region was reduced by approximately 20 nm during dry etching, leading to refractive index guidance of the optical modes and helping to reduce the threshold. After removing the masking material, a PECVD SiO2 layer 550 was deposited on a portion of the surface, and the structure was annealed at 350°C for 20 minutes (Figure 10, second row, center). Annealing is thought to restore the conductivity of layer 470 that was damaged by ion implantation. Next, a mesa structure 560 was formed through a wet etching process carried out by wet chemical etching with a dilute HCl solution, followed by citric acid and hydrogen peroxide, at which point the lower part of the mesa structure reached layer 420 (Figure 10, second row, far right). Then, a layer 570 of PECVD SiO2 was deposited and patterned to cover most of the surface except for the left edge portion, serving as a dry etching mask for the next step and also preventing the mesa structure from being attacked during the subsequent electrochemical (EC) etching process (Figure 10, third row, far left). In other words, SiO2570 was deposited on top of the entire mesa structure, with only the upper edge portions around the sidewalls not covered by SiO2570. Deep dry etching was performed using SiO2570 as a mask to form trenches reaching the bottom of the periodic layer (stack 410) (Figure 10, third row, center). Next, the structure (anode) and platinum (Pt) wire / plate (cathode) were immersed in the electrolyte and electrochemical (EC) etching was performed (Figure 10, third row, far right). By applying a forward bias to the structure, EC etching was initiated from the trench sidewalls. The porous region (dark area) expanded laterally to cover the entire aperture region above. Porousing occurred in the n of stack 410. +-Note that this was limited to the InP layer only, and the lightly doped InP layer remained intact (non-porous). Selectivity between porous and non-porous regions was achieved through differences in doping concentration. As a result of porosity, n + -The InP layer was filled with air, resulting in a lower refractive index compared to a lightly doped InP layer. The alternating structure with high and low refractive index layers formed mirrors in the DBR structure, which were used to form the VCSEL. Subsequently, a 600 nm PECVD SiO2 layer 580 was deposited to provide uniform and complete coverage on the exposed sidewalls (Figure 10 (continued), bottom, left). The SiO2 layer 580 functioned as 1) a mesa sidewall passivation layer and 2) an EC etching sidewall protector to prevent wet chemicals in subsequent processes from penetrating the nanoporous (NP)InP within the stack 410. Finally, as shown in Figure 10 (continued), bottom, right, an luminescent structure 600 with DBR mirrors was formed by creating openings in the SiO2 layer 580 above and around the mesa structure for the purpose of arranging metal contacts and upper dielectric DBR deposition.

[0184] The light-emitting structure 600, which includes a DBR mirror, is shown in detail in Figure 12. From bottom to top, the light-emitting structure 600 consists of the following: (1)n + -InP and n - -A substructure 610 formed by a stack consisting of 12 pairs of alternating layers with InP, n + (1) Substructure 610, in which -InP is selectively porous by electrochemical etching as indicated by the dark band; (2) Layer 620 of a thick n-InP layer of at least about 200 nm; (3) Layer 630 of InAlGaAs, layer 640 of p-InAlAs, from bottom to top, providing an active region with a target emission wavelength of 1550 nm. ++ - InAlAs layer 650, n ++ A mesa structure comprising a layer of -InP 660 and an upper current-diffusing layer of n-InP 670, wherein the upper surface of the current-diffusing layer 670 includes a step feature 680. Within the mesa structure are p-InAlAs, p ++ -InAlAs, n ++-InP and n-InP portions are included, which are shown as regions 645, 655, and 665 located below step feature 680. Here, outside the aperture region are p-InAlAs, p ++ -InAlAs, n ++ -InP and n-InP underwent ion implantation, which reduced their conductivity, and subsequent annealing restored their conductivity, at least in the current diffusion layer of n-InP above the aperture region. The additional layer, including the SiO2 layer 690 shown in Figure 12, is present due to the fabrication process but is not necessary for the function of the light-emitting structure or the DBR mirror provided therein.

[0185] A VCSEL 700, as shown in Figure 13, was formed using an emissive structure 600 equipped with a DBR mirror. The emissive structure 600, with its internal DBR mirror, forms the lower DBR mirror of the VCSEL, and as shown in Figure 13, the upper dielectric DBR mirror 710 is located on top of the mesa structure, and metal contacts 720 are also present. The process for forming the VCSEL 300 is shown in Figure 14 and proceeds by forming the upper DBR 710 and metal contacts 720 on the emissive structure 600. The upper DBR mirror is formed by lifting off the dielectric DBR deposited by sputtering (patterning a photoresist, depositing DBR across the entire surface, and using a solvent to lift off the DBR on the photoresist). As a result, the upper DBR remained only in the previous PR aperture region. The upper DBR mirror can also be formed by removing the DBR outside the intended region by patterned dry etching, following full-surface sputtering deposition. The metal contact 720 was formed through the lift-off of the metal stack deposited by electron beam deposition.

[0186] Characterization and discussion of luminescent structures and VCSELs having aperture regions formed by ion implantation: To ensure current confinement using the ion implantation approach, two light-emitting structures were fabricated. One structure had a current aperture region with a diameter of 10 μm, while the other did not. Both light-emitting structures had an NP-InP-based lower DBR mirror with a porous region. The forward IV curves of these two devices are shown in Figure 15. At 2V, the current of the device with the aperture region, e.g., light-emitting structure 600 with the DBR mirror, was found to be nearly three orders of magnitude higher than that of the device without such an aperture. This confirmed that the current was successfully confined within the aperture region.

[0187] We designed VCSELs with different structures that emit light at 1380 nm and 1550 nm, both of which followed the same fabrication process shown in Figure 10. Wafer-level testing was performed on a probe station for the fully fabricated VCSEL devices. All tests were conducted under continuous-wave (CW) operation. A Keithley 2400 current source was used for characterization, and the optical output was measured using a photodiode (Thorlab S122C) placed directly above the device.

[0188] Figure 16A shows the LIV curve for a 1380 nm VCSEL device with a 7 μm aperture. The threshold current is 0.5 mA, and the LIV is 1.3 kA / cm². 2 This corresponds to a current density of approximately 0.23 W / A, and the extracted slope efficiency is approximately 0.23 W / A. The power conversion efficiency of this device reaches a maximum of 10.4% with an injection current of 2.5 mA. The laser oscillation spectrum was collected with Thorlab OSA 203 and is shown in Figure 16B. Single-mode operation with a side-mode suppression ratio (SMSR) close to 30 dB was observed. As the injection current increased from 0.5 mA (threshold) to 8 mA (near the thermal rollover point), a redshift in the laser oscillation wavelength was observed due to heating of the device.

[0189] Similarly, room-temperature CW operation of a 1550 nm VCSEL was also achieved using different InP VCSEL structures in which all dimensions were scaled proportionally to wavelength. The LIV curve and laser oscillation spectrum of the 7 μm aperture device are shown in Figures 17A and 17B, respectively. The threshold current was 0.67 mA and 1.7 kA / cm². 2 This corresponds to a current density of approximately 0.15 W / A, and the extracted slope efficiency is approximately 0.15 W / A. The significantly higher threshold current density and lower slope efficiency of the 1550 nm VCSEL (compared to the 1380 nm device) are thought to be due to the unoptimized process of the upper dielectric DBR (a-Si:H / SiO2) mirror during deposition of the 1550 nm device, which was corrected in the subsequent process of the 1380 nm device. Nevertheless, single-mode operation with a side-mode suppression ratio (SMSR) of over 30 dB was also achieved.

[0190] Conclusion: Examples 1 and 2 above demonstrate the concept of forming an NP-InP DBR-equipped light-emitting structure through two different processes for current confinement, which led to the demonstration of CW VCSEL operation. These exemplary VCSELs are short-wave infrared (SWIR) VCSELs equipped with NP-InP DBRs, operating in CW at room temperature with a current flow rate of 1 kA / cm². 2 We demonstrated a threshold current density in the vicinity, an output power of approximately mW class, and a power conversion efficiency (PCE) of 10%.

[0191] Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art in the field to which the disclosed invention pertains. Publications cited herein and materials from which they are cited expressly constitute part of this specification by reference.

[0192] Those skilled in the art will recognize, or can confirm by ordinary experiment, many equivalents to specific embodiments of the present invention. Such equivalents are intended to be covered by the appended claims.

Claims

1. A semiconductor structure comprising an embedded tunnel junction (BTJ), wherein the structure is A substructure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, A layer of n-doped first semiconductor on the aforementioned substructure, The emissive structure includes multiple quantum wells (MQWs) on the n-doped first semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, An embedded tunnel junction (BTJ) located on the p-doped first semiconductor layer, The embedded tunnel joint is Approximately 1×10 １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer, Optionally, the p-doped second semiconductor layer and the n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, and An n-doped current-diffusing layer enclosing at least a portion of the n-doped second semiconductor layer and optionally at least a portion of the p-doped second semiconductor layer, The current diffusion layer outside the portion having the n-doped second semiconductor layer is in contact with the p-doped second semiconductor or the p-doped first semiconductor. The surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, the region being raised and forming a stepped feature that provides a photoconfinement effect, and the n-doped current diffusion layer A semiconductor structure comprising the features described above.

2. The semiconductor structure according to claim 1, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

3. The semiconductor structure according to claim 1 or 2, wherein the n-doped semiconductor layers in the substructure each have the same thickness, and / or the undoped or low-doped semiconductor layers in the substructure each have the same thickness.

4. The semiconductor structure according to any one of claims 1 to 3, wherein the alternating layers of the substructure include a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, and gallium antimonide, and the alternating layers are lattice-matched to the semiconductor substrate.

5. The semiconductor structure according to any one of claims 1 to 4, wherein the alternating layers of the substructure include a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

6. The semiconductor structure according to any one of claims 1 to 4, wherein the alternating layers of the substructure include a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

7. The semiconductor structure according to any one of claims 1 to 6, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current diffusion layer each comprise one or more semiconductor materials lattice-matched to the semiconductor substrate.

8. The semiconductor structure according to claim 7, wherein one or more semiconductor materials are lattice-matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb, or the semiconductor material is lattice-matched to a gallium arsenide semiconductor substrate and is selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP, or the semiconductor material is lattice-matched to a gallium antimonide semiconductor substrate and is selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

9. The semiconductor structure according to any one of claims 1 to 6, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

10. The semiconductor structure according to claim 9, wherein one or more semiconductor materials are lattice mismatched with an indium phosphide semiconductor substrate and selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb, or the one or more semiconductor materials are lattice mismatched with a gallium arsenide semiconductor substrate and selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP, or the one or more semiconductor materials are lattice mismatched with a gallium antimonide semiconductor substrate and selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

11. A method for manufacturing a semiconductor structure having an embedded tunnel junction (BTJ), wherein the method is (i) A step of forming a substructure on a semiconductor substrate comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers, (ii) A step of depositing a layer of n-doped first semiconductor on the substructure, (iii) A step of depositing or forming an emissive structure including multiple quantum wells (MQWs) on the first semiconductor layer, (iv) A step of depositing a p-doped first semiconductor layer on the emissive structure, (v) On the p-doped first semiconductor layer, about 1 × 10 １８ cm －３ A step of depositing a second p-doped semiconductor layer having a higher p-doping level, (vi) On the p-doped second semiconductor layer, about 1 × 10 １８ cm －３ A step of depositing a second n-doped semiconductor layer having a higher n-doping level, (vii) A step of forming or patterning a masking material on the upper surface portion of the n-doped second semiconductor layer, (viiii) Etching and removing at least the n-doped second semiconductor layer and optionally the p-doped second semiconductor on the outside of the surface portion having the masking material on it, (ix) A step of removing the masking material, (x) A step of depositing an n-doped current diffusion layer that encloses at least a portion of the n-doped second semiconductor layer and optionally the p-doped second semiconductor portion, wherein the current diffusion layer outside the surface portion is in contact with the p-doped second semiconductor layer or the p-doped first semiconductor, Methods that include...

12. The method according to claim 11, wherein each of the structures or layers is independently formed or deposited by metal-organic vapor deposition (MOCVD), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE).

13. The method according to claim 11 or 12, wherein the masking material is selected from the group consisting of dielectrics (silicon dioxide, silicon nitride, aluminum oxide, etc.) and / or photoresists.

14. The method according to any one of claims 11 to 13, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

15. The method according to any one of claims 11 to 14, wherein the n-doped semiconductor layers in the substructure each have the same thickness, and / or the undoped or low-doped semiconductor layers in the substructure each have the same thickness.

16. The method according to any one of claims 11 to 15, wherein the alternating layers of the substructure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide, and the alternating layers are lattice-matched to the semiconductor substrate.

17. The method according to any one of claims 11 to 15, wherein the alternating layers of the substructure include a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

18. The method according to any one of claims 11 to 15, wherein the alternating layers of the substructure include a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

19. The method according to any one of claims 11 to 18, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current diffusion layer comprise one or more semiconductor materials lattice-matched to the semiconductor substrate.

20. The method according to claim 19, wherein one or more semiconductor materials are lattice-matched to an indium phosphide semiconductor substrate and are selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb, or the semiconductor material is lattice-matched to a gallium arsenide semiconductor substrate and is selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP, or the semiconductor material is lattice-matched to a gallium antimonide semiconductor substrate and is selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

21. The method according to any one of claims 11 to 18, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

22. The method according to claim 21, wherein one or more semiconductor materials are lattice mismatched with an indium phosphide semiconductor substrate and selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb, or one or more semiconductor materials are lattice mismatched with a gallium arsenide semiconductor substrate and selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP, or one or more semiconductor materials are lattice mismatched with a gallium antimonide semiconductor substrate and selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

23. A light-emitting structure comprising a buried tunnel joint (BTJ), wherein the light-emitting structure is A lower mirror structure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, wherein the n-doped layers are porous and contain a plurality of pores, and the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; A layer of n-doped first semiconductor on the aforementioned substructure, An emissive structure including multiple quantum wells (MQWs) on the semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, An embedded tunnel junction (BTJ) located on a portion of the p-doped first semiconductor layer, The embedded tunnel junction defines the aperture region, about 1×10 １８ cm －３ a layer of p-doped second semiconductor having a p-doping level greater than Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer, Optionally, the p-doped second semiconductor layer and the n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, and An n-doped current-diffusing layer enclosing at least a portion of the n-doped second semiconductor layer and optionally at least a portion of the p-doped second semiconductor layer, The current diffusion layer outside the portion having the n-doped second semiconductor layer is in contact with the p-doped second semiconductor or the p-doped first semiconductor. The surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, the region being raised and forming a stepped feature that provides a photoconfinement effect, and the n-doped current diffusion layer A light-emitting structure comprising:

24. The light-emitting structure according to claim 23, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

25. The light-emitting structure according to claim 23 or 24, wherein each of the n-doped semiconductor layers in the substructure has the same thickness, and / or each of the undoped or low-doped semiconductor layers in the substructure has the same thickness.

26. The light-emitting structure according to any one of claims 23 to 25, wherein the alternating layers of the substructure comprise a binary semiconductor material selected from the group consisting of indium phosphide, gallium arsenide, or gallium antimonide, and the alternating layers are lattice-matched to the semiconductor substrate.

27. The light-emitting structure according to any one of claims 23 to 25, wherein the alternating layers of the lower structure include a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

28. The light-emitting structure according to any one of claims 23 to 25, wherein the alternating layers of the substructure include a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

29. The light-emitting structure according to any one of claims 23 to 28, wherein the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current diffusion layer each comprise one or more semiconductor materials lattice-matched to the semiconductor substrate.

30. The light-emitting structure according to claim 29, wherein one or more semiconductor materials are lattice-matched to an indium phosphide semiconductor substrate and selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb, or the semiconductor material is lattice-matched to a gallium arsenide semiconductor substrate and selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP, or the semiconductor material is lattice-matched to a gallium antimonide semiconductor substrate and selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

31. The light-emitting structure according to any one of claims 23 to 28, wherein the emissive structure, the p-doped second semiconductor layer, and the n-doped second semiconductor layer each comprise one or more semiconductor materials that are lattice mismatched with the semiconductor substrate.

32. The light-emitting structure according to claim 31, wherein one or more semiconductor materials are lattice mismatched with an indium phosphide semiconductor substrate and selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb, or the one or more semiconductor materials are lattice mismatched with a gallium arsenide semiconductor substrate and selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP, or the one or more semiconductor materials are lattice mismatched with a gallium antimonide semiconductor substrate and selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

33. The light-emitting structure according to any one of claims 23 to 32, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

34. The light-emitting structure according to any one of claims 23 to 33, wherein a refractive index contrast (Δn) exists between the alternating layers, and this contrast is in the range of about 0.1 to about 2 or about 0.1 to about 2.

5.

35. A method for forming a light-emitting structure, wherein the method is (i') A step of providing or forming a structure that includes an embedded tunnel joint (BTJ), wherein the structure is A substructure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, A layer of n-doped first semiconductor on the aforementioned substructure, The emissive structure includes multiple quantum wells (MQWs) on the n-doped first semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, An embedded tunnel junction (BTJ) located on the p-doped first semiconductor layer, The embedded tunnel joint is Approximately 1×10 １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer, Optionally, the p-doped second semiconductor layer and the n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, and An n-doped current-diffusing layer enclosing at least a portion of the n-doped second semiconductor layer and optionally at least a portion of the p-doped second semiconductor layer, The current diffusion layer outside the portion having the n-doped second semiconductor layer is in contact with the p-doped second semiconductor or the p-doped first semiconductor. The surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, the region being raised and forming a stepped feature that provides a photoconfinement effect, and the n-doped current diffusion layer A process that includes, (ii') A step of forming a mesa structure by etching the current diffusion layer, the emissive structure, the p-doped first semiconductor layer, and optionally a portion of the p-doped second semiconductor layer, (iii') A step of depositing a layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-doped first semiconductor layer is not covered by the silicon dioxide layer, (iv') A step of etching the portion not covered by the silicon dioxide layer to form a trench that exposes the side wall of the alternating layer of the substructure, (v') A step of selectively porousizing the n-doped semiconductor layer in the alternating layers of the substructure, wherein a plurality of pores are formed and the undoped or low-doped semiconductor layer remains non-porous or substantially non-porous, (vi') A step of depositing one or more materials so as to cover the trench, the side wall, and the side wall of the mesa structure, (vii') If covered by one or more of the materials, a step of selectively removing the one or more of the materials to expose at least a portion of the upper part of the mesa structure and optionally a portion of the n-doped first semiconductor, (viiii') A step of forming a metal contact on a part of the upper part of the mesa structure and optionally on a part of the n-doped first semiconductor, Methods that include...

36. The method according to claim 35, wherein the porosity formed in step (v') is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

37. The method according to claim 35 or 36, wherein step (v') is carried out by electrochemical etching in an electrolyte solution under an applied bias voltage.

38. The electrolyte solution contains halide ions, hydrochloric acid (HCl), sulfuric acid (H ２ SO ４ ), hydrofluoric acid (HF), KOH, NaOH, Ba(OH) ２ Ca(OH) ２ , Sr(OH) ２ NH ４ OH, NaCl, NaF, nitric acid (HNO ３ The method according to claim 37, comprising ), organic acids and salts thereof (such as oxalic acid and citric acid), and mixtures thereof.

39. The method according to any one of claims 35 to 38, wherein the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, silicon nitride, and spin-on glass, and / or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist, and are combinations thereof.

40. The method according to any one of claims 35 to 39, wherein the metal contact formed during step (viii') comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

41. A light-emitting structure according to any one of claims 23 to 34, Upper distributed Bragg reflector mirror, Metal contacts and A photoelectronic device equipped with the following features.

42. The above-mentioned upper distributed Bragg reflector is a-Si / SiO ２ , TiO ２ / SiO ２ Ta ２ O ５ / SiO ２ , Nb ２ O ５ / SiO ２ ZnSe / SiO ２ a-Si / Al ２ O ３ , a-Si / MgF, ZnS / MgF, a-Si / CaF ２ The optoelectronic device according to claim 41, comprising alternating layers of any one of the above, or a combination thereof.

43. The optoelectronic device according to claim 41 or 42, wherein the metal contact comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

44. The optoelectronic device according to any one of claims 41 to 43, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

45. The optoelectronic device according to claim 44, wherein the vertical cavity surface-emitting laser operates at room temperature (approximately 25°C) and in continuous wave mode.

46. The optoelectronic device according to claim 44, wherein the vertical cavity surface-emitting laser operates at a temperature of less than approximately 0°C, more than approximately 25°C, or more than approximately 85°C.

47. The optoelectronic device according to claim 44, wherein the vertical cavity surface-emitting laser operates in pulse mode.

48. The optoelectronic device according to claim 44, wherein the vertical cavity surface-emitting laser emits light in the infrared wavelength region.

49. The optoelectronic device according to claim 44, wherein the vertical cavity surface-emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

50. A method for manufacturing an optoelectronic device, wherein the method is (i'') A step of providing or forming a light-emitting structure, wherein the light-emitting structure is A lower mirror structure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, wherein the n-doped layers are porous and contain a plurality of pores, and the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; A layer of n-doped first semiconductor on the aforementioned substructure, An emissive structure including multiple quantum wells (MQWs) on the semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, An embedded tunnel junction (BTJ) located on a portion of the p-doped first semiconductor layer, The embedded tunnel junction defines the aperture region, Approximately 1×10 １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, Equipped with, At least the n-doped second semiconductor layer has a smaller surface area than the p-doped first semiconductor layer, Optionally, the p-doped second semiconductor layer and the n-doped second semiconductor layer have equal or substantially equal areas on the p-doped first semiconductor layer, and An n-doped current-diffusing layer enclosing at least a portion of the n-doped second semiconductor layer and optionally at least a portion of the p-doped second semiconductor layer, The current diffusion layer outside the portion having the n-doped second semiconductor layer is in contact with the p-doped second semiconductor or the p-doped first semiconductor. The surface of the current diffusion layer optionally includes a region above the embedded tunnel junction, the region being raised and forming a stepped feature that provides a photoconfinement effect, and the n-doped current diffusion layer A process that includes, (ii'') A step of providing or forming an upper distributed Bragg reflector mirror on the light-emitting structure, (iii'') A step of providing or forming a metal contact on the optoelectronic device, Methods that include...

51. The upper distributed Bragg reflector mirror of step (ii'') is a-Si / SiO ２ , TiO ２ / SiO ２ Ta ２ O ５ / SiO ２ , Nb ２ O ５ / SiO ２ ZnSe / SiO ２ a-Si / Al ２ O ３ , a-Si / MgF, ZnS / MgF, a-Si / CaF ２ The method according to claim 50, comprising alternating layers of any one of the above, or a combination thereof.

52. The method according to claim 50 or 51, wherein the metal contact in step (iii'') comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

53. The method according to any one of claims 50 to 52, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

54. A light-emitting structure, A lower mirror structure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, wherein the n-doped semiconductor layers are porous and contain a plurality of pores, and the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; A layer of n-doped first semiconductor on the aforementioned substructure, An emissive structure including multiple quantum wells (MQWs) on the semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, Approximately 1 × 10 on the p-doped first semiconductor layer １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, An n-doped current-diffusing layer on the n-doped second semiconductor layer, Equipped with, An aperture region exists, and the electrical conductivity of the p-doped first semiconductor layer within the aperture region is greater than the electrical conductivity of the p-doped first semiconductor layer outside the aperture region. The p-doped first semiconductor layer, optionally the p-doped second semiconductor, and optionally the n-doped semiconductor have higher electrical resistance outside the aperture region compared to within the aperture region. The current diffusion layer is electrically conductive on the inside and outside of the aperture. A light-emitting structure wherein the current diffusion layer optionally includes a region on the upper surface above the aperture region, the region being raised, and forming a step feature that provides a light-confinement effect.

55. The light-emitting structure according to claim 54, wherein the semiconductor substrate is made of indium phosphide, gallium arsenide, or gallium antimonide.

56. The light-emitting structure according to claim 54 or 55, wherein each of the n-doped semiconductor layers in the substructure has the same thickness, and / or each of the undoped or low-doped semiconductor layers in the substructure has the same thickness.

57. The light-emitting structure according to claim 54, wherein the alternating layers of the lower structure include a binary semiconductor material that is lattice-matched to the semiconductor substrate.

58. The light-emitting structure according to claim 54, wherein the alternating layers of the lower structure include a ternary semiconductor material that is lattice-matched to the semiconductor substrate.

59. The light-emitting structure according to claim 54, wherein the alternating layers of the lower structure include a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

60. The light-emitting structure according to any one of claims 54 to 59, comprising one or more materials in which the n-doped first semiconductor, the emissive structure, the p-doped first semiconductor, the p-doped second semiconductor, the n-doped second semiconductor, and the current diffusion layer are each independently lattice-matched to the semiconductor substrate.

61. The light-emitting structure according to claim 60, wherein one or more materials are lattice-matched to an indium phosphide semiconductor substrate and selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, and AlGaAsSb, or the one or more semiconductor materials are lattice-matched to a gallium arsenide semiconductor substrate and selected from the group consisting of GaAs, AlGaAs, AlAs, InAlP, and InGaP, or the one or more semiconductor materials are lattice-matched to a gallium antimonide semiconductor substrate and selected from the group consisting of GaSb, AlAsSb, and AlGaAsSb.

62. The light-emitting structure according to any one of claims 54 to 59, wherein the emissive structure, the p-doped second semiconductor, and the n-doped second semiconductor each independently comprise one or more materials that are lattice mismatched to an indium phosphide semiconductor substrate.

63. The light-emitting structure according to claim 62, wherein one or more semiconductor materials are lattice mismatched with an indium phosphide semiconductor substrate and selected from the group consisting of InAlGaAs, InGaAsP, InGaAs, InAs, and InGaAsSb, or the one or more semiconductor materials are lattice mismatched with a gallium arsenide semiconductor substrate and selected from the group consisting of InGaAs, AlGaAs, and In(Al)GaP, or the one or more semiconductor materials are lattice mismatched with a gallium antimonide semiconductor substrate and selected from the group consisting of InAl(As)Sb, AlAsSb, and AlGaAsSb.

64. The light-emitting structure according to any one of claims 54 to 63, wherein the layer of the p-doped first semiconductor outside the aperture region, optionally the p-doped second semiconductor, and optionally the n-doped second semiconductor have an electrical conductivity that is about one to four orders of magnitude lower than that inside the aperture region.

65. The light-emitting structure according to any one of claims 54 to 64, wherein the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

66. The light-emitting structure according to any one of claims 54 to 65, wherein a refractive index contrast (Δn) exists between the alternating layers in the lower mirror structure, and this contrast is in the range of about 0.1 to about 2 or about 0.1 to about 2.

5.

67. A method for forming a light-emitting structure, wherein the method is (a) A step of providing or forming a structure, wherein the structure is A substructure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, A layer of n-doped first semiconductor on the aforementioned substructure, The emissive structure includes multiple quantum wells (MQWs) on the first semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, Approximately 1 × 10 on the p-doped first semiconductor layer １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, An n-doped current-diffusing layer on the n-doped second semiconductor layer, A process that includes, (b) A step of placing a masking material on the upper surface region of the current diffusion layer of the structure, (c) A step of performing ion implantation to reduce the conductivity of at least the p-doped first semiconductor layer that is not covered by the masking material, (d) A step of etching a portion of the current diffusion layer, wherein the etching does not remove the current diffusion layer located beneath the masking material. (e) A step of removing the masking material, (f) A step of depositing a first layer of silicon dioxide on a part of the current diffusion layer to cover at least the area where the masking material was present, (g) A step of annealing the structure to increase the electrical conductivity of the uppermost layer of the current diffusion layer, (h) A step of forming a mesa structure by etching the current diffusion layer, the n-doped second semiconductor, the p-doped second semiconductor, the p-doped first semiconductor, and a part of the emissive structure that are not covered by the first silicon dioxide layer, (i) A step of depositing a second layer of silicon dioxide over the mesa structure, wherein at least a portion of the n-doped first semiconductor is not covered by the second layer of silicon dioxide. (j) A step of etching the structure not covered by the second layer of silicon dioxide to form a trench that exposes the side walls of the alternating layers of the substructure, (k) A step of selectively porousizing the n-doped semiconductor layer in the alternating layers of the substructure, wherein the formed pores contain air, and the undoped or low-doped semiconductor layer remains non-porous or substantially non-porous. (l) A step of depositing one or more materials to cover the trench, the side walls of the trench, and the side walls of the mesa structure, (m) If covered by one or more of the above materials, a step of selectively removing the one or more of the above materials to expose at least a portion of the upper part of the mesa structure and optionally a portion of the semiconductor layer, (n) A step of forming a metal contact on a part of the upper part of the mesa structure and optionally on a part of the semiconductor layer, Methods that include...

68. The method according to claim 67, wherein the masking material is a dielectric material selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride, or an organic material (such as a photoresist), or a metal (such as nickel), or a combination thereof.

69. The method according to claim 67 or 68, wherein the porosity formed in step (k) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

70. The method according to any one of claims 67 to 69, wherein step (k) is carried out by electrochemical etching in an electrolyte solution under an applied bias voltage.

71. The electrolyte solution contains halide ions, hydrochloric acid (HCl), sulfuric acid (H ２ SO ４ ), hydrofluoric acid (HF), KOH, NaOH, Ba(OH) ２ Ca(OH) ２ , Sr(OH) ２ NH ４ OH, NaCl, NaF, nitric acid (HNO ３ The method according to claim 70, comprising ), organic acids and salts thereof (such as oxalic acid and citric acid), and mixtures thereof.

72. The method according to any one of claims 67 to 71, wherein the one or more materials are selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride, and / or the one or more materials are organic materials selected from the group consisting of benzocyclobutene (BCB), polyimide, and photoresist, and are combinations thereof.

73. The method according to any one of claims 67 to 72, wherein the metal contact comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

74. A light-emitting structure according to any one of claims 54 to 66, Upper distributed Bragg reflector mirror, Metal contacts and A photoelectronic device equipped with the following features.

75. The upper distributed Bragg reflector mirror is a-Si / SiO ２ , TiO ２ / SiO ２ Ta ２ O ５ / SiO ２ , Nb ２ O ５ / SiO ２ ZnSe / SiO ２ a-Si / Al ２ O ３ , a-Si / MgF, ZnS / MgF, a-Si / CaF ２ The optoelectronic device according to claim 74, comprising alternating layers of any one of the above, or a combination thereof.

76. The optoelectronic device according to claim 74 or 75, wherein the metal contact comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

77. The optoelectronic device according to any one of claims 74 to 76, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

78. The optoelectronic device according to claim 77, wherein the vertical cavity surface-emitting laser operates at room temperature (approximately 25°C) and in continuous wave mode.

79. The optoelectronic device according to claim 77, wherein the vertical cavity surface-emitting laser operates at a temperature of less than approximately 0°C, more than approximately 25°C, or more than approximately 85°C.

80. The optoelectronic device according to claim 77, wherein the vertical cavity surface-emitting laser operates in pulse mode.

81. The optoelectronic device according to claim 77, wherein the vertical cavity surface-emitting laser emits light in the infrared wavelength region and / or the red wavelength region.

82. The optoelectronic device according to claim 77, wherein the vertical cavity surface-emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

83. A method for manufacturing an optoelectronic device, wherein the method (a') A step of providing or forming a light-emitting structure, wherein the light-emitting structure is A lower mirror structure comprising alternating layers of n-doped semiconductor layers and undoped or low-doped semiconductor layers on a semiconductor substrate, wherein the n-doped semiconductor layers are porous and contain a plurality of pores, and the undoped or low-doped semiconductor layers are non-porous or substantially non-porous; A layer of n-doped first semiconductor on the aforementioned substructure, An emissive structure including multiple quantum wells (MQWs) on the semiconductor layer, A p-doped first semiconductor layer on the aforementioned emissive structure, Approximately 1 × 10 on the p-doped first semiconductor layer １８ cm －３ A second semiconductor layer p-doped with a higher p-doping level, Approximately 1 × 10 on the p-doped second semiconductor layer １８ cm －３ A second n-doped semiconductor layer having a higher n-doping level, An n-doped current-diffusing layer on the n-doped second semiconductor layer, Equipped with, An aperture region exists, and the electrical conductivity of the p-doped first semiconductor layer within the aperture region is greater than the electrical conductivity of the p-doped first semiconductor layer outside the aperture region. The p-doped first semiconductor layer, and optionally the p-doped second semiconductor, and optionally the n-doped second semiconductor, have higher electrical resistance outside the aperture region compared to within the aperture region. The current diffusion layer is electrically conductive on the inside and outside of the aperture. The current diffusion layer optionally includes a region on the upper surface above the aperture region, the region being raised, and forming a step feature that provides a light confinement effect. (b') A step of providing or forming an upper distributed Bragg reflector mirror on the light-emitting structure, (c') A step of providing or forming a metal contact on the optoelectronic device, Methods that include...

84. The upper distributed Bragg reflector mirror of the engineering (b') is a-Si / SiO ２ , TiO ２ / SiO ２ , Ta ２ O ５ / SiO ２ , Nb ２ O ５ / SiO ２ , ZnSe / SiO ２ , a-Si / Al ２ O ３ , a-Si / MgF, ZnS / MgF, a-Si / CaF ２ The method according to claim 83, comprising any one of, or a combination of, alternating layers thereof.

85. The method according to claim 83 or 84, wherein the metal contact in step (c') comprises one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

86. The method according to any one of claims 83 to 85, wherein the optoelectronic device is a vertical cavity surface-emitting laser (VCSEL).

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