Method for ion-assisted self-limiting conformal etching

Abstract

A method for forming a semiconductor device provides a substrate having a patterned structure containing a semiconductor material, wherein the patterned structure has a side profile including depressions, such as a patterned film stack, and a spacer layer conformally deposited on and within the depressions of the patterned structure; and a reaction layer formed on the spacer layer by reacting the surface of the spacer layer with a plasma-excited first etching gas, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen to form the reaction layer, and at least a portion of the reaction layer is removed by ion bombardment caused by exposure to a plasma-excited second etching gas. The spacer layer may be SiOCN. The reaction layer may be ammonium silicofluoride. The first etching gas may contain SF6, H2, and N2, or NF3, H2, and N2. The reaction and removal may be carried out at room temperature in the same chamber.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 465,436, filed on May 10, 2023, and U.S. Non - Provisional Patent Application No. 18 / 619,628, filed on Mar. 28, 2024, which are hereby incorporated by reference herein.

[0002] This disclosure generally relates to methods of manufacturing semiconductor devices, and more particularly, to ion - assisted self - limiting conformal etching in methods of manufacturing semiconductor devices.

Background Art

[0003] Conventional plasma etching techniques in structures having advanced geometries such as nanosheet transistors and nanowire transistors have problems related to top - to - bottom etching variations (differences), and isolated - area to nested - area etching variations (differences), and excessive etching in nanosheet areas, all of which can lead to insufficient epitaxial growth of the source and drain, and as a result, can cause device failures.

[0004] Figures 1A to 1C are cross-sectional views illustrating common problems in etching film structures with highly geometric shapes. More specifically, Figures 1A to 1C show intermediate structures during semiconductor processing for forming gate-all-around nanosheet channel transistors. Film structures, such as patterned film stacks 20, may include alternating vertically stacked films of silicon germanium (SiGe) and silicon (Si). The SiGe layer 30 can be selectively etched with respect to the Si channel layer 40 such that the SiGe layer 30 has depressions 32. A spacer layer 50 can be conformally deposited on the patterned film stacks 20 to fill the depressions 32 and cover the intermediate structure. The spacer layer 50 can then be etched to expose alternating nanowires or nanosheets. In other words, the goal at this stage is to expose the side surface 42 of the Si channel layer 40 for subsequent epitaxial growth of the source and drain regions, while retaining the material of the spacer layer 50 that covers the recess 32 of the SiGe layer 30, which is often called an inner spacer.

[0005] Figure 1A shows a sparse-to-dense area etching problem, where the etching rate of the sidewalls of the spacer layer 50 is slower in the dense area 61 than in the sparse area 62. Figure 1B shows a top-to-bottom etching problem, where the etching rate of the spacer layer 50 is slower near the bottom or lower region 63 of the intermediate structure than near the top or upper region 64 of the intermediate structure. Figure 1C shows an etching problem, where the etching rate of the spacer layer 50 is faster near the bottom or lower region 63 of the intermediate structure in the patterned film stack 20 than near the top or upper region 64 of the intermediate structure, resulting in excessive spacer loss in recesses, in depressions 32 of the SiGe layer 30, between adjacent nanosheets, or between Si channel layers 40.

[0006] In high-quality epitaxial growth of the source and drain following etching of the patterned film stack 20, it is necessary that the spacer layer 50 is etched sufficiently to expose the leading edges of the silicon nanosheets or the sides 42 of the Si channel layer 40 in all areas (upper and lower) of the patterned film stack 20, that the exposed leading edges of the silicon nanosheets are not damaged by the etching process, that a spacer layer thickness sufficient to protect the polysilicon dummy gate structure 70 from epitaxial growth is maintained on top of the patterned structure, and that a spacer layer thickness (inner spacer) sufficient for isolation and structural integrity is maintained between the nanosheets.

[0007] Therefore, there is a need for new etching methods to address these problems in etching patterned film structures. [Overview of the project] [Means for solving the problem]

[0008] According to one embodiment of the present disclosure, a method for forming a semiconductor device is to provide a substrate having a patterned structure comprising a semiconductor material, wherein the patterned structure has a side profile including depressions, and a spacer layer conformally deposited on and within the depressions of the patterned structure; and to form a reaction layer on the spacer layer by reacting the surface of the spacer layer with a plasma-excited first etching gas, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen to form the reaction layer, and to remove at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas.

[0009] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided to provide a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, and the spacer layer comprises a silicon-carbon-containing material, a silicon-oxygen-containing material, or a silicon-carbon-oxygen-containing material, and the spacer layer The method may include reacting the surface with a plasma-excited first etching gas to form a reaction layer on a spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen, and the reaction layer contains ammonium silicofluoride (AFS); removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas; and sequentially repeating the reaction of the spacer layer surface and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while holding at least a portion of the spacer layer in the depression of the second film.

[0010] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided to provide a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, and a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, wherein the spacer layer comprises SiOCN; and a method for forming a reaction layer on the spacer layer by reacting the surface of the spacer layer with a plasma-excited first etching gas, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen. The reaction layer may include forming a reaction layer containing ammonium silicate (AFS), removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas, and sequentially repeating the reaction of the spacer layer surface and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while retaining at least a portion of the spacer layer in a recess of the second film, wherein the reaction of the spacer layer surface and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure in the same chamber of the same plasma processing system, and the reaction of the spacer layer surface and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range of 8 to 28 degrees Celsius, and the side surface of the first film is exposed.

[0011] To gain a more complete understanding of this disclosure and its merits, refer hereto to the following description, which should be read in conjunction with the attached drawings. [Brief explanation of the drawing]

[0012] [Figure 1A] This is a cross-sectional view showing an intermediate structure of a semiconductor device manufactured using a conventional method. [Figure 1B] This is a cross-sectional view showing an intermediate structure of a semiconductor device manufactured using a conventional method. [Figure 1C]This is a cross-sectional view showing an intermediate structure of a semiconductor device manufactured using a conventional method. [Figure 2A] This is a cross-sectional perspective view showing a portion of an intermediate structure of a semiconductor device having alternately stacked, vertically arranged films. [Figure 2B] This is a cross-sectional perspective view showing a portion of an intermediate structure of a semiconductor device having alternately stacked, vertically arranged films. [Figure 3] This is a cross-sectional view showing an intermediate structure of a semiconductor device made using a method according to some embodiments of this disclosure. [Figure 4] This is a cross-sectional view showing an intermediate structure of a semiconductor device made using a method according to some embodiments of this disclosure. [Figure 5] This is a cross-sectional view showing an intermediate structure of a semiconductor device made using a method according to some embodiments of this disclosure. [Figure 6] This figure shows a chamber for a plasma processing system for carrying out a method for manufacturing semiconductor devices according to some embodiments of the present disclosure. [Figure 7] This graph shows experimental results regarding some exemplary etching amounts for some exemplary materials at various reaction times for the formation of a reaction layer, using some method embodiments of the present disclosure. [Figure 8] A flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of this disclosure is shown. [Figure 9] A flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of this disclosure is shown. [Figure 10] A flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of this disclosure is shown. [Modes for carrying out the invention]

[0013] Herein, illustrative embodiments for explanatory purposes are illustrated and described with reference to the drawings. In this specification, similar reference numerals may be used in the drawings to designate similar or identical elements throughout the various drawings. The drawings are not drawn to actual size, and in some cases, they are exaggerated or simplified in places for illustrative purposes. Those skilled in the art will recognize many possible uses and variations relating to other embodiments based on the following illustrative embodiments provided in this disclosure.

[0014] In some embodiments of the present disclosure, a method for forming an intermediate structure during the manufacture of a semiconductor device is provided, comprising: providing a substrate having a patterned structure comprising a semiconductor material, wherein the patterned structure has a side profile including depressions, such as a patterned film stack for making a transistor; conformally depositing a spacer layer on and within the depressions of the patterned structure; reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer; and removing at least a portion of the reaction layer by ion bombardment resulting from exposure to a plasma-excited second etching gas. In some embodiments, the reaction to form the reaction layer and the removal of the reaction layer may be repeated and cyclical until a desired amount of spacer layer is removed. Some exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings of the present disclosure in order to describe some exemplary variations relating to some embodiments of the present disclosure. Other embodiments may also be understood from the whole of this specification and the claims appended herein.

[0015] In this disclosure, terms such as “first,” “second,” etc., may be used to describe various components, but components are not necessarily limited to such terms in terms of, for example, the order, arrangement, importance, or number of such components that may be possible in a given embodiment. Such terms may be used simply for the purpose of distinguishing one component from another in a given embodiment or group of embodiments. For example, without departing from the scope of rights provided by this disclosure, a first component may be called a second component, and similarly, a second component may be called a first component. Because the geometric shapes and sizes of semiconductors can be very small (e.g., on the order of 1 to 5 nm), the terms “film” and “layer” may be used interchangeably in this specification.

[0016] For the purposes of simplification and explanation, Figures 2A to 5 show only some parts of a substrate for a semiconductor device as an intermediate structure that may relate to a method for fabricating a semiconductor device according to some embodiments of the present disclosure. Accordingly, in Figures 2A to 5, in order to simplify the figures, additional layers and structures of the substrate for a semiconductor that are fabricated below, below, or adjacent to the intermediate structures shown in the figures may be omitted, so as can be easily understood by those skilled in the art, and such additional layers and structures include any structure, type, and semiconductor device, such as additional front-end-of-line (FEOL) stages or levels, additional transistors, diodes, capacitors, resistors, inductors, integrated circuits, memory cells, logic, processor parts, digital devices, analog devices, bipolar devices, power devices, mixed-signal devices, high-frequency devices, embedded oxide films, additional shallow trench isolation regions, complete semiconductor wafers, or any combination thereof. Therefore, in Figures 2A to 5, in order to simplify the figures so that it can be easily understood by those skilled in the art, additional layers and structures of substrates for semiconductors that are made on top of, above, or adjacent to the intermediate structures shown in the figures may be omitted and not shown, such additional layers and structures include any structures, types, and semiconductor devices, such as additional front-end-of-line (FEOL) stages or levels, additional transistors, diodes, capacitors, resistors, inductors, integrated circuits, memory cells, logic, processor components, digital devices, analog devices, bipolar devices, power devices, mixed-signal devices, high-frequency devices, interconnects, vias, trenches, interlayer dielectric layers, intermetallic dielectric layers, back-end-of-line (BEOL) stages or levels, passivation layers, contact pads, local interconnects, global interconnects, wire bonding, packaging, or any combination thereof.Furthermore, in the cross-section of an actual completed semiconductor device, the intermediate structure or the remaining part thereof illustrated and represented in the drawings of the present disclosure, which is simplified to have right-angled edges, a rectangular block shape, and / or a linear shape, may actually have a more rounded shape, a more curved shape, and a less linear shape. Also, due to the very small size, thickness, and scale of some layers and the resulting features (e.g., those on a scale less than 5 nanometers), it may be visually difficult to see even in images obtained by a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0017] Figures 2A to 5 are various diagrams of various intermediate structures of an exemplary semiconductor device, and schematically show a processing sequence for forming an intermediate structure of an exemplary semiconductor device using a method according to some embodiments of the present disclosure. In Figures 2A to 5, the exemplary semiconductor device being constructed includes alternately vertically stacked films (e.g., those with SiGe films and Si films stacked) to create a gate-all-around stacked nanosheet channel for a transistor. More specifically, Figure 2A is a cross-sectional perspective view showing a part of an intermediate structure of an exemplary semiconductor device being made using a method according to some embodiments of the present disclosure. Figures 2B to 5 are cross-sectional views taken along line A-A of Figure 2A, and show an intermediate structure of an exemplary semiconductor device being made using a method according to some embodiments of the present disclosure. However, some embodiments of the present disclosure can also be used to create other structures for other semiconductor devices.

[0018] Figure 2B is a cross-sectional view along line AA of Figure 2A. Referring to Figures 2A and 2B, the intermediate structure may include a patterned film laminate 20 composed of alternating vertically stacked films, i.e., SiGe layers 30 (e.g., SiGe sacrificial layers) and Si channel layers 40 formed on the wafer 72, a shallow trench isolation 74 formed on the wafer 72, and a polysilicon dummy gate structure 70. The polysilicon dummy gate structure 70 may include a dielectric layer (e.g., silicon oxide, SiO2) around the top and sides of the polysilicon layer. The polysilicon dummy gate structure 70 may function as a hard mask in this intermediate stage. The SiGe layer 30 is selectively etched relative to the Si channel layer 40 such that the SiGe layer 30 has a recess 32 and is recessed relative to the Si channel layer 40. The Si channel layer 40 may have a first external dimension, and the SiGe layer 30 may have a second external dimension in the recess 32 of the SiGe layer 30, the second external dimension being smaller than the first external dimension.

[0019] Referring to FIG. 3, the spacer layer 50 can be conformally deposited over the patterned film stack 20 and within the recess 32 in the SiGe layer 30 between the tips of the Si channel layers 40. The spacer layer 50 can be conformally deposited over the patterned film stack 20 including the sides of the alternating SiGe layers 30 and Si channel layers 40, and the spacer layer 50 overfills the recess 32 between adjacent Si channel layers 40. The spacer layer 50 can completely fill the recess 32 and then can also overfill the recess 32. In some embodiments, the spacer layer 50 can include a silicon-carbon-containing material, a silicon-nitrogen-containing material, a silicon-oxygen-containing material, a silicon-carbon-oxygen-containing material, or any combination thereof. In some embodiments, the spacer layer 50 contains SiO2, SiC, SiN, SiOC, SiOCN, or any combination thereof. In some embodiments, the spacer layer 50 contains a low dielectric constant dielectric material. In one example, the spacer layer 50 contains a SiOCN material. The spacer layer 50 can have a thickness of, for example, from about 5 nm to about 20 nm. The spacer layer can be deposited, for example, by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or any combination thereof.

[0020] Referring to Figure 4, according to a method of one embodiment of the present disclosure, the exposed surface of the spacer layer 50 can be reacted with a plasma-excited first etching gas in the chamber of a plasma processing system to form a reaction layer 80 on the spacer layer 50. Such a reaction layer 80 may have a thickness of, for example, about 1 nm to about 3 nm. In some embodiments, the plasma-excited first etching gas may contain fluorine and nitrogen. In some embodiments, the plasma-excited first etching gas may contain fluorine, hydrogen, and nitrogen. In some embodiments, the plasma-excited first etching gas may contain SF6, NF3, N2, H2, NH3, HF, CF4, CHF3, CH2F2, CH3F, or any combination thereof. In one example, the plasma-excited first etching gas contains SF6, H2, and N2. In another example, the plasma-excited first etching gas contains NF3, H2, and N2. Therefore, the reaction layer 80 may be or include an ammonium silicofluoride ((NH4)2SiF6) (AFS) layer. In some embodiments, the reaction layer 80 may be or include a salt layer (modified surface layer) on the spacer layer 50.

[0021] In some embodiments, the formation of the reaction layer 80 may be self-limiting or quasi-self-limiting, such that when the reaction layer 80 reaches a certain thickness (e.g., about 1 nm to 3 nm), it can prevent further reaction between the plasma-excited first etching gas and the unreacted portion (unexposed) beneath the rest of the spacer layer 50. In some embodiments, the self-limiting nature of the formation of the reaction layer 80 may result in the reaction layer having a uniform thickness throughout the patterned film stack 20 and / or throughout the intermediate structure, which may be advantageous for uniformly etching or nanofiring the spacer layer 50 as a uniform conformal etching process.

[0022] Referring to Figure 5, according to a method of one embodiment of the present disclosure, part, most, or all of the reaction layer 80 can be removed by ion bombardment resulting from exposure to a plasma-excited second etching gas. The plasma-excited second etching gas may include N2, H2, O2, Ar, CO, He, Kr, Xe, or any combination thereof. Removal of the reaction layer 80 can reduce the thickness of the spacer layer 50. In some embodiments, removal of the reaction layer 80 exposes the side surface 42 of the Si channel layer 40 while retaining at least a portion of the spacer layer 50 in the recess 32 of the SiGe layer 30, thereby forming an inner spacer between the tips of the Si channel layer 40. The inner spacer may provide structural support for the tips of the Si channel layer 40 and electrical insulation, as the inner spacer is typically a dielectric material.

[0023] Exposing the sides 42 of the Si channel layer 40 may be the goal of this intermediate structure for a patterned film laminate 20 (see, e.g., Figure 5) in preparation for the next operation of epitaxial growth and / or deposition of source and drain regions electrically connected to the Si channel layer 40 via these sides 42. Depending on several factors such as the thickness of the spacer layer 50, the density of the spacing between structures, the choice of material, the allowable reaction time, and the parameters of the plasma processing system (e.g., the type of plasma source, the choice of gas, the power level, the RF bias, the gas flow rate), the operation of reacting the surface of the spacer layer 50 with a plasma-excited first etching gas to form a reaction layer 80 and the operation of removing the reaction layer 80 may vary the amount or thickness of the spacer layer removed. In some cases, the reaction and removal operations may be sequentially repeated or cyclically one or more times, while holding at least a portion of the spacer layer 50 in the recess 32 of the SiGe layer 30 (i.e., to form an inner spacer), until the side surface 42 of the Si channel layer 40 is exposed, fully exposed, or even the top and / or bottom surface of the Si channel layer 40 is partially exposed (i.e., reducing the size of the inner spacer). In some embodiments, the reaction operations on the surface of the spacer layer to form the reaction layer and the removal operations of at least a portion of the reaction layer may be collectively referred to, for example, as a conformal etching process.

[0024] Generally, high-quality epitaxial growth for forming source and drain regions after the intermediate structure shown in Figure 5 can be achieved if four main factors are met. First, a sufficient amount of spacer layer 50 is etched to adequately expose the leading edge or side 42 of the Si channel layer 40 (nanosheet). Second, the exposed leading edge or side 42 of the Si channel layer 40 (nanosheet) is not damaged by the etching process. Third, sufficient thickness of the spacer layer 50 is maintained above and / or on top of the intermediate structure to protect the silicon or polysilicon dummy gate from epitaxial nucleation during the formation of the source and drain regions (e.g., protecting the polysilicon dummy gate structure 70). Fourth, sufficient thickness of the spacer layer 50 is maintained in the recesses 32 of the SiGe layer 30 for isolation and structural reliability (i.e., sufficient inner spacers between nanosheets). Using a method according to one embodiment of the present disclosure may help satisfy these factors, for example, by providing a precisely controlled conformal etching process for the thinning and shaping of the spacer layer 50.

[0025] In some embodiments, the operation of reacting to form the reaction layer 80 and the operation of removing part or all of the reaction layer 80 may be performed at substantially the same substrate temperature or within the same substrate temperature range. For example, the substrate temperature may be approximately room temperature. For example, the same substrate temperature range may be 8 to 28 degrees Celsius, with some margin of approximately plus or minus 2 to 3 degrees Celsius on both sides of that range.

[0026] In some embodiments, the operation of reacting to form the reaction layer 80 and the operation of removing the reaction layer 80 may be performed using isotropic plasma exposure.

[0027] In some embodiments, a substrate including a patterned film stack can be introduced into a plasma processing chamber including an inductively coupled plasma (ICP) source. An exemplary plasma processing chamber including an ICP source is schematically shown in Figure 6.

[0028] In some embodiments, the substrate may be placed on an electrically unbiased substrate holder, thereby allowing sequential isotropic exposure of the patterned film stack to a plasma-excited first etching gas and a plasma-excited second etching gas. The isotropic exposure may be uniform in the vertical and horizontal directions on the patterned film stack. Alternatively, the substrate holder may be electrically biased, thereby allowing anisotropic exposure of the patterned film stack to a plasma-excited second etching gas. The anisotropic exposure may be primarily in the vertical direction on the patterned film stack (e.g., perpendicular to the wafer surface).

[0029] As described above, by cyclically forming and subsequently removing the reaction layer, controlled removal of the spacer layer thickness in each etching cycle may be possible. Exposure to the plasma-excited first etching gas and the plasma-excited second etching gas may be isotropic to provide uniform vertical and horizontal etching of the spacer layer (i.e., no electrical bias is applied to the substrate holder). In some embodiments, using isotropic exposure to the plasma-excited first etching gas and the plasma-excited second etching gas prevents excessive variation in the removal of the upper region versus the lower region with respect to the thinning of the spacer layer (or, for example, at least minimal or less variation in the removal of the upper region versus the lower region compared to the best known methods at present), and / or prevents excessive variation in the removal of the sparse region versus the dense region (or, for example, at least minimal or less variation in the removal of the sparse region versus the dense region compared to the best known methods at present).

[0030] In some embodiments, the cyclical formation and subsequent removal of the reaction layer, as described above, may be performed in a single plasma processing chamber, where the substrate is maintained at substantially the same substrate temperature during the processing operation. In some embodiments, the substrate holder may be electrically biased (to provide anisotropic plasma exposure) or not electrically biased (to allow isotropic plasma exposure) during the process operation. An advantage of using the method according to one embodiment of the present disclosure may be a reduction in the number of substrate transfer steps in the process tool, which may increase process stability and improve substrate throughput.

[0031] Figure 6 shows a chamber of a plasma processing system 800 that may be used to carry out a method for manufacturing semiconductor devices according to some embodiments of the present disclosure. The plasma processing system 800 may be used to perform a plasma etching process, for example, etching a patterned film stack including a spacer layer. The plasma processing system 800 may have a plasma processing chamber 850 configured to maintain plasma directly above a substrate 802 loaded on a substrate holder 810. A process gas may be introduced into the plasma processing chamber 850 through a gas inlet 822 and pumped out of the plasma processing chamber 850 through a gas outlet 824. The gas inlet 822 and the gas outlet 824 may each include a set of multiple gas inlets and gas outlets. The gas flow rate and chamber pressure may be controlled by a gas flow control system 820 coupled to the gas inlet 822 and the gas outlet 824. The gas flow control system 820 may comprise various components, such as a high-pressure gas canister, valves (e.g., throttle valves), pressure sensors, gas flow sensors, a vacuum pump, pipes, and an electronically programmable controller. The radio frequency (RF) bias power supply 834 and the RF source power supply 830 may be coupled to the respective electrodes of the plasma processing chamber 850. The substrate holder 810 may also be an electrode coupled to the RF bias power supply 834 (for example, to provide an electrically biased substrate holder). The RF source power supply 830 may be coupled to a helical electrode 832 wound around the dielectric sidewall 816. The gas inlet 822 may be an opening in the top plate 812. The gas outlet 824 may be an opening in the bottom plate 814. The top plate 812 and the bottom plate 814 may be conductive and may be electrically connected to the system ground (reference potential).

[0032] The plasma processing system 800 is merely an example. In various alternative embodiments, the plasma processing system 800 may be configured to maintain inductively coupled plasma (ICP) using RF source power coupled to a planar coil on an upper dielectric cover, or capacitively coupled plasma (CCP) maintained using a disc-shaped upper electrode in the plasma processing chamber 850. Alternatively, other suitable configurations such as an electron cyclotron resonance (ECR) plasma source and / or a helical resonator may be used. The RF bias power supply 834 may be used to supply continuous wave (CW) power or pulsed RF power to maintain the plasma. According to some embodiments, the RF bias power supply 834 may not be powered so that the substrate holder 810 is not electrically biased. The gas inlet and gas outlet may be coupled to the sidewall of the plasma processing chamber, and in some embodiments, pulsed RF power supplies and pulsed DC power supplies may also be used. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rate, and other plasma processing parameters can be selected according to the respective process recipe. In some embodiments, remote plasma systems and / or batch systems may be used. For example, a substrate holder may be configured to support multiple wafers that are rotated about a central axis as they pass through different plasma zones.

[0033] Accordingly, some embodiments of the present disclosure can provide semiconductor processing using existing or newly developed plasma processing systems to enable room-temperature self-limiting conformal etching of carbon-containing and oxygen-containing materials, focusing on low dielectric constant materials such as SiOCN. Methods according to some embodiments of the present disclosure can address and resolve etching profile issues present in conventional methods, such as top / bottom and sparse / dense etching differences, thereby promoting high-quality epitaxial growth in advanced structures.

[0034] In some embodiments, an ICP reactor can be used to grow ammonium siliconfluoride (AFS) on the surface oxide film and oxygen-containing material such as SiOCN to form a modified surface layer, and the modified surface layer can then be etched by sublimating the AFS using an ion-assisted process. In some embodiments, a cyclic pulsed plasma technique can enable highly controlled conformal etching of or on nanosheet structures. In some embodiments, the removal of the oxide film and oxygen-containing material can be self-rate-limited to about 1 nm of the surface, where the AFS grows on the surface and is then removed in a subsequent step.

[0035] The graph in Figure 7 shows experimental results for several exemplary etching amounts (in nm) for several exemplary materials (SiN, SiO2, polysilicon, SiOCN, and SiCN) at various reaction times (in seconds) for forming the reaction layer of AFS using several methods according to several embodiments of the present disclosure. The graph in Figure 7 shows that the amount of material conformally etched per cycle can be adjusted and fine-tuned for a wide variety of uses and applications.

[0036] In some embodiments, based on the selection of a plasma-excited second etching gas for the spacer layer material, the underlying spacer layer is not removed, or is only minimally removed, by ion bombardment upon exposure to the plasma-excited second etching gas while the reaction layer is being removed and / or after the reaction layer has been removed. This selective etching of the reaction layer over an unreacted / unmodified spacer layer, combined with the self-limiting nature of reaction layer formation (as described above), can provide the advantages of a precisely controlled conformal etching process. For example, by controlling the reaction time for forming the reaction layer, and / or by selecting gas, material, and plasma processing parameters, a predictable and reproducible thickness of the reaction layer (e.g., a thickness of 1 nm per cycle may be possible) can be formed and then removed for a precisely controlled, uniform conformal etching process.

[0037] Next, some advantages that can be achieved by implementing some embodiments of the present disclosure will be described. Some methods according to some embodiments can provide surface growth of AFS to enhance conformal removal of native oxide films. Advantages of using some method embodiments may include self-limiting selective etching of oxide films and low dielectric constant materials. Advantages of using some method embodiments may include controlled thickness removal per cycle. Advantages of using some method embodiments may include their potential use as part of or as a substitute for isotropic quasi-atomic layer etching (qALE) techniques. Advantages of using some method embodiments may include conformal deposition and removal of AFS using unbiased plasma. Advantages of using some method embodiments may include uniform vertical and lateral etching with minimal or no excessive top loss or sparse / dense difference compared to conventional biased processes. Advantages of using some method embodiments may include the resolution of top / bottom difference and sparse / dense difference problems to less than 1 nm. An advantage of using some method embodiments may be the ability to use a single existing plasma processing system or platform (e.g., the Model ACTIA platform by Tokyo Electron Limited (TEL)) for the AFS-based selective etching and subsequent inner spacer etching steps, thereby reducing tool movement and improving throughput. An advantage of using some method embodiments may be the provision of a single temperature process for process stability at room temperature, etc. (i.e., no extra heating or thermal budget is required). Thus, some embodiments of the present disclosure can overcome the problems of the conventional processing methods described above with reference to Figures 1A to 1C.

[0038] Figure 8 shows a flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of the present disclosure.

[0039] In one embodiment, a method for forming a semiconductor device includes providing a substrate having a patterned structure containing a semiconductor material, wherein the patterned structure has a side profile including depressions, and a spacer layer conformally deposited on and within the depressions of the patterned structure (box 910). The method includes reacting the surface of a spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen to form the reaction layer (box 920). The method also includes removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas (box 930).

[0040] Figure 9 shows a flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of the present disclosure.

[0041] In one embodiment, a method for forming a semiconductor device provides a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, and the spacer layer comprises a silicon-carbon-containing material, a silicon-oxygen-containing material, or a silicon-carbon-oxygen-containing material (box 940). The method also comprises reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen, and the reaction layer comprises ammonium silicofluoride (AFS) (box 950). This method includes removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas (box 960). This method includes sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, while exposing the side surface of the first film while retaining at least a portion of the spacer layer in the depression of the second film (box 970).

[0042] Figure 10 shows a flowchart for performing ion-assisted self-limiting conformal etching according to one embodiment of the present disclosure.

[0043] In one embodiment, a method for forming a semiconductor device provides a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, and a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, the spacer layer comprising SiOCN (Box 1010). The method also includes forming a reaction layer on the spacer layer by reacting the surface of the spacer layer with a plasma-excited first etching gas, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen, and the reaction layer comprises ammonium silicofluoride (AFS) (Box 1020). The method also includes removing at least a portion of the reaction layer by ion bombardment resulting from exposure to a plasma-excited second etching gas (Box 1030). This method involves sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, while retaining at least a portion of the spacer layer in a recess of the second film, and includes exposure of the side surface of the first film (box 1040), wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure in the same chamber of the same plasma processing system, and the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range of 8 to 28 degrees Celsius.

[0044] The embodiments described in Figures 8 to 10 can be implemented as described in detail using Figures 1 to 7.

[0045] Herein, we summarize further exemplary embodiments of the present disclosure. Other embodiments can also be understood from the entirety of this specification and the claims filed herein.

[0046] Example 1. A method for forming a semiconductor device, the method comprising: providing a substrate having a patterned structure comprising a semiconductor material, wherein the patterned structure has a side profile including depressions, and a spacer layer conformally deposited on and within the depressions of the patterned structure; and a method comprising: reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen to form the reaction layer; and removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas.

[0047] Example 2. The method according to Example 1, wherein the patterned structure comprises a patterned film laminate comprising alternating first and second films stacked vertically, the first film having a first external dimension and the second film having a second external dimension, the second film having a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film laminate and in the recess of the second film, and removing at least a portion of the reaction layer exposes the sides of the first film while retaining at least a portion of the spacer layer in the recess of the second film.

[0048] Example 3. The method according to Example 1 or 2, further comprising sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while retaining at least a portion of the spacer layer in the recess of the second film.

[0049] Example 4. The method according to any one of Examples 1 to 3, wherein the surface reaction of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range.

[0050] Example 5. The method described in any one of Examples 1 to 4, wherein the same substrate temperature range is 8 to 28 degrees Celsius.

[0051] Example 6. The method according to any one of Examples 1 to 5, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure.

[0052] Example 7. The method according to any one of Examples 1 to 6, wherein the reaction on the surface of the spacer layer comprises generating a first etching gas plasma-excited in a first chamber of a plasma processing system using a capacitively coupled plasma (CCP) source, and removing at least a portion of the reaction layer comprises generating a second etching gas plasma-excited in a first chamber of a plasma processing system using a CCP source.

[0053] Example 8. The method according to any one of Examples 1 to 7, further comprising supporting the substrate using an electrically unbiased substrate holder.

[0054] Example 9. The method according to any one of Examples 1 to 8, wherein the spacer layer contains a silicon-carbon material, a silicon-oxygen material, a silicon-nitrogen material, or a silicon-carbon-oxygen material.

[0055] Example 10. The method according to any one of Examples 1 to 9, wherein the spacer layer comprises SiO2, SiC, SiN, SiOC, or SiCN.

[0056] Example 11. The method according to any one of Examples 1 to 10, wherein the reaction layer includes an ammonium silicofluoride (AFS) layer.

[0057] Example 12. The method according to any one example from Examples 1 to 11, wherein the plasma-excited first etching gas includes SF6, NF3, N2, H2, NH3, HF, CF4, CHF3, CH2F2, CH3F, or any combination thereof.

[0058] Example 13. The method according to any one of Examples 1 to 12, wherein the plasma-excited first etching gas contains SF6, H2, and N2, or the plasma-excited first etching gas contains NF3, H2, and N2.

[0059] Example 14. The method according to any one of Examples 1 to 13, wherein the plasma-excited second etching gas includes N2, H2, O2, Ar, CO, He, Kr, Xe, or any combination thereof.

[0060] Example 15. A method for forming a semiconductor device, wherein the method provides a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, and the spacer layer comprises a silicon-carbon-containing material, a silicon-oxygen-containing material, a silicon-nitrogen-containing material, or a silicon-carbon-oxygen-containing material. A method comprising: reacting the surface of a spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen, and the reaction layer contains ammonium silicofluoride (AFS); removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas; and sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while retaining at least a portion of the spacer layer in the depression of the second film.

[0061] Example 16. The method according to Example 15, wherein the reaction on the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range, which is 8 to 28 degrees Celsius.

[0062] Example 17. The method according to Example 15 or 16, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure, the spacer layer comprises SiOCN, and the plasma-excited first etching gas comprises SF6, H2, and N2, or the plasma-excited first etching gas comprises NF3, H2, and N2, and the plasma-excited second etching gas comprises N2, H2, O2, Ar, CO, He, Kr, Xe, or any combination thereof.

[0063] Example 18. A method for forming a semiconductor device, the method providing a substrate having a patterned film stack comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film stack and in the recess of the second film, the spacer layer comprising SiOCN, and reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas comprises fluorine, hydrogen, and nitrogen. A method comprising: forming a reaction layer containing ammonium silicate (AFS); removing at least a portion of the reaction layer by ion bombardment caused by exposure to a plasma-excited second etching gas; and sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while retaining at least a portion of the spacer layer in a recess of the second film, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure in the same chamber of the same plasma processing system, and the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range of 8 to 28 degrees Celsius, and the exposure of the side surface of the first film.

[0064] Example 19. The method according to Example 18, wherein the plasma-excited first etching gas contains SF6, H2, and N2, or the plasma-excited first etching gas contains NF3, H2, and N2.

[0065] Example 20. The method according to Example 18 or 19, wherein the plasma-excited second etching gas includes N2, H2, O2, Ar, CO, He, Kr, Xe, or any combination thereof.

[0066] While illustrative embodiments for illustrative purposes have been described with reference to the explanatory drawings, this specification is not intended to be constrained. Various modifications and combinations of the illustrative embodiments for illustrative purposes, as well as other embodiments, will be apparent to those skilled in the art by reference to this disclosure. Accordingly, the appended claims are intended to encompass all such modifications, equivalents, or embodiments.

Claims

1. A method for forming a semiconductor device, wherein the method is To provide a substrate having a patterned structure containing a semiconductor material, wherein the patterned structure has a side profile including depressions, and a spacer layer is conformally deposited on and within the patterned structure. The process involves reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen to form the reaction layer. At least a portion of the reaction layer is removed by ion bombardment caused by exposure to a plasma-excited second etching gas. Methods that include...

2. The patterned structure includes a patterned film laminate comprising alternating first and second films stacked vertically, wherein the first film has a first external dimension, the second film has a second external dimension, and the second film has the recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, and the spacer layer is conformally deposited on the patterned film laminate and in the recess of the second film. The method according to claim 1, wherein removing at least a portion of the reaction layer exposes the side surface of the first film while retaining at least a portion of the spacer layer in the recess of the second film.

3. The method according to claim 2, further comprising sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, thereby exposing the side surface of the first film while holding at least a portion of the spacer layer in the recess of the second film.

4. The method according to claim 1, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range.

5. The method according to claim 4, wherein the same substrate temperature range is 8 degrees Celsius to 28 degrees Celsius.

6. The method according to claim 1, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure.

7. The method according to claim 6, wherein the reaction on the surface of the spacer layer comprises generating the plasma-excited first etching gas in a first chamber of a plasma processing system using a capacitively coupled plasma (CCP) source, and the removal of at least a portion of the reaction layer comprises generating the plasma-excited second etching gas in the first chamber of the plasma processing system using the CCP source.

8. The method according to claim 7, further comprising supporting the substrate using an electrically unbiased substrate holder.

9. The method according to claim 1, wherein the spacer layer comprises a silicon-carbon-containing material, a silicon-nitrogen-containing material, a silicon-oxygen-containing material, or a silicon-carbon-oxygen-containing material.

10. The spacer layer is SiO ２ The method according to claim 9, comprising SiC, SiN, SiOC, or SiOCN.

11. The method according to claim 10, wherein the reaction layer includes an ammonium silicafluoride (AFS) layer.

12. The plasma-excited first etching gas is SF ６ , NF ３ , N ２ , H ２ , NH ３ , HF, CF ４ , CHF ３ , CH ２ F ２ , CH ３ F, or any combination thereof, the method according to claim 1.

13. The plasma-excited first etching gas is SF ６ , H ２ , and N ２ The first etching gas contains NF ３ , H ２ , and N ２ The method according to claim 1, comprising:

14. The plasma-excited second etching gas is N ２ , H ２ , O ２ The method according to claim 1, comprising Ar, CO, He, Kr, Xe, or any combination thereof.

15. A method for forming a semiconductor device, wherein the method is To provide a substrate having a patterned film laminate comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film laminate and in the recess of the second film, and the spacer layer comprises a silicon-carbon-containing material, a silicon-nitrogen-containing material, a silicon-oxygen-containing material, or a silicon-carbon-oxygen-containing material. The process involves reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen, and the reaction layer contains ammonium silicofluoride (AFS). At least a portion of the reaction layer is removed by ion bombardment caused by exposure to a plasma-excited second etching gas, The reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are repeated sequentially at least once, so that at least a portion of the spacer layer is held in the recess of the second film while the side surface of the first film is exposed. Methods that include...

16. The method according to claim 15, wherein the reaction on the surface of the spacer layer and the removal of at least a portion of the reaction layer are carried out within the same substrate temperature range, the same substrate temperature range being 8 degrees Celsius to 28 degrees Celsius.

17. The reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure. The spacer layer includes SiOCN, The plasma-excited first etching gas is SF ６ , H ２ , and N ２ The first etching gas contains NF ３ , H ２ , and N ２ It contains, The plasma-excited second etching gas is N ２ , H ２ , O ２ The method according to claim 15, comprising Ar, CO, He, Kr, Xe, or any combination thereof.

18. A method for forming a semiconductor device, wherein the method is To provide a substrate having a patterned film laminate comprising vertically stacked alternating first and second films, wherein the first film has a first external dimension, the second film has a second external dimension, the second film has a recess such that the second external dimension of the second film is smaller than the first external dimension of the first film, a spacer layer conformally deposited on the patterned film laminate and in the recess of the second film, and the spacer layer comprises SiOCN. The process involves reacting the surface of the spacer layer with a plasma-excited first etching gas to form a reaction layer on the spacer layer, wherein the plasma-excited first etching gas contains fluorine, hydrogen, and nitrogen, and the reaction layer contains ammonium silicofluoride (AFS). At least a portion of the reaction layer is removed by ion bombardment caused by exposure to a plasma-excited second etching gas, The process of sequentially repeating the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer at least once, while holding at least a portion of the spacer layer in the recess of the second film, wherein the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed using isotropic plasma exposure in the same chamber of the same plasma processing system, and the reaction of the surface of the spacer layer and the removal of at least a portion of the reaction layer are performed within the same substrate temperature range of 8 to 28 degrees Celsius, thereby exposing the side surface of the first film. Methods that include...

19. The plasma-excited first etching gas is SF ６ , H ２ , and N ２ The first etching gas contains NF ３ , H ２ , and N ２ The method according to claim 18, comprising:

20. The plasma-excited second etching gas is N ２ , H ２ , O ２ The method according to claim 18, comprising Ar, CO, He, Kr, Xe, or any combination thereof.

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