High-concentration doped semiconductor devices for power distribution

Abstract

A device comprising a first integrated device die and a semiconductor device. The first integrated device die may include a die insulating layer and die conductive features at least partially embedded in the die insulating layer. The semiconductor device may include a first insulating layer on a first surface, device conductive features at least partially embedded in the first insulating layer, and a first highly doped semiconductor material electrically connected to the device conductive features. The die conductive features may be connected to power or ground at least via the first highly doped semiconductor material.

Description

[Technical Field]

[0001] (Integrated by reference) This application claims priority under U.S. Nonprovisional Application No. 18 / 745238, filed on 17 June 2024, and U.S. Provisional Application No. 63 / 511598, filed on 30 June 2023, which are incorporated herein by reference. All applications in which foreign or national priority claims are identified in the application data sheets filed with this application are incorporated herein by reference pursuant to 37 CFR 1.57.

[0002] This field relates to bonded structures, and more particularly to bonded structures in which semiconductor materials are highly doped for power distribution. [Background technology]

[0003] As semiconductor device features become smaller, concerns about power supply are increasing due to challenges such as thermal issues, electrical insulation problems, limitations on feature size, and losses due to passing through numerous metal layers, making efficient power supply to semiconductor devices difficult. Therefore, there remains a continuing need for improved power supply devices.

[0004] Detailed explanations are provided in the attached drawings. When the same number is used in different drawings, it indicates similar or identical items.

[0005] In this description, the illustrated devices and systems are shown having multiple components. Various embodiments of the devices and / or systems described herein are within the scope of this disclosure even if they include fewer components. Alternatively, other embodiments of the devices and / or systems are within the scope of this disclosure even if they include additional components or various combinations of the components described. [Brief explanation of the drawing]

[0006] [Figure 1A] This is a schematic side cross-sectional view of a power supply device soldered to an integrated device die.

[0007] [Figure 1B] This is a schematic side cross-sectional view of a power supply device in which multiple integrated device dies and an interposer are joined together.

[0008] [Figure 2A] This is a schematic side cross-sectional view of a junction structure including a semiconductor device having an interposer configured to supply power to one or more integrated device dies. [Figure 2B] This is a schematic side cross-sectional view of a junction structure including a semiconductor device having an interposer configured to supply power to one or more integrated device dies.

[0009] [Figure 3A] This is a schematic side cross-sectional view of a semiconductor device containing a highly doped semiconductor material according to various embodiments. [Figure 3B] This is a schematic side cross-sectional view of a semiconductor device containing a highly doped semiconductor material according to various embodiments. [Figure 3C] This is a schematic side cross-sectional view of a semiconductor device containing a highly doped semiconductor material according to various embodiments. [Figure 3D] This is a schematic side cross-sectional view of a semiconductor device containing a highly doped semiconductor material according to various embodiments.

[0010] [Figure 4] This is a schematic side cross-sectional view of a semiconductor device, including a highly doped semiconductor material connected to the back surface of an integrated device die.

[0011] [Figure 5] This is a schematic side cross-sectional view of a semiconductor device, including a highly doped semiconductor material connected to the surface of an integrated device die.

[0012] [Figure 6]Schematic side cross-sectional view of a semiconductor device including a high-concentration doped semiconductor material that is connected to a plurality of integrated device dies and functions as an interposer when power supply is provided from above the semiconductor device.

[0013] [Figure 7] Schematic side cross-sectional view of a semiconductor device including a high-concentration doped semiconductor material that is connected to a plurality of integrated device dies and functions as an interposer when power supply is provided from below the semiconductor device.

[0014] [Figure 8A] Schematic side cross-sectional view of a semiconductor device including a high-concentration doped semiconductor material and a cooling channel mounted on the back surface of the integrated device die (e.g., directly hybrid bonded).

[0015] [Figure 8B] Schematic top view of a semiconductor device including a high-concentration doped semiconductor material temperature-controlled by a cooling channel.

[0016] [Figure 9A] Schematic side cross-sectional view of a semiconductor element prepared for direct hybrid bonding without an intervening adhesive.

[0017] [Figure 9B] Schematic side cross-sectional view of a structure directly hybrid bonded without an intervening adhesive.

Summary of the Invention

Problems to be Solved by the Invention

[0018] Power distribution or power supply devices may supply power to electronic components (such as integrated device dies) using a metal plane or metal wire with a high coefficient of thermal expansion (CTE). The metal plane within the power supply device is formed to a thickness that supports the power requirements of a single integrated device die or a stack of integrated device dies. As a result, the stacked die may not receive sufficient power from the power supply device due to the limited power capacity of the metal plane. Furthermore, thermomechanical stress is applied to the metal plane throughout the stack due to the difference in CTE between the die or die stack and the metal plane. In addition, the device is typically limited by the space required to connect vias to the metal plane. Thus, there remains an ongoing need for improved power distribution or power supply devices.

[0019] Providing an adequate amount of power to one or more integrated device dies can be challenging. In particular, some power supply devices use a metal plane to supply power and ground to integrated device dies. For example, a metal plane can be used as a panel-level redistribution layer (RDL). The RDL may be a multi-die power supply medium / structure manufactured as a panel used to provide power. Because metal planes have a high CTE, the metal expands when heated. This expansion of the metal plane within a power supply device results in high mechanical and thermal strain at the junctions connecting the device and / or power paths. To mitigate or prevent strain in power supply devices, the metal plane is often kept cool, limiting the power it can supply. Increasing the size of the metal plane to allow higher currents while limiting temperature can increase the effects of a high CTE and the physical stresses caused by it. Furthermore, reducing the thickness of the RDL layer to allow more layers in the same limited space offers design advantages. Due to CTE limitations and space requirements, a metal RDL plane may not be thick enough to provide power to both sides (e.g., top and bottom) of a power supply device. Furthermore, when stacking multiple integrated device dies and supplying power from a power supply device, the power may be insufficient.

[0020] Furthermore, metal vias are used for each additional power connection to connect the metal plane to the integrated device die. Due to the limited amount of space, there is a limit to the number of connections (power, signal, and / or ground connections) that can be formed between the power supply device and the integrated device die. In particular, in some devices, power, ground, and signal connections are made on the surface active side of the chip. In such devices, power and ground connections occupy valuable space in the wiring layer, reducing the number of signal lines that can be connected to the surface active circuit. Attempts to overcome these challenges have included adding an interposer layer to the power supply device. Such attempts have revealed that the metal is not thick enough to supply sufficient power. Moreover, the interposer layer does not eliminate the space constraints that limit the number of connections that can be formed with vias. [Means for solving the problem]

[0021] The embodiments disclosed herein have the advantage of addressing these challenges by providing methods and structures for providing power and ground to an integrated device die using highly doped semiconductor material within a semiconductor power supply device. In some embodiments, the semiconductor power supply device can be bonded to the back surface of the die opposite the active surface of the die (e.g., direct hybrid bonding). In such embodiments, back-side bonding to the die can increase the number of signal connections on the die's surface (which may include the active surface). In other embodiments, the semiconductor power supply device can be bonded to the active surface of the die (e.g., direct hybrid bonding). The disclosed embodiments can more effectively utilize limited space and maintain multiple potentials, including power and / or ground, while preventing thermal stress.

[0022] Some examples: A semiconductor device comprising: a first layer comprising a first highly doped semiconductor material and a first insulating junction layer; a second layer comprising a second highly doped semiconductor material and a second insulating junction layer; and a first via extending through the second layer and electrically connected to the first highly doped semiconductor material, wherein the first layer and the second layer are directly bonded to each other without an intervening adhesive.

[0023] Some examples: The semiconductor device wherein the first via connects either power or ground to the first highly doped semiconductor material of the first layer. Some examples: The semiconductor device wherein the first layer further comprises a first conductive feature, and the second layer further comprises a second conductive feature, wherein the first conductive feature and the second conductive feature are directly bonded to each other without an intervening adhesive. Some examples: The semiconductor device wherein the second layer is hybrid-bonded to the first layer such that the second insulating bonding layer of the second layer is directly bonded to the first insulating bonding layer of the first layer, and the second conductive feature of the second layer is directly bonded to the first conductive feature of the first layer.

[0024] Some examples: The semiconductor device further comprising a third layer comprising a third highly doped semiconductor material and a third insulating junction layer, wherein the second layer and the third layer are directly bonded to each other without an intervening adhesive. Some examples: The semiconductor device further comprising an insulating ring around the first via of the first layer. Some examples: The semiconductor device having a plurality of dielectric spacers embedded in the first highly doped semiconductor material, which isolates the first highly doped semiconductor material into highly doped semiconductor islands. Some examples: The semiconductor device having a first highly doped semiconductor island of the highly doped semiconductor island connected to a first power supply at a first voltage, and a second highly doped semiconductor island of the highly doped semiconductor island connected to ground.

[0025] Some examples: The semiconductor device wherein the plurality of highly doped semiconductor islands are configured to be connected to different potentials. Some examples: The semiconductor device wherein the second highly doped semiconductor material is connected to electrical ground. Some examples: The semiconductor device wherein the first highly doped semiconductor material includes an insulating end cap. Some examples: The first highly doped semiconductor material and the second highly doped semiconductor material each have at least 10 18 atoms / cm 3 and 10 22 atoms / cm 3 The semiconductor device having a dopant concentration less than a certain amount. Some examples: The semiconductor device further comprising: a fluid inlet; an inlet channel connected to the fluid inlet; a fluid outlet; an outlet channel connected to the outlet; and one or more cooling channels extending at least through the first insulating layer, wherein the one or more cooling channels are connected to the inlet channel and the outlet channel.

[0026] Some examples: The semiconductor device wherein the inlet, the inlet channel, and the one or more cooling channels are arranged to allow fluid to flow into the semiconductor device, thereby connecting the inlet channel and the one or more cooling channels integrally, so that the fluid can flow from the inlet channel to the one or more cooling channels. Some examples: The semiconductor device wherein the outlet, the outlet channel, and the one or more cooling channels are arranged to allow fluid to flow out of the semiconductor device, thereby connecting the one or more cooling channels and the outlet channel integrally, so that the fluid can flow from the one or more cooling channels to the outlet channel and exit the semiconductor device at the outlet. Some examples: The semiconductor device wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity, the cavity sealing a cooling fluid.

[0027] Some examples: The semiconductor device wherein the cooling fluid is a dielectric fluid. Some examples: The semiconductor device wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity and a barrier surrounding the cavity, the barrier separating the cavity from the first insulating junction layer. Some examples: A junction structure comprising the semiconductor device, wherein the junction structure further comprises an integrated device die, the integrated device die comprises a front and a back surface, and the semiconductor device is directly bonded to the integrated device die.

[0028] Some examples: A bonding structure comprising: a first integrated device die having a front surface and a back surface, wherein the first integrated device die includes a die insulating layer and die conductive features at least partially embedded in the die insulating layer; and a semiconductor device having a first surface and a second surface opposite the first surface, wherein the semiconductor device includes on the first surface a first insulating layer, device conductive features at least partially embedded in the first insulating layer, and a first highly doped semiconductor material electrically connected to the device conductive features, wherein the first insulating layer is directly bonded to the die insulating layer without an intervening adhesive, and the die conductive features are directly bonded to the device conductive features without an intervening adhesive, wherein the die conductive features are connected to power or ground at least via the first highly doped semiconductor material.

[0029] Some examples: The bonding structure wherein the surface of the first integrated device die is an active side including one or more transistors, and the one or more transistors are located closer to the surface than to the back surface. Some examples: The bonding structure wherein the semiconductor device is directly bonded to the back surface of the first integrated device die without an intervening adhesive. Some examples: The bonding structure wherein the semiconductor device includes a second highly doped semiconductor material disposed on a first highly doped semiconductor material.

[0030] Some examples: The bonding structure wherein the first highly doped semiconductor material is connected to either a first power or ground, the second highly doped semiconductor material is connected to either a second power or ground, and the first highly doped semiconductor material and the second highly doped semiconductor material are electrically connected to the first integrated device die. Some examples: The bonding structure further comprises vias extending through the first highly doped semiconductor material, the vias electrically connecting the die conductive features to the second highly doped semiconductor material. Some examples: The bonding structure further comprises a second integrated device die having a second insulating layer on its back surface, the second integrated device die being directly bonded to the semiconductor device on the side opposite to the first integrated device die.

[0031] Some examples: The bonding structure wherein the first highly doped semiconductor material is a conductive material whose coefficient of thermal expansion (CTE) of the first highly doped semiconductor material is within 50% to 150% of the CTE of the device portion of the first integrated device die. Some examples: The bonding structure further comprises a fluid inlet, an inlet channel connected to the fluid inlet, a fluid outlet, an outlet channel connected to the outlet, and one or more cooling channels extending at least through the first insulating layer, wherein the one or more cooling channels are connected to the inlet channel and the outlet channel. Some examples: The semiconductor device wherein the inlet, the inlet channel, and the one or more cooling channels are arranged to allow fluid to flow into the semiconductor device, thereby connecting the inlet channel and the one or more cooling channels integrally, and allowing the fluid to flow from the inlet channel to the one or more cooling channels.

[0032] Some examples: The semiconductor device wherein the outlet, the outlet channel, and the one or more cooling channels are arranged to allow fluid to flow out of the semiconductor device, thereby integrally connecting the one or more cooling channels and the outlet channel, so that the fluid can flow from the one or more cooling channels to the outlet channel and exit the semiconductor device at the outlet. Some examples: The semiconductor device wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity, the cavity sealing a cooling fluid. Some examples: The semiconductor device wherein the cooling fluid is a dielectric fluid. Some examples: The semiconductor device wherein the inlet, the inlet channel, the outlet, the outlet channel, and the one or more cooling channels include a cavity and a barrier surrounding the cavity, the barrier separating the cavity from the first insulating junction layer.

[0033] Some examples: A method comprising depositing a first insulating junction layer on a highly doped semiconductor material, at least partially embedding conductive features in the first insulating junction layer, and preparing the first insulating junction layer for hybrid bonding with an electronic component, wherein the highly doped semiconductor material has a coefficient of thermal expansion (CTE) within 50% to 150% of the CTE of the device portion of the electronic component. Some examples: The method further comprising directly bonding a second insulating junction layer of the electronic component to the first insulating junction layer, and directly bonding a second conductive feature of the electronic component to a first conductive feature at least partially embedded in the first insulating junction layer. Some examples: The method comprising a highly doped semiconductor material.

[0034] Some examples: A bonded structure comprising: a highly doped semiconductor material having a first insulating bond layer on a first surface and a first conductive feature at least partially embedded in the first insulating bond layer; and an electronic component having a second insulating bond layer and a second conductive feature at least partially embedded in the second insulating bond layer, wherein the first insulating bond layer is directly bonded to the second insulating bond layer without an intervening adhesive, and the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, wherein the highly doped semiconductor material has a coefficient of thermal expansion (CTE) within 50% to 150% of the CTE of the device portion of the electronic component. Some examples: The bonded structure comprising the highly doped semiconductor material. [Modes for carrying out the invention]

[0035] Figure 1A shows a schematic side cross-sectional view of a power supply device 116 soldered to the back surface 106 of an integrated device die 102, opposite the front surface 104. The front surface 104 may have, for example, one or more transistors on the active side, closer to the active surface 104 than the back surface 106. In the illustrated device 116, power within the device 116 is wired to the integrated device die 102 via metal planes or metal planes 110 (e.g., planes 110a to 110c) separated by an insulating layer 112. The metal planes 110 are individually connected to electrical connectors 118 (e.g., bonding wires) via upper conductive contact features or pads 122, providing first power from electrical connector 118a on metal plane 110a, ground from electrical connector 118c on metal plane 110b, and second power from electrical connector 118b on metal plane 110c. The metal plane 110 and the insulating layer 112 are patterned to route power and ground to the corresponding pads 114 on the integrated device die 102. The conductive pads 114 on the die and the conductive pads 122 on the underside of the device 116 can be connected using solder 108. The conductive pads 114 and 122 may include suitable metals such as copper, nickel, and gold. The metal pad 122 on the die 102 can be connected in a continuous manner to the lower metal plane 110c (for example, the pad 122 can be connected directly to the metal layer of plane 110c). The pad 114 on the die 102 can be electrically connected to the upper and intermediate metal planes 110a and 110b using conductive vias 124 (e.g., metal vias). Together, the metal pads 114 and 122 and the vias 124 provide power and ground from the metal plane 110 to the integrated device die 102. To transmit potential from the electrical connector 118 to the metal plane 110, the metal plane 110 receives power from the electrical connector 118, which is attached to metal pads 122 and vias 124 as needed.For example, electrical connector 118a provides a first potential (e.g., a first power level) to metal plane 110a via metal pad 122, electrical connector 118c connects metal plane 110b to a second potential (e.g., electrical ground) using metal pad 122 and via 124, and electrical connector 118b provides a third potential (e.g., a second power level) to metal plane 110c via metal pad 122 and via 124. Metal plane 110 is connected to integrated device die 102 using a bonding method such as solder 108 connecting the metal pad 122 of device 116 to the metal pad 114 on the back surface of integrated device die 102. Power supplied by device 116 to the conductive pad 114 on the back surface 106 of integrated device die 102 can be transmitted to transistors and devices on surface 104 using through-substrate vias or through-silicon vias (TSVs) (not shown in Figure 1A). These TSVs may be through-vias or blind vias (e.g., power vias, nanoTSVs, etc.) that supply power to transistors.

[0036] In Figure 1A, the metal pads 114 and 122 and the metal plane 110 are made of one or more metals with a high CTE (for example, copper with a CTE of about 17 ppm / °C). The device and material to which the metal plane 110 and the metal pads 114 and 122 are attached (for example, semiconductor material or dielectric material) generally has a lower CTE, for example, in the range of 0.2 ppm / °C to 5 ppm / °C. Due to the mismatch in CTE, as the temperature rises, the metals expand differently from the device and material to which the metal plane 110 and the metal pads 114 and 122 are attached. For example, when the metal plane 110 conducts electricity and supplies power from the device 116 to the integrated device die 102, the metal pad 114 heats up and expands along with the metal plane 110, causing strain in the solder joint connecting the metal pad 114 and the integrated device die 102, and in the device 116 and device die 102, which expand more slowly. Such distortion may damage device 116, die 102, and / or solder 108 or other connections connecting device 116 and integrated device die 102.

[0037] Furthermore, in a device like the one shown in Figure 1A, relying solely on the metal plane 110 may not provide sufficient power to support the power distribution of the device 116 to the integrated device die 102 on multiple sides. Figure 1B shows a schematic side cross-sectional view of a device 116 bonded to a substrate 120 with multiple integrated device dies 102. The integrated device die 102c can be mounted on the substrate 120, and the lower part of the power supply device 116 can be mounted on the integrated device die 102c. The integrated device die 102b can be mounted on the upper side of the power supply device 116, and the integrated device die 102a can be mounted on the integrated device die 102b. In various embodiments, the power supply device 116 can function as an interposer, enabling the ability to supply power to the integrated device die 102 from the top and bottom of the device 116. For example, the device 116 can be bonded to the surface 104 of the integrated device die 102b. The integrated device die 102a can be bonded to the back surface 106 of the integrated device die 102b connected to the device 116. The integrated device die 102c can be bonded to the device 116 by the back surface 106 and mounted to the substrate 120. In this configuration, the device 116 can function as an interposer for electrically connecting the integrated device die 102 together, for example, as an interposer for providing potential (power and / or ground) to the die. In Figure 1B, dies 102b and 102c can be directly hybrid bonded to the power supply device 116, and die 102a can be directly hybrid bonded to die 102b. In some embodiments, die 102c can be directly hybrid bonded to the substrate 120. In other embodiments, other bonding methods (such as flip-chip or solder bonding, or thermal compression bonding) can be used. Note that, although not shown in Figure 1B, the die 102 (e.g., dies 102b and 102c) may be provided with through-substrate vias (TSVs) for transmitting signals and / or power and ground through dies 102b and 102c.

[0038] Figures 2A and 2B show an example of a power supply device 206 configured to supply power from a metal plane 110 within device 206 to a die 102. Specifically, Figures 2A and 2B show schematic side cross-sectional views of a bonding structure 200 including device 206 with an embedded interposer 202. As previously stated, device 206 utilizes the metal plane 110 as an RDL to distribute power and / or ground to the integrated device die 102. A first power level (e.g., a non-zero potential difference or voltage) is supplied to the first metal plane 110a from an electrical connector 118b. The metal plane 110b is connected to the potential of the electrical connector 118a. The integrated device die 102 receives the first power level from the power supply device 206 via a via 124 connecting the metal plane 110a to a metal pad 122 connected to the electrical connector 118b. The current passes through a metal pad 122 connected to a metal pad 114 of the die 102 using, for example, solder 108, connecting the device 206 to the back surface 106 of the integrated device die 102. The back surface 106 of the integrated device die 102 faces the front surface 104 of the integrated device die 102. The front surface 104 may be on the active side, which includes one or more transistors, in which case the one or more transistors are positioned closer to the front surface 104 than to the back surface 106.

[0039] The buried interposer 202 is also connected to the integrated device die 102 using solder 108. The buried interposer connects the devices and provides additional power and ground connections. In various embodiments, the interposer 202 may include semiconductor materials, dielectric materials, and the like.

[0040] Figure 2B shows a power supply device 206 in which multiple integrated device dies 102a to 102c are stacked. In addition to the embedded interposer 202, this stack includes a substrate 204 connected to the surface 104 of the integrated device die 102c. For example, device 206 is bonded to the surface 104 of the integrated device die 102b (for example, by solder balls as shown). An additional integrated device die 102a is bonded to the back surface 106 of the integrated device die 102b mounted on device 206. A third integrated device die 102c is bonded to device 206 on its back surface 106 and attached to the interposer 202 on the surface 104 of the integrated device die 102c.

[0041] Figures 3A to 3D are schematic side cross-sectional views of semiconductor devices 300 having highly doped or highly doped semiconductor materials according to various embodiments. Figure 3A shows a semiconductor power supply device 300 with a layer of highly doped semiconductor material 304 (e.g., semiconductor material 304). As described herein, the highly doped semiconductor material 304 (e.g., semiconductor material layers 304a to 304c) can be configured to wire potential input sections 302 (e.g., input power 302a and 302b and / or input ground 302c) to an integrated device die (not shown in Figure 3A). In some embodiments, the highly doped semiconductor material 304 may include a conductive doped material that functions as a conductor. In some embodiments, the highly doped semiconductor material may include a degenerate semiconductor material (e.g., degenerate silicon). In some embodiments, the highly doped semiconductor material 304 may include a semiconductor material having a dopant level of at least one dopant atom per 10,000 semiconductor material atoms (e.g., silicon density 10 22 atoms / cm 3 In this case, the dopant density is at least 10 18 atoms / cm 3(it can be). In some embodiments, the dopant level is at least 1 dopant atom per 10,000 semiconductor material atoms and less than 1000 dopant atoms per 10,000 semiconductor material atoms. In some embodiments, the dopant concentration is at least 1 dopant atom per 10,000 semiconductor material atoms and less than 100 dopant atoms per 10,000 semiconductor material atoms. For example, intrinsic crystalline Si having an impurity doping concentration of 10 18 atoms / cm 3 or higher (having about 5×l0 22 atoms / cm 3 ) may be regarded as conductive Si, and the higher the doping concentration, the better the conductivity. In some examples, the highly doped semiconductor material 304 can have a dopant concentration of at least 10 18 atoms / cm 3 and less than 10 22 atoms / cm 3 . In some embodiments, the semiconductor material 304 can be doped with an impurity such as boron to fabricate a p-type semiconductor, doped with an impurity such as phosphorus to fabricate an n-type semiconductor, or doped with other suitable elements and compounds to enhance conductivity. In some embodiments, a semiconductor material such as undoped silicon (e.g., single crystal Si or poly Si) having high resistance and low conductivity can be converted into a highly doped semiconductor material having low resistance and high conductivity. When the semiconductor material 304 is doped, the conductivity of the semiconductor material 304 is improved, and the semiconductor material 304 can function as an electrical bus to provide power and / or ground to the attached device die.

[0042] In some embodiments, the semiconductor material 304 can be doped to make it conductive so that it can support providing potential to the electronic device. For example, in some embodiments, the semiconductor material 304 may be doped so that it can maintain a potential such as power or ground. In some embodiments, one or more passive devices (e.g., capacitors, inductors, resistors, etc.) can be formed within the device 300. The passive devices can be integrated into the power supply device 300 to further regulate the power supplied to the device die.

[0043] In some embodiments, the semiconductor device 300 may be fabricated using direct bonding without the use of an intervening adhesive. In some embodiments, the semiconductor material 304 may be part of a layer comprising the semiconductor material 304 and one or more insulating bonding layers 306. The insulating bonding layers 306 may be deposited on the front and back surfaces of the semiconductor material layers 304a to 304c. In some embodiments, the insulating bonding layer 306a may be deposited on the upper surface 314 and the lower surface 316 of the semiconductor material 304a. The insulating bonding layer 306 electrically isolates the semiconductor material 304a from the rest of the semiconductor device 300.

[0044] In some embodiments, the semiconductor device 300 may include a plurality of highly doped semiconductor materials 304. In some embodiments, the highly doped semiconductor material 304 is any conductive material in which the CTE of the highly doped semiconductor material is in the range of 50% to 200%, 50% to 150%, 25% to 150%, or 50% to 100% of the CTE of the device portion of the integrated device die (such as die 102, not shown in Figure 3A). In some embodiments, the CTE of the highly doped semiconductor material can be about half to twice the CTE of the device portion of the integrated device die. For example, in the case of silicon with a CTE of 3 ppm / °C, the range of the CTE of the highly doped semiconductor material may be 1.5 ppm / °C to 6 ppm / °C, or 2.5 ppm / °C to 3 ppm / °C. Semiconductor material 304a may be a first doped material, semiconductor material 304b may be a second doped material, and semiconductor material 304c may be a third doped material. The highly doped material of the semiconductor material layers 304a, 304b, and 304c can, in some embodiments, be the same material (having the same or different amounts of dopant) or different materials separated into separate layers. The semiconductor materials 304a to 304c can include any suitable type of semiconductor material, such as silicon, germanium, silicon-germanium, or any other suitable semiconductor. In some embodiments, the semiconductor materials 304a, 304b, and 304c can be doped to be conductive. The semiconductor materials 304a and 304b can each have an insulating junction layer 306a deposited on the upper surface 314 and an insulating junction layer 306b deposited on the lower surface 316, with the insulating layer 306b deposited on the lower surface 316 of the first semiconductor material 304a directly bonding to the insulating junction layer 306a on the upper surface 314 of the second semiconductor material 304b. Similarly, the insulating junction layer 306b deposited on the lower surface 316 of the second semiconductor material 304b directly bonds with the insulating junction layer 306a on the upper surface 314 of the third semiconductor material 304c. The semiconductor device 300 may be formed by the damascene method, the non-damascene method, or a combination of both.

[0045] The semiconductor device 300 can be electrically connected to an integrated device die (not shown) via conductive contact features 308a-308f, at least partially embedded in the insulating junction layer 306b. The conductive contact features 308a-308f may comprise individual conductive contact pads or exposed ends of conductive vias (e.g., metal vias 324). The contact features 308a-308f may include metals such as copper. For example, a third semiconductor layer 304c can be electrically connected to a second electrical component (such as an integrated device die) using conductive contact features 308a embedded in the insulating layer 306b deposited on the lower surface 316 of the third semiconductor material 304c. A first semiconductor layer 304a can be electrically connected to a lower second component (such as a lower integrated device die 102) using exposed conductive vias (e.g., metal vias 324b) and conductive contact features 308c, which are embedded in the insulating layer 306b deposited on the lower surface 316 of the third semiconductor material 304c. The second semiconductor layer 304b can be electrically connected to a second component (such as an integrated device die) below it using metal vias 324a and conductive contact features 308b embedded in an insulating layer 306b deposited on the lower surface 316 of the third semiconductor material 304c. The conductive contact features 308 are exposed on the underside of the semiconductor device 300, and together with the bonding layer 306, they form a hybrid bonding surface 318 that bonds to an electronic device such as an integrated device die 102.

[0046] The semiconductor device 300 further includes electrical paths such as a potential input section 302, a metallic conductive contact feature 308, highly doped semiconductor vias 310 (e.g., semiconductor vias 310a, 310b), and / or conductive metal vias 324 (e.g., metal vias 324a-324d). The input section 302 can be used to provide potential (e.g., power and / or ground) to the highly doped semiconductor material 304. Conductive contact features 308g-308i may be connected to the input sections 302a-c and arranged to connect to the corresponding highly doped semiconductor material 304. For example, the highly doped semiconductor material 304b can be connected to ground via the input section 302c, conductive contact feature 308i and via 324d, and also to ground to a die (not shown) below using, for example, metal via 324a and metallic conductive contact feature 308b. In some embodiments, the highly doped semiconductor material layer 304b can be connected to the die via highly doped semiconductor vias 310a and conductive contact features 308e. To prevent the highly doped semiconductor materials 304a and 304c from electrically short-circuiting to vias 324a and 324d, conductive contact features 308b, 308e, and 308i, and / or doped semiconductor material via 310a, vias 324a and 324d can be insulated by a ring 320 of insulating material, which may be different from or the same as the material used in the insulating junction layer 306. In various embodiments, the insulating ring 320 may include an inorganic dielectric such as silicon oxide or silicon nitride. In other embodiments, the insulating ring may include an organic material.

[0047] The ring 320 may extend through the highly doped semiconductor layers 304a, 304b, and 304c to ensure that vias 324 or 310 are electrically connected to one layer but not to the other. For example, a doped semiconductor material via 310b can be insulated by the ring 320 to prevent electrical connection with layers 304b and 304c. A metal via 324b can be electrically connected to the highly doped semiconductor material 304a and can supply power via the conductive feature 308c without distributing power to other layers. In some embodiments, a first conductive contact feature 308g supplies either power or ground (e.g., a first power level) to the first highly doped semiconductor material 304a of the first layer from a bonding wire connected to the input 302a. In some embodiments, a conductive barrier layer (not shown) may be placed between the highly doped semiconductor material and the metal conductor. For example, a conductive barrier may later be placed between the highly doped semiconductor material 304b and the metal conductor 324a.

[0048] Similar to the conductive contact features 308a-308c and vias 324a-324b, 310a-310b for power supply, the input section 302 can supply power to a specific highly doped semiconductor material 306, but other highly doped semiconductor materials 306 do not receive power or ground input from its input section. For example, the input section 302b, isolated by the ring 320, can supply power or ground through highly doped semiconductor layers 304a and 304b and supply input power to the highly doped semiconductor layer 304c without short-circuiting the highly doped semiconductor layers 304a and 304b.

[0049] In some embodiments, some or all of the conductive contact features may be made of doped semiconductor material. The highly doped semiconductor material via 310 in Figure 3A may include conductive vias to provide an electrical path connecting the highly doped semiconductor material 304 to the conductive contact features 308d-308f in order to supply power and / or ground between the input 302 and the integrated device die (die 102, etc.). The highly doped semiconductor material via 310 and the metal via 324 may be insulated by a dielectric ring 320 to prevent short circuits. For example, the doped semiconductor material via 310b extends through the highly doped semiconductor material 304b and 304c and is electrically connected to the highly doped semiconductor material 304a. Furthermore, the doped semiconductor material via 310a extends through the highly doped semiconductor material 304c and is electrically connected to the highly doped semiconductor material 304b. The doped semiconductor material vias 310a and 310b are hybrid-junctioned to the highly doped semiconductor materials 304b and 304a via contacts 308j and 308k, respectively, forming an electrical connection for transmitting potential to the highly doped semiconductor materials 304b and 304a via the doped semiconductor material vias 310a and 310b.

[0050] In some embodiments, one or more of the metal vias 324 and doped semiconductor vias 310 may be formed within the semiconductor device 300 in a via-last or via-middle process after layers 304a-304c are directly bonded. For example, after an insulating bonding layer 306 is deposited on individual highly doped semiconductor materials 304 and bonded using techniques such as direct bonding, trenches for the metal vias 324, highly doped semiconductor vias 310, and insulating rings 320 can be formed within the layers (etched or drilled). In some embodiments, the rings 320 can be deposited on the inner surface of the trenches, and then conductive contact features can be electroplated or deposited within the rings 320. In the embodiment of Figure 3A, layers 304a-304c can be directly bonded using interdielectric bonding techniques (such as only insulating layers 306a and 306b being directly bonded). In some embodiments, only insulating bonding layers 306a and 306b can be directly bonded, as vias and pads (such as conductive contact features) can be formed after direct bonding. In other embodiments, as described herein, vias and conductive contact features can be formed within each layer 304a-304c before bonding, and the layers can be hybrid bonded after the conductive contact features have been formed.

[0051] A semiconductor device 300 having a layer of conductively doped semiconductor material 304 can offer the advantage of applying power via vias 324, 310 without the drawbacks of a metal plane. For example, the CTE of the semiconductor device 300 can be brought close to the CTE of a connected electronic device, such as an integrated device die 102. As heat generation increases due to power use, both the semiconductor device 300 and the electronic device expand, thus reducing mechanical strain on the components and connection points.

[0052] Figure 3B shows a semiconductor device 300 comprising a highly doped semiconductor material layer 304 and an insulating bonding material 306 bonded using direct hybrid bonding technology. Unless otherwise specified, the components in Figure 3B may be the same as, or substantially the same as, the similarly numbered components in Figure 3A. Potential can be provided to and from the highly doped semiconductor material 304 via conductive contact features 308 and vias 324, 310. Parts of the vias 324 may be provided separately in each layer 304a-304c before bonding, such that each section extends through the corresponding highly doped semiconductor material layer 304. The semiconductor material layers 304a-304c may be directly hybrid bonded such that the insulating bonding layers 306a, 306b are directly bonded, and the opposing conductive contact features (whether exposed ends of vias 324 or individual pads) are also directly bonded. The conductive contact feature can be connected to an external device such as a lower integrated device die (e.g., lower die 102, not shown), and / or an upper component such as an upper integrated device die or power supply device.

[0053] In various embodiments, for example, a conductive contact feature 308c1 may have an exposed end of a first via section 324b1 extending through a highly doped semiconductor material 304c. The upper exposed portion of the first via section 324b1 can be directly bonded to a second via section 324b2 for electrical connection. The second via section 324b2 extends through the highly doped semiconductor material 304b and can be electrically connected to a conductive contact feature 308c2 that is electrically connected to the highly doped semiconductor material 304a. The first via section 324b1 may extend through two insulating junction layers 306a, 306b deposited in the highly doped semiconductor material 304c, and the via section 324b2 may extend through two insulating junction layers 306a, 306b deposited in the highly doped semiconductor material 304b. As described herein, a hybrid bond can be formed between the conductive contact feature and the opposing junction layer 306 to provide electrical connection.

[0054] In some embodiments, conductive contact features 308 and vias 324 may be formed within the semiconductor device 300 during the formation of layers 304a-304c and before layers 304a-304c are joined using direct bonding techniques. For example, during the formation of layers 304a-304c, which include an insulating bonding layer 306 and a highly doped semiconductor material 304, the conductive contact features 308, vias 324, and insulating rings 320 can be at least partially embedded in the highly doped semiconductor material 304. The insulating layer 306 can be deposited on the surface of the semiconductor material 304, after which the conductive contact features 308, vias 324, and rings 320 are deposited in etched trenches. In some embodiments, conductive contact features 302, 308, and 310 are exposed to allow electrical connections between layers 304a-304c.

[0055] Figure 3C shows a semiconductor device 300 in which each highly doped semiconductor material 304 is sealed by first and second insulating junction layers 306 and dielectric spacers 322 made of insulating material. The dielectric spacers 322 can function to laterally isolate the highly doped semiconductor material 304 from laterally adjacent layers (not shown). In some embodiments, as in Figure 3D, the first highly doped semiconductor material 304a includes a dielectric spacer 322. The dielectric spacer 322 isolates the first highly doped semiconductor material 304a into highly doped semiconductor islands, such as doped semiconductor islands. The dielectric spacer 322 allows each island to be connected to a different power or ground. For example, as shown in Figure 3D, the first highly doped semiconductor island 304a can be connected to a first power supply at a first voltage, the second highly doped semiconductor island 304d can be connected to a second power supply at a second voltage, the third highly doped semiconductor island 304e can be connected to a third power supply at a third voltage, and the fourth highly doped semiconductor island 304f can be connected to ground. In various embodiments, the second highly doped semiconductor island 304d can connect the underlying die 102 (not shown) to a second power level via a metal via 324b. The third highly doped semiconductor island 304e can connect the die to a third power level via a metal via 324f. Additional vias (not shown) can be connected to semiconductor islands 304a and 304f. In some embodiments, the highly doped semiconductor islands 304a, 304d, 304e, and 304f are configured to be connected to different potentials. Therefore, the various embodiments disclosed herein allow for wiring at different potentials within the semiconductor layer 304. Although a metal via 324 is shown in Figure 3D, it should be understood that in another embodiment, the conductive via may comprise a conductive semiconductor via, which may be similar to the via 310 described herein.

[0056] Figure 4 is a schematic side cross-sectional view of a semiconductor device 300 having a highly doped semiconductor material 304 mounted (e.g., directly hybrid-bonded) on the back surface 406 of an integrated device die 402. The semiconductor device 300 includes one or more highly doped semiconductor material layers 304 (e.g., semiconductor materials 304a to 304c), as described above. One or more highly doped semiconductor materials 304 may include insulating junction layers 306 deposited on the upper surface 314 and the lower surface 316 opposite the upper surface 314. In some embodiments, a dielectric spacer 322 extends from the insulating junction layer 306 deposited on the upper surface 314 to the insulating junction layer 306 deposited on the lower surface 316. The dielectric spacer 322 can function as an insulating end cap to complete an enclosure that completely seals the highly doped semiconductor material 304 within the insulating material. Electrical paths such as vias 324a-324e extend through the selected layer 304 and provide potential to each layer. Vias 324c and 324d receive potential from inputs 302b and 302c at conductive contact features 308h and 308i at the exposed ends of vias 324c and 324d, respectively. In some embodiments, vias are not used. For example, input 302a provides first power to semiconductor material 304a via conductive contact feature 308g without using vias. Additional vias 324a-324b and 324e-324f extend through the illustrated layer 304 and, as described above, provide power from the highly doped semiconductor layer 304 to the integrated device die 402.

[0057] In some embodiments, the integrated device die 402 is connected to the semiconductor device 300 on the back surface 406 of the integrated device die 402. In Figure 4, the semiconductor device 300 and the integrated device die 402 are connected via a hybrid bond without the use of an intervening adhesive. For example, the conductive features 404 (i.e., die conductive features) of the integrated device die 402 within the insulating bonding layer 306a (i.e., die insulating layer) of the die 402 can be directly bonded to the corresponding conductive contact features 308a-308f (e.g., contact pads or vias) of the power supply device 300.

[0058] In some embodiments, the integrated device die 402 includes a front surface 408 and a back surface 406. The front surface 408 is the active side containing one or more transistors, which are deposited closer to the front surface 408 than to the back surface 406.

[0059] In some embodiments, the integrated device die 402 can receive power or ground input. For example, a first highly doped semiconductor layer 304a can receive a first potential (e.g., first power) from input 302a. A second highly doped semiconductor layer 304b can be connected to a second potential (e.g., ground) by input 302c. A third highly doped semiconductor layer 304c can receive a third potential (e.g., second power) from input 302b. The integrated device die 402 can connect to the first power of the first highly doped semiconductor material 304a via vias 324b, 324f and corresponding conductive contact features 308c and 308f. In the illustrated embodiment, the illustrated via 624 may comprise a metal via. Furthermore, or alternatively, some or all of the vias may be doped semiconductor vias.

[0060] The integrated device die 402 can be connected to ground from the second highly doped semiconductor material 304b via vias 324a and 324e and corresponding conductive contact features 308b and 308e. The integrated device die 402 can be connected to a second power source from the third highly doped semiconductor material 304c via conductive contact features 308a and 308d. Beneficially, the embodiment in Figure 4 allows for the supply of power to the back surface 406 of die 402 opposite to the active front surface, thereby enabling an increase in signal connections on the front surface 408.

[0061] Figure 5 is a schematic side cross-sectional view of a semiconductor device 300 having a highly doped semiconductor material 304 connected to the surface 408 of an integrated device die 402. The semiconductor device 300 includes one or more highly doped semiconductor materials 304 bonded using insulating bonding layers 306 deposited on the upper surface 314 and lower surface 316 of each highly doped semiconductor material 304. Conductive contact features 308 (i.e., device conductive features) electrically connect the highly doped semiconductor material 304 to the integrated device die 402 with or without the use of vias 324. Conductive contact features 308 (e.g., individual contact pads or exposed ends of vias) can be directly bonded to conductive features 504 embedded in the insulating bonding layer 306 deposited on the integrated device die 402. The corresponding insulating bonding layer 306 on the die 402 and the device 300 can be directly bonded without the use of an intervening adhesive. In some embodiments, the insulating junction layer 306 on the integrated device die 402 can be deposited on the surface 408, which is closer to the transistors of the integrated device die 402, rather than on the back surface 406.

[0062] Figure 6 is a schematic side cross-sectional view of a semiconductor device 600 comprising a highly doped semiconductor material 304 connected to a substrate 610 and a plurality of integrated device dies 402. The semiconductor device 600 receives power from the top surface 602 of the semiconductor device 600 via an input section 302. In some embodiments, the semiconductor device 600 is connected to a potential via the input section 302, thereby enabling it to supply power to a stack of integrated device dies 402 stacked on the top surface 602 and to one or more dies below on which the bottom surface 604 of the device 600 is mounted. A plurality of integrated devices 402 may be stacked on the highly doped semiconductor device 600. In some embodiments, the integrated device dies 402 may be attached to conductive contact features 308 of the semiconductor device 600 using a hybrid junction by the front surface 408 or back surface 406 of the integrated device die 402.

[0063] For example, the semiconductor device 600 can be bonded to the back surface 406 of the integrated device die 402c mounted on the substrate 610. The semiconductor device 600 receives a potential from the input section 302 as described above and provides a potential to the integrated device dies 402b and / or 402c. The semiconductor device 600 can be attached to additional integrated device dies 402b and 402a that can be bonded to the semiconductor device 600 using a semiconductor material 304 having a low CTE, in order to reduce physical strain due to CTE mismatch. Thus, as described above, the die 402c can be mounted on the substrate 610 (e.g., directly bonded), and the power supply device 600 can be mounted on the die 402c (e.g., directly bonded). The die 402c may be equipped with a TSV to provide telecommunications between the device 600 and the substrate 610. Die 402b can be mounted on the power supply device 600 (for example, by direct bonding), and die 402a can be mounted on die 402b (for example, by direct bonding). A TSV can be provided via die 402b to connect die 402a to the power supply device 600.

[0064] In some embodiments, the semiconductor device 600 includes one or more thermal vias 608. The thermal vias 608 of the semiconductor device 600 can provide a heat dissipation path between an integrated device die 402b connected to one side of the semiconductor device 600 and an integrated device die 402c connected to the opposite side of the semiconductor device 600. The thermal vias 608 can further improve heat dissipation to prevent thermally induced strain within the dies 402a-402b or within the device 600.

[0065] A thermal via 608 extends through the semiconductor device 600 and can connect two integrated device dies 402b and 402c. This thermal via 608 connection provides a path for dissipating heat from the integrated device die 402b to die 402c. As heat is dissipated through the thermal via 608, the integrated device die 402 can return to a lower temperature, thereby reducing mechanical strain on the semiconductor device 600 and dies 402a-402c. Furthermore, although not shown, additional thermal vias can be provided through the lower die 402c to dissipate heat to the substrate 610 via die 402c. The semiconductor device 600 can be fabricated or configured using any of the configurations listed above.

[0066] In some embodiments, the semiconductor device 600 and the integrated device die 402 may be stacked on a substrate 610. The substrate 610 can be used to connect the integrated device die 402 to an external device such as a system board. For example, the substrate 610 may be connected to an external device that can provide additional power or ground (and signals) and send power and ground (and signals) to the integrated device die 402c.

[0067] Figure 7 is a schematic side cross-sectional view of a semiconductor power supply device 700 comprising a plurality of integrated device dies 402 and a highly doped semiconductor material 304 connected to a substrate 712. The substrate 712 provides power and ground from the semiconductor device 700 to the semiconductor device via a connector block 702. The semiconductor device 700 can be configured using any of the embodiments described above. The connector block 702 may further include an input conductor 710 extending through the conductor block 702 for connection to the substrate 712. The connector block 702 may include an insulating material 708 with an embedded input conductor 710 connecting the substrate 712 to the highly doped semiconductor layer 304 via contact features 308 and vias 714 (which may include metal vias or highly doped semiconductor vias). Thus, in Figure 7, the substrate 712 supplies power and / or ground to the input conductor 710 of the connector block 702, and as a result, the connector block 702 can supply power and / or ground to the semiconductor power supply device 700.

[0068] In some embodiments, the semiconductor device 700 may receive input from an input device and an interposer. In some embodiments, the interposer may simultaneously supply power to the semiconductor device 700 and at least one integrated device die 402.

[0069] Figure 8A is a schematic side cross-sectional view of a semiconductor device 800 comprising a highly doped semiconductor material 304, which has cooling channels 804a to 804d and is temperature-controlled by a cooling device mounted on an integrated device die 402 (e.g., directly hybrid-bonded). The semiconductor device 300 comprises one or more highly doped semiconductor material layers 304 (e.g., semiconductor materials 304a to 304c), as described above. One or more highly doped semiconductor materials 304 can be cooled by cooling channels 804 extending through one or more highly doped semiconductor materials 304. For example, as shown in Figure 8A, the cooling channels 804 can be cavities within the highly doped semiconductor material 304. The cavities can be formed by any suitable method, such as etching or drilling. Coolant can be supplied to the cooling channels 804 at a cooling inlet 802a (e.g., fluid inlet). From there, the coolant can flow through the cooling channels 804 and out at a cooling outlet 802b (e.g., fluid outlet). As the coolant passes through the cooling channel 804, it can lower the temperature of the highly doped semiconductor layer 304 through which it extends, and / or the temperature of the underlying die 402, by thermal conduction. The coolant may include a liquid, such as a non-conductive dielectric fluid. As shown in the figure, the coolant can come into contact with the junction layer 306a located on the die 402.

[0070] In some embodiments, as shown in Figure 4, the highly doped semiconductor layer 304 is connected to a potential via vias 324 and 310.

[0071] Electrical paths such as vias 324a to 324b extend through the selected layer 304, as described above, and provide potential to each layer. Via 324b receives potential from input 302c at the conductive contact feature 308f at the exposed end of via 324b. In some embodiments, vias are not used. For example, input 302a provides a first potential or power to the semiconductor material 304a via the conductive contact feature 308e through a contact pad via junction layer 306b, 306a. Additional vias 324a and 310a and 310b (which can be metal vias or highly doped semiconductor vias) extend through the illustrated layer 304 and, as described above, provide power from the highly doped semiconductor layer 304 to the integrated device die 402. In some embodiments, the fluid flowing through the cooling channel 804 may include a non-conductive fluid or a dielectric fluid.

[0072] In some embodiments, the cooling channel 804 may extend through the insulating junction layer 306b of the highly doped semiconductor layer 304b. In this embodiment and other embodiments, the cavity of the cooling channel 804 may be sealed within a barrier that isolates the coolant from the highly doped semiconductor layer 304 and other features of the semiconductor device 300. For example, a barrier around the cavity of the cooling channel 804d can seal the coolant and prevent the coolant flowing through the cooling channel 804d from coming into contact with the via 324d, potentially causing a short circuit in the electrical connection with the highly doped semiconductor layer 304b.

[0073] In some embodiments, the integrated device die 402 is connected to the semiconductor device 300 on the back surface 406 of the integrated device die 402. In Figure 8A, the semiconductor device 300 and the integrated device die 402 are connected directly via a hybrid bond without the use of adhesive. In such embodiments, the integrated device die 402 can be isolated from the cooling channel by an insulating bonding layer 306a. In some embodiments, the integrating bonding layer 306a can be made of a material that allows thermal conduction cooling of the integrated device die 402 from the cooling channel 804b. In some embodiments, the integrating bonding layer 306 allows the cooling channel 804 to regulate the temperature of the integrated device die 402 and lower the temperature of the integrated device die 402.

[0074] Figure 8B is a schematic top view of a semiconductor device 300 comprising a highly doped semiconductor material whose temperature is controlled by a cooling channel 804 extending through a single highly doped semiconductor layer 304 (such as the highly doped semiconductor layer 304b in Figure 8A). Coolant can enter from an external cooling source into the cooling inlet 802a of the cooling inlet channel 806a. The cooling channel 804 extends non-parallel to (e.g., perpendicular to) the cooling inlet channel 806a and connects the cooling inlet channel 806a to the cooling outlet channel 806b. Coolant can exit the semiconductor device 300 through the cooling outlet 802b of the cooling outlet channel 806b. As described above, the cooling channels 804 and 806 can be sealed by barriers to prevent the coolant from affecting the electrical function of the highly doped semiconductor layer 304b. In various embodiments, one or more pumps can be used to pump cooling fluid through the cooling channels in continuous flow or semi-continuous flow mode during system operation to cool the semiconductor device and / or die 402.

[0075] Examples of direct joining methods and directly joined structures Various embodiments disclosed herein relate to direct bonding structures that can directly bond two or more elements without the use of intervening adhesives. Such processes and structures are referred to herein as “direct bonding” processes or “direct bonding” structures. Direct bonding may include bonding one material on one element to one material on another element (also referred to herein as “uniform” direct bonding), in which the materials on the different elements do not need to be the same, and no conventional adhesives are used. Direct bonding may also include bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0076] In some embodiments (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. An example of a uniform direct bonding process is the ZIBOND® technology, commercially available from Adeia, Inc. in San Jose, California. The materials of opposing bonding layers on different elements may be the same or different, and may include elemental or compound materials. For example, in some embodiments, the non-conductive bonding layer can be blanket-deposited onto the base substrate without patterning with conductive features (e.g., without pads). In other embodiments, the bonding layers may be patterned on one or both elements, and may be the same or different from each other, but one material from each element is directly bonded to the face of the element (or the face of the smaller element if the elements are of different sizes) without the use of adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may contain one or more conductive features, but these conductive features do not participate in the bonding. For example, in some embodiments, opposing nonconductive bonding layers can be uniformly and directly bonded to each other, and then, after bonding, through-substrate vias (TSVs) can be formed through one element to provide electrical communication to the other element.

[0077] In various embodiments, the bonding layers 108a and / or 108b may include nonconductive materials such as dielectric materials, or undoped semiconductor materials such as undoped silicon, which may include native oxides. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, and may also include carbon such as silicon carbide, silicon oxycarbonitride, low dielectric materials, silicon carbonitride, or materials containing diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic despite containing carbon. In some embodiments, the dielectric material at the bonding surface does not include polymer materials such as epoxy (e.g., epoxy adhesives, cured epoxy, or epoxy composite materials such as FR-4 materials), resins, or molding materials.

[0078] In other embodiments, the bonding layer may include, for example, a deposited conductive oxide material (e.g., indium tin oxide (ITO)) as described in U.S. Provisional Patent Application No. 63 / 524564 filed June 30, 2023 (the entire contents thereof are incorporated herein by reference to provide an example of a conductive bonding layer without short circuits due to contact across the interface).

[0079] In direct bonding, the first and second elements can be directly bonded without adhesive, which differs from deposition processes and results in a structurally different interface from those fabricated by deposition. In some applications, the width of the first element in the bonded structure is similar to the width of the second element. In other embodiments, the width of the first element in the bonded structure is different from the width of the second element. The width or area of ​​a larger element in the bonded structure may be at least 10% greater than the width or area of ​​a smaller element. Furthermore, the interface between directly bonded structures, unlike interfaces beneath deposited layers, may contain defect regions where nanometer-scale voids (nanovoids) exist. Nanovoids may be formed by activation of one or both of the bonding surfaces (e.g., exposure to plasma as described below).

[0080] The bonding interface between non-conductive bonding surfaces may contain higher concentrations of material from the activation process and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, the nitrogen concentration peak may be detected using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, nitrogen-terminated surfaces can be obtained by replacing the OH groups of hydrolyzed (OH-terminated) surfaces with NH2 molecules, for example, by nitrogen termination (e.g., exposing the bonding surfaces to a nitrogen-containing plasma). In embodiments utilizing oxygen plasma for activation, an oxygen concentration peak may be formed at the bonding interface between non-conductive bonding surfaces. In some embodiments, the bonding interface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding can include covalent bonds stronger than van der Waals bonds. The bonding layer may also include highly smooth, planar polished surfaces.

[0081] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are joined without an intervening adhesive. In non-direct bonding processes that utilize adhesives, an intervening material is typically applied to one or both elements to achieve a physical connection between them. For example, in some adhesive-based processes, a fluid adhesive (such as an organic adhesive like epoxy) that may contain conductive fillers can be applied to one or both elements and cured to form a physical (not chemical or conjugated) connection between the elements. Typical organic adhesives do not form strong chemical or covalent bonds with either element. In such processes, the connection between elements is weak and / or easily reversed by reheating or flux cleaning.

[0082] In contrast, direct bonding processes join two elements by forming a strong chemical bond (e.g., a covalent bond) between opposing nonconductive materials. For example, in direct bonding processes between nonconductive materials, one or both of the nonconductive surfaces of the two elements are planarized and chemically treated (e.g., activated and / or terminated) so that a chemical bond (e.g., a covalent bond) stronger than van der Waals bonds or hydrogen bonds is formed when the elements come into contact. In some embodiments (e.g., between opposing dielectric surfaces such as opposing silicon oxide surfaces), the chemical bond may spontaneously form at room temperature upon contact. In some embodiments, the chemical bond between the opposing nonconductive materials can be strengthened after annealing of the elements.

[0083] As described above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to other non-conductive features, and conductive features are directly bonded to the conductive features of the elements being bonded. While non-conductive bonding materials and interfaces can be as described above, conductive bonding can be formed, for example, as a direct connection between metals. In conventional metal bonding processes, a fusible metal alloy (such as solder) is placed between the conductors of two elements, heated to melt the alloy, and then cooled to form a connection between the two elements. The resulting bond often exhibits a sharp interface with the conductors of both elements and can revert upon reheating. In contrast, the direct metal bonding used in hybrid bonding does not require a molten metal alloy or an intermediate fusible metal alloy, and in many cases, interdiffusion of the bonded conductive features and grain growth at the bonding interface between elements are observed, resulting in a strong mechanical and electrical connection without the much higher temperatures and pressures of thermal compression bonding.

[0084] Figures 9A and 9B schematically show side cross-sectional views of the first and second elements 902 and 904 before and after the process of forming a direct bond structure, more specifically, a hybrid bond structure, according to several embodiments. In Figure 9B, the bond structure 900 comprises a first element 902 and a second element 904 that are directly bonded to each other at a bond interface 918 without the interposition of an adhesive. The conductive feature 906a of the first element 902 may be electrically connected to the corresponding conductive feature 906b of the second element 904. In the illustrated hybrid bond structure 900, the conductive feature 906a is directly bonded to the corresponding conductive feature 906b without the interposition of solder or conductive adhesive.

[0085] The conductive features 906a and 906b in the illustrated embodiment are embedded in the first bonding layer 908a of the first element 902 and the second bonding layer 908b of the second element 904, respectively, and can be considered as part of them. The field regions of the bonding layers 908a and 908b extend between the conductive features 906a and 906b and partially or completely surround the conductive features 906a and 906b. The bonding layers 908a and 908b may comprise a layer of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded without adhesive. The non-conductive bonding layers 908a and 908b may be placed on the individual surfaces 914a and 914b of the base substrate portions 910a and 910b.

[0086] The first and second elements 902, 904 may include microelectronic elements such as semiconductor elements including, for example, integrated device dies, wafers, passive devices, and discrete active devices (power switches, MEMS, etc.). In some embodiments, the base substrate portion may comprise device portions such as bulk semiconductor (e.g., silicon) portions of elements 902, 104 and back-end obline brine (BEOL) interconnect layers on such semiconductor portions. The junction layers 908a, 908b may be provided as part of the BEOL layer during device manufacturing, as part of a redistribution layer (RDL), or as specific junction layers added to an existing device with junction pads extending from underlying contacts. Active devices and / or circuits may be patterned and / or otherwise arranged within or on the base substrate portions 910a, 910b and may electrically communicate with at least some of the conductive features 906a, 906b. Active devices and / or circuits may be located on the front side 914a, 914b of the base substrate portions 910a, 910b or near thereto, and / or on the opposite rear side 916a, 916b of the base substrate portions 910a, 910b or near thereto. In other embodiments, the base substrate portions 910a, 910b may not include active circuits and may instead include dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, diffraction gratings, lenses), etc. Although the junction layers 908a, 908b are shown to be located on the front side of the elements, similar junction layers may be additionally or alternatively located on the rear side of the elements.

[0087] In some embodiments, the base substrate portions 910a and 910b may have significantly different coefficients of thermal expansion (CTE), and a junction element including such different base substrate portions may form a heterogeneous junction structure. The CTE difference between the base substrate portions 910a and 910b, and in particular between the bulk semiconductor (typically single crystal) portions of the base substrate portions 910a and 910b, may be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 910a and 910b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0088] In some embodiments, one of the base substrate portions 910a, 910b may include an optoelectronic single crystal material, including a perovskite material useful for photoelectric or pyroelectric applications, while the other base substrate portion 910a, 910b may include a more conventional substrate material. For example, one of the base substrate portions 910a, 910b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other base substrate portion 910a, 910b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 910a, 910b may include a III-V single semiconductor material such as gallium arsenide (GaAs) or gallium nitride (GaN), while the other base substrate portion 910a, 910b may include a non-III-V semiconductor material such as silicon (Si), or other materials having a similar CTE, such as quartz, fused silica glass, sapphire, or glass. In yet another embodiment, one of the base substrate portions 910a and 910b includes a semiconductor material, while the other base substrate portion 910a and 910b includes a packaging material such as a glass, organic, or ceramic substrate.

[0089] In some configurations, the first element 902 may comprise a fragmented element, such as a fragmented integrated device die. In another configuration, the first element 902 may comprise a carrier or substrate (e.g., a semiconductor wafer) containing multiple (e.g., tens, hundreds, or more) device regions that, when fragmented, form multiple integrated device dies, while in other embodiments, such a carrier may be a package substrate or a passive or active interposer. Similarly, the second element 904 may comprise a fragmented element, such as a fragmented integrated device die. In another configuration, the second element 904 may comprise a carrier or substrate (e.g., a semiconductor wafer). Thus, the embodiments disclosed herein can be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers can be directly bonded to each other (e.g., direct hybrid bonding) and fragmented using an appropriate fragmentation process. After framing, the side edges of the framing structures (e.g., the side edges of two bonded elements) can be substantially flush (substantially aligned x and y dimensions), and / or the edges of the bond interfaces of both the bonded elements and the framing elements may be symmetry and may include marks indicating a common framing process of the bonded structures (e.g., saw markings when a saw framing process is used).

[0090] Although only two elements 902 and 904 are shown, any appropriate number of elements can be stacked within the junction structure 900. For example, a third element (not shown) can be stacked on top of the second element 904, or a fourth element (not shown) can be stacked on top of the third element. In such embodiments, vertical electrical communication can be provided between vertically stacked elements (two and / or three or more) by forming through-substrate vias (TSVs). Furthermore, or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to one another along the first element 902. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the junction structure can be sealed with an insulating material such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitrocarbide, etc.). One or more insulating layers can be provided on the junction structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the junction structure, or the first insulating layer can be provided on top of a second insulating layer (which may contain the same material as the first insulating layer or a different material).

[0091] To achieve direct bonding between bonding layers 908a and 908b, bonding layers 908a and 908b can be prepared for direct bonding. The non-conductive bonding surfaces 912a and 912b on the top or outer surfaces of bonding layers 908a and 908b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 912a and 912b can be less than 30 Årms. For example, the roughness of the bonding surfaces 912a and 912b can be in the range of approximately 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. Polishing can also be adjusted so that the conductive features 906a and 906b remain recessed relative to the field area of ​​bonding layers 908a and 908b.

[0092] Preparation for direct bonding may include cleaning one or both of the bonding surfaces 912a, 912b and exposing them to plasma and / or etchant, and activating at least one of the surfaces 912a, 912b. One or both of the surfaces 912a, 912b may be terminated with a specific species after or during activation (e.g., during the plasma process and / or etching process). While not constrained by theory, in some embodiments the activation process may be performed to break chemical bonds at the bonding surfaces 912a, 912b, and the termination process may provide additional chemical species at the bonding surfaces 912a, 912b, thereby altering the chemical bonds and / or improving the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step (e.g., plasma for activating and terminating surfaces 912a, 912b). In other embodiments, one or both of the bonding surfaces 912a, 912b may be terminated in separate processes to provide additional species for direct bonding. In various embodiments, the termination species may include nitrogen. For example, in some embodiments, the bonding surfaces 912a and 912b can be exposed to a nitrogen-containing plasma. Other termination treatments can be suitable for improving the bonding energy, depending on the materials of the bonding surfaces 912a and 912b. Furthermore, in some embodiments, the bonding surfaces 912a and 912b can be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 918 between the first element 902 and the second element 904. Typically, the fluorine concentration peaks are located at the interface between material layers.Examples of additional activation and / or termination processing are found in U.S. Patent No. 9391143, specifically in columns 5, row 55 to 7, row 3; 8, row 52 to 9, row 45; 10, row 24 to 36; 11, rows 24 to 32, 42 to 47, 52 to 55, and 60 to 64; 12, rows 3 to 14, 31 to 33, and 55 to 67; and 14. The following is described in Ram lines 38-40 and 44-50; and in column 4 lines 41-50 of No. 10434749; in column 5 lines 7-22, 39, 55-61; in column 8 lines 25-31, 35-40, and 49-56; and in column 12 lines 46-61 (the teachings for the activation and termination processes are incorporated herein by reference).

[0093] Therefore, in the direct bond structure 900, the bond interface 918 between the two nonconductive materials (e.g., bond layers 908a, 908b) can have a very smooth interface with higher peaks of nitrogen (or other termination species) content and / or fluorine concentration at the bond interface 918. In some embodiments, the peaks of nitrogen and / or fluorine concentration can be detected using various types of inspection techniques, such as SIMS technology. The polished bond surfaces 912a and 912b may become slightly rougher after the activation process (e.g., about 1 Årms to 30 Årms, 3 Årms to 20 Årms, or possibly rougher). In some embodiments, the activation and / or termination treatment may make the surface slightly smoother before bonding, such as when the plasma treatment preferentially erodes the high points of the bond surface.

[0094] The non-conductive bonding layers 908a and 908b can be directly bonded to each other without adhesive. In some embodiments, elements 902 and 904 are bonded at room temperature without the need for voltage application or the application of external pressure or force exceeding the pressure used to initiate contact between the two elements 902 and 904. Contact alone can result in a direct bond (e.g., a dielectric bond by covalent bonding) between the non-conductive surfaces of the bonding layers 908a and 908b. Subsequent annealing of the bonding structure 900 allows the conductive features 906a and 906b to be directly bonded.

[0095] In some embodiments, prior to direct bonding, the conductive features 906a and 906b are recessed relative to the surrounding field region such that the total gap between opposing contacts after dielectric bonding and before annealing is less than 15 nm or less than 10 nm. Because the recess depth of the conductive features 906a and 906b may vary between elements due to process variations, the described gap may represent the maximum or average gap (before annealing) between the corresponding conductive features 906a and 906b of the two bonded elements. Annealing causes the conductive features 906a and 906b to expand and come into contact with each other, forming a metal-to-metal direct bond.

[0096] During annealing, the conductive features 906a, 906b (e.g., metallic material) expand, while the direct bonding between the non-conductive materials surrounding the bonding layers 908a, 908b resists separation of the elements. Therefore, thermal expansion may increase the internal contact pressure between the opposing conductive features. Annealing also induces the growth of metallic particles at the bonding interface, which may cause particles from one element to migrate at least partially to the other element at the bonding interface, and vice versa. Thus, in some embodiments of hybrid bonding, the opposing conductive materials are bonded without exceeding the melting temperature of the conductive material, allowing for bonding at lower annealing temperatures compared to soldering or thermal compression bonding.

[0097] In various embodiments, the conductive features 906a, 906b may comprise individual pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field regions of the bonding layers 908a, 908b. In some embodiments, the conductive features 906a, 906b may comprise exposed contact surfaces of the TSV (e.g., through-silicon vias).

[0098] As described above, in some embodiments, the elements 902 and 904 of Figure 9A before direct bonding may have portions of the individual conductive features 906a and 906b recessed below the nonconductive bonding surfaces 912a and 912b (for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or 4 nm to 10 nm). Due to process variations, both the dielectric thickness and the conductor recess depth may vary in the element. Therefore, the above recess depth ranges may apply to individual conductive features 906a and 906b, or to the average recess depth relative to a local nonconductive field region. Even in the case of individual conductive features 906a and 906b, the vertical recess may vary across the feature and can therefore be measured at or near the lateral center of the cavity in which a given conductive feature 906a or 906b is formed, or on the side of the cavity.

[0099] Beneficial for this purpose, the use of hybrid bonding technology (such as Direct Bond Interconnect, or DBI®, commercially available from Adeia, Inc. in San Jose, California) enables high-density connections between conductive features 906a and 906b (e.g., small pitch or fine pitch for typical arrays) at the direct bonding interface 918.

[0100] In some embodiments, the pitch p of conductive features 906a, 906b, such as conductive traces embedded in one bonding surface of a bonded element, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or less than 1 μm. In some applications, the ratio of the pitch of conductive features 906a and 906b to the pitch of the lateral dimension (e.g., diameter) of the bonding pad is less than 20, less than 10, less than 5, less than 3, and in some cases preferably less than 2. In various embodiments, the conductive features 906a and 906b and / or traces may include copper or copper alloys, but other metals such as nickel, aluminum or alloys thereof may be appropriate. Conductive features disclosed herein, for example, conductive features 906a and 906b, may include fine-grained metal (e.g., fine-grained copper). Furthermore, the main lateral dimensions (e.g., pad diameter) can also be reduced, for example, to a range of approximately 0.25 μm to 30 μm, approximately 0.25 μm to 5 μm, or approximately 0.5 μm to 5 μm.

[0101] In the case of hybrid junction elements 902, 904, as shown in the figure, the orientation of one or more conductive features 906a, 906b from opposing elements may be opposite to one another. As is known in the art, conductive features can generally be formed with substantially vertical sidewalls, particularly when directional reactive ion etching (RIE) defines the conductor sidewalls directly through etching of the conductive material or indirectly through etching of the surrounding insulator in a damascene process. However, some taper may exist in the conductor sidewalls, with the conductor becoming narrower away from the surface first exposed to etching. The taper may be more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet etching or dry etching. In the illustrated embodiment, at least one conductive feature 906b (and / or at least one internal conductive feature, e.g., a BEOL feature) in the junction layer 908b of the upper element 904 may be tapered or narrowed upward away from the junction surface 912b. In contrast, at least one conductive feature 906a (and / or at least one internal conductive feature, e.g., a BEOL feature) within the bonding layer 908a of the lower element 902 may be tapered or narrowed downward away from the bonding surface 912a. Similarly, any bonding layers (not shown) on the back surfaces 916a, 916b of elements 902, 904 may be tapered or narrowed away from the back surface in the opposite tapered direction to the front conductive features 906a, 906b of the same element.

[0102] As described above, during the annealing stage of the hybrid junction, the conductive features 906a and 906b can expand and come into contact with each other to form a direct metal-metal junction. In some embodiments, the materials of the conductive features 906a and 906b of the opposing elements 902 and 904 can interdiffuse during the annealing process. In some embodiments, metal particles grow across the junction interface 918. In some embodiments, the metal is or contains copper, and this copper may have particles oriented along the 111 crystal plane to improve the diffusion of copper at the junction interface 918. In some embodiments, the conductive features 906a and 906b may include a nanotwinned copper grain structure that helps fuse the conductive features during annealing. There is substantially no gap between the nonconductive junction layers 908a and 908b or near the bonded conductive features 906a and 906b. A barrier layer may be provided below and / or around the conductive features 906a and 906b (which may contain, for example, copper). However, in other embodiments, a barrier layer may not be present beneath the conductive features 906a and 906b.

[0103] Unless otherwise explicitly required by the context, throughout this specification and the claims, the terms “comprise,” “comprising,” “include,” and similar terms shall be interpreted in a comprehensive sense, as opposed to an exclusive or exhaustive sense, i.e., “including, but not limited to.” The word “coupled,” as commonly used herein, refers to two or more elements that may be directly connected or connected by one or more intermediate elements. Similarly, the word “connected,” as commonly used herein, refers to two or more elements that may be directly connected or connected by one or more intermediate elements. Furthermore, the words “herein,” “above,” “below,” and similar words, as used in this application, refer to the entire application and not to any particular part thereof. Furthermore, where used herein, if a first element is described as being positioned "on" or "on" a second element, the first element may be positioned directly on or on the second element such that the first element and the second element are in direct contact, or the first element may be positioned indirectly on or on the second element such that one or more elements are interposed between the first element and the second element. Where the context allows, words used singular or plural in the above "Detailed Description of the Invention" may also include plural or singular forms. The word "or" relating to a list of two or more items encompasses all interpretations of that word, namely any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0104] Furthermore, conditional expressions used herein, in particular "can, could," "might, may," "eg, for example," and "etc.," are generally intended to convey that a particular embodiment includes a particular feature, element, and / or state, while other embodiments do not, unless otherwise specified or understood in the context in which they are used. Thus, such conditional expressions are generally not intended to imply that a feature, element, and / or state is required in any way in one or more embodiments.

[0105] While specific embodiments have been described above, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. In fact, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of this disclosure. For example, while blocks are presented in a given arrangement, in alternative embodiments, similar functions may be performed with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any preferred combination of elements and operations of the various embodiments described above can be combined to provide other embodiments. The appended claims and their equivalents are intended to cover forms or improvements that fall within the scope and spirit of this disclosure.

Claims

1. It is a semiconductor device, A first layer comprising a first highly doped semiconductor material and a first insulating junction layer, A second layer comprising a second highly doped semiconductor material and a second insulating junction layer, A first via extending through the second layer and electrically connected to the first highly doped semiconductor material, A semiconductor device comprising the first layer and the second layer being directly bonded to each other without the intervening adhesive.

2. The semiconductor device according to claim 1, wherein the first via connects either power or ground to the first highly doped semiconductor material of the first layer.

3. The semiconductor device according to claim 1, wherein the first layer further comprises a first conductive feature, and the second layer further comprises a second conductive feature, wherein the first conductive feature and the second conductive feature are directly bonded to each other without an intervening adhesive.

4. The semiconductor device according to claim 3, wherein the second layer is hybrid-bonded to the first layer such that the second insulating bonding layer of the second layer is directly bonded to the first insulating bonding layer of the first layer, and the second conductive feature of the second layer is directly bonded to the first conductive feature of the first layer.

5. The semiconductor device according to claim 1, further comprising a third layer comprising a third high-concentration doped semiconductor material and a third insulating junction layer, wherein the second layer and the third layer are directly bonded to each other without an intervening adhesive.

6. The semiconductor device according to claim 1, further comprising an insulating ring around the first via of the first layer.

7. The semiconductor device according to claim 1, wherein a dielectric spacer is embedded in the first highly doped semiconductor material, and the dielectric spacer separates the first highly doped semiconductor material into a plurality of highly doped semiconductor islands.

8. The semiconductor device according to claim 7, wherein the first highly doped semiconductor island of the highly doped semiconductor island is connected to a first power supply with a first voltage, and the second highly doped semiconductor island of the highly doped semiconductor island is connected to ground.

9. The semiconductor device according to claim 7, wherein a plurality of the high-concentration doped semiconductor islands are configured to be connected to different potentials.

10. The semiconductor device according to claim 1, wherein the second highly doped semiconductor material is connected to electrical ground.

11. The semiconductor device according to claim 1, wherein the first highly doped semiconductor material includes an insulating end cap.

12. The first highly doped semiconductor material and the second highly doped semiconductor material each have at least 10 18 atoms / cm 3 and 10 22 atoms / cm 3 A semiconductor device according to claim 1, having a dopant concentration of less than 1.

13. Fluid inlet and An inlet channel connected to the fluid inlet, Fluid outlet and An outlet channel connected to the fluid outlet, One or more cooling channels extending at least through the first insulating bonding layer, wherein the one or more cooling channels are connected to the inlet channel and the outlet channel, The semiconductor device according to claim 1, further comprising:

14. The semiconductor device according to claim 13, wherein the fluid inlet, the inlet channel, and the one or more cooling channels are arranged so that a fluid can flow into the semiconductor device, thereby connecting the inlet channel and the one or more cooling channels integrally, and allowing the fluid to flow from the inlet channel to the one or more cooling channels.

15. The semiconductor device according to claim 13, wherein the fluid outlet, the outlet channel, and the one or more cooling channels are arranged so that fluid can flow from the semiconductor device, thereby connecting the one or more cooling channels and the outlet channel integrally, so that the fluid can flow from the one or more cooling channels to the outlet channel and exit the semiconductor device at the fluid outlet.

16. The semiconductor device according to claim 13, wherein the fluid inlet, the inlet channel, the fluid outlet, the outlet channel, and the one or more cooling channels include a cavity, and the cavity seals a cooling fluid.

17. The semiconductor device according to claim 16, wherein the cooling fluid is a dielectric fluid.

18. The semiconductor device according to claim 13, wherein the fluid inlet, the inlet channel, the fluid outlet, the outlet channel, and the one or more cooling channels include a cavity and a barrier surrounding the cavity, the barrier separating the cavity from the first insulating junction layer.

19. A bonding structure comprising a semiconductor device according to claim 1, wherein the bonding structure further comprises an integrated device die, the integrated device die comprises a front surface and a back surface, and the semiconductor device is directly bonded to the integrated device die.

20. A joint structure, A first integrated device die comprising a front surface and a back surface, wherein the first integrated device die includes a die insulating layer and die conductive features at least partially embedded in the die insulating layer, A semiconductor device having a first surface and a second surface facing the first surface, wherein the semiconductor device includes a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first highly doped semiconductor material electrically connected to the device conductive feature, wherein the first insulating layer is directly bonded to the die insulating layer without an intervening adhesive, and the die conductive feature is directly bonded to the device conductive feature without an intervening adhesive. A junction structure comprising, wherein the die conductive feature is connected to power or ground via at least the first highly doped semiconductor material.

21. The junction structure according to claim 20, wherein the surface of the first integrated device die is an active side including one or more transistors, and the one or more transistors are located closer to the surface than to the back surface.

22. The bonding structure according to claim 21, wherein the semiconductor device is directly bonded to the back surface of the first integrated device die without the use of an intervening adhesive.

23. The bonding structure according to claim 20, wherein the semiconductor device includes a second highly doped semiconductor material disposed on the first highly doped semiconductor material.

24. The bonding structure according to claim 23, wherein the first highly doped semiconductor material is connected to either a first power source or ground, the second highly doped semiconductor material is connected to either a second power source or ground, and the first highly doped semiconductor material and the second highly doped semiconductor material are electrically connected to the first integrated device die.

25. The bonding structure according to claim 23, further comprising vias extending through the first highly doped semiconductor material, wherein the vias electrically connect the die conductive feature to the second highly doped semiconductor material.

26. The bonding structure according to claim 20, further comprising a second integrated device die having a second insulating layer on its back surface, wherein the second integrated device die is directly bonded to the semiconductor device on the side opposite to the first integrated device die.

27. The bonding structure according to claim 23, wherein the first highly doped semiconductor material is a conductive material whose coefficient of thermal expansion (CTE) of the first highly doped semiconductor material is 50% to 150% of the CTE of the device portion of the first integrated device die.

28. Fluid inlet and An inlet channel connected to the fluid inlet, Fluid outlet and An outlet channel connected to the fluid outlet, One or more cooling channels extending at least through the first insulating layer, wherein the one or more cooling channels are connected to the inlet channel and the outlet channel, The joining structure according to claim 20, further comprising:

29. The semiconductor device according to claim 28, wherein the fluid inlet, the inlet channel, and the one or more cooling channels are arranged so that a fluid can flow into the semiconductor device, thereby connecting the inlet channel and the one or more cooling channels integrally, and allowing the fluid to flow from the inlet channel to the one or more cooling channels.

30. The semiconductor device according to claim 28, wherein the fluid outlet, the outlet channel, and the one or more cooling channels are arranged so that fluid can flow from the semiconductor device, thereby connecting the one or more cooling channels and the outlet channel integrally, so that the fluid can flow from the one or more cooling channels to the outlet channel and exit the semiconductor device at the fluid outlet.

31. The semiconductor device according to claim 28, wherein the fluid inlet, the inlet channel, the fluid outlet, the outlet channel, and the one or more cooling channels include a cavity, and the cavity seals a cooling fluid.

32. The semiconductor device according to claim 31, wherein the cooling fluid is a dielectric fluid.

33. The semiconductor device according to claim 28, wherein the fluid inlet, the inlet channel, the fluid outlet, the outlet channel, and the one or more cooling channels include a cavity and a barrier surrounding the cavity, the barrier separating the cavity from the first insulating layer.

34. It is a method, Depositing a first insulating junction layer on a highly doped semiconductor material, The conductive feature is embedded at least partially in the first insulating bonding layer, To prepare the first insulating bonding layer for hybrid bonding with electronic components, A method comprising the high-concentration doped semiconductor material having a coefficient of thermal expansion (CTE) of 50% to 150% of the CTE of the device portion of the electronic component.

35. The method according to claim 34, further comprising: directly bonding the second insulating bonding layer of the electronic component to the first insulating bonding layer; and directly bonding the second conductive feature of the electronic component to a first conductive feature at least partially embedded in the first insulating bonding layer.

36. The method according to claim 34, wherein the high-concentration doped semiconductor material includes a high-concentration doped semiconductor material.

37. A highly doped semiconductor material having a first insulating junction layer on a first surface and a first conductive feature at least partially embedded in the first insulating junction layer, An electronic component having a second insulating bonding layer and a second conductive feature at least partially embedded in the second insulating bonding layer, wherein the first insulating bonding layer is directly bonded to the second insulating bonding layer without an intervening adhesive, and the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive. A bonding structure comprising the above, wherein the highly doped semiconductor material has a coefficient of thermal expansion (CTE) of 50% to 150% of the CTE of the device portion of the electronic component.

38. The bonding structure according to claim 37, wherein the high-concentration doped semiconductor material includes a high-concentration doped semiconductor material.

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