Read Ahead Based on Read Size and Queue Identifier

Abstract

Various embodiments provide a way to perform one or more data read-ahead operations on a memory system based on the read size and queue identifier of a read request. Specifically, in some embodiments, the memory system is configured to perform at least one read-ahead operation if each read request received from a host system in relation to a queue identifier has a read size equal to the maximum data transfer size (MDTS) of the memory system.

Description

Technical Field

[0001] Priority Application This application claims the benefit of priority of U.S. Provisional Application No. 63 / 526,514, filed Jul. 13, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure generally relate to memory devices, and more particularly to performing one or more data read-ahead operations on a memory system (e.g., a memory subsystem) based on a read size and a queue identifier of a read request.

Background Art

[0003] A memory subsystem can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data in and retrieve data from the memory devices.

[0004] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be construed as limiting the present disclosure to specific embodiments, but are for illustration and understanding only.

Brief Description of the Drawings

[0005] [Figure 1] FIG. is a block diagram illustrating an exemplary computing system including a memory subsystem according to some embodiments of the present disclosure. [Figure 2] FIG. is a block diagram illustrating an exemplary architecture of a host system and a memory subsystem according to some embodiments of the present disclosure. [Figure 3]This is a flowchart illustrating exemplary methods for performing one or more data read-ahead operations on a memory system, according to some embodiments of the present disclosure. [Figure 4A] This is a flowchart illustrating exemplary methods for performing one or more data read-ahead operations on a memory system, according to some embodiments of the present disclosure. [Figure 4B] This is a flowchart illustrating exemplary methods for performing one or more data read-ahead operations on a memory system, according to some embodiments of the present disclosure. [Figure 5] This is a block diagram of an exemplary computer system in which embodiments of the present disclosure may operate. [Modes for carrying out the invention]

[0006] Aspects of this disclosure relate to performing one or more data read-ahead operations on a memory system (e.g., a memory subsystem) based on the read size and the queue identifier of the read request. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with Figure 1. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system may send access requests to the memory subsystem, such as storing data in the memory subsystem and reading data from the memory subsystem.

[0007] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem, such as storing data in the memory subsystem's memory devices, reading data from the memory subsystem's memory devices, or writing / reading constructs (e.g., submission queues and completion queues) to / from memory devices on the memory subsystem. The data specified, read, or written by a host request (e.g., a data access request or a command request) is hereafter referred to herein as "host data". A host request may include logical address information for the host data (e.g., a logical block address (LBA), namespace), which is where the host system associates the host data. The logical address information (e.g., LBA, namespace) may be part of the host data's metadata. Metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity code), data version (e.g., used to distinguish the age of written data), valid bitmap (where the LBA or logical transfer unit contains valid data), etc.

[0008] The memory subsystem can initiate media management operations, such as write operations, on host data stored in the memory device. For example, the firmware of the memory subsystem can rewrite previously written host data from its current location to a new location on the memory device as part of garbage collection management operations. For example, data that is rewritten when initiated by the firmware is referred to herein as "garbage collection data."

[0009] Hereinafter, “user data” generally refers to host data and garbage collection data. Hereinafter, “system data” refers to data created and / or maintained by the memory subsystem in order to perform operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables, also known herein as L2P tables), data from logging, and scratchpad data.

[0010] A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. In some types of non-volatile memory devices (e.g., non-logical AND (NAND) devices), each plane consists of a set of physical blocks. In some memory devices, a block is the smallest area that can be erased. Each block consists of a set of pages. Each page consists of a set of memory cells that store bits of data. A memory device can be a raw memory device (e.g., NAND) that is managed externally, for example by an external controller. A memory device can be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0011] Certain memory devices, such as NAND memory devices, contain one or more blocks (e.g., multiple blocks), each of which contains multiple memory cells. For example, a memory device may contain multiple pages (also called word lines), each of which contains a subset of the memory cells of the memory device. Generally, writing data to such a memory device involves programming the memory device (by programmatic operation) at the page level of blocks, and erasing data from such a memory device involves erasing the memory device at the block level (e.g., page-level erasure of data is not possible).

[0012] A memory device can contain one or more cache blocks and one or more non-cache blocks. Data written to the memory device can be written first to one or more cache blocks to facilitate faster write performance. Data stored in the cache blocks can eventually be moved (e.g., copied) to one or more non-cache blocks at a later time (e.g., when the memory device is idle), thereby facilitating higher capacity storage on the memory device. Cache blocks can contain single-level cell (SLC) blocks containing multiple SLCs, and non-cache blocks can contain multi-layer cell (MLC) blocks containing multiple MLCs, triple-level cell (TLC) blocks containing multiple TLCs, or quad-level cell (QLC) blocks containing QLCs. Writing first to one or more SLC blocks may be called SLC write caching or SLC caching (also called buffering in SLC mode). Generally, when using traditional full SLC caching, data is moved from SLC blocks to non-cache blocks (such as QLC blocks), and after the non-cache blocks are verified to be error-free, the data in the SLC blocks is released.

[0013] A block compression (or garbage collection) operation can be performed on a cache block (containing one or more memory cells) of a memory device (e.g., a NAND memory device), and the data stored in the cache block is copied (e.g., transferred) to a non-cache block. For example, if there are no cache blocks available to cache new data (e.g., cache newly written data), a compression operation may be performed on a set of cache blocks. As used herein, a block compression operation may be performed on a cache block and may include reading the data stored on the cache block and writing the read data to a non-cache block (e.g., programming the non-cache block with the data read from the cache block), thereby copying the data from the cache block to the non-cache block. An exemplary block compression operation may include an SLC-QLC block compression operation. A block compression operation may be performed, for example, when the available cache blocks in a memory device are full or approaching a fill limit.

[0014] In conventional memory devices, including non-logical AND (NAND) memory cells (hereinafter referred to as NAND memory devices), sequential writing and erasing generally leads to a decrease or reduction in write amplification (e.g., low write amplification factor (WAF)) and improved data performance. Modern software on a host system (e.g., software applications, databases, and file systems) tends to read and write data sequentially to and from a memory system (e.g., a memory subsystem coupled to the host system). However, when such software is run on one or more multi-core hardware processors in the host system, the continuity of data access requests to the memory system (e.g., read and write requests) is usually lost. For example, when modern software runs on one or more multi-core hardware processors in a host system, the block layer of the host system typically divides the work performed by each process (of the software) across two or more cores of the multi-core hardware processor (e.g., in a way that the work is evenly distributed across the cores to achieve maximum throughput). While each core of the host system's hardware processor may still issue mostly sequential data access requests to the memory system, these requests are typically mixed with each other (e.g., interleaved) and appear random or pseudo-random from the memory system's perspective. This can be due to data aggregation and request prioritization policies at the data link layer between the host system and the memory system. For example, memory systems with a non-volatile memory express (NVMe) architecture are typically designed to have a non-sequential traffic handshake between the host system and the memory system's controller for data performance reasons.

[0015] The architecture of conventional memory systems, such as those implemented by the NVMe standard, includes multiple queues for processing data access requests (e.g., read and write requests) from a host system. For example, a memory system based on the NVMe standard may include multiple queue pairs, each queue pair associated with a different queue identifier (QID), and each queue pair includes a submission queue for incoming requests that need to be completed / processed, and a completion queue for command requests that have already been completed / processed by the memory system. In this specification, a submission queue identifier (SQID) may refer to the submission queue of a given queue pair and may be equal to the QID of a given queue pair. The QID may be included as a parameter (e.g., a QID tag) in a data access request from the host system to the memory system and may function as a pointer to the submission queue on the memory system that receives the data access request. Generally, each core of a host system's hardware processor is individually associated with (e.g., allocated, mapped, and attached to) a different QID (e.g., different queue pairs on a memory system with unique QIDs), and data access requests from a given core (e.g., read and write requests) are received and stored by submission queues having the queue identifier associated with the given core. Furthermore, a given thread running on the host system (e.g., a software application or database on the host system) tends to start / run on the same core of the host system's hardware processor (e.g., threads on the host system have core affinity). A given core of the host system's hardware processor can have multiple threads (e.g., 4-5 threads) running on that core and having affinity to that core.

[0016] In conventional memory systems, read-ahead operations (or processes) can be performed to improve memory access latency, optimize data retrieval, or both. Typically, performing read-ahead operations on a memory system involves the memory system fetching (or prefetching) data from one of its memory devices before it is explicitly requested by the host system (e.g., a hardware processor on the host system or a software application running on the host system). Specifically, read-ahead operations (also called read-look-ahead operations) can take advantage of the spatial locality of data stored on memory devices and the tendency of the host system (e.g., a software application running on it) to access data from contiguous memory locations. When a particular memory location on a memory device is accessed (or a series of particular memory locations on a memory device) in response to a request from the host system (e.g., a read request), the host system is likely to explicitly request data access from one or more subsequent memory locations on the memory device in a contiguous sequence. Based on this prediction, the memory system can initiate a read-ahead operation to fetch (or prefetch) data from a subsequent memory location into a cache, buffer, or other temporary data storage area. Then, when the host system explicitly requests the fetched / prefetched data from the memory system (e.g., via an explicit read request), the memory system has already made the requested data available in the cache or buffer, resulting in faster read access times. In this way, read-ahead operation can reduce, or assist in reducing, read access latency.

[0017] Generally, if a host system is configured to detect read-ahead opportunities on the host side and consolidate such opportunities into individual read requests that are sent to the memory system, then conventional memory systems have few opportunities to perform read-ahead operations. Nevertheless, conventional block input / output (I / O) drivers on a host system typically decompose individual read requests (submitted by the host system) into a series of smaller read requests, each with a read size less than or equal to the MDTS, if the read size of an individual read request reaches or exceeds the memory system's maximum data transfer size (MDTS). The sequences are typically sent to the memory system as a contiguous sequence (e.g., submitted to and received by the memory system). For example, if the memory system's MDTS is 512KB and the host system generates a single read request with a read size of 3MB, the host system's block I / O driver may split the single read request into five smaller sequences with a read size of 512KB each and a sixth read request with a read size of 410 bytes, thereby representing the remainder 3MB. The memory systems of the various embodiments described herein are configured to detect and utilize opportunities to perform read-ahead operations based on this action by a host-side block I / O driver.

[0018] Aspects of this disclosure relate to performing one or more data read-ahead operations on a memory system (e.g., a memory subsystem) based on the read size and the queue identifier of the read request. Specifically, in some embodiments, the memory system is configured to perform at least one read-ahead operation if each individual read request received from a host system in relation to a queue identifier has a read size equal to the memory system's MDTS. Furthermore, in some embodiments, the memory system continues to perform one or more subsequent read-ahead operations as long as subsequent requests received from the host system in relation to a queue identifier have a read size equal to the MDTS and specify a subsequent memory location (e.g., a subsequent LBA) for the last request received from the host system in relation to the queue identifier.

[0019] For example, if a memory system receives a first read request from a host system associated with QID#21, having an MDTS read size (e.g., 512KB), and specifying a first memory location on the memory device of the memory system (e.g., LBA100), the memory system can perform a read-ahead operation at a second memory location on the memory device following the first memory location (e.g., LBA101). Subsequently, if the memory system receives a second read request from a host system associated with QID#21, following the first read request (e.g., in a submission queue associated with QID#21), having an MDTS read size (e.g., 512KB), and specifying a memory location following the first memory location (e.g., the second memory location), the memory system can perform a read-ahead operation at a third memory location on the memory device following the second memory location (e.g., LBA102). The continuous performance of this read-ahead operation can continue until a sequence of read requests to contiguous memory locations on a memory device with an MDTS read size (e.g., a contiguous sequence) stops flowing from the submission queue associated with QID#21 (e.g., until the continuous sequence of read requests ends). For example, the performance of a continuous read-ahead operation can end when (a) a write request is taken out of the submission queue associated with QID#21, (b) a read request with a discontinuous memory location is taken out of the submission queue associated with QID#21, or (c) a read request with a read size smaller than MDTS is taken out of the submission queue associated with QID#21.

[0020] Various embodiments are described herein with respect to comparing read sizes for the MDTS of a memory system. For alternative embodiments, a reference read transfer size may be used instead of the MDTS of the memory system, where the reference read transfer size can be set to a value different from the MDTS (e.g., smaller or larger than the MDTS). It will be understood that the reference read transfer size may be used according to the embodiment, and the reference read transfer size may include a value set or updated by a user of the memory system or by a process (e.g., a process configured to dynamically adjust a value based on one or more conditions).

[0021] Overall, the use of the various embodiments described herein can provide advantages common to the use of read-ahead operations, such as reducing read latency and optimizing data acquisition, on a memory system.

[0022] Data access requests and command requests are used interchangeably herein. As used herein, a data access request / command request can include a data access command for a memory system. Thus, a write request can include a write command for a memory system, and a read request can include a read command for a memory system.

[0023] As used herein, a superblock of a memory device (e.g., a memory system) includes a plurality of blocks (e.g., a set or group) of the memory device. For example, a superblock of a NAND-type memory device can include a plurality of blocks that share the same position in each plane of each NAND-type memory die of the NAND-type memory device.

[0024] Some examples of performing one or more data read-ahead operations on a memory system (e.g., a memory subsystem) based on a read size and a queue identifier of a read request are disclosed herein as described herein.

[0025] FIG. 1 shows an exemplary computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 can include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

[0026] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, secure digital (SD) cards, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0027] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an aircraft, a drone, a train, an automobile, or other means of transportation), an Internet of Things (IoT) device, an embedded computer (e.g., those included in vehicles, industrial equipment, or networked commercial devices), or such a computing device including memory and processing devices.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 shows an example of a host system 120 coupled to one memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to connections between components, whether wired or wireless, including electrical, optical, magnetic, and other connections, which may be indirect or direct communication connections (e.g., without intervening components).

[0029] The host system 120 may include a processor chipset and a software stack run by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110.

[0030] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, SATA interfaces, Peripheral Component Interconnect Express (PCIe) interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory buses, DIMM interfaces (e.g., DIMM socket interfaces that support DDR), Open NAND Flash Interface (ONFI), DDR, Low Power Double Data Rate (LPDDR), or any other interfaces. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130). The physical host interface can provide an interface for passing control signals, address signals, data signals, and other signals between the memory subsystem 110 and the host system 120. Figure 1 shows a memory subsystem 110 as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0031] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, a random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and write-in-place memory such as three-dimensional (3D) crosspoint memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can work in conjunction with stackable cross-grid data access arrays to perform bit storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, which allow programming of non-volatile memory cells without pre-erasing them. NAND flash memory includes, for example, two-dimensional (2D) NAND and three-dimensional NAND.

[0033] Each of the memory devices 130 may contain one or more arrays of memory cells. For example, one type of memory cell, such as SLC, can store one bit per cell. Other types of memory cells, such as MLC, TLC, QLC, and pentalevel cells (PLC), can store multiple fractional bits per cell. In some embodiments, each of the memory devices 130 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may contain an SLC portion and an MLC portion, a TLC portion, or a QLC portion of the memory cells. The memory cells of the memory device 130 can be grouped as pages, which may refer to logical units of the memory device used to store data. In some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0034] As used herein, a block containing SLC may be called an SLC block, a block containing MLC may be called an MLC block, a block containing TLC may be called a TLC block, and a block containing QLC may be called a QLC block.

[0035] While non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D crosspoint arrays of non-volatile memory cells are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selection memory, other chalcogenide-based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random-access memory (FeRAM), magnetic random-access memory (MRAM), spin-transfer-to-reverse (STT) MRAM, conductive bridge RAM (CBRAM), resistive random-access memory (RRAM), oxide-based RRAM (OxRAM), negative OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, the controller 115) can perform operations such as reading data from the memory device 130, writing data to the memory device 130, or erasing data from the memory device 130, and can communicate with the memory device 130 to perform other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or separate components, buffer memory, or a combination thereof. The hardware may include digital circuits with dedicated (i.e., hardcoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing routines that control the operation of the memory subsystem 110, including processing various processes, operations, logical flows, and communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, the local memory 119 may include memory registers for storing memory pointers, fetched data, and so on. The local memory 119 may also include ROM for storing microcode. The exemplary memory subsystem 110 in Figure 1 is shown to include a memory subsystem controller 115, but in other embodiments of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands, requests, or actions from the host system 120 and translate these commands, requests, or actions into instructions or appropriate commands to achieve desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may also perform other operations such as wear leveling, garbage collection, error detection and ECC correction code operations, encryption, caching, and address translation between logical addresses (e.g., LBA, namespace) and physical memory addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that receives addresses from the memory subsystem controller 115 and decodes the addresses to access the memory device 130.

[0041] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] Each of the memory devices 130 and 140 includes memory dies 150 and 160. In some embodiments, each of the memory devices 130 and 140 represents a memory device including a printed circuit board on which the respective memory dies 150 and 160 are soldered.

[0043] The memory subsystem controller 115 includes a read-size and queue identifier-based read-ahead unit 113 (hereinafter, read-ahead unit 113) which enables or facilitates the memory subsystem controller 115 to perform one or more data read-ahead operations on the memory subsystem 110, as described herein. In some embodiments, the read-ahead unit 113 may be part of a larger queue identifier-based request processor (not shown). Alternatively, part or all of the read-ahead unit 113 may be included by a local media controller 135 which enables or facilitates the performance of one or more data read-ahead operations on the memory subsystem 110, as described herein.

[0044] Figure 2 shows exemplary architectures 200 of the host system 120 and memory subsystem 110 of Figure 1, according to some embodiments of the present disclosure. In exemplary architecture 200, the host system 120 includes a plurality of hardware processor cores 214, a software application 210 running on the plurality of hardware processor cores 214, and a kernel 212 (e.g., of an operating system) running on the plurality of hardware processor cores 214. Furthermore, in exemplary architecture 200, the memory subsystem 110 includes a data stream identifier 220 (e.g., part of a queue identifier-based request processor) and a plurality of queue pairs 222, including queue pairs associated with queue identifier-1 (QID-1) via queue identifier-N (QID-N). The queue pair associated with queue identifier-1 (QID-1) includes submission queue 1 (SQ-1) and completion queue (CQ-1); the queue pair associated with queue identifier-2 (QID-2) includes submission queue 2 (SQ-2) and completion queue (CQ-2); the queue pair associated with queue identifier-3 (QID-3) includes submission queue 3 (SQ-3) and completion queue (CQ-3); the queue pair associated with queue identifier-4 (QID-4) includes submission queue 4 (SQ-4) and completion queue (CQ-4), and so on. During operation, the software application 210 can trigger the execution of processes (each having a process identifier (PROCESS_ID)) by the kernel 212, and one or more of these processes may include generating sequential data access requests. The kernel 212 can execute at least one of these processes by dividing the processes into multiple threads (each having a thread identifier (THREAD_ID)) executed by the multi-hardware processor core 214.Each thread can be assigned to run on one of the multi-hardware processor cores 214 (for example, according to core affinity), and the execution of a thread by a given hardware processor core can cause the given hardware processor core to generate and issue one or more data access requests to the memory subsystem 110, each of which generates / issues a queue identifier (QID) of the given hardware processor core.

[0045] Since data access requests are generated and issued by the multi-hardware processor core 214, data access requests from each hardware processor core can be interleaved with requests generated and issued by one or more other hardware processor cores. Therefore, data access requests received by the memory subsystem 110 may appear random or pseudo-random to the memory subsystem 110.

[0046] Upon receiving a given data access request, the memory subsystem 110 can use the data stream identifier 220 to determine a given queue identifier for the given data access request, and the memory subsystem 110 can store the given data access request in the submission queue of a queue pair (a pair of queues 222) corresponding to (e.g., matching) the given queue identifier (e.g., in an entry added to the submission queue). If the given data access request is being processed (e.g., executed) by the memory subsystem 110, the result of the given data access request can be stored (e.g., queued) in the completion queue (a entry added to the completion queue) of a queue pair (a pair of queues 222) corresponding to (e.g., matching) the given queue identifier, from which the host system 120 can retrieve (e.g., collect) the result.

[0047] Figures 3, 4A, and 4B are flowcharts of exemplary methods 300, 400 for performing one or more data read-ahead operations on a memory system, according to some embodiments of the present disclosure. Any of the methods 300, 400 can be performed by processing logic that may include hardware (e.g., processing devices, circuits, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions actuated or executed by the processing device), or a combination thereof. In some embodiments, at least one of the methods 300, 400 is performed by the memory subsystem controller 115 of Figure 1 based on the read-ahead unit 113. Additionally or alternatively, in some embodiments, at least one of the methods 300, 400 is performed at least partially by the local media controller 135 of the memory device 130 of Figure 1. Although shown in a particular sequence or order, the order of processes can be modified unless otherwise specified. Thus, the embodiments shown should be understood as examples only, the processes shown can be performed in a different order, and some processes can be performed in parallel. Furthermore, in various embodiments, one or more processes can be omitted. Therefore, not all processes are used in all embodiments. Other process flows are possible.

[0048] Referring now to method 300 in Figure 3, in operation 302, the processing device (e.g., the processor 117 of the memory subsystem controller 115) retrieves a first read request from an individual submission queue (e.g., for an individual queue pair) associated with an individual queue identifier (e.g., QID#5) to read first stored data starting from a first memory location on the memory system (e.g., on the memory device 130 of the memory subsystem 110). Next, in operation 304, the processing device (e.g., the processor 117) determines whether the first read request satisfies an initial set of conditions for performing a first read-ahead operation based on the first memory location. In some embodiments, the initial set of conditions includes the first read request having a read size that is not less than the MDTS of the memory system (e.g., a read size equal to the MDTS, or a read size greater than the MDTS).

[0049] If, at decision point 306, the processing device (e.g., processor 117) determines that the initial set of conditions is not met, method 300 proceeds to operation 322, where the processing device causes the first read request to be executed without performing or initiating the execution of a (first) read-ahead operation. For example, the execution of the first read request allows the first stored data to be read starting from a first memory location, and the amount of data to be read is specified by the first read size of the first read request. However, if, at decision point 306, the processing device (e.g., processor 117) determines that the initial set of conditions is met, method 300 proceeds to operation 308.

[0050] During operation 308, a processing device (e.g., processor 117) initiates (e.g., calls) a first read-ahead operation based on a first memory location. According to some embodiments, the first read-ahead operation based on a first memory location includes reading (e.g., fetching) second stored data starting from a second memory location, where an MDTS amount of data is read starting from the second memory location, and the second memory location is contiguous to the first memory location after the MDTS amount of data (e.g., the second memory location is the next memory location following the end of the first stored data). In various embodiments, the second stored data read from the second memory location by the first read-ahead operation is stored in a staging memory location (e.g., a pending or reserved memory location) on the memory system (e.g., local memory 119), where the staging memory location is associated (e.g., indexed) with an individual queue identifier (e.g., QID#5) for the first read request. A staging memory location associated with an individual queue identifier can function as temporary data storage for second stored data read by a first read-ahead operation. By storing the second stored data in a staging memory location associated with an individual queue identifier, the memory system can stage (e.g., hold) the second stored data before sending it to (e.g., passing it on) the host system (e.g., before sending the second stored data to the host system 120 by the completion queue associated with the individual queue identifier (e.g., QID#5)).

[0051] After initiating the execution of the first read-ahead operation, in operation 310, the processing device (e.g., processor 117) retrieves the next consecutive request from the individual submission queue of the memory system (e.g., memory subsystem 110). In operation 312, the processing device determines whether the next consecutive request (retrieved from the individual submission queue) satisfies a subsequent set of conditions for performing the next read-ahead operation based on the next memory location (e.g., a second memory location). In some embodiments, the subsequent set of conditions includes that the next request is a read request that has a read size not less than the MDTS of the memory system (e.g., a read size equal to or greater than the MDTS), requests the memory system to read data from the next memory location (e.g., a second memory location), and specifies the next memory location (e.g., specifies the second memory location).

[0052] If, at decision point 314, the processing device (e.g., processor 117) determines that the subsequent set of conditions is not met, method 300 proceeds to operation 320, where the processing device does not initiate any read-ahead operations (e.g., does not make any calls). However, if, at decision point 314, the processing device (e.g., processor 117) determines that the subsequent set of conditions is met, method 300 proceeds to operation 316.

[0053] In operation 316, the processing device (e.g., processor 117) causes the host system (e.g., 120) to send the last data stored in the staging memory location associated with each individual queue identifier (e.g., QID#5) (the last read-ahead operation performed in relation to the same individual queue identifier, hereafter referred to as the last read-ahead operation) via the completion queue associated with the individual queue identifier. For example, the processing device may cause the host system to send the last data by submitting the last data to the completion queue associated with the individual queue identifier (e.g., by copying the last data into a newly submitted entry).

[0054] Subsequently, in operation 318, the processing device (e.g., processor 117) initiates the execution of the next consecutive read-ahead operation (e.g., call) based on the last memory location read (e.g., the last memory location read by the last executed read-ahead operation). In this way, the memory system can continue the consecutive sequence of read-ahead operations being performed for consecutive read requests received by the memory system in relation to individual queue identifiers (e.g., QID#5). In various embodiments, executing a read-ahead operation based on the last memory location read includes reading data stored from the next memory location following the last memory location after the MDTS amount of data. For example, if the last memory location read by the read-ahead operation (the last read-ahead operation performed for an individual queue identifier) ​​corresponds to memory address LBA200 and the MDTS amount of data corresponds to a single data block, the next memory location may correspond to LBA201. According to some embodiments, the next consecutive read-ahead operation based on the last memory location read (e.g., LBA200) includes reading (e.g., fetching) the next stored data starting from the next memory location (e.g., LBA201), with an MDTS amount of data being read starting from the next memory location, and the next memory location being consecutively followed by the last memory location after the MDTS amount of data. In various embodiments, the next stored data read from the next memory location by the next consecutive read-ahead operation is stored in a staging memory location (e.g., a pending or reserved memory location) on the memory system (e.g., local memory 119), where the memory location is associated (e.g., indexed) with an individual queue identifier (e.g., QID#5) of the first read request. As described above, the staging memory location associated with an individual queue identifier can function as temporary data storage for the next stored data read by the next consecutive read-ahead operation.

[0055] After operation 318, method 300 returns to operation 310, and the processing device (e.g., processor 117) may repeat method 300 for the next request from the submission queue associated with an individual queue identifier (e.g., QID#5), thereby continuing the sequence of read-ahead operations being performed.

[0056] Referring here to Method 400 in Figures 4A and 4B, Method 400 illustrates another exemplary method for performing one or more data read-ahead operations on a memory system, and more specifically, represents an exemplary implementation of Method 300 in Figure 3. In operation 402, a processing device (e.g., a processor 117 of the memory subsystem controller 115) receives a set of command requests from a host system. In various embodiments, each individual command request in the set of command requests includes an individual queue identifier (e.g., a QID tag), and the individual command request is stored in an individual submission queue of an individual queue pair of the memory system, and the individual queue pair is associated with the individual queue identifier of the individual command request (e.g., corresponding). Then, in operation 404, the processing device retrieves a first read request (e.g., a single read request) from a single submission queue of one of the multiple queue pairs of the memory system to read data from a specified memory location on the memory device, and the single queue pair is associated with the single queue identifier of the first read request (e.g., corresponding).

[0057] In operation 406, the processing device (e.g., processor 117) determines a first read size (e.g., single read size) for the first read request, the first read size specifying the amount of data to be read from the specified memory location. Then, in operation 408, the processing device (e.g., processor 117) determines whether the first read size is less than the maximum data transfer size (MDTS) of the memory subsystem. If, at determination point 410, the processing device determines that the first read size is less than the MDTS (e.g., the first read size is not equal to the MDTS), method 400 proceeds to operation 412, where the processing device causes the first read request to be executed without performing or initiating a read-ahead operation. In various embodiments, the execution of the first read request reads the stored data from the memory device starting from the specified memory location, and the stored data is sent to the host system (e.g., 120) via individual completion queues (associated with individual queue identifiers) of a single queue pair (e.g., without staging). However, if at decision point 410 the processing device determines that the first read size is not smaller than MDTS (for example, the first read size is greater than or equal to MDTS), then method 400 proceeds to operation 414.

[0058] During operation 414, a processing device (e.g., processor 117) executes a first read request, which, upon execution of the first read request, reads stored data from the memory device starting from a specified memory location, and the stored data is sent to the host system (e.g., 120) via individual completion queues (associated with individual queue identifiers) of a single queue pair (e.g., without staging). Subsequently, in operation 416, the processing device performs, or initiates, a (first) read-ahead operation based on the specified memory location and MDTS. In some embodiments, the execution of a (first) read-ahead operation based on the specified memory location and MDTS includes causing a second amount of stored data (of MDTS) to be read, starting from a second memory location on the memory system, where the second memory location is the next memory location following the first memory location after the amount of data of MDTS. Furthermore, in some embodiments, the execution of a (first) read-ahead operation based on a specified memory location and MDTS includes causing the second stored data (data read from the next memory location) to be stored in a staging memory location associated with a single queue identifier.

[0059] Method 400 proceeds to operation 418, in which the processing device (e.g., processor 117) retrieves from a single submission queue the next consecutive request following the first read request. The next consecutive request may include a read request or a write request. In operation 420, the processing device (e.g., processor 117) determines whether the next consecutive request is a second read request to read data from the memory device, starting from a second memory location.

[0060] If, at operation 422, the processing device (e.g., processor 117) determines that the next consecutive request is a second read request to read data starting from a second memory location, method 400 proceeds to operation 424. However, if, at decision point 422, the processing device determines that the next consecutive request is not a second read request (e.g., the next consecutive request is a write request or a read request to read from another memory location), method 400 returns to operation 412, causing the processing device to execute the next consecutive request without performing or restarting a read-ahead operation again. Alternatively, if the processing device determines that the next consecutive request is not a second read request, the processing device causes the second stored data from the staging memory location to be sent to the host system via a single completion queue of a single queue pair without performing or restarting a read-ahead operation again.

[0061] In operation 424, the processing device (e.g., processor 117) determines the second read size of the second read request, and in operation 426, the processing device determines whether the second read size is less than MDTS. Then, at decision point 428, if the processing device determines that the second read size is less than MDTS, method 400 proceeds to operation 412, where the processing device causes the second read request to be executed without performing or restarting a read-ahead operation again. Alternatively, if the processing device determines that the second read size is less than MDTS, the processing device causes the second stored data at the staging memory location to be sent to the host system via a single completion queue of a single queue pair without performing or restarting a read-ahead operation again. However, if at decision point 428 the processing device determines that the second read size is not less than MDTS (e.g., greater than or equal to MDTS), then method 400 proceeds to operation 430, in which the processing device causes the second stored data in the staging memory location to be sent to the host system via a single completion queue of a single queue pair. For example, this could include the processing device copying the second stored data into a new entry submitted to the completion queue associated with the individual queue identifier.

[0062] Following operation 430, method 400 proceeds to operation 432, in which a processing device (e.g., processor 117) performs or initiates a second read-ahead operation based on a second memory location and MDTS. In some embodiments, the execution of the second read-ahead operation based on a second memory location and MDTS includes causing a third stored data (of MDTS) to be read, starting from a third memory location on the memory system, where the third memory location is the next memory location following the second memory location after the amount of data of MDTS.

[0063] Figure 5 shows an exemplary machine of the form of computer system 500, in which a set of instructions can be executed to cause the machine to perform one or more of the methods described herein. In some embodiments, computer system 500 may correspond to a host system (e.g., host system 120 in Figure 1) which is coupled to or utilizes a memory subsystem (e.g., memory subsystem 110 in Figure 1), or which can be used to perform the operations described herein. In alternative embodiments, the machine may be connected to (e.g., network-connected to) other machines in a local area network (LAN), intranet, extranet, and / or the internet. The machine may function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0064] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify the actions to be taken by that machine. Furthermore, although a single machine is shown, the term “machine” shall also be interpreted as including any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methods described herein.

[0065] An exemplary computer system 500 includes processing devices 502, main memory 504 (e.g., ROM, flash memory, SDRAM or DRAM such as Rambus DRAM (RDRAM)), static memory 506 (e.g., flash memory, static random access memory (SRAM)), and data storage devices 518, all of which communicate with each other via a bus 530.

[0066] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor or a central processing unit. More specifically, the processing device 502 may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processing device 502 may also be one or more dedicated processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device 502 is configured to execute instructions 526 for performing the operations and steps described herein. The computer system 500 may further include a network interface device 508 for communication over the network 520.

[0067] The data storage device 518 may include a machine-readable storage medium 524 (also known as a computer-readable medium) containing one or more instruction sets 526 or software that embody one or more of the methods or functions described herein. The instructions 526 may also reside entirely or at least partially in the main memory 504 and / or the processing device 502 while the computer system 500, main memory 504, and processing device 502, which constitute the machine-readable storage medium, execute it. The machine-readable storage medium 524, the data storage device 518, and / or main memory 504 may correspond to the memory subsystem 110 in Figure 1.

[0068] In one embodiment, instruction 526 includes instructions that implement a function corresponding to performing one or more data read-ahead operations in the memory subsystem 110 (e.g., the read-ahead unit 113 in Figure 1), as described herein. Although the machine-readable storage medium 524 is shown to be a single medium in exemplary embodiments, the term “machine-readable storage medium” should be interpreted as including a single or more mediums that store one or more sets of instructions. The term “machine-readable storage medium” should also be interpreted as including any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine to perform one or more of the methods of the present disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0069] Some of the preceding detailed explanations are presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. Such descriptions and representations of algorithms are methods used by those skilled in the art in data processing techniques to most effectively convey the essence of their operation. Here, and generally, an algorithm is considered to be a self-consistent sequence of operations leading to a desired result. Operations require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has sometimes been found convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0070] However, it should be recognized that all these and similar terms should correspond to appropriate physical quantities and are merely convenient designations applicable to those quantities. This disclosure may refer to the operation and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memory of a computer system and converts it into other data similarly represented as physical quantities in the memory or registers of a computer system or such information storage system.

[0071] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be configured specifically for a particular purpose of use, or may include a general-purpose computer that is selectively started or reconfigured by a computer program stored in the computer. Such a computer program may be stored in any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus, but is not limited to these.

[0072] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be programmed according to the teachings herein, or it may be advantageous to construct a more dedicated device for performing the method. The various structures of these systems will appear as described below. Furthermore, this disclosure does not describe any particular programming language. It should be understood that various programming languages ​​can be used to perform the teachings of this disclosure as described herein.

[0073] This disclosure may be provided as a computer program product or software that includes a machine-readable medium (e.g., non-temporary machine-readable medium) containing instructions that can be used to program a computer system (or other electronic device) to perform a process in accordance with this disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer)-readable storage media such as ROM, RAM, magnetic disk storage media, optical storage media, and flash memory components.

[0074] In the above-mentioned specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments. It is evident that various modifications can be made without departing from the broader spirit and scope of the embodiments of the disclosure set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. It is a system, Multiple queues, Memory devices and, A processing device operably coupled with the aforementioned memory device, Retrieving a read request from a submission queue among the plurality of queues for reading data from a specified memory location on the memory device, wherein the submission queue is associated with a queue identifier, and the retrieval is performed accordingly. Determining the read size of the read request, wherein the read size specifies the amount of data to be read from the specified memory location. Determining whether the read size is smaller than the maximum data transfer size, In response to determining that the read size is not smaller than the maximum data transfer size, The act of executing the read request, wherein the execution of the read request causes the data stored with the maximum data transfer size to be read from the memory device starting from the specified memory location, Based on the specified memory location and the maximum data transfer size, the read-ahead operation is initiated. The processing device, configured to perform an operation including, The system comprising the above.

2. The aforementioned operation, The system according to claim 1, which, in response to determining that the read size is smaller than the maximum data transfer size, causes the read request to be executed without initiating the execution of the read-ahead operation, wherein the execution of the read request causes the stored data to be read from the memory device starting from the specified memory location and transmitted to the host system via a completion queue among the plurality of queues, and the completion queue is associated with the queue identifier.

3. The stored data is the first stored data, the specified memory location is the first memory location, and the execution of the read-ahead operation based on the specified memory location and the maximum data transfer size is The system according to claim 1, comprising reading a second stored data of the maximum data transfer size from the memory device, starting from a second memory location on the memory device, wherein the second memory location is the next memory location following the first memory location after the data of the maximum data transfer size.

4. The execution of the read-ahead operation based on the specified memory location and the maximum data transfer size is as follows: The system according to claim 3, comprising storing the second stored data read from the memory device in a staging memory location associated with the queue identifier.

5. The read request is a first read request, the read size is a first read size, and the operation occurs after the start of the execution of the read-ahead operation based on the specified memory location and the maximum data transfer size. From the aforementioned submission queue, retrieve the next consecutive request following the aforementioned read request, Determining whether the next consecutive request is a second read request to read data from the memory device starting from the second memory location, In response to determining that the next consecutive request is the second read request for reading data starting from the second memory location, Determining the second read size of the second read request, Determining whether the second read size is smaller than the maximum data transfer size, In response to determining that the second read size is not smaller than the maximum data transfer size, The transmission of the second stored data at the staging memory location to the host system via a completion queue among the plurality of queues, wherein the completion queue is associated with the queue identifier. Based on the second memory location and the maximum data transfer size, the execution of the read-ahead operation is initiated. The system according to claim 4, including the system described in claim 4.

6. The aforementioned operation, The system according to claim 5, comprising, in response to determining that the next consecutive request is not the second read request for reading data starting from the second memory location, causing the next consecutive request to be executed without initiating the execution of the read-ahead operation.

7. The aforementioned operation, The system according to claim 5, wherein, in response to determining that the second read size is smaller than the maximum data transfer size, the second read request is executed without initiating the execution of the read-ahead operation, the execution of the second read request causes the data stored in the second read size to be read from the memory device, starting from the second memory location.

8. The aforementioned operation, The system according to claim 5, which, in response to determining that the second read size is smaller than the maximum data transfer size, causes the second stored data at the staging memory location to be transmitted to the host system without initiating the execution of the read-ahead operation, wherein the second stored data is transmitted to the host system via a completion queue among the plurality of queues, and the completion queue is associated with the queue identifier.

9. The execution of the read-ahead operation based on the second memory location and the maximum data transfer size is The system according to claim 5, comprising reading a third stored data of the maximum data transfer size from the memory device, starting from a third memory location on the memory device, wherein the third memory location is the next memory location following the second memory location after the data of the maximum data transfer size.

10. The execution of the read-ahead operation based on the second memory location and the maximum data transfer size is The system according to claim 9, comprising storing the third stored data read from the memory device in the staging memory location associated with the queue identifier.

11. The submission queue is a selective submission queue, the read request is a selective read request, and the operation is The system according to claim 1, which includes receiving a set of command requests from a host system, wherein each of the individual command requests in the set of command requests includes an individual queue identifier, and the individual command request is stored in an individual submission queue of the plurality of queues associated with the individual queue identifier.

12. The system according to claim 1, wherein the read request is a selective read request, the read size is a selective read size, and the block input / output driver of the host system is configured to divide a large read request having a read size larger than the maximum data transfer size into a plurality of read requests, each having an individual read size less than or equal to the maximum data transfer size.

13. When executed by the processing device of the memory subsystem, the processing device will Retrieving a read request from the submission queue of the memory subsystem to read data from a specified memory location of the memory device of the memory subsystem, wherein the submission queue is associated with a queue identifier, and the retrieve is performed accordingly. Determining the read size of the read request, wherein the read size specifies the amount of data to be read from the specified memory location. Determining whether the read size is smaller than the maximum data transfer size, In response to determining that the read size is not smaller than the maximum data transfer size, The act of executing the read request, wherein the execution of the read request causes the data stored with the maximum data transfer size to be read from the memory device starting from the specified memory location, A non-temporary machine-readable storage medium comprising an instruction for causing an operation to be performed, which includes initiating a read-ahead operation based on the specified memory location and the maximum data transfer size.

14. The aforementioned operation, The at least one non-temporary machine-readable storage medium according to claim 13, which includes, in response to determining that the read size is smaller than the maximum data transfer size, causing the read request to be executed without initiating the execution of the read-ahead operation, wherein the execution of the read request causes the stored data to be read from the memory device, starting from the specified memory location, and transmitted to the host system via the completion queue of the memory subsystem, the completion queue being associated with the queue identifier.

15. The stored data is the first stored data, the specified memory location is the first memory location, and the execution of the read-ahead operation based on the specified memory location and the maximum data transfer size is The at least one non-temporary machine-readable storage medium according to claim 13, comprising reading a second stored data of the maximum data transfer size from the memory device, starting from a second memory location on the memory device, wherein the second memory location is the next memory location following the first memory location after the data of the maximum data transfer size.

16. The execution of the read-ahead operation based on the specified memory location and the maximum data transfer size is as follows: The at least one non-temporary machine-readable storage medium according to claim 15, comprising storing the second stored data read from the memory device in a staging memory location associated with the queue identifier.

17. The read request is a first read request, the read size is a first read size, and the operation occurs after the start of the execution of a read-ahead operation based on the specified memory location and the maximum data transfer size. From the aforementioned submission queue, retrieve the next consecutive request following the aforementioned read request, Determining whether the next consecutive request is a second read request to read data from the memory device starting from the second memory location, In response to determining that the next consecutive request is the second read request for reading data starting from the second memory location, Determining the second read size of the second read request, Determining whether the second read size is smaller than the maximum data transfer size, In response to determining that the second read size is not smaller than the maximum data transfer size, The transmission of the second stored data at the staging memory location to the host system via the completion queue of the memory subsystem, wherein the completion queue is associated with the queue identifier. Based on the second memory location and the maximum data transfer size, the execution of the read-ahead operation is initiated. The at least one non-temporary machine-readable storage medium according to claim 16, including

18. The aforementioned operation, At least one non-temporary machine-readable storage medium according to claim 17, comprising causing the subsequent consecutive requests to be executed without initiating the execution of the read-ahead operation, in response to determining that the subsequent consecutive requests are not the second read requests for reading data starting from the second memory location.

19. The aforementioned operation, The at least one non-temporary machine-readable storage medium according to claim 17, which includes causing the host system to transmit the second stored data at the staging memory location without initiating the execution of the read-ahead operation, in response to determining that the second read size is smaller than the maximum data transfer size, wherein the second stored data is transmitted to the host system via a completion queue of the memory subsystem, and the completion queue is associated with the queue identifier.

20. Retrieving a first read request from a processing device of the memory subsystem and from a submission queue of the memory subsystem for reading data from a first memory location on the memory subsystem, wherein the submission queue is associated with a queue identifier, The processing device determines whether the first read request satisfies an initial set of conditions for executing the first read-ahead operation, In response to determining that the first read request satisfies the initial set of conditions, The processing device starts executing the first read-ahead operation based on the first memory location, The processing device retrieves the next consecutive request from the submission queue, The processing device determines whether the next consecutive request satisfies a subsequent set of conditions for performing the next consecutive read-ahead operation, In response to determining that the subsequent consecutive requests satisfy the subsequent set of conditions, the processing device initiates the execution of the next consecutive read-ahead operation based on the last memory location read by the last executed read-ahead operation. Methods that include...

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