CMOS-based Ising machine with quantized states and current-mode coupling

Abstract

The network comprises a plurality of coupled compute nodes and a plurality of active coupled units, each compute node comprising an input section configured to receive current from a subset of the plurality of coupled units in the network, an output section configured to generate at least two discrete output voltages, a capacitor configured to store its internal state as a voltage, and a quantizer electrically connected to the capacitor and configured to quantize the voltage of the capacitor to one of at least two discrete values, and having an output section connected to the output section of the compute node; each active coupled unit comprises an input section to receive an output voltage from one of the plurality of compute nodes, an output section connected to the input section of one of the plurality of compute nodes, a programmable current source, a programmable current sink, and a control circuit configured to connect either the current source or the current sink to the output section of the active coupled unit according to a voltage measured at the input section of the active coupled unit.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the priority of U.S. Provisional Patent Application No. 63 / 517,750, filed on August 4, 2023, the entire content of which is incorporated herein by reference.

[0002] Statement Regarding Federally Sponsored Research or Development The present invention was made with government support under Grant No. FA8650 - 23 - C - 7312 awarded by the Air Force Research Laboratory. The government has certain rights in the invention.

Background Art

[0003] Physical Inging Machines (IMs) are promising platforms that offer extremely high performance and efficiency for a variety of optimization problems. IMs have shown several orders of magnitude improvement in speed and energy efficiency compared to von Neumann - type systems when solving combinatorial optimization problems. However, the construction of such systems is still in its initial stages, and scalable and robust implementations remain difficult challenges.

[0004] For a long time, industry focused on improving general-purpose systems and dramatically increasing computing power. However, in recent years, dedicated designs have increasingly been adopted to prove highly effective in solving specific types of tasks such as encryption and network operations (see C. Johnson, et al., in 2010 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2010; B. Erbagci, et al., in 2015 IEEE Custom Integrated Circuits Conference (CICC), 2015; S. Song, et al., in 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018; and H. Kaul, et al., in 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016). Meanwhile, computing processes demand even better mechanisms to solve the diverse problems of today.

[0005] To facilitate computation of diverse workloads, researchers are attempting to map entire algorithms to physical processes so that the resulting states represent solutions to the mapped algorithms. One example is D-Wave Systems' quantum annealer (PI Bunyk, et al., IEEE Transactions on Applied Superconductivity, 2014), which maps combinatorial optimization problems to a system of qubits to minimize a Hamiltonian system. Careful control is required for the system to converge to an equilibrium state (i.e., the optimal solution), and the qubit states are read out as solutions to the mapped problem.

[0006] The common characteristics of Ising machines are as follows: (1) the problem is mapped to its physical configuration, (2) the internal state changes according to the machine's inherent physical laws, (3) the changes optimize a specific equation ("Ising model"), and (4) the machine's physical state is read out to obtain the solution to the mapped problem. Unlike von Neumann machines, these nature-based machines do not follow explicit algorithms. In recent years, a variety of Ising machines have been implemented in various ways (see T. Inagaki, et al., Science, 2016; T. Wang et al., 2019 and C. Roques-Carmes, et al., Nature Communications, 2020), and the complexity of the underlying physical principles varies. [Overview of the project] [Problems that the invention aims to solve]

[0007] Despite its potential to surpass conventional computers in terms of capability and solution search time, building a robust and versatile IM infrastructure remains challenging, and scalability is a crucial factor to consider. As the complexity of the problem to be solved increases, the number of required hardware components increases exponentially. Simple components are preferable in the implementation of an Ising machine to maintain a small form factor and chip area comparable to (or greater than) conventional computing infrastructure. However, trade-offs must be considered between component size, power consumption, and precise functionality. To address these challenges, this specification discloses a CMOS-compatible Ising machine with quantized node state and current mode-based nodal interaction (QS-CIM), which significantly improves the predictability and robustness of node coupling against device mismatches and process, voltage, and temperature (PVT) variations. The dynamic system naturally finds a local minimum in the energy landscape of the objective function. By applying spin-fixed annealing, the system reaches the minimum with high probability. [Means for solving the problem]

[0008] In one embodiment, the network comprises a plurality of coupled compute nodes and a plurality of active coupled units, each compute node comprising an input section configured to receive current from a subset of the plurality of coupled units in the network, an output section configured to generate at least two discrete output voltages, a capacitor configured to store its internal state as a voltage, and a quantizer electrically connected to the capacitor and configured to quantize the voltage of the capacitor to one of at least two discrete values, the quantizer having an output section connected to the output section of the compute node, each active coupled unit comprising an input section to receive an output voltage from one of the plurality of compute nodes, an output section connected to the input section of one of the plurality of compute nodes, a programmable current source, a programmable current sink, and a control circuit configured to connect either the current source or the current sink to the output section of the active coupled unit in accordance with a voltage measured at the input section of the active coupled unit.

[0009] In one embodiment, the quantizer of each arithmetic node is a comparator configured to compare the voltage across a capacitor with a threshold and generate two discrete voltages at the output of the arithmetic node according to the comparison result. In one embodiment, each quantizer is clocked by the same or substantially the same clock and configured to generate an output at the same or substantially the same clock edge. In one embodiment, the current from the current source or current sink of the active coupling unit is connected to a constant voltage source when it is not connected to the output of the active coupling unit. In one embodiment, each active coupling unit further comprises a 1-bit memory device having a stored value, which is used to adjust the input to the active coupling unit.

[0010] In one embodiment, the stored value is the complement of the input to the active coupling unit. In one embodiment, at least one programmable current source and programmable current sink in the active coupling unit is implemented as a metal-oxide-semiconductor transistor. In one embodiment, at least one programmable current source and programmable current sink in the active coupling unit is implemented as a non-volatile memory device selected from flash memory transistors or charge trap transistors. In one embodiment, the network further comprises at least one programming unit configured to program the programmable current source and programmable current sink.

[0011] In one embodiment, the programming unit includes at least one binary polarity output unit configured to supply polarity values ​​to at least one active coupling unit of the network; at least one magnitude output unit configured to supply a voltage magnitude to bias one or both of the current source and current sink of at least one active coupling unit of the network; a polarity memory element connected to the at least one binary polarity output unit and configured to store polarity values ​​and supply them to the at least one binary polarity output unit; an array of memory elements configured to store voltage magnitudes as a set of binary values; a digital-to-analog converter connected to the array of memory elements and configured to generate voltage magnitudes from the set of binary values; and a current mirror element connected to the digital-to-analog converter and the magnitude output unit and configured to mirror the current output from the digital-to-analog converter to the magnitude output unit.

[0012] In one embodiment, the network further comprises an inverted binary polarity output unit connected to the inverted output unit of a polarity memory element and configured to output a binary value having the opposite polarity to at least one binary polarity output unit. In one embodiment, the network further comprises a current conveyor having an input unit connected to the input unit of an arithmetic node and an output unit connected to a capacitor, wherein the current conveyor is configured to maintain its input unit at a constant voltage and to mirror a current proportional to the current received at the input unit to the capacitor. [Brief explanation of the drawing]

[0013] The above-mentioned objectives and features, as well as other objectives and features, will become apparent from the following description and accompanying drawings, which are described in order to understand the present invention and constitute part of the specification. In the drawings, the same numbers indicate the same component. [Figure 1] Figure 1 shows an example of a computer device. [Figure 2] Figure 2 is an example block diagram showing the components of a 3-node QS-CIM system. In this diagram, a node is represented by Node i, and a coupling unit is represented by CUij. [Figure 3] Figure 3 shows an example of a circuit implementation of a QS-CIM node. [Figure 4] Figure 4 shows an example of a diagonal coupling unit in a coupling array. [Figure 5] Figure 5 shows an example of a circuit diagram for an off-diagonal coupling unit of a coupling array. [Figure 6] Figure 6 shows an example of a circuit diagram for a programming unit of a coupled array. [Figure 7] Figure 7 shows the connection relationships between the coupling units and programming units of a coupled array. [Modes for carrying out the invention]

[0014] It should be understood that the drawings and description of the present invention are simplified to illustrate the elements necessary for a clear understanding of the invention, and many other elements found in related systems and methods have been omitted for clarity. Those skilled in the art will recognize that other elements and / or procedures are desired and / or necessary when carrying out the invention. However, such elements and procedures are well known to those skilled in the art and do not enhance the understanding of the invention, and are therefore not described in detail herein. The disclosure herein covers any variations and modifications to such elements and methods that are well known to those skilled in the art.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the meanings generally understood by those skilled in the art to which the present invention pertains. Methods and materials similar to or equivalent to those described herein may be used in carrying out or testing the present invention; however, this specification describes exemplary methods and materials.

[0016] In this specification, the following terms have the meanings defined in this section.

[0017] In this specification, “a” and “an” are used to indicate that the grammatical object referred to by the article is one or more (i.e., at least one). For example, “element” means one or more elements.

[0018] In this specification, "approximately" when referring to measurable values ​​such as quantity or duration of time shall be interpreted as including variations within ±20%, ±10%, ±5%, ±1%, and ±0.1% of the specified value, depending on the context.

[0019] Throughout this specification, various aspects of the invention may be presented in range form. It should be understood that range form is merely for convenience and conciseness and should not be interpreted as a strict limitation on the scope of the invention. Therefore, range descriptions should be considered to specifically disclose not only the individual numerical values ​​within that range but also all conceivable subranges. For example, a range description such as "1 to 6" is considered to include subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., and the individual numerical values ​​within those ranges (e.g., 1, 2, 2.7, 3, 4, 5, 5.3, 6 and any integers and partial increments between them). This applies regardless of the breadth of the range.

[0020] In one embodiment of the present invention, software that performs the instructions described herein may be stored in a non-temporary computer-readable medium, and the software performs some or all of the steps of the present invention when executed by a processor.

[0021] Aspects of the present invention relate to algorithms executed in computer software. While certain embodiments may be described as being written in a specific programming language or running on a specific operating system or computing platform, it should be understood that the systems and methods of the present invention are not limited to any specific programming language, platform, or combination thereof. Software executing the algorithms described herein may be written, compiled, or interpreted in any programming language well known to those skilled in the art, including but not limited to C, C++, C#, Objective-C, Java®, JavaScript®, MATLAB®, Python®, PHP, Perl, Ruby, or Visual Basic. Furthermore, it is understood that components of the present invention may run on any acceptable computing platform, including but not limited to servers, cloud instances, workstations, thin clients, mobile devices, embedded microcontrollers, televisions, or other suitable computing devices well known to those skilled in the art.

[0022] Part of the present invention will be described as software that runs on a computer device. While the software described herein may be disclosed as running on a specific computer device (e.g., a dedicated server or workstation), it will be understood by those skilled in the art that the software is inherently highly portable, and that most software that runs on a dedicated server can run on a wide range of devices for the purposes of the present invention, including desktop or mobile devices, laptops, tablets, smartphones, watches, wearable electronic devices, other wireless digital / mobile phones, televisions, cloud instances, embedded microcontrollers, thin client devices, or other suitable computer devices known to those skilled in the art.

[0023] Similarly, parts of the present invention will be described as communicating over various wireless or wired computer networks. In the present invention, the terms “network,” “networked,” and “networked” are understood to include wired Ethernet, fiber optic connections, wireless connections including various 802.11 standards, cellular WAN infrastructure such as 3G, 4G / LTE, or 5G networks, Bluetooth®, Bluetooth® Low Energy (BLE), Zigbee® communication links, or any other way by which one electronic device can communicate with another electronic device. In some embodiments, elements of the networked portion of the present invention may be implemented via a virtual private network (VPN).

[0024] Figure 1 and the following description are intended to provide a brief and general description of suitable computing environments in which the present invention may be implemented. Although the present invention has been described above in the general context of a program module that runs in conjunction with an application program running on a computer operating system, those skilled in the art will understand that the present invention may also be implemented in combination with other program modules.

[0025] Generally, a program module includes routines, programs, components, data structures, and other types of structures that perform a specific task or implement a specific abstract data type. Furthermore, those skilled in the art will understand that the present invention can also be implemented in other computer system configurations, including portable devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The present invention may also be implemented in a distributed computing environment in which tasks are performed by remote processing units connected via a communication network. In a distributed computing environment, program modules may be located in both local memory and remote storage devices.

[0026] Figure 1 shows an exemplary computer architecture of a computer 100 that implements various embodiments of the present invention. The computer architecture shown in Figure 1 represents a typical personal computer having a central processing unit (CPU) 150, a system memory 105 having random access memory (RAM) 110 and read-only memory (ROM) 115, and a system bus 135 connecting the system memory 105 to the CPU 150. A basic input / output system, including basic routines that help transfer information between elements within the computer, such as during startup, is stored in the ROM 115. The computer 100 further includes an operating system 125, applications / programs 130, and a storage device 120 for storing data.

[0027] The storage device 120 is connected to the CPU 150 via a storage controller (not shown) connected to the bus 135. The storage device 120 and its associated computer-readable media provide non-volatile storage area to the computer 100. Although the description of computer-readable media in this specification refers to storage devices such as hard disks or CD-ROM drives, those skilled in the art should understand that computer-readable media refers to any available media accessible by the computer 100.

[0028] As an example, computer-readable media may include, but are not limited to, computer storage media. Computer storage media include volatile and non-volatile media, as well as removable and non-removable media, implemented by any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EPROM, EEPROM, flash memory, other solid-state memory technologies, CD-ROM, DVD, other optical discs, magnetic cassettes, magnetic tapes, magnetic disk storage devices, other magnetic storage devices, or other media that can be used to store desired information and are accessible by a computer.

[0029] According to various embodiments of the present invention, computer 100 may operate in a network environment that uses a logical connection to a remote computer via a network 140, such as a TCP / IP network like the Internet or an intranet. Computer 100 may connect to network 140 via a network interface unit 145 connected to bus 135. Note that the network interface unit 145 can also be used for connections to other types of networks and remote computer systems.

[0030] Computer 100 may have an input / output controller 155 that receives and processes input from a plurality of input / output devices 160, including a keyboard, mouse, touchscreen, camera, microphone, controller, joystick, or other type of input device. Similarly, the input / output controller 155 may supply output to a display screen, printer, speaker, or other type of output device. Computer 100 may connect to the input / output devices 160 via wired connections, including but not limited to optical fiber, Ethernet®, or copper wire, or wireless means, including but not limited to Wi-Fi®, Bluetooth®, Near Field Communication (NFC), infrared, or other suitable wired or wireless connections.

[0031] As described above, the computer 100 may store multiple program modules and data files, including an operating system 125 suitable for controlling the operation of a networked computer, in the storage device 120 and / or RAM 110. The storage device 120 and RAM 110 may also store one or more applications / programs 130. In particular, the storage device 120 and RAM 110 may store applications / programs 130 that provide various functions to the user. For example, the applications / programs 130 may include many types of programs such as word processing applications, spreadsheet applications, DPA (desktop publishing) applications, database applications, game applications, internet browsing applications, email applications, and messaging applications. According to embodiments of the present invention, the applications / programs 130 include a multifunctional software application that provides word processing functions, slide presentation functions, spreadsheet functions, database functions, etc.

[0032] In some embodiments, the computer 100 may have various sensors 165 that monitor the environment around and inside the computer 100. These sensors 165 may include a Global Positioning System (GPS) sensor, an optical sensor, a gyroscope, a magnetometer, a thermometer, a proximity sensor, an accelerometer, a microphone, a biometric sensor, a barometer, a humidity sensor, a radiation sensor, or other suitable sensors.

[0033] This disclosure relates to a complementary metal-oxide-semiconductor (CMOS) compatible Ising machine having quantized node states (or node variables) and current-based internode interactions (QS-CIM). In the QS-CIM, the spin of the node variables (node ​​outputs) is represented as the polarity of a capacitor voltage, and the coupling between nodes is realized through an array of programmable current sources whose outputs are controlled by the corresponding spin values.

[0034] In one embodiment of the present invention, the QS-CIM comprises N nodes (an example of nodes shown in Figure 2) and an array of (N-1) × (N-1) coupling units, each coupling unit having a programmable current source having programmable current magnitude and polarity controlled by the output from the corresponding node, and N current programming units, each current programming unit having a digital-to-analog converter (DAC) that converts a digital representation of the coupling coefficient into an analog value supplied to the current source for programming. Each of the N nodes has a voltage that is a binary value (e.g., 0V or V dd ) has a capacitor that is quantized to form the output of the node N. i The binary output is used to control the polarity (i.e., sign or direction) of the output current generated by the i-th row current source. For example, N i The output from the node is V dd In the case of V, the current source in the i-th row generates a positive current at its output, and the output current is negative when the node output is 0V. All currents from the current sources in the j-th column (j = 1, ..., N, j ≠ i) are summed, and the resulting total current is supplied to the capacitor at the j-th node, charging (or discharging) its voltage. The magnitude of the current for all current sources in the array is programmed by the corresponding current programming unit. An example of QS-CIM operation in this embodiment is as follows: (1) a) connect the j-th column of the coupling unit to the column of the current programming unit, and b) the magnitude of the coupling coefficient |J ij |(1≦i≦N)| is converted to an analog value and stored in the j-th column coupling unit to bias the current source, in this step the polarity bit of the coupling coefficient is also stored in the j-th column coupling unit, and c) move to the next column, repeating steps a) to c) until the last column of the array is programmed, thereby programming the coupling coefficient J ij (2) Map the current source to the capacitor voltage. ddIt is initialized randomly. (3) The internal state (i.e., the capacitor voltage) changes according to machine-dependent physical laws. (4) The change optimizes a specific formula (e.g., the "Ising model"). (5) The physical state of the machine is quantized (i.e., each capacitor voltage is compared with a threshold and quantized into a binary value) and read out to obtain the solution to the mapped problem.

[0035] Ising model The Ising model is used to describe the Hamiltonian of a spin system. The value of the spin is either +1 or -1. The energy of the system is the pairwise coupling J between the spins ij and the response h of each spin to an external magnetic field (μ) i is a function of. The resulting Hamiltonian is as follows.

Equation

[0036] When the external field is ignored, the Hamiltonian simplifies as follows.

Equation

[0037] This simplified version is even more useful for the purposes of this specification. In this specification, the "Ising model" or "Ising equation" refers to Equation (2).

[0038] A physical system with such a Hamiltonian naturally converges to a low-energy state. Therefore, if the parameters (e.g., J ij ) can be configured to match an equation equivalent to the Ising equation of the problem, the physical system can be used to solve the optimization problem using an equation equivalent to the Ising equation.

[0039] The relationship between the Ising model and the maximum cut problem Many optimization problems naturally map to Ising machines. Perhaps the simplest problem for mapping is the maximum cut problem. For a graph G=(V, E), a "cut" is a vertex, for example, V + and V - It is divided into two sets, and in this case, V - =VV + The objective is to find the cut that maximizes the sum of the edge weights connecting two sets of vertices. In other words, the maximum cut is

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[0040] The similarity between equation (2) and equation (3) is immediately obvious. In fact, the bond weight (J ij ) edge weight (-W ij When setting the value to a negative value, Ising's formula simply becomes twice the negative cut-off value multiplied by the problem-specific constant (ΣW), as follows: ij ) is added (to simplify notation, if i≧j, W ij (Set to 0).

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[0041] Therefore, if the machine finds the ground state of the Hamiltonian, it finds the maximum cut. Finding the maximum cut of any graph is an NP-hard problem. Practical algorithms only attempt to find a reasonable solution. Similarly, all existing Ising machines (including the disclosed design) are Ising "sampling" machines that typically provide reasonable samples of low-energy states but do not guarantee optimality.

[0042] Designers of Ising machines sometimes focus on the maximum cut problem for its trivial mapping to the Ising equation. However, other optimization problems can also be mapped to Ising machines.

[0043] Existing Ising machines may be classified into three categories based on the technology used in their design: quantum annealers, optical annealers, and electronic annealers.

[0044] The latest quantum Ising annealers manufactured by D-Wave can support up to 2000 qubits (see D-Wave 2000Q Quantum Computer). The qubits are coupled to form a chimera graph. As a result of local coupling, D-Wave's machines can only map up to 64 nodes in a fully coupled graph (see R. Hamerly, et al., Science advances, 2019 and R. Hamerly, et al., arXiv, 2018). Furthermore, these annealers are susceptible to noise and require a cryogenic operating environment that consumes a large amount of power (25kW for the D-Wave 2000Q) (see D-Wave 2000Q Quantum Computer).

[0045] The most widely known of the optical-based Ising machines is the coherent Ising machine (CIM) (see T. Inagaki, et al., Science, 2016; Y. Yamamoto, et al., npj Quantum Information, 2017; PL McMahon, et al, Science, 2016; K. Takata, et al., Scientific Reports, 2016 and F. Bohm, et al., Nature Communications, 2019). It uses optical parametric oscillators (OPOs) to generate and process signals representing a single spin. Unlike D-Wave, the nodes of the CIM are all coupled together. The machine has two components: optical cavities constructed using several kilometers of fiber optic cables and auxiliary computers to realize the coupling between the nodes. The amplitude and phase of each pulse in the optical cavity are detected, and the interaction with all other pulses is calculated using the auxiliary computer (FPGA). This calculation result is used to modulate new pulses injected into and returned from the optical cavity. Strictly speaking, the current implementation is a natural simulation hybrid Ising machine. Therefore, in addition to the challenges of cavity construction, CIM also requires large-scale support structures involving high-speed conversion between optical and electrical signals.

[0046] The operating principle of CIM can be viewed as the Kuramoto model (see Y. Takeda, et al., Quantum Science and Technology, 2017), and theoretically, similar objectives can be achieved using other oscillators. This led to the design of electron oscillator-based Ising machines (OIMs). These systems use the oscillation phase of an LC tank oscillator or ring oscillator to represent spin and (programmable) resistance as a coupling unit. However, the inductors of LC tank-based oscillators can present practical challenges in on-chip integration. OIM-based machines have undesirable parasites that involve area aggregation, as well as degradation of quality and increased phase noise, which poses practical challenges in maintaining frequency uniformity and phase synchronization among thousands of on-chip oscillators.

[0047] Other electronic circuit designs with resistive coupling include the bistable resistively coupled Ising machine (BRIM) (see R. Afoakwa, et al., 2021) and the quantized BRIM (QuBRIM) (Y. Zhang, et al., in 2022 IEEE / ACM International Conference On Computer Aided Design (ICCAD), 2022), which implement Ising spin as a capacitor voltage or the polarity of the capacitor voltage. Because these use voltage or its polarity (as opposed to phase) to represent spin, they allow for a direct interface with additional architectural support for computational tasks. In QuBRIM, the polarity of the voltage across the capacitor represents the spin of the node, and the coupling strength is inversely proportional to the resistance of the coupling resistor, i.e., R ij =R / |J ij| Here, R is the scaling factor, and negative coupling is achieved by cross-coupling the coupling resistance. Additional information on BRIM and QuBRIM can be found in U.S. Patent Application No. 17 / 996,283 filed on 14 October 2022 and International Application PCT / US2023 / 06056 filed on 12 January 2023, which are incorporated herein by reference in their entirety.

[0048] Furthermore, researchers have designed various chips to accelerate simulated annealing (see S. Kirkpatrick, et al., Science, 1983) or variations of classical algorithms (see M. Yamaoka, et al., in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015; and T. Takemoto, et al., in IEEE International Solid-State Circuits Conference, 2019). In these designs, spin is virtual in that it is both a bit in memory and manipulated by the algorithm (simulated annealing). These machines are specifically built to accelerate that algorithm. Therefore, such machines are called "accelerated simulated annealers (ASAs)." Such machines differ fundamentally from ordinary Ising machines in that they follow a specific algorithm, whereas ordinary Ising machines are guided by the laws of physics themselves.

[0049] The connections between nodes are crucial for building robust Ising machines because the problems to be solved are directly embedded within them. While spin takes only two discrete values, the physical quantities representing spin can fluctuate significantly, which can lead to numerous problems. For example, in resistively coupled Ising machines (see R. Afoakwa, et al., 2021 and S. Dutta, et al., Nature Electronics, 2021), this can cause large fluctuations in coupling resistance, making it highly likely that the machine is solving different problems over time. Furthermore, trade-offs between component size, power consumption, and precise functionality limit scalability (see A. Sharma, et al., in Proceedings of the 49th Annual International Symposium on Computer Architecture, ser. ISCA, 2022). To address these challenges, we hereby disclose a CMOS-based Ising machine, QS-CIM, which utilizes current-mode coupling between interacting nodes, enabling improved linearity and accuracy of coupling, as well as reduced sensitivity to PVT and mismatch, in conjunction with binary outputs (i.e., binary value outputs) from interacting nodes connected to the input of the coupling unit.

[0050] This specification provides a theoretical analysis supporting the optimization capabilities of QS-CIM, followed by a discussion of high-level design of QS-CIM systems and disclosure of circuit-level implementation examples. The dynamics of QS-CIM can be described by the changes in each node voltage caused by other nodes connected to each node. Without loss of generality, the following description deals with the dynamics of only one node for the sake of simplicity in the analysis, but it does not apply to the entire system.

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[0051] The dynamics of node i are:

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[0052] From the above set of differential equations describing QS-CIM as a dynamic system, it can be shown that there exists a Lyapunov function of the following form.

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[0053] To demonstrate QS-CIM's optimal solution search capability, the Lyapunov stability analysis is shown below, which is as follows:

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[0054] After finding the time derivative of Equation 7 and applying the chain rule, the following result is obtained.

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[0055] System-level design and circuit implementation The following describes the design of QS-CIM at the system level. An example of a 3-node QS-CIM system is shown in Figure 2, which can be viewed as a group of components as follows.

[0056] First, the node (201) on the left side of Figure 2 is referred to as N in this specification. i This is referred to as [the state of each node 201].

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[0057] Each node sets the capacitor voltage to a threshold (e.g., V CM ) is compared to and depending on the result of the comparison, high (for example, V dd The node may have a comparator that supplies a voltage output of 0V or low (e.g., 0V). The node's comparator performs the quantization operations described above.

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[0058] Next, the coupling unit 203 shown as part of the coupling array 202 in Figure 2 has two types of coupling units. As shown in Figure 4, the diagonal coupling unit (i.e., i=j) is a passive unit that provides connections between rows and columns of the array, outputs from the nodes, control signals, and programming units PU. i Bias voltage from (e.g., V bpi and V bni ) and control signals from the column selector 204 are transmitted to the adjacent coupling unit. As shown in Figure 4, diagonal CUs transmit the following signals: (1) Node N i Two outputs N from the i-th row to the off-diagonal CU i_out and

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[0059] Unlike diagonal CUs, off-diagonal CUs are active (i.e., they have a power source such as a current source), and an example of a circuit diagram for an off-diagonal CU is shown in Figure 5. The off-diagonal CU in this embodiment of the present invention has 20 transistors. Transistors M1 and M2 function as a current source and a current sink, respectively. The gate-source bias of M1 and M2 is such that the gates of M1 and M2 are biased by a bias voltage V bpi and V bniDuring the programming phase, the bias voltage is supplied by asserting access switches M7 and M8, which are connected to the CU, in which case the bias voltage is generated by the programming unit at the end of the i-th row. Note that during normal operation of the device (i.e., when the internal state of the device is allowed to change), the two access switches M7 and M8 are disabled and the gate capacitances of M1 and M2 hold the programmed bias voltage. Additional capacitors may be provided at the gate terminals of M1 and M2 to offset the loss of gate bias due to gate leakage current. Transistors M5 and M6 function as output switches connecting either the current source M1 or the current sink M2 to the output of the coupling unit. The selection between the current source and the current sink is determined by a coupling polarity bit (S) stored in the CU during the programming phase. ij ) and node (N i_out It depends on the output of ) and . For example, if the coupling polarity of CU at position (i,j) is positive (e.g., S ij =V dd or logical 1) and node N i The output from is negative (for example, N i_out When the signal is 0V (or logic 0), the gate control signal G is positive (or logic 1), which activates the output switch M6 that connects the current sink M2 to output Out, resulting in a negative current (i.e., current flowing into CU). Transistors M9-M12 have a control signal with polarity bit S ij It functions as a 2-to-1 multiplexer, which is its complement. The input to the multiplexer is node N. i Two outputs from (i.e., N) i_out The multiplexer generates gate control signals G that control the gates of output switches M5 and M6. Transistors M13 and M14 drive the gates of switches M3 and M4 with signals that are the complement of G.

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[0060] In various embodiments, some or all of the current sources or current sinks of the coupling units disclosed herein may be programmable. In some embodiments, some or all of the programmable current sources or programmable current sinks are implemented as metal-oxide-semiconductor transistors. In some embodiments, some or all of the programmable current sources or programmable current sinks are implemented as volatile or non-volatile memory devices such as flash memory transistors or charge trap transistors.

[0061] The off-diagonal CU also has memory elements in the form of latches (transistors M15-M18) and their access switches M19 and M20. The latch of each off-diagonal CU is programmed with bit P i and its complement

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[0062] Finally, Programming Unit 205 (PU) i The right side of the diagram in Figure 2 is shown. An example of a programming unit is shown in Figure 6. The programming unit of this embodiment sets a programming current I to reference devices (or so-called diode-connected devices) M1 and M2 that establish a bias voltage to the gate. prog By supplying a bias voltage V bpi and V bni Generates the control signal C during programming of the j-th column. j and

number

Number

[0063] FIG. 7 shows a diagram illustrating a connection example between the coupling unit shown in FIG. 5 and the programming unit shown in FIG. D.

[0064] The disclosures of all patents, patent applications, and publications cited in this specification are hereby incorporated by reference in their entirety. Although the invention has been disclosed with reference to specific embodiments, it is clear that those skilled in the art can conceive of other embodiments and modifications of the invention without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent modifications.

[0065] References The following references are incorporated herein by reference in their entirety.

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[0075] R. Hamerly, T. Inagaki, P. L. McMahon, D. Venturelli, A. Marandi, T. Onodera, E. Ng, C. Langrock, K. Inaba, T. Honjo et al., “Experimental investigation of performance differences between coherent ising machines and a quantum annealer,” Science advances, vol. 5, no. 5, p. eaau0823, 2019

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[0080] K. Takata, A. Marandi, R. Hamerly, Y. Haribara, D. Maruo, S. Tamate, H. Sakaguchi, S. Utsunomiya, and Y. Yamamoto, “A 16-bit coherent ising machine for one-dimensional ring and cubic graph problems,” Scientific Reports, vol. 6, no. 1, p. 34089, 2016

[0081] F. Bohm, G. Verschaffelt, and G. Van der Sande, “A poor man’s coherent ising machine based on opto-electronic feedback systems for solving optimization problems,” Nature Communications, vol. 10, no. 1, p. 3538, 2019. [Online]. Available: https: / / doi.org / 10.1038 / s41467-019-11484-3

[0082] Y. Takeda, S. Tamate, Y. Yamamoto, H. Takesue, T. Inagaki, and S. Utsunomiya, “Boltzmann sampling for an XY model using a non-degenerate optical parametric oscillator network,” Quantum Science and Technology, vol. 3, no. 1, p. 014004, nov 2017

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Claims

1. A network comprising multiple coupled computing nodes and multiple active coupling units, wherein each computing node is An input unit configured to receive current from a subset of multiple coupling units within the aforementioned network, An output section configured to generate at least two discrete output voltages, A capacitor configured to store its internal state as a voltage, A quantizer electrically connected to the capacitor and configured to quantize the voltage of the capacitor to at least one of two discrete values, having an output unit connected to the output unit of the arithmetic node, Each active coupling unit is equipped with, An input unit that receives an output voltage from one of the multiple calculation nodes, An output unit connected to the input unit of one of the multiple calculation nodes, A programmable current source, A programmable current sink, A control circuit configured to connect either the current source or the current sink to the output of the active coupling unit in accordance with the voltage measured at the input of the active coupling unit, A network equipped with these features.

2. The network according to claim 1, wherein the quantizer of each computing node is a comparator configured to compare the voltage across the capacitor with a threshold and generate two discrete voltages at the output of the computing node according to the comparison result.

3. The network according to claim 1 or 2, wherein each of the quantizers is clocked by the same or substantially the same clock and configured to generate an output on the same or substantially the same clock edge.

4. The network according to any one of claims 1 to 3, wherein the current from the current source or current sink of the active coupling unit is connected to a constant voltage source when it is not connected to the output of the active coupling unit.

5. The network according to any one of claims 1 to 4, wherein each active coupling unit further comprises a one-bit storage device having a stored value, the stored value being used to adjust the input to the active coupling unit.

6. The network according to claim 5, wherein the stored value is the complement of the input to the active coupling unit.

7. The network according to any one of claims 1 to 6, wherein at least one of the programmable current sources and programmable current sinks among the active coupling units is implemented as a metal-oxide-semiconductor transistor.

8. The network according to any one of claims 1 to 7, wherein at least one of the programmable current sources and programmable current sinks among the active coupling units is implemented as a non-volatile memory device selected from flash memory transistors or charge trap transistors.

9. The network according to any one of claims 1 to 8, further comprising at least one programming unit configured to program the programmable current source and the programmable current sink.

10. The aforementioned programming unit is At least one binary polarity output unit configured to supply polarity values ​​to at least one of the active coupling units of the network, At least one magnitude output unit configured to supply magnitude voltage to bias one or both of the current source and current sink of at least one of the active coupling units of the network, A polarity memory element connected to the at least one binary polarity output unit, configured to store the polarity value and supply it to the at least one binary polarity output unit, An array of memory elements configured to store the magnitude of the voltage as a set of binary values, A digital-to-analog converter connected to the array of memory elements and configured to generate the magnitude of the voltage from the set of binary values, A current mirror element connected to the digital-to-analog converter and the magnitude output unit, configured to mirror the current output from the digital-to-analog converter to the magnitude output unit, The network according to claim 9, comprising:

11. The network according to claim 10, further comprising an inverted binary polarity output unit connected to the inverted output unit of the polarity memory element and configured to output a binary value having the opposite polarity to that of the at least one binary polarity output unit.

12. The network according to any one of claims 1 to 11, further comprising a current conveyor having an input section connected to the input section of the calculation node and an output section connected to the capacitor, wherein the current conveyor is configured to maintain its input section at a constant voltage and to mirror a current proportional to the current received at the input section to the capacitor.

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