Enabling microbump architecture without the use of sacrificial pads for wafer probing.
A method for reforming microbumps on wafers without sacrificial pads addresses probing challenges, preserving silicon area and reducing electromigration risk, enabling efficient integration of microbumps in dies.
Patent Information
- Application Number
- JP2026500698
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-08-23
- Filing Date
- 2024-07-25
- Publication Date
- 2026-08-26
AI Technical Summary
Current probing techniques for microbumps on wafers are not mature enough and can damage the delicate microbumps, and the use of sacrificial pads consumes significant die area and requires keep-out zones, leading to wasted silicon space.
A method that forms first and second set of bumps with smaller diameters, probes the wafer using these bumps, and then reforms them into microbumps without using sacrificial pads, maintaining a large contact surface with the contact pad to mitigate electromigration-induced damage.
Enables effective probing of microbumps without sacrificial pads, preserving silicon area for functional use and reducing electromigration risk, allowing for efficient integration of microbumps in dies without redesigning existing silicon IP.
Smart Images
Figure 2026528878000001_ABST
Abstract
Description
Background Art
[0001]
[0001] Increasingly, computing and communication systems include dies interconnected via an interposer. As an example, chiplets or dies can be stacked side by side on a passive interposer or an active interposer. Alternatively, one or more memory dies can be stacked on a logic die. Multiple logic dies can also be stacked on top of each other. In other arrangements, a mixture of logic dies and memory dies is used, and they can use an interposer.
[0002]
[0002] In many such arrangements, there is a need for a high-bandwidth connection between the logic die and the memory die. Bumps having smaller critical dimensions (e.g., microbumps) are used to attach the chiplet or die to the interposer. During the manufacture of such a system, the microbumps formed on the wafer require probing. Current probing techniques for testing known good dies (KGD) are not sufficiently mature to probe the microbumps. This is because they are small and delicate, and thus probing can damage them. In addition, more dense microbumps are more difficult to probe using conventional probes used to probe larger bumps such as C4 bumps.
[0003]
[0003] To address these challenges, a common solution has been the use of sacrificial (SAC) pads. SAC pads are formed together with microbumps, and probing is performed by using the SAC pads instead of the microbumps. SAC pads are used solely for probing purposes and therefore do not provide any other device functionality. SAC pads consume a significant amount of area on the die. In addition, there may be a large amount of keepout area surrounding each SAC pad to allow for easy access by using a probe. This results in potentially wasted silicon area on the die.
[0004]
[0004] Therefore, there is a need for improved methods and systems to enable a microbump architecture that does not require the presence of SAC pads. [Overview of the project] [Means for solving the problem]
[0005]
[0005] In one example, the present disclosure relates to a method comprising: (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on a wafer substrate, each of which is formed according to a defined second diameter smaller than the defined first diameter. The method may further include probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0006]
[0006] The method may further include removing material associated with both the first bump and the first set of bumps in order to enable the reformation of the first bump and the first set of bumps. The method may further include: (1) forming a second set of bumps in place of the first bump, wherein each of the second set of bumps is formed according to a specified second diameter, and (2) forming a third set of bumps in place of the first set of bumps, wherein each of the third set of bumps is formed according to a specified second diameter.
[0007]
[0007] In another example, the present disclosure relates to a method comprising (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on a wafer substrate, each of which is formed according to a defined second diameter smaller than the defined first diameter. The method may further comprise probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0008]
[0008] The method may further include forming a protective layer on the first bump and the first set of bumps. The method may further include removing the protective layer and the material associated with both the first bump and the first set of bumps in order to allow the reformation of bumps in place of the first bump and the first set of bumps. The method may further include: (1) forming a second set of bumps in place of the first bump, each of which is formed according to a specified second diameter, and (2) forming a third set of bumps in place of the first set of bumps, each of which is formed according to a specified second diameter.
[0009]
[0009] In yet another example, the present disclosure relates to a method comprising (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on the wafer substrate, each of the first set of bumps according to a defined second diameter smaller than the defined first diameter. The method may further comprise probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0010]
[0010] The method may further include forming a protective layer on the first bump and the first set of bumps. The method may further include removing the protective layer and the material associated with both the first bump and the first set of bumps in order to allow the reformation of bumps in place of the first bump and the first set of bumps. The method may further include forming (1) a second set of bumps in place of the first bump, each of the second set of bumps being formed according to a defined second diameter and a defined first height, and each of the second set of bumps relating to a first active circuit configuration formed as part of the wafer, and (2) a third set of bumps in place of the first set of bumps, each of the third set of bumps being formed according to a defined second diameter and a defined first height, and each of the second set of bumps relating to a second active circuit configuration (different from the first active circuit configuration) formed as part of the wafer.
[0011]
[0011] This “Outline of the Invention” is provided in a simplified form to introduce selected concepts from those further described in the following “Modes for Carrying Out the Invention.” This “Outline of the Invention” is not intended to identify any important or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
[0012] Brief explanation of the drawing
[0012] This disclosure is provided as an example and is therefore not limited by the accompanying drawings, where similar reference numerals indicate similar elements. Elements in the accompanying drawings are shown for brevity and clarity and are therefore not necessarily drawn to actual size. [Brief explanation of the drawing]
[0013] [Figure 1]
[0013] An example of a wafer during the manufacturing process is shown. [Figure 2]
[0014] An example diagram of a wafer during the manufacturing process is shown. [Figure 3]
[0015] An example shows the layout of bumps on a wafer for probing. [Figure 4]
[0016] An example diagram of a wafer during the manufacturing process is shown. [Figure 5]
[0017] An example diagram of a wafer during the manufacturing process is shown. [Figure 6]
[0018] An example diagram of a wafer during the manufacturing process is shown. [Figure 7]
[0019] This shows a bottom view of an exemplary die formed after a wafer has been separated into multiple dies. [Figure 8]
[0020] A flowchart illustrating a method for probing bumps and nets formed within a wafer, according to one example, is shown. [Modes for carrying out the invention]
[0014] Detailed explanation
[0021] The examples described in this disclosure relate to a method for enabling a microbump architecture that does not use sacrificial pads for wafer probing. As previously described, many computing systems require high-bandwidth connectivity between logic dies and memory dies. Bumps with smaller critical dimensions (e.g., microbumps) are used to mount chiplets or dies to an interposer.
[0015]
[0022] Current probing techniques for testing known good dies (KGDs) are not mature enough to probe wafers with microbumps. This is because microbumps are small (e.g., less than 30 micrometers in diameter) and delicate, and therefore probing can damage them. In addition, higher density microbumps are more difficult to probe using conventional probes used to probe larger bumps such as C4 bumps. Furthermore, because microbumps have smaller critical dimensions, they have a small amount of solder as part of the solder cap. If the solder is damaged during probing, bonding with damaged microbumps becomes unreliable. For example, microbumps with damage to the solder are more likely to have electrical issues, such as open circuits.
[0016]
[0023] To address these challenges, a common solution was the use of sacrificial (SAC) pads. SAC pads are formed with microbumps, and probing is performed by using the SAC pads instead of the microbumps. As mentioned above, SAC pads are used solely for probing purposes and therefore do not provide any other device functionality. SAC pads consume a significant amount of area on the die. In addition, a large keep-out area may exist surrounding each SAC pad to allow for easy access by using a probe. Advantageously, as part of the process described herein, no sacrificial pads are formed for probe testing.
[0017]
[0024] Figure 1 shows a view 100 of a wafer 10 during the manufacturing process according to an example. The wafer 10 includes a silicon substrate 110. During this manufacturing process, as shown in view 100, the wafer 10 further includes inert layer portions 112, 114, 116, 118, and 122 formed on the silicon substrate 110. The inert layer portions 112, 114, 116, 118, and 122 are the remaining portions of an inert layer formed on the entire surface of the wafer to protect the entire surface of the wafer. In one example, the inert layer can be composed of silicon nitride or silicon oxide.
[0018]
[0025] Continuing to refer to FIG. 1, view 100 of the wafer 10 further shows contact pads 130, 132, 134, and 136 formed on the silicon substrate 110. The contact pads 130, 132, 134, and 136 are related to sites where an interconnect structure such as a bump can be formed. FIG. 1 shows the wafer 10 having a certain number of layers and components arranged in a certain way, but there can be more or fewer layers or components that may be arranged differently.
[0019]
[0026] FIG. 2 shows a view 200 of the wafer 10 during the manufacturing process according to an example. Unless otherwise indicated, the same or similar layers and components shown in FIG. 2 are referred to by using the same reference numbers as those used in the previous figure (e.g., FIG. 1). As part of view 200, bumps 210, 220, 230, and 240 are shown as part of the wafer 10. Each bump includes a metal layer (e.g., a plated copper layer) formed on the wafer 10. As an example, bump 210 includes metal layer 212, bump 220 includes metal layer 222, bump 230 includes metal layer 232, and bump 240 includes metal layer 242. In this example, each of these metal layers is formed by plating copper. Additionally, FIG. 200 shows solder caps formed for each bump. As an example, solder cap 214 is shown as part of bump 210, solder cap 224 is shown as part of bump 220, solder cap 234 is shown as part of bump 230, and solder cap 244 is shown as part of bump 240.
[0020]
[0027] Continuing to refer to FIG. 2, in one example, bumps 210, 220, 230, and 240 are formed by using several processes. In this example, the first process includes barrier / seed sputtering on wafer 10. The formation of the barrier prevents any metal migration into the silicon area of the wafer. Materials such as tantalum, tantalum nitride, titanium, or titanium nitride can be used to form the barrier layer. Next, assuming that the microbumps are constructed by using copper, the copper seed layer is formed by using physical vapor deposition or chemical vapor deposition. In another example, the combination of the barrier / seed material can correspond to under-bump metallurgy (UBM).
[0021]
[0028] As part of the next process, a photosensitive material (e.g., photoresist) is applied on the sputtered UBM. The next process includes lithography for patterning the area on wafer 10 corresponding to the bumps for further processing. The next process includes plating a metal such as copper. The plating can be performed by using an electroplating process. This process results in the formation of metal layers 212, 222, 232, and 242 shown in FIG. 2. The next process includes the removal of the photoresist.
[0022]
[0029] The next step involves etching the barrier / seed material from wafer 10. Finally, the solder material is reflowed to form caps (e.g., solder caps 214, 224, 234, and 244). Microbumps 220, 230, and 240 may have a diameter of 30 micrometers or less and a pitch of 55 micrometers or less. Figure 2 shows wafer 10 with a certain number of layers and components arranged in a certain way, but there may be more or fewer layers or components that are arranged in a different way. As an example, solder caps 214, 224, 234, and 244 are shown as part of the bumps, but these solder caps may not be required. As an example, in a manufacturing process where the metal layer for the bumps is formed by using gold (Au), the solder caps may be omitted as part of the process. As another example, even if the metal layer is formed by using copper, the solder caps may be omitted at this stage. This is because in some cases probing may be performed without the need for solder caps. In addition, instead of bump 210 being a C4 bump, bump 210 could be formed as a different type of contact for probing.
[0023]
[0030] Figure 3 shows an example layout 300 of bumps on a wafer for probing. Layout 300 is merely an example, and therefore, bumps for probing can be laid out in different ways. Layout 300 shows four bumps 310, 320, 330, and 340. Bump 310 corresponds to a bump similar to bump 210 previously described with respect to Figure 2. Bumps 320, 330, and 340 correspond to microbumps similar to bumps 220, 230, and 240 previously described with respect to Figure 2. Thus, in this example, bump 310 is formed based on a specified diameter (DI), and each of bumps 320, 330, and 340 is formed based on a different specified diameter (D2) such that the diameter DI is greater than the diameter D2. Bump 310 is coupled to bump 320 via trace 312. Bump 310 is coupled to bump 330 via trace 314. Bump 310 is coupled to bump 340 via trace 316. Layout 300 in Figure 3 shows direct coupling between bump 310 and bumps 320, 330, and 340, although these may be indirectly coupled via other structures or metal layers. In addition, layout 300 shows NET 1 322 coupled to bump 320 via trace 324. NET 2 332 is coupled to bump 330 via trace 334. NET 3 342 is coupled to bump 340 via trace 344. A net being tested via bumps consists of one or more bumps and the interconnecting wiring between them. A net, which is a pairing between one or more connections or bumps, can be probed by using the same probe bump (e.g., bump 310). In short, a net represents a portion of the wafer being tested.
[0024]
[0031] The routing of bumps to the microbumps or other types of bumps being probed does not have to be simple and linear, as shown in Figure 3. Instead, the bump 310 in contact with the probe may have routed connections to other microbumps contained within various nets. Probes associated with integrated circuit probers (IC probers) may be used to make contact with bumps 310 to test any of the nets shown in layout 300. The IC probers may further be coupled to IC testers, which enable the performance of various types of tests for testing the nets shown in layout 300.
[0025]
[0032] The tests may relate to wafer / device testing, including testing to determine whether the die is a good die in terms of the absence of any open or short circuits along the various nets being tested. As an example, automated test equipment (ATE) may be connected to an IC prober which may have probes that are in direct contact with bumps for testing. The probes may provide voltage for testing to the bumps to test for any defects in the wafer. Advantageously, no sacrificial pads are formed for the probe testing. Instead, after the probe testing is complete, additional steps are taken to remove the material associated with probes 310, 320, 330, and 340 and to form new bumps (e.g., microbumps), as will be described later with respect to Figure 4-6.
[0026]
[0033] Figure 4 shows a wafer 10 during an example manufacturing stage. Unless otherwise indicated, the same or similar layers and components shown in Figure 4 are referred to by the same reference numbers used in previous figures (e.g., Figures 1 and 2). During this manufacturing stage, the wafer 10 is covered by using a protective layer 410 to protect the wafer 10. The protective layer 410 may be a polyimide film or a polybenzoxazole (PBO) layer. The protective layer 410 provides protection to components and layers that will be formed as part of the wafer 10 during subsequent processes, including the removal of certain materials. Figure 4 shows a wafer 10 with a certain number of layers and components arranged in a certain manner, but there may be more or fewer layers or components that are arranged in different ways.
[0027]
[0034] Figure 5 shows a diagram of a wafer during the manufacturing stage as an example. Unless otherwise indicated, the same or similar layers and components shown in Figure 5 are referred to by the same reference numbers used in previous figures (e.g., Figures 1, 2, and 4). During this manufacturing stage, the protective layer 410, solder caps 214, 224, 234, and 244, and the material corresponding to parts of the metal layers 212, 222, 232, and 234 are removed. Material removal can be achieved by grinding the surface. Alternatively, the protective layer 410, solder caps 214, 224, 234, and 244, and the material corresponding to parts of the metal layers 212, 222, 232, and 234 can be removed by cutting or sawing. The remaining surface can be smoothed using chemical mechanical polishing.
[0028]
[0035] As shown in Figure 5, the wafer 10 now has a portion of the protective layer 410 remaining, including portions 522, 524, 526, 528, and 530. In addition, at this fabrication stage, Figure 500 shows metal layer portions 512, 514, 516, and 518. These metal layer portions correspond to the locations of bumps formed prior to circuit probing within the wafer 10. Figure 5 shows a wafer 10 with a certain number of layers and components arranged in a certain way, but there may be more or fewer layers or components that are arranged in a different way.
[0029]
[0036] Figure 6 shows a diagram of a wafer during the manufacturing process as an example. Unless otherwise indicated, the same or similar layers and components shown in Figure 5 are referred to by using the same reference numbers as used in the previous figures (e.g., Figures 1, 2, 4, and 5). In Figure 600, bumps 610, 620, 630, 640, 650, and 660 are shown as part of wafer 10. Each of these bumps is formed based on the same specified diameter and specified height. As an example, each of these bumps is a microbump. Bumps 610, 620, and 630 are formed in place of bump 210 in Figure 2. Microbumps with a smaller surface area in contact with the contact pad can cause more problems related to electromigration-induced damage at the boundary between the contact pad and the copper metal layer. Advantageously, forming multiple microbumps in place of a larger bump (e.g., bump 210 in Figure 2) allows for maintaining the same size pad (e.g., contact pad 130) as the previous size. Therefore, both Figure 2 and Figure 6 show the contact pad 130 having a large surface area. This is because multiple microbumps (e.g., bumps 610, 620, and 630) are formed on the shared contact pad 130, thereby creating a surface area between the metal (e.g., copper) associated with these microbumps and the contact pad 130 that remains almost the same size as the surface area between the larger bump (e.g., bump 210) and the contact pad 130.
[0030]
[0037] Having this larger surface area of the contact pad allows for the reuse of existing silicon IP that can be designed to work with conductor pads having an area commensurate with the size of larger bumps (e.g., C4 bumps). In other words, silicon IP designed to work with larger bumps does not need to be redesigned to have smaller contact pads that can work with microbumps, thus saving the cost of redesigning such silicon IP. Furthermore, having this larger surface area helps to mitigate electromigration-induced damage at the boundary between the contact pad 130 and the bump 210. Bumps 640, 650, and 660 are formed in place of bumps 220, 230, and 240 in Figure 2.
[0031]
[0038] Each bump includes a metal layer (e.g., a plated copper layer) formed on the wafer 10. For example, bump 610 includes a metal layer 612, bump 620 includes a metal layer 622, bump 630 includes a metal layer 632, bump 640 includes a metal layer 642, bump 650 includes a metal layer 652, and bump 660 includes a metal layer 662. In this example, these metal layers are formed by plating copper. In addition, Figure 600 shows solder caps formed on each bump. For example, solder cap 614 is shown as part of bump 610, solder cap 624 as part of bump 620, solder cap 634 as part of bump 630, solder cap 644 as part of bump 640, solder cap 654 as part of bump 650, and solder cap 664 as part of bump 660.
[0032]
[0039] Continuing to refer to Figure 6, in one example, bumps 610, 620, 630, 640, 650, and 660 are formed by using several steps. In this example, the first step involves barrier / seed sputtering on wafer 10. The formation of the barrier prevents any metal migration into the silicon area of the wafer. Materials such as tantalum, tantalum nitride, titanium, or titanium nitride may be used to form the barrier layer. Next, assuming that the microbumps are constructed using copper, the copper seed layer is formed by using physical vapor deposition or chemical vapor deposition. In another example, the combination of barrier / seed materials may correspond to an under-bump metallurgy (UBM). As part of the next step, a photosensitive material (e.g., photoresist) is applied on top of the sputtered UBM. The next step involves lithography to pattern the areas on wafer 10 corresponding to the bumps for further processing. The next step involves plating a metal such as copper. Plating may be performed by using electroplating. This process forms the metal layers 612, 622, 632, 642, 652, and 662 shown in Figure 6. The next step involves removing the photoresist.
[0033]
[0040] The next step involves etching the barrier / seed material from wafer 10. Finally, the solder material is reflowed to form caps (e.g., solder caps 614, 624, 634, 644, 654, and 664). Microbumps 610, 620, 630, 640, 650, and 660 may have a diameter of 30 micrometers or less and a pitch of 55 micrometers or less. Figure 6 shows wafer 10 with a certain number of layers and components arranged in a certain way, but there may be more or fewer layers or components that are arranged in a different way. Similarly, bumps 610, 620, 630, 640, 650, and 660 do not need to be formed as microbumps. Instead, they may be other types of interconnect structures such as hybrid bonds. As another example, solder caps 614, 624, 634, 644, 654, and 664 are shown as part of bumps, but these solder caps may not be necessary. For example, in a manufacturing process where the metal layer for the bump is formed using gold (Au), the solder cap may be omitted as part of the process.
[0034]
[0041] Figure 7 is a bottom view of an exemplary die 700 formed after a wafer (e.g., wafer 10) has been separated into multiple dies. Thus, die 700 is one of several dies that may be obtained after wafer 10 has been fully processed and tested. Die 700 includes a core region (the region inside the inner rectangle) and a peripheral region (the region outside the core region). Each region contains several arrays of microbumps. As described above, the processes described with respect to Figures 1, 2 and 4-6 do not require the formation of sacrificial pads for probing the wafer. Thus, in the absence of the methodology described above for probing the wafer, die 700 may contain several sacrificial pads. The presence of such sacrificial pads would prevent the formation of microbumps not only within the area where these sacrificial pads are located, but also in the keep-out region beyond the sacrificial pads. This would prevent the utilization of silicon area consumed by the sacrificial pads and associated keep-out regions. Examples of such potentially wasted silicon area that would have been occupied by the sacrificial pads are identified through the dotted rectangles 710, 720 and 730. Since sacrificial pads would likely have needed to be placed elsewhere as well, these dotted rectangles represent just a few specific examples of potential wasted silicon area.
[0035]
[0042] In addition, many dies have metal-insulator-metal (MiM) capacitors for use with those areas of the die that contain high-performance mixed-signal and / or high-frequency circuits. Having MiM capacitors allows chip designers to include capacitors with a high-quality coefficient (Q) and low area consumption. Despite these advantages, MiM capacitors cannot be formed within areas of the die that contain microbumps or sacrificial pads. Advantageously, the absence of any sacrificial pads solely for probing as part of die 700 allows for better placement and use of MiM capacitors for dies containing high-performance mixed-signal and / or high-frequency circuits. Figure 7 shows die 700 with a certain arrangement of microbumps, although there may be more or fewer microbumps, which may be arranged in different ways.
[0036]
[0043] Figure 8 shows a flowchart 800 of a method for probing bumps and nets formed in a wafer 10 according to one example. Step 810 includes: (1) forming a first bump on the wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on the wafer substrate, each of the first set of bumps according to a defined second diameter smaller than the defined first diameter. In one example, the process steps previously described with respect to Figures 1 and 2 may be used to perform this step. Thus, as part of this step, the first bump may correspond to bump 210 in Figure 2, and the first set of bumps may correspond to bumps 220, 230 and 240 in Figure 2. As previously described, bump 210 has a larger diameter compared to the diameters of bumps 220, 230 and 240, which may be formed as microbumps.
[0037]
[0044] Step 820 includes probing a portion of the wafer associated with one or more of the first set of bumps by using the first bump. In one example, the methodology previously described with respect to Figures 2 and 3 may be used to perform this step. Thus, as previously described, a net associated with a microbump may be probed by using bump 210 in Figure 2.
[0038]
[0045] Continuing to refer to Figure 8, step 830 includes removing material associated with both the first bump and the first set of bumps to allow for the reshaping of replacement bumps for the first bump and the first set of bumps. In one example, as previously described with respect to Figures 4 and 5, material corresponding to the protective layer 410 in Figure 4, the solder caps 214, 224, 234 and 244 in Figure 2, and parts of the metal layers 212, 222, 232 and 234 in Figure 2 is removed. This allows for the reshaping of new bumps (e.g., microbumps) to replace bump 210 in Figure 2 and bumps 220, 230 and 240 in Figure 2.
[0039]
[0046] Step 840 includes: (1) forming a second set of bumps in place of the first set of bumps, each of which is formed according to a specified second diameter; and (2) forming a third set of bumps in place of the first set of bumps, each of which is formed according to a specified second diameter. In one example, the process steps previously described with respect to Figure 6 may be used to perform this step. Thus, as part of this step, the second set of bumps may correspond to bumps 610, 620 and 630 in Figure 6, and the third set of bumps may correspond to bumps 640, 650 and 660 in Figure 6. As previously described, each of these bumps may be formed as a microbump.
[0040]
[0047] After these processes are completed, the wafer 10 can be diced into separate dies or chiplets. Each die may contain both logic and memory. The processing logic may contain one or more cores or other types of processing logic. The memory may contain a memory array or several banks of a memory array. The memory array may be implemented as a static random access memory (SRAM) array. In addition, each SRAM may be implemented as a 2-port SRAM enabling simultaneous read / write operations via a buffer. Other memory technologies may also be used. The die or chiplet may contain a central processing unit (CPU), application-specific integrated circuit (ASIC), graphics processing unit (GPU), field-programmable gate array (FPGA), microcontroller, I / O circuitry, Ethernet PHY, or other silicon IP. By using the microbumps formed as part of the processing of the wafer 10, the separated dies can be combined with multiple dies in various systems. In short, the die or chiplet formed from the wafer 10 can be carried out in relation to various types of stacking arrangements, including face-to-face (F2F) stacking, face-to-back (F2B) stacking, or back-to-back (B2B) stacking.
[0041]
[0048] In conclusion, the present disclosure relates to a method comprising (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on a wafer substrate, each of which is formed according to a defined second diameter smaller than the defined first diameter. The method may further comprise probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0042]
[0049] The method may further include removing material associated with both the first bump and the first set of bumps in order to enable the reformation of replacement bumps for the first bump and the first set of bumps. The method may further include: (1) forming a second set of bumps in place of the first bump, wherein each of the second set of bumps is formed according to a specified second diameter; and (2) forming a third set of bumps in place of the first set of bumps, wherein each of the third set of bumps is formed according to a specified second diameter.
[0043]
[0050] Each of the second set of bumps and the third set of bumps may include microbumps. Each of the second set of bumps and the third set of bumps may be formed according to the same specified height. Removing material associated with both the first bump and the first set of bumps may include polishing, cutting, or grinding the material.
[0044]
[0051] Forming a second set of bumps may involve forming multiple microbumps to maintain a large contact surface between the multiple microbumps and the contact pads beneath them. This large contact surface between the multiple microbumps and the contact pads beneath them is configured to mitigate the effects of any electromigration-induced damage. None of the first, second, or third sets of bumps are probed by using sacrificial pads formed on the wafer.
[0045]
[0052] In another example, the disclosure relates to a method comprising (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) forming a first set of bumps on the wafer substrate, each of which is formed according to a defined second diameter smaller than the defined first diameter. The method may further comprise probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0046]
[0053] The method may further include forming a protective layer on the first bump and the first set of bumps. The method may further include removing the protective layer and the material associated with both the first bump and the first set of bumps in order to allow for the reformation of bumps in place of the first bump and the first set of bumps. The method may further include: (1) forming a second set of bumps in place of the first bump, each of which is formed according to a specified second diameter; and (2) forming a third set of bumps in place of the first set of bumps, each of which is formed according to a specified second diameter.
[0047]
[0054] Each of the second set of bumps and the third set of bumps may include microbumps. Each of the second set of bumps and the third set of bumps may be formed according to the same specified height. Removing the protective layer and the material associated with both the first bump and the first set of bumps may include sanding, cutting, or grinding the material.
[0048]
[0055] Forming a second set of bumps may involve forming multiple microbumps to maintain a large contact surface between the multiple microbumps and the contact pads beneath them. This large contact surface between the multiple microbumps and the contact pads beneath them is configured to mitigate the effects of any electromigration-induced damage. None of the first, second, or third sets of bumps are probed using sacrificial pads formed on the wafer.
[0049]
[0056] In yet another example, the Disclosure relates to a method comprising: (1) forming a first bump on a wafer substrate according to a defined first diameter, and (2) each of the first set of bumps forming a first set of bumps on the wafer substrate according to a defined second diameter smaller than the defined first diameter. The method may further comprise probing a portion of the wafer relating to one or more of the first set of bumps by using the first bumps.
[0050]
[0057] The method may further include forming a protective layer on the first bump and the first set of bumps. The method may further include removing the protective layer and the material associated with both the first bump and the first set of bumps in order to allow the reformation of bumps in place of the first bump and the first set of bumps. The method may further include forming (1) a second set of bumps in place of the first bump, each of which is formed according to a defined second diameter and a defined first height, and each of which is associated with a first active circuit configuration formed as part of the wafer, and (2) a third set of bumps in place of the first set of bumps, each of which is formed according to a defined second diameter and a defined first height, and each of which is associated with a second active circuit configuration different from the first active circuit configuration formed as part of the wafer.
[0051]
[0058] Each of the second set of bumps and the third set of bumps may include microbumps. Removing the protective layer and the material associated with both the first bump and the first set of bumps may include polishing, cutting, or grinding the material.
[0052]
[0059] Forming a second set of bumps may involve forming multiple microbumps to maintain a large contact surface between the multiple microbumps and the contact pads beneath them. This large contact surface between the multiple microbumps and the contact pads beneath them is configured to mitigate the effects of any electromigration-induced damage. None of the first, second, or third sets of bumps are probed using sacrificial pads formed on the wafer.
[0053]
[0060] The methods, modules, and components described herein should be understood to be merely illustrative. Alternatively or in addition, the functionalities described herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-chip systems (SOCs), complex-programmable logic devices (CPLDs), and so on. In summary, but still clearly, any arrangement of components that achieve the same functionality is effectively “associated” in such a way that the desired functionality is achieved. Thus, any two components combined herein to achieve a particular functionality may be “associated” with each other in such a way that the desired functionality is achieved regardless of architecture or intermediary components. Similarly, any two such associated components may also be considered to be “operably connected” or “joined” with each other in such a way that the desired functionality is achieved.
[0054]
[0061] Furthermore, those skilled in the art should recognize that the boundaries between the functionalities of the aforementioned actions are merely illustrative. The functionalities of multiple actions can be combined into a single action, and / or the functionalities of a single action can be distributed among additional actions. Moreover, alternative embodiments may include multiple instances of a particular action, and the order of actions may be modified in various other embodiments.
[0055]
[0062] While this disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the disclosure set forth in the claims. Accordingly, this specification and accompanying drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. No benefit, advantage, or solution to a problem described herein with respect to specific examples is intended to be construed as a critical, necessary, or essential feature or element of any claim.
[0056]
[0063] Furthermore, as used herein, the terms "a" or "an" are defined as one or more. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as meaning that any particular claim containing such an introductory phrase is limited to an invention containing only one such element by the introduction of another claim element by the indefinite article "a" or "an," even if the same claim contains the introductory phrase "one or more" or "at least one" and the indefinite article "a" or "an." The same applies to the use of the definite article.
[0057]
[0064] Unless otherwise noted, terms such as "first" and "second" are used to arbitrarily distinguish between the elements they describe. Therefore, these terms are not necessarily intended to indicate any temporal or other priority of such elements.
Claims
1. (1) A first bump (210) formed according to a defined first diameter on the substrate (110) of the wafer (10), and (2) a first set of bumps (220, 230, 240), each formed according to a defined second diameter smaller than the defined first diameter, on the substrate (110) of the wafer (10) (step 810); Step 820: Probing a portion of the wafer (10) related to one or more of the first set of bumps (220, 230, 240) by using the first bump (210); Step 830: Remove material associated with both the first bump (210) and the first set of bumps (220, 230, 240) in order to allow the reshaping of bumps in place of the first bump (210) and the first set of bumps (220, 230, 240); and (1) A second set of bumps (610, 620, 630) in place of the first bump (210), wherein each of the second set of bumps (610, 620, 630) is formed according to the second specified diameter, and (2) A third set of bumps (640, 650, 660) in place of the first set of bumps (220, 230, 240), wherein each of the third set of bumps (640, 650, 660) is formed according to the second specified diameter (step 840). A method that includes this.
2. The method according to claim 1, wherein each of the second set of bumps and the third set of bumps includes a microbump.
3. The method according to claim 1, wherein each of the second set of bumps and the third set of bumps is formed according to the same specified height.
4. The method according to claim 1, wherein removing the material associated with both the first bump and the first set of bumps comprises polishing, cutting, or grinding the material.
5. The method according to claim 1, wherein forming the second set of bumps includes forming a plurality of microbumps to maintain a large contact surface between the plurality of microbumps and the contact pad beneath the microbumps.
6. The method according to claim 5, wherein the large contact surface between the plurality of microbumps and the contact pads beneath the microbumps is configured to mitigate the effects of any electromigration-induced damage.
7. The method according to claim 1, wherein none of the first set of bumps, the second set of bumps, or the third set of bumps are probed by using a sacrificial pad formed on the wafer.
8. (1) A first bump (210) formed according to a defined first diameter on the substrate (110) of the wafer (10), and (2) a first set of bumps (220, 230, 240), each formed according to a defined second diameter smaller than the defined first diameter, on the substrate (110) of the wafer (step 810); Step 820: Probing a portion of the wafer (10) related to one or more of the first set of bumps (220, 230, 240) by using the first bump (210); Forming a protective layer (410) on the first bump (210) and the first set of bumps (220, 230, 240); Step 830: Remove the material associated with both the protective layer (410) and the first bump (210) and the first set of bumps (220, 230, 240) in order to allow the reshaping of bumps in place of the first bump (210) and the first set of bumps (220, 230, 240); and (1) A second set of bumps (610, 620, 630) in place of the first bump (210), wherein each of the second set of bumps (610, 620, 630) is formed according to the second specified diameter, and (2) A third set of bumps (640, 650, 660) in place of the first set of bumps (220, 230, 240), wherein each of the third set of bumps (640, 650, 660) is formed according to the second specified diameter (step 840). A method that includes this.
9. The method according to claim 8, wherein each of the second set of bumps and the third set of bumps includes a microbump.
10. The method according to claim 8, wherein each of the second set of bumps and the third set of bumps is formed according to the same specified height.
11. The method of claim 8, wherein removing the material associated with the protective layer and both the first bump and the first set of bumps includes polishing, cutting or grinding the material.
12. The method according to claim 8, wherein forming the second set of bumps includes forming the plurality of microbumps in order to maintain a large contact surface between the plurality of microbumps and the contact pad beneath the microbumps.
13. The method according to claim 12, wherein the large contact surface between the plurality of microbumps and the contact pad located beneath the plurality of microbumps is configured to mitigate the effects of any electromigration-induced damage.
14. The method according to claim 8, wherein none of the first set of bumps, the second set of bumps, or the third set of bumps are probed by using a sacrificial pad formed on the wafer.