Memory architecture

Abstract

It provides a memory architecture that facilitates preventative replacement by maintenance personnel. [Solution] The memory architecture 1 includes an input module, an overcurrent protection module electrically connected to the input module, a surge protection module electrically connected to the overcurrent protection module, a power management integrated circuit (PMIC) electrically connected to the overcurrent protection module and the surge protection module, a voltage conversion module electrically connected to the PMIC, a microcontroller electrically connected to the voltage conversion module and the input module, an electrostatic discharge (ESD) protection module electrically connected to the input module, and a memory integrated circuit (IC) electrically connected to the microcontroller, the ESD protection module, and the input module. The overcurrent protection module limits the input current, the surge protection module protects the PMIC by conducting a surge signal or ESD current, and the ESD protection module protects the memory IC by conducting an ESD current.

Description

Technical Field

[0001] This invention relates to a memory architecture, and more particularly to a memory architecture that can incorporate surge protection, electrostatic discharge (ESD) protection, and overcurrent protection, and can record abnormal signals via a microcontroller.

Background Art

[0002] In the pursuit of ultimate performance, modern memory devices are facing unprecedented physical challenges and design problems. Among them, three electrical threats, namely, surges (e.g., voltages above 4 kV), ESD, and overcurrents (e.g., above 1 A / pin), have become major technical bottlenecks with the miniaturization of the process. As the semiconductor manufacturing process enters the nanometer level, the width of the internal wiring and the thickness of the insulating layer are approaching physical limits. As a result, the tolerance of the memory to voltage fluctuations has been significantly reduced. Even a surge with slight fluctuations (e.g., above ±200 V) in the conventional process may cause destructive dielectric breakdown in modern high-density memory dies. This has become a major problem in current hardware design.

[0003] In the surges generated during power-on or grid switching, an overly high voltage may directly affect the oxide layer inside the memory. The manufacturing process of the memory is extremely precise, and the thickness of each gate of each transistor is only a few nanometers. Therefore, once the voltage exceeds the breakdown voltage limit, permanent dielectric breakdown damage will occur. This can lead to various situations, from frequent blue screens and data corruption in computers to instantaneous failures of the entire memory module. Furthermore, such hardware damage caused by surge voltage overload is usually irreparable.

[0004] During prolonged use, if a short circuit occurs or the resistance of components abnormally decreases due to aging caused by high temperatures, the current can increase rapidly and uncontrollably, generating a large amount of heat. In such situations, heat accumulates rapidly, causing scorching and delamination of the circuit board, and even melting the memory die package. In the most serious cases, the overcurrent can not only destroy the memory itself, but also travel back up the slot on the mainboard to the mainboard, potentially burning out the power supply unit or, in the worst case, causing a more serious hardware fire.

[0005] At the same time, ESD often occurs accidentally during manufacturing or operation, and damage can also occur due to ESD that occurs during installation. Although the total energy of ESD is not high, the instantaneous voltage is extremely high, sufficient to generate invisible arcs between the microcircuits inside the memory chip. If the charge is not conducted to the outside, this ESD energy flows directly into the high-speed data bus, causing serious damage to signal integrity. Furthermore, ESD damage often manifests as a "latent failure." That is, the memory may still function in the initial stages of damage, but random bit errors occur during subsequent use, and the entire system falls into an unstable state that is difficult to diagnose.

[0006] Therefore, while memory pursues extreme performance, it must overcome the three electrical threats mentioned above. The main role of surge protection is to withstand surge signals and voltage pulses caused by instability of the external power supply when powered on, and therefore excess energy must be quickly discharged to ground. The main role of ESD protection is to protect the data transmission path. The gold finger of the memory integrated circuit (memory IC) frequently comes into contact with the human body or the external package, making it prone to generating ESD voltages exceeding 1,000 volts, and it is necessary to discharge the charge when ESD energy is detected. Finally, the main role of overcurrent protection is to maintain the overall safety of the system and prevent thermal runaway. When the current exceeds a preset threshold, the protection circuit immediately shuts off the power supply.

[0007] Surge protection, ESD protection, and overcurrent protection are crucial for hardware safety, yet the current memory industry lacks products that combine all three comprehensive protection mechanisms. In the pursuit of ultra-thin LPDDR memory, circuit board space is extremely limited, making it difficult to accommodate large transient suppression (TVS) diodes and high-precision sensing resistors together. Furthermore, each additional protection component introduces minute impedance fluctuations to high-speed data signals (e.g., transmission speeds exceeding tens of gigabytes per second (GB / s)). Some designers choose to simplify protection circuits to ensure signal purity in order to achieve higher transmission frequencies, but simplified designs sacrifice reliability and increase the risk of memory damage.

[0008] Therefore, a memory architecture that provides surge protection, ESD protection, and overcurrent protection together, and can record abnormal signals via a microcontroller, thereby warning maintenance personnel of potential overvoltage, surge, or ESD occurrences and facilitating preventative replacement, is a problem that those skilled in the art should address. [Overview of the project] [Problems that the invention aims to solve]

[0009] The objective of this invention is to provide a memory architecture that protects the memory architecture using surge protection modules, ESD protection modules, and overcurrent protection modules. Furthermore, by sending abnormal signals detected by the three protection modules to a microcontroller, which then sends them to registers, the user can access the register information via a host computer, facilitating preventative replacement by maintenance personnel. [Means for solving the problem]

[0010] To achieve the above objective, the present invention provides a memory architecture comprising: a main board; an input module disposed on the side of the main board; an overcurrent protection module disposed on the main board and electrically connected to the input module; a surge protection module disposed on the main board and electrically connected to the overcurrent protection module; a power management integrated circuit (PMIC) disposed on the main board and electrically connected to the overcurrent protection module and the surge protection module; a voltage conversion module disposed on the main board and electrically connected to the PMIC; a microcontroller disposed on the main board and electrically connected to the voltage conversion module and the input module; an electrostatic discharge (ESD) protection module disposed on the main board and electrically connected to the input module; and a memory integrated circuit (IC) disposed on the main board and electrically connected to the microcontroller, the ESD protection module, and the input module. The overcurrent protection module protects the PMIC by controlling the input current of the input module to be below a preset current threshold, thereby preventing the PMIC from being damaged. The surge protection module protects the PMIC by directing the surge signal or ESD current from the input module to a first ground terminal. The ESD protection module protects the memory IC by directing the ESD current to a second ground terminal. This provides the memory architecture with surge protection, ESD protection, and overcurrent protection.

[0011] In one embodiment of the present invention, the main board further comprises a plurality of grounding vias.

[0012] In one embodiment of the present invention, the microcontroller receives an overcurrent message transmitted by the overcurrent protection module.

[0013] In one embodiment of the present invention, the microcontroller receives a surge message transmitted by the surge protection module.

[0014] In one embodiment of the present invention, the microcontroller receives an ESD message transmitted by the ESD protection module.

[0015] In one embodiment of the present invention, a register is further provided on the main board and electrically connected to the microcontroller, wherein the microcontroller sends at least one of the overcurrent message, surge message, and ESD message to the register, and the register stores at least one of the overcurrent message, surge message, and ESD message.

[0016] In one embodiment of the present invention, the register is an integrated circuit (I 2 C) Electrically connected to the microcontroller via a bus.

[0017] In one embodiment of the present invention, the ESD protection module is configured to correspond to a plurality of data lines of the memory IC and the input module.

[0018] In one embodiment of the present invention, the PMIC is I 2 It is electrically connected to the microcontroller via the C bus.

[0019] As described herein, the problem to be solved by those skilled in the art is to provide a memory architecture that combines surge protection, ESD protection, and overcurrent protection and can record abnormal signals via a microcontroller. [Brief explanation of the drawing]

[0020] [Figure 1] This is a block diagram of a memory architecture according to one embodiment of the present invention.

[0021] [Figure 2] This is a schematic diagram of a memory architecture according to one embodiment of the present invention.

[0022] [Figure 3] A block diagram of a memory architecture according to another embodiment of the present invention.

[0023] [Figure 4] A schematic diagram of a memory architecture according to the present invention.

[0024] [Figure 5] A schematic diagram of a memory architecture according to the present invention.

Mode for Carrying Out the Invention

[0025] In order to better understand and recognize the features and effects achieved by the present invention, preferred embodiments are shown below together with detailed descriptions.

[0026] In conventional architectures, protective components usually introduce additional parasitic capacitance. In today's high-speed transmission environment, protective components can cause signal reflections and waveform distortions, thereby limiting the potential of the memory bandwidth. Furthermore, most memory ICs overly rely on main board-level power protection and lack autonomous defense at the module level. Therefore, when facing unstable power supplies or extreme ESD environments, potential bit errors and even circuit burnout are likely to occur. Such incomplete protection designs and excessive dependence on external environments are the main problems in modern memories.

[0027] This invention protects the memory architecture from electrical threats by incorporating three protection modules—a surge protection module, an ESD protection module, and an overcurrent protection module—into the memory architecture. In addition, the microcontroller records and stores abnormal signals detected by these three modules, allowing the user to retrieve the abnormal signals via a host computer to determine whether the memory architecture has been exposed to overvoltage, ESD, surge, or overcurrent, thereby facilitating preventative replacement of the memory architecture.

[0028] The present invention will be described in detail below by illustrating various embodiments shown in the drawings. However, the concept of the present invention can be realized in various forms and should not be construed as being limited to the exemplary embodiments described herein.

[0029] First, an embodiment provided by the present invention will be shown. Please refer to Figure 1. Figure 1 is a block diagram of the memory architecture according to the present invention. As shown in the figure, the memory architecture 1 according to the present invention will be described in detail below. Memory architecture 1 includes a main board 10, an input module 20 located on the side of the main board 10, an overcurrent protection module 30 located on the main board 10 and electrically connected to the input module 20, a surge protection module 40 located on the main board 10 and electrically connected to the overcurrent protection module 30, a power management integrated circuit (PMIC) 50 located on the main board 10 and electrically connected to the overcurrent protection module 30 and the surge protection module 40, a voltage conversion module 60 located on the main board 10 and electrically connected to the PMIC 50, a microcontroller 70 located on the main board 10 and electrically connected to the voltage conversion module 60 and the input module 20, an ESD protection module 80 located on the main board 10 and electrically connected to the input module 20, and a memory integrated circuit (IC) 90 located on the main board 10 and electrically connected to the microcontroller 70, the ESD protection module 80, and the input module 20. The overcurrent protection module 30 protects the PMIC 50 by controlling the input current of the input module 20 to less than a preset current threshold (e.g., 1mA, based on the specifications of the PMIC 50). The surge protection module 40 protects the PMIC 50 by directing the surge signal from the input module 20 (e.g., a current signal exceeding 1A flowing in 8μs / 20μs, or a voltage signal of 0.5kV to 4kV flowing in 1.2μs / 50μs) or ESD current (e.g., a rapidly flowing current of 0.5A to 60A, or a voltage of 2kV to 15kV, e.g., with a rise time of at least 1ns and a discharge time of at least 10ns) to the first ground terminal 212 (e.g., pin 65, pin 68, or pin 71 (VSS pin) in the pinout definition of a basic DDR5 UDIMM, with pin 71 in the pinout being used as an example here).The ESD protection module 80 protects the memory IC 90 by directing ESD current to a second ground terminal 232 (for example, at least one VSS pin adjacent to at least one DQ pin in the pinout definition of a basic DDR5 UDIMM; in this embodiment, the ESD protection module 80 includes a plurality of nodes electrically connected to a plurality of VSS terminals in the input module 20). The input module 20 includes a first command section 21A, a first data section 23A, a second command section 21B, and a second data section 23B, where the first ground terminal 212 is a VSS terminal located in the first command section 21A, and the second ground terminal 232 is a VSS terminal located in the first data section 23A and the second data section 23B. However, the invention is not limited thereto, and the nodes of the ESD protection module 80 may be connected to the same VSS terminal in the pinout definition of a basic DDR5 UDIMM.

[0030] Please refer to Figure 2, which is a schematic diagram of the memory architecture according to the present invention. As shown in the figure, in this embodiment the main board 10 is a printed circuit board, but is not limited thereto. The main purpose of the main board 10 is to mount a plurality of memory ICs 90 and a plurality of modules referred to in this invention. The main board 10 has a plurality of data lines for accurately transmitting electrical signals received by the input module 20 to the memory ICs 90.

[0031] Continuing from the above, in this embodiment, the overcurrent protection module 30 is a self-resetting fuse, but is not limited thereto. The purpose of the overcurrent protection module 30 is to prevent damage to the PMIC 50 by dielectric breakdown under abnormal current conditions. In this embodiment, a self-resetting fuse is a preferred embodiment. If the input current of the input module 20 is greater than a preset current threshold (e.g., 1 mA / pin), the overcurrent protection module 30 may increase its internal resistance. This reduces the input current passing through it, preventing damage to the PMIC 50. The self-resetting fuse automatically limits the current under overcurrent conditions and provides protection. After the fault is cleared, the overcurrent protection module 30 can automatically reduce its resistance and restore conduction.

[0032] As described above, in this embodiment, a preferred embodiment of the surge protection module 40 is a transient voltage suppression (TVS) diode, but is not limited thereto. The surge protection module 40 is connected in parallel between the PMIC 50 and the overcurrent protection module 30 and is also connected to the first ground terminal 212. When the surge protection module 40 receives a surge signal or ESD current, it can quickly conduct and release energy to the first ground terminal 212, thereby preventing the PMIC 50 and subsequent circuits from being damaged by overvoltage.

[0033] Following the above, in this embodiment, a preferred embodiment of the ESD protection module 80 is a low-capacitance ESD protection element. However, it is not limited thereto. To prevent dielectric breakdown of the memory IC 90 due to ESD during manufacturing or operation of the memory architecture 1, the ESD protection module 80 is positioned between the memory IC 90 and the input module 20 and is also connected to the second ground terminal 232. The generated ESD current is guided to the second ground terminal 232 via the low-capacitance ESD protection element of the ESD protection module 80, protecting the memory IC 90.

[0034] Following the above, another embodiment is shown. In this embodiment, the ESD protection module 80 is configured to correspond to multiple data lines of the memory IC 90 and the input module 20. Each data line connected to the memory IC 90 must be electrically connected to the ESD protection module 80 to prevent dielectric breakdown of the memory IC 90 caused by the data line transmitting excessive ESD current.

[0035] Please refer to Figure 3, which follows the above. Figure 3 is a block diagram of a memory architecture according to another embodiment of the present invention. As shown in the figure, the memory architecture 1 according to the present invention will be described in detail below. The memory architecture 1 includes a main board 10, an input module 20 located on the side of the main board 10, an overcurrent protection module 30 located on the main board 10 and electrically connected to the input module 20, a surge protection module 40 located on the main board 10 and electrically connected to the overcurrent protection module 30, a PMIC 50 located on the main board 10 and electrically connected to the overcurrent protection module 30 and the surge protection module 40, a voltage conversion module 60 located on the main board 10 and electrically connected to the PMIC 50, a microcontroller 70 located on the main board 10 and electrically connected to the voltage conversion module 60, an ESD protection module 80 located on the main board 10 and electrically connected to the input module 20, a memory IC 90 located on the main board 10 and electrically connected to the microcontroller 70, the ESD protection module 80, and the input module 20, and a register 75 located on the main board 10 and electrically connected to the microcontroller 70. The overcurrent protection module 30 protects the PMIC 50 by controlling the input current of the input module 20 to be below a preset current threshold (for example, 1mA, based on the specifications of the PMIC 50). The surge protection module 40 protects the PMIC 50 by directing the surge signal or ESD current from the input module 20 to the first ground terminal 212. The ESD protection module 80 protects the memory IC 90 by directing the ESD current to the second ground terminal 232.

[0036] Next, please refer to Figure 4. Figure 4 is a schematic diagram of the memory architecture of the present invention. As shown in the figure, in another embodiment, if the input current of the input module 20 is greater than a preset current threshold (e.g., 1 mA / pin), the overcurrent protection module 30 increases its internal resistance, thereby reducing the input current passing through it. This prevents damage to the PMIC 50 and then sends an overcurrent message to the microcontroller 70.

[0037] In a subsequent embodiment, when the surge protection module 40 receives a surge signal or ESD current, the surge protection module 40 quickly turns on and can release energy to the first ground terminal 212 to prevent overvoltage from damaging the PMIC 50 and subsequent circuits, and then transmits a surge message to the microcontroller 70.

[0038] Following the above, in another embodiment, the ESD protection module 80 protects the memory IC 90 by directing the generated ESD current to the second ground terminal 232, and then sends an ESD message to the microcontroller 70.

[0039] Following the above, the PMIC 50 uses an integrated circuit (I) to send messages. 2 C) Electrically connected to the microcontroller 70 via the bus.

[0040] Following the above, the microcontroller 70 sends at least one of the overcurrent message, surge message, and ESD message to register 75. Register 75 stores at least one of the overcurrent message, surge message, and ESD message. By storing the overcurrent message, surge message, and ESD message in register 75, a user can read register 75 via a host computer (not shown) to determine if the memory architecture 1 has experienced an overvoltage or ESD event and thereby determine whether the memory architecture 1 needs to be replaced.

[0041] Following the above, register 75 is I 2 The register 75 is electrically connected to the microcontroller 70 via the C bus, and the microcontroller 70 uses this connection to send at least one of the following messages to the register: an overcurrent message, a surge message, and an ESD message.

[0042] Next, please refer to Figure 5. Figure 5 is a schematic diagram of the memory architecture according to the present invention. As shown in the figure, in another embodiment, the memory architecture 1 of the present invention will be described in detail below. The memory architecture 1 includes a main board 10 having a plurality of ground vias 15, an input module 20 located on the side of the main board 10, an overcurrent protection module 30 located on the main board 10 and electrically connected to the input module 20, a surge protection module 40 located on the main board 10 and electrically connected to the overcurrent protection module 30, a PMIC 50 located on the main board and electrically connected to the overcurrent protection module 30 and the surge protection module 40, a voltage conversion module 60 located on the main board 10 and electrically connected to the PMIC 50, a microcontroller 70 located on the main board 10 and electrically connected to the voltage conversion module 60 and the input module 20, an ESD protection module 80 located on the main board 10 and electrically connected to the input module 20, a memory IC 90 located on the main board 10 and electrically connected to the microcontroller 70, the ESD protection module 80, and the input module 20, and a register 75 located on the main board 10 and electrically connected to the microcontroller 70. The overcurrent protection module 30 protects the PMIC 50 by controlling the input current of the input module 20 to below a preset current threshold (for example, 1mA, based on the specifications of the PMIC 50) to prevent the PMIC 50 from being destroyed. The surge protection module 40 protects the PMIC 50 by directing the surge signal or ESD current from the input module 20 to the first ground terminal 212. The ESD protection module 80 protects the memory IC 90 by directing the ESD current to the second ground terminal 232.

[0043] In addition to the above, the ground via 15 provides a better discharge path, which can more effectively avoid damage to the PMIC 50 or memory IC 90 due to ESD current during contact.

[0044] In the embodiments described above, the present invention provides a memory architecture that integrates surge protection, ESD protection, and overcurrent protection mechanisms, and further incorporates a microcontroller for monitoring abnormal signals. When a protection circuit is triggered, the system automatically saves fault data so that the user can be aware of it via the host interface. This makes visible electrical impacts that were previously difficult to detect, shifting hardware management from passive maintenance to proactive preventative replacement.

[0045] Therefore, this invention certainly possesses novelty, inventiveness, and industrial applicability, and undoubtedly satisfies the requirements for utility model registration application under the Utility Model Act. Accordingly, the applicant hereby files a utility model registration application under the Utility Model Act and respectfully requests early registration.

[0046] The above description is merely a preferred embodiment of the present invention, and all equivalent modifications and changes made within the scope of the utility model claims of the present invention are intended to be included within the scope of the present invention.

Claims

1. It is a memory architecture, Main board and An input module located on the side of the main board, An overcurrent protection module, which is placed on the main board and electrically connected to the input module, A surge protection module is placed on the main board and electrically connected to the overcurrent protection module, A power management integrated circuit is placed on the main board and electrically connected to the overcurrent protection module and the surge protection module, A voltage conversion module is placed on the main board and electrically connected to the power management integrated circuit, A microcontroller is placed on the main board and electrically connected to the voltage conversion module and the input module, An electrostatic discharge protection module, which is placed on the main board and electrically connected to the input module, A memory integrated circuit is arranged on the main board and electrically connected to the microcontroller, the electrostatic discharge protection module, and the input module, Includes, The overcurrent protection module prevents the power management integrated circuit from being damaged and protects the power management integrated circuit by controlling the input current of the input module to be below a preset current threshold. The surge protection module protects the power management integrated circuit by guiding the surge signal or electrostatic discharge current of the input module to the first ground terminal. The electrostatic discharge protection module protects the memory integrated circuit by guiding the electrostatic discharge current to the second ground terminal. Memory architecture.

2. The memory architecture according to claim 1, wherein the main board further comprises a plurality of ground vias.

3. The memory architecture according to claim 1, wherein the microcontroller receives an overcurrent message transmitted from the overcurrent protection module.

4. The main board further includes registers arranged on the main board and electrically connected to the microcontroller, The microcontroller transmits the overcurrent message to the register, and the register stores the overcurrent message. The memory architecture according to claim 3.

5. The memory architecture according to claim 4, wherein the registers are electrically connected to the microcontroller via an integrated circuit bus.

6. The memory architecture according to claim 1, wherein the microcontroller receives surge messages transmitted by the surge protection module.

7. The main board further includes registers arranged on the main board and electrically connected to the microcontroller, The microcontroller transmits the surge message to the register, and the register stores the surge message. The memory architecture according to claim 6.

8. The memory architecture according to claim 7, wherein the registers are electrically connected to the microcontroller via an integrated circuit bus.

9. The memory architecture according to claim 1, wherein the microcontroller receives electrostatic discharge messages transmitted by the electrostatic discharge protection module.

10. The main board further includes registers arranged on the main board and electrically connected to the microcontroller, The microcontroller transmits the electrostatic discharge message to the register, and the register stores the electrostatic discharge message. The memory architecture according to claim 9.

11. The memory architecture according to claim 10, wherein the registers are electrically connected to the microcontroller via an integrated circuit bus.

12. The memory architecture according to claim 1, wherein the electrostatic discharge protection module is configured to correspond to a plurality of data lines of the memory integrated circuit and the input module.

13. The memory architecture according to claim 1, wherein the power management integrated circuit is electrically connected to the microcontroller via an interconnected circuit bus.

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