Partial shutdown of a computer processor core

Abstract

An aspect of the present disclosure relates to a processor core including an execution unit and a utilization controller. The execution unit is operable to execute commands forwarded to the execution unit. The utilization controller is operably coupled to the execution unit. The utilization controller is operable to control utilization of the execution unit. The utilization corresponds to a portion of an observation period during which the execution unit is executing commands of an application. Another aspect of the present disclosure relates to a method for detecting or analyzing bottlenecks in a processor core for a given application. The method includes controlling utilization of at least one execution unit of the processor core and measuring resulting application performance.

Description

[Technical field]

[0001] The present invention relates generally to computer systems, and more particularly to processor cores. [Background technology]

[0002] Increases in application performance are to a large extent the result of increases in hardware performance. Comparable performance increases from hardware advances can no longer be expected, as structure sizes have reached fundamental physical limits, as well as technological and economic limits.

[0003] However, there remains the possibility to optimize the software. For example, the software algorithms themselves can be improved. Perhaps even more promising is hardware-aware tuning of the software. Conventionally, it may be desirable to have knowledge of the hardware units that actually limit the performance of an application, i.e., which hardware units represent the bottleneck for a given application. For example, memory units may represent the bottleneck for an application while computational units are utilized. It may then be possible to adapt the software to reduce the use of memory units and increase the use of computational units. Alternatively or additionally, knowledge of the bottlenecks may allow the development of future hardware that is better adapted to the requirements of the application. Thus, methods and systems for improved processor cores may be desirable. Summary of the Invention

[0004] Aspects of the present disclosure relate to a processor core including at least one execution unit and a utilization controller. The execution unit is operable to execute commands forwarded to the execution unit. The utilization controller is operatively coupled to the execution unit. The utilization controller is operable to control a utilization of the execution unit, which corresponds to a fraction of a total execution period during which the execution unit is executing commands.

[0005] Another aspect of the present disclosure relates to a method for detecting or analyzing bottlenecks in a processor core for a given application, execution of which corresponds to a given set of commands executed by an execution unit of the processor core, the method including controlling utilization of at least one execution unit of the processor core and measuring the resulting application performance.

[0006] The above summary is not intended to describe each exemplary embodiment or every implementation of the present disclosure.

[0007] The following detailed description is given by way of example and is not intended to be solely limiting of the invention, and is best understood in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0008] [Figure 1] 1 is an exemplary computer system according to an embodiment of the present disclosure. [Diagram 2] 1 illustrates a first exemplary processor core according to an embodiment of the present disclosure. [Diagram 3] 4 illustrates a second exemplary processor core according to an embodiment of the present disclosure. [Figure 4] 4 illustrates a third exemplary processor core according to an embodiment of the present disclosure. [Diagram 5] 13 illustrates a fourth exemplary processor core according to an embodiment of the present disclosure. [Figure 6]13 illustrates a fifth exemplary processor core according to an embodiment of the present disclosure. [Figure 7] 1 is a flowchart illustrating an exemplary method for detecting a bottleneck in a processor core for a given application, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to represent only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0010] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it can be understood that the disclosed embodiments are merely examples of the claimed structures and methods that can be embodied in various forms. However, the present invention can be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0011] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present invention relate generally to the field of computer systems, and more particularly to processor cores. Exemplary embodiments described below provide, among other things, a system, method, and computer program product that uses a duty cycle controller to measure the performance and performance limits of a processor core. Thus, the present embodiments have the ability to advance the technical field of computer systems by providing an approach to identify bottlenecks in a given application based on, among other parameters, determining critical components of the system, the need for more units in the system, and identifying units utilized in the system. Specifically, embodiments of the present disclosure may control utilization of multiple execution units and determine application performance dependency on utilization of each, which may enable identification of bottlenecks in the processor core that are limiting the performance of the application.

[0012] 1, there is illustrated an exemplary computer system / server 12 applicable for implementing embodiments of the present disclosure. The computer system / server 12 is merely exemplary and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the present invention described herein.

[0013] 1, computer system / server 12 is depicted in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 coupling various system components including system memory 28 to processor 16.

[0014] Bus 18 represents one or more of any of several types of bus structures, such as a memory bus or memory controller, a bus for peripherals, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example and without limitation, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0015] Computer system / server 12 typically includes a variety of computer system readable media. Such media may be any available media that can be accessed by computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0016] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. In such a case, each of these may be connected to the bus 18 by one or more data media interfaces. As further illustrated and described below, memory 28 may include at least one program product having a set (e.g., at least one) program module configured to perform functions of an embodiment of the present invention.

[0017] By way of example, and not limitation, a program / utility 40 having a set (e.g., at least one) program module 42, an operating system, one or more application programs, other program modules, and program data may be stored in memory 28. The operating system, one or more application programs, other program modules, and program data, or some combination thereof, may each include an embodiment of a networking environment. The program modules 42 generally perform the functions and / or methods of embodiments of the present invention described herein.

[0018] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, one or more devices that allow a user to interact with the computer system / server 12, or any device (e.g., network card, modem, etc.) that allows the computer system / server 12 to communicate with one or more other computing devices, or a combination thereof. Such communication may occur via an input / output (I / O) interface 22. Still further, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown, it should be understood that other hardware and / or software components may be used in conjunction with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0019] It should be noted that embodiments of the present disclosure may be implemented as programs / utilities 40 or program modules 42 of FIG.

[0020] Referring now to FIG. 2, a first exemplary processor core 100 according to an embodiment of the present disclosure is illustrated. The first exemplary processor core 100 includes an execution unit 120 operable to execute commands. In the example of FIG. 2, the execution unit 120 is also shown as unit A. The first exemplary processor core 100 may include more than one execution unit 120. For example, the first exemplary processor core 100 may additionally include a unit B, a unit C, etc. (not shown in the figure). In addition to an input for receiving a command C for initiating a computation, which may also be referred to as an issue command, the execution unit 120 may include a further input 121. For example, the further input 121 may be used to receive data to be operated on by the execution unit 120. It should be noted that the execution of a given application corresponds to a given set of commands executed by the execution units of the processor core.

[0021] Additionally, the first exemplary processor core 100 includes one or more utilization controllers 130, which may also be referred to as Ready Blockers. Each utilization controller 130 is operatively coupled to one or more execution units 120. Each utilization controller 130 may be operable to control the utilization of the execution unit 120 to which it is coupled. As known to those skilled in the art, an execution unit of a processor core may be in a state in which it is in a state where ... A Only one active ratio may be active. A / T is called the utilization rate.

[0022] Execution unit 120 may transmit a ready signal R indicating that the previous computation has been performed and that execution unit 120 is ready to perform the next computation. As shown in the figure, utilization controller 130 is operable to generate a modified ready signal R* from ready signal R.

[0023] The first exemplary processor core 100 may further include an issue unit 110 operable to forward a next command C that triggers the execution units to begin computation based on the modified ready signal R*. The issue unit 110 may include a further input 111 through which a further signal must be received before the issue unit 110 issues the command C.

[0024] The utilization controller 130 may mask the ready signal R for a certain percentage of time. A modified ready signal R* may then be sent to the issue unit 110, not necessarily every time the utilization controller 130 receives a ready signal R from the execution unit 120. The utilization of the execution unit 120 may thus be modified, in particular reduced. The ready signal R or the modified ready signal R*, or both, may correspond to a static voltage (i.e., high or low) of a static electrical connection between the corresponding units. However, it may also be possible to send the ready signal R and the modified ready signal R* as messages on the bus.

[0025] Individual modification of the utilization of individual execution units may allow a more detailed analysis of bottlenecks limiting the performance of a given application compared to decreasing the operating frequency of a processor core. Known side effects of known methods for analyzing the impact of hardware on application performance may be avoided. For example, decreasing the operating frequency of a processor core may not only decrease the utilization of the execution units, but may also affect the electrical behavior of the processor core, i.e., voltage, current, capacity. Furthermore, the techniques proposed in this application may provide a finer granularity compared to conventional methods of influencing hardware performance. For example, the proposed method and related system may provide a finer granularity than simply using more or fewer cores per socket. Furthermore, the proposed utilization controller may have the additional advantage that it may be used for different execution units. For example, the same type of utilization controller may be used for execution units performing arithmetic calculations and for execution units controlling memory accesses.

[0026] Separately, controlling the utilization of multiple execution units and determining application performance dependencies on their respective utilization may make it possible to identify processor core bottlenecks that limit the performance of a given application.

[0027] The utilization controller 130 may include a feedback shift register 132 and an AND gate 131 to provide a modified ready signal R*. The AND gate 131 receives the ready signal R at a first input and the gate signal G sent by the feedback shift register 132 at a second input. The feedback shift register 132 may shift every clock cycle of the first exemplary processor core 100. The feedback shift register and the AND gate are very easy to implement in an integrated circuit. In particular, the feedback shift register and the AND gate require very little space on a semiconductor die. The feedback shift register 132 may be an n-bit feedback shift register. The feedback shift register 132 may be preloaded at initialization time with j zeros ("0") and k ones ("1"), where the sum of j and k is equal to n. The relationship between j (or k) and n may determine the proportion of clock cycles during which the utilization controller 130 masks the ready signal R. The number of bits n of the feedback shift register 132 may determine how granular this ratio may be selected, for example, the length of the feedback shift register 132 may be less than 100 bits, particularly less than 50 bits, or more than 5 bits, particularly 10 bits.

[0028] 3, there is illustrated a second exemplary processor core 200 including an issue unit 210 having an input 211, an execution unit 220 having an input 221, and a utilization controller unit 230, according to an embodiment of the present disclosure. With regard to the interaction of the issue unit 210, the input 211, the execution unit 220, the input 221, and the utilization controller unit 230 with each other, reference is made to the above description of the first exemplary processor core 100 of FIG. 2 and its corresponding elements, namely the issue unit 110, the further input 111, the execution unit 120, the further input 121, and the utilization controller 130.

[0029] The second exemplary processor core 200 differs from the first exemplary processor core 100 in the internal structure of the utilization controller unit 230. Just as the utilization controller 130 includes an AND gate 131, the utilization controller unit 230 includes an AND gate 231, both of which receive a ready signal R from the respective execution unit 120, 220 at a first input and send a modified ready signal R* to the respective issue unit 110, 210. A comparator 233 compares a random number B received from a random number generator, e.g., a pseudo-random number generator, 235, with a limit value A stored in a limit value register 234.

[0030] The random number generator 235 may generate a random number B between zero and n-1. Correspondingly, the limit value register 234 may store a limit value A between zero and n-1. Only when the random number B is smaller than the limit value A, the comparator 233 sends a gate signal G to the AND gate 231. Generating the gate signal based on the random number may avoid generating regular beats in the electrical circuitry of the processor core, which may have unexpected side effects.

[0031] 4, a third exemplary processor core 300 according to an embodiment of the present disclosure is illustrated, including an issue unit 310 having an input 311, an execution unit 320 having an input 321, and a utilization controller unit 330. With regard to the interaction of the issue unit 310, the input 311, the execution unit 320, the input 321, and the utilization controller unit 330 with each other, reference is made to the above description of the first exemplary processor core 100 of FIG. 2 and its corresponding elements, i.e., the issue unit 110, the further input 111, the execution unit 120, the further input 121, and the utilization controller 130.

[0032] The third exemplary processor core 300 differs from the first exemplary processor core 100 and the second exemplary processor core 200 in the internal structure of the utilization controller unit 330. Just as the utilization controller unit 230 includes the comparator 233, the limit value register 334, and the random generator 235, the utilization controller unit 330 includes a comparator 333, a limit value register 334, and a random generator 335. However, the comparator 333 sends a gate signal G to a finite state machine (FSM) 336 instead of the AND gate 231.

[0033] The finite state machine 336 receives the ready signal R as a first input and the gating signal G as a second input, and transmits its current state, i.e., 1 or zero, as a modified ready signal R*. When both the ready signal R and the gating signal G are 1, i.e., R / G=1 / 1, the finite state machine 336 goes to state 1, i.e., "1". As long as the ready signal R is 1, i.e., R / G=1 / -, the finite state machine 336 maintains state 1, i.e., "1". Only when the ready signal R becomes zero, i.e., R / G=0 / -, the finite state machine 336 goes to state zero, i.e., "0". As long as the ready signal R maintains zero, i.e., R / G=0 / -, or as long as the gating signal G maintains zero, i.e., R / G=- / 0, the finite state machine 336 maintains state zero, i.e., "0", which is transmitted to the issue unit 310.

[0034] The proposed utilization controller unit 330 using the finite state machine 336 only allows the utilization of the execution unit 320 to be increased once the FSM is in state 1 and the execution unit 320 is waiting for a new command, without interspersing additional busy cycles.

[0035] This improves, but does not 100% eliminate, the problem that the previous two embodiments have of interspersing busy cycles however long the execution unit has already been waiting for a new command. Additionally, the random generator 335 can help prevent beats from forming.

[0036] In an alternative embodiment of the utilization controller unit 330, the circuitry including the comparator 333, the limit value register 334, and the random generator 335 may be replaced by a feedback shift register similar to the feedback shift register 132.

[0037] 5, a fourth exemplary processor core 400 according to an embodiment of the present disclosure is illustrated, comprising an issue unit 410 having an input 411, an execution unit 420 having an input 421, and a utilization controller unit 430. With regard to the interaction of these elements, i.e. issue unit 410, input 411, execution unit 420, input 421, and utilization controller unit 430 with each other, reference is made to the above description of the first exemplary processor core 100 of FIG. 2 and its corresponding elements, i.e. issue unit 110, further input 111, execution unit 120, further input 121, and utilization controller 130.

[0038] The fourth exemplary processor core 400 differs from the previously described exemplary processor cores 100, 200 and 300 in the internal structure of utilization controller unit 430. Utilization controller unit 430 includes AND gate 431, similar to how utilization controller units 130 and 230 include AND gates 131 and 231, respectively. Similar to AND gates 131 and 231, AND gate 431 receives a ready signal R from the respective execution unit 420 at a first input. In addition, AND gate 431 receives a gate signal G from utilization limiter 436 at a second input.

[0039] The utilization limiter 436 includes a utilization circuit 440 that measures the recent utilization of the execution unit 420. The utilization circuit 440 includes a shift register 441 that receives the ready signal from the execution unit 420, and a counter 442. The counter receives at a first input a signal from the shift register 441 that decrements the value stored in the counter 442, and at a second input a ready signal R from the execution unit 420 that increments the value stored in the counter 442. The counter 442 may count the number of "1's" in the shift register 441. In an alternative embodiment, the utilization circuit may be used for multiple N execution units. The N execution units may correspond to multiple instances of the same execution unit. In this case, the utilization circuit may receive N ready signals R from the N execution units. Instead of shifting in / adding "0's" and "1's" as previously described herein, the number of ready signals R that are "1's" is shifted in / added.

[0040] The value stored in counter 442 may represent the utilization of execution unit 420. Comparator 433 compares the value sent by counter 442 to a limit value stored in limit value register 434. If the utilization is greater than the desired utilization, comparator 433 sends a gate signal G to AND gate 431.

[0041] The limit value stored in the limit value register 434 and the number of bits in the shift register 441 may determine the desired maximum utilization of the execution unit. The larger the number of bits in the shift register, the finer the granularity of the utilization limiter 436 and the longer the measurement window. For example, the number of bits in the shift register may range from 5 to 100 bits, and in particular from 10 to 50 bits.

[0042] Measuring the recent actual utilization of an execution unit may allow explicit utilization expansion only when the recent actual utilization is already relatively high. Increasing the utilization of an already highly utilized execution unit may allow better detection of whether the highly utilized execution unit truly represents a performance bottleneck for a given application.

[0043] 6, a fifth exemplary processor core 500 according to an embodiment of the present disclosure is illustrated, which includes an issue unit 510 having an input 511, an execution unit 520 having an input 521, and a utilization controller unit 530. With regard to the interaction of these elements, i.e., issue unit 510, input 511, execution unit 520, input 521, and utilization controller unit 530, with each other, reference is made to the above description of the first exemplary processor core 100 of FIG. 2 and its corresponding elements, i.e., issue unit 110, further input 111, execution unit 120, further input 121, and utilization controller 130.

[0044] The utilization circuit 540 corresponds to the utilization circuit 440 and similarly includes a shift register 541 and a counter 542. Notably, as described above, the utilization circuit 540 may also be modified to be used for multiple execution units.

[0045] The multiplexer 550 receives a signal from the utilization limiter 536 and, depending on the value, sends either the upper limit value stored in the upper limit value register 538 or the lower limit value stored in the lower limit value register 539 to the comparator 533. The comparator 533 compares the received value with the random number received from the random number generator 535 and, depending on the result of the comparison, sends a gate signal G to the AND gate 531.

[0046] The proposed utilization controller unit 530 may be capable of controlling the utilization based on a comparison between a measured utilization and a desired utilization. If the measured utilization is greater than the desired utilization, a higher probability may be selected for sending a gating signal. Conversely, if the measured utilization is less than the desired utilization, a lower probability may be selected for sending a gating signal.

[0047] 7, a flow chart illustrating steps of a method for detecting a bottleneck in a processor core for a given application according to an embodiment of the present disclosure is shown. In step 702, utilization of an execution unit of the processor core is controlled, where the execution unit executes commands forwarded to the execution unit. In step 704, application performance can be measured based on the utilization. The utilization corresponds to a fraction of a total observation period during which the execution unit is executing commands.

[0048] In some embodiments, the issue unit may be used to forward commands to the execution unit based on the modified ready signal. Further, in some cases, the time period during which the ready signal indicates that the execution unit can begin executing the command may be limited.

[0049] In another embodiment, the modified ready signal may be generated based on a random signal, and the duty cycle may be ( Desired ) usage rate limiter The control can be based on the following:

[0050] Accordingly, an embodiment of the present disclosure relates to a processor core comprising an execution unit, the execution unit operable to execute commands forwarded to the execution unit, and a utilization controller operably coupled to the execution unit, the utilization controller operable to control a utilization of the execution unit, the utilization corresponding to a portion of a total observation period during which the execution unit is executing commands.

[0051] In an embodiment, the utilization controller is operable to generate a modified ready signal from a ready signal sent by the execution unit, the ready signal indicating that the execution unit is ready to receive a command.

[0052] According to another embodiment, the processor core includes an issue unit operable to forward a command to an execution unit based on the modified ready signal.

[0053] In another embodiment, the utilization controller includes a utilization limiter, the utilization limiter operable to limit the period during which the ready signal indicates that the execution unit may begin executing commands.

[0054] According to an additional embodiment, the utilization controller includes a shift register for sampling the ready signal generated by the execution unit, and circuitry for generating a modified ready signal based on the contents of the shift register.

[0055] According to a further embodiment, the duty cycle controller includes a random generator for generating a random signal and circuitry for generating a modified ready signal based on the random signal.

[0056] In an embodiment, the execution unit is or is part of a load-store unit. The execution unit may be a vector unit and / or a binary-coded decimal unit (BCD unit).

[0057] According to a further embodiment, the execution unit is an arithmetic unit.

[0058] Further, the present disclosure relates to a method for detecting or analyzing bottlenecks in a processor core for a given application, the method including controlling utilization of at least one execution unit of the processor core and measuring application performance.

[0059] In an embodiment, the method includes generating a modified ready signal from a ready signal transmitted by the execution unit, the ready signal indicating that the execution unit is ready to receive a command.

[0060] According to a further embodiment, the method includes using the issue unit to forward the command to the execution unit based on the modified ready signal.

[0061] According to an additional embodiment, the method includes limiting a time period during which the ready signal indicates that the execution unit can begin executing the command.

[0062] In another embodiment, the method further includes generating a modified ready signal based on the random signal.

[0063] According to a further embodiment, the method includes controlling the duty cycle based on a desired duty cycle.

[0064] According to another embodiment, the method further includes controlling a second utilization rate of the second execution unit and determining an application performance dependency on the utilization rate of the one execution unit and the second utilization rate of the second execution unit.

[0065] The present invention may be a system, method, and / or computer program product at any conceivable level of technical detail of integration. The computer program product may include one (or more) computer readable storage medium having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

[0066] A computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in the grooves in which the instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not itself to be construed as being a transitory signal, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0067] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into each computing / processing device or may be downloaded to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof, including copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0068] The computer readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, such as assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state configuration data, configuration data for an integrated circuit, or object oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, such as a local area network (LAN) or wide area network (WAN), or a connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the invention.

[0069] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0070] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored in a computer-readable storage medium that may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium having stored thereon the instructions includes an article of manufacture including instructions that implement aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0071] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams, causing a series of operational steps to be performed on the computer, other programmable apparatus, or other device to generate a computer-implemented process.

[0072] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in the blocks may occur in a different order than that described in the figures. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially simultaneously, and in some cases these blocks may be executed in the reverse order. It will also be noted that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be realized by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0073] Although steps of the disclosed methods and components of the disclosed systems and environments have been identified sequentially or consecutively using numbers or letters, the addition of these numbers or letters does not indicate that such steps should be performed in the order described, but is merely provided to facilitate clear reference of the method steps. Moreover, method steps may be performed in parallel with the performance of their described functions.

[0074] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles, practical applications, or technical improvements to the technology found in the marketplace of the embodiments, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. an execution unit for executing one or more commands of an application transferred to said execution unit; a utilization controller unit operably coupled to the execution unit, the utilization controller unit controlling a utilization of the execution unit, the utilization corresponding to a portion of a total observation period during which the execution unit is executing the one or more commands of the application, the utilization controller unit generating a modified ready signal from a ready signal sent by the execution unit; A processor core comprising:

2. 2. The processor core of claim 1, wherein the ready signal indicates that the execution unit is ready to receive the one or more commands.

3. 2. The processor core of claim 1, further comprising an issue unit for forwarding the one or more commands to the execution unit based on the modified ready signal.

4. The utilization controller unit comprises: Utilization Limiter The processor core of claim 1 further comprising:

5. 5. The processor core of claim 4, wherein the utilization limiter limits the period during which the ready signal indicates that the execution unit can begin executing the one or more commands.

6. The utilization controller unit includes: a shift register for sampling the ready signal generated by the execution unit; a first circuit for generating the modified ready signal based on the contents of the shift register; The processor core of claim 1 further comprising:

7. The utilization controller unit comprises: a random generator for generating a random signal; a second circuit for generating the modified ready signal based on the random signal; The processor core of claim 1 further comprising:

8. The processor core of claim 1 , wherein the execution unit is an arithmetic unit.

9. 2. The processor core of claim 1, wherein the execution unit is part of a load store unit, a vector unit, or a binary coded decimal unit.

10. 1. A computer-implemented method for detecting a bottleneck in a processor core, the computer-implemented method comprising: controlling, by a computer, a utilization of an execution unit of the processor core, the execution unit executing one or more commands of an application transferred to the execution unit; determining, by the computer, an application performance dependency on the utilization rate, the utilization rate corresponding to a portion of a total observed period during which the execution unit is executing the one or more commands of the application; generating a modified ready signal from the ready signal transmitted by the execution unit; A computer-implemented method comprising:

11. 11. The method of claim 10, wherein the ready signal indicates that the execution unit is ready to receive the one or more commands.

12. using an issue unit to forward the one or more commands to the execution unit based on the modified ready signal. The method of claim 10 further comprising:

13. Limiting the time period during which the ready signal indicates that the execution unit can begin executing the one or more commands. The method of claim 10 further comprising:

14. generating the modified ready signal based on a random signal; The method of claim 10 further comprising:

15. Controlling the utilization based on a utilization limiter. The method of claim 10 further comprising:

16. controlling a second utilization rate of a second execution unit; determining an application performance dependency on the utilization of the execution unit and the second utilization of the second execution unit; The method of claim 10 further comprising:

17. 1. A computer system for detecting a bottleneck in a processor core, the computer system comprising: one or more processors; one or more computer readable memories; one or more computer readable tangible storage devices; and program instructions stored in at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories. Equipped with The computer system comprises: controlling, by a computer, a utilization of an execution unit of the processor core, the execution unit executing one or more commands of an application transferred to the execution unit; determining, by the computer, an application performance dependency on the utilization rate, the utilization rate corresponding to a portion of a total observed period during which the execution unit is executing the one or more commands of the application; generating a modified ready signal from a ready signal transmitted by the execution unit, the ready signal indicating that the execution unit is ready to receive the one or more commands; A computer system capable of carrying out a method comprising:

18. The computer system of claim 17, wherein the ready signal indicates that the execution unit is ready to receive the one or more commands.

19. The computer system, using an issue unit to forward the one or more commands to the execution unit based on the modified ready signal.

20. The computer system of claim 17 further capable of performing a method comprising:

20. The computer system, Limiting the time period during which the ready signal indicates that the execution unit can begin executing the one or more commands.

20. The computer system of claim 17 further capable of performing a method comprising:

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