NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application

Abstract

To provide a nitride semiconductor device with good characteristics in terms of mobility and threshold voltage by adjusting a fixed charge distribution in a dielectric film.SOLUTION: Provided is a nitride semiconductor device, comprising a Ga-containing nitride semiconductor layer, an insulating film stacked on a top surface of the nitride semiconductor layer, and an electrode provided above the insulating film, and the product of the fixed charge density in the insulating film and the thickness of the insulating film is in a range of -4E6(q / cm) or more and +1E7(q / cm) or less and the interfacial fixed charge surface density in the nitride semiconductor layer in the insulating film is -1E11(q / cm2) or more and +1E11(q / cm2) or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Patent Documents 1, 2, and 3 describe semiconductor devices including a wide-gap semiconductor such as gallium nitride. [Prior art document] [Patent documents] [Patent Document 1] JP 2016-54250 A [Patent Document 2] JP 2016-66641 A [Patent Document 3] JP 2016-72358 A Summary of the Invention [Problem to be solved by the invention]

[0003] A nitride semiconductor device having excellent characteristics such as mobility and threshold voltage is provided by adjusting the fixed charge distribution in an insulating film. [Means for solving the problem]

[0004] In a first aspect of the present invention, a semiconductor device includes a nitride semiconductor layer containing Ga, an insulating film laminated on an upper surface of the nitride semiconductor layer, and an electrode provided above the insulating film, wherein the product of the fixed charge density in the insulating film and the thickness of the insulating film is When the fixed charge is positive 1E7 ( / cm) or less in the insulating film. The interface fixed charge density at , When the fixed charge is positive 1E11 ( / cm 2 )below is The present invention provides a nitride semiconductor device.

[0005] The Ga concentration of the insulating film is +4E17cm in the region 30 nm above the interface. -3 It may be the following:

[0006] The insulating film may include an oxide containing Si.

[0007] The insulating film may include an oxynitride.

[0008] The insulating film may have a thickness of 30 nm or more and 100 nm or less.

[0009] The nitride semiconductor layer may include GaN.

[0010] The nitride semiconductor layer may include Mg-doped p-type GaN.

[0011] The Mg concentration in the nitride semiconductor layer is +1E16cm -3 Above, +1E18cm -3 It may be the following:

[0012] The nitride semiconductor layer, the insulating film and the electrodes may form a field effect transistor having a MOS gate structure.

[0013] The field effect transistor may have a threshold voltage of +3V or greater.

[0014] The C impurity concentration of the insulating film is +4E17cm -3 It may be the following:

[0015] In a second aspect of the present invention, a method for fabricating a semiconductor device comprising the steps of providing a nitride semiconductor layer containing Ga, providing an insulating film laminated on an upper surface of the nitride semiconductor layer, and providing an electrode above the insulating film, wherein the product of the fixed charge density in the insulating film and the thickness of the insulating film is When the fixed charge is positive 1E7 ( / cm) below In the insulating film, The interface fixed charge density at , When the fixed charge is positive 1E11 ( / cm 2 )below is The present invention provides a method for manufacturing a nitride semiconductor device.

[0016] The step of providing an insulating film may be performed by plasma CVD.

[0017] The source gas in the plasma CVD may include monosilane or disilane.

[0018] The source gas in the plasma CVD may contain oxygen gas, water, or oxygen radicals.

[0019] In the step of providing the insulating film, the insulating film may be provided at a deposition rate of 25 nm / min or more.

[0020] In the step of providing the insulating film, the temperature of the nitride semiconductor layer may be set to 350° C. or lower.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0022] [Figure 1] An example of the configuration of a nitride semiconductor device 100 is shown. [Diagram 2] An example of the relationship between the deposition rate of the insulating film 30 and the Ga concentration (cm −3 ) is shown below. [Diagram 3] An example of the carbon (C) concentration of the insulating film 30 is shown. [Figure 4A] The relationship between the depth of the insulating film 30 and the Ga concentration is shown. [Figure 4B] The relationship between the Ga concentration in the insulating film 30 and the fixed charge density of the insulating film 30 is shown. [Figure 4C] The relationship between the Ga concentration in the insulating film 30 and the fixed charge density / thickness of the insulating film 30 is shown. [Diagram 5] 1 shows an example of the configuration of a nitride semiconductor device 200 according to a second embodiment. [Figure 6] A method for manufacturing the nitride semiconductor device 200 according to the second embodiment will be described. [Figure 7] 4 shows the relationship between the fixed charge density Neff of the insulating film 30 and the threshold voltage Vth. [Figure 8A]1 shows the relationship between the film thickness dox and the fixed charge density Neff when the film formation rate is changed. [Figure 8B] 1 shows the relationship between the interface fixed charge density of the insulating film 30 and the maximum value μmax of the field effect mobility μ. [Figure 9] 1 shows an example of the configuration of a nitride semiconductor device 300 according to a third embodiment. [Figure 10] 1 shows an example of the configuration of a nitride semiconductor device 400 according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] 1 shows an example of the configuration of a nitride semiconductor device 100 according to the first embodiment. The nitride semiconductor device 100 of this example includes a bottom electrode 42, a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, an insulating film 30, and a top electrode 40.

[0025] In the nitride semiconductor device 100 of this embodiment, the insulating film 30 is provided between the lower electrode 42 and the upper electrode 40. That is, the nitride semiconductor device 100 of this embodiment forms a capacitor with the insulating film 30 as a dielectric.

[0026] The nitride semiconductor substrate layer 10 of this example includes GaN. As an example, the nitride semiconductor substrate layer 10 is obtained using a method such as a vapor phase epitaxy method or a liquid phase epitaxy method.

[0027] The nitride semiconductor layer 20 is a layer obtained by epitaxial growth on the nitride semiconductor substrate layer 10. The nitride semiconductor layer 20 of this example contains Ga.

[0028] The insulating film 30 is laminated on the upper surface 21 of the nitride semiconductor layer 20. The insulating film 30 may be a layer formed by a chemical vapor deposition (CVD) method. As an example, the insulating film 30 is provided by a plasma CVD method such as a microwave plasma CVD method, a remote plasma CVD method, or a radio frequency (RF) plasma CVD method. For the insulating film 30, monosilane or disilane may be used as a Si source gas in the CVD method for providing the insulating film 30. Furthermore, oxygen gas, water, or oxygen radicals may be used as an oxygen source gas in the CVD method.

[0029] As an example, the insulating film 30 is an oxide layer containing Si. 2 In another embodiment, the insulating film 30 may include an oxynitride. As an example, the insulating film 30 has a thickness of 30 nm or more and 100 nm or less. 2 In the case of a film, an insulating film 30 having a breakdown voltage of about 10 MV / cm can be used. In this case, if the thickness of the insulating film is set to 30 nm or more and 100 nm or less, an insulating film having a breakdown voltage of about 30 V or more and about 100 V or less can be manufactured.

[0030] The lower electrode 42 and the upper electrode 40 include a conductive material such as a metal. The lower electrode 42 and the upper electrode 40 may be made of the same metal or different metals. As an example, the material of the lower electrode 42 and the upper electrode 40 is aluminum (Al). The upper electrode 40 may be provided above the insulating film 30 by aluminum deposition. The lower electrode 42 is provided on the lower surface 11 of the nitride semiconductor substrate layer 10.

[0031] FIG. 2 shows the deposition rate and Ga concentration (cm -3 In this example, the horizontal axis represents the deposition rate (nm / min) and the vertical axis represents the Ga concentration The figure shows the above.

[0032] Since GaN is easily thermally decomposed, when the insulating film 30 is formed on the upper surface of the nitride semiconductor layer 20 containing Ga, Ga is introduced from the nitride semiconductor layer 20 into the insulating film 30. Furthermore, a GaOx interface layer is formed in the insulating film 30 near the upper surface 21 of the nitride semiconductor layer 20. When the concentration of introduced Ga increases, the absolute value of the charge of the GaOx interface layer also increases. By increasing the deposition rate of the insulating film 30, the time during which the nitride semiconductor layer 20 is exposed to plasma is shortened. As a result, when the insulating film 30 is formed at a high deposition rate, the concentration of Ga introduced into the insulating film 30 decreases. As an example, the insulating film 30 is formed at a deposition rate of 25 nm / min or more.

[0033] In addition, in the manufacture of the nitride semiconductor device 100, it may be possible to select whether or not to perform a heat treatment for the purpose of thermally stabilizing the interface between the insulating film 30 and the nitride semiconductor layer 20. In this example, the Ga concentration of the insulating film 30 when the heat treatment is performed and the Ga concentration of the insulating film 30 when the heat treatment is not performed are shown. As an example, the heat treatment is performed at 800°C. When the heat treatment is performed, Ga is easily diffused from the nitride semiconductor layer 20 into the insulating film 30, and the Ga concentration becomes high. When the heat treatment is not performed, the Ga concentration taken into the insulating film 30 becomes low. When the heat treatment is not performed, as an example, the temperature of the nitride semiconductor layer 20 is kept at 350°C or less when the insulating film 30 is provided.

[0034] In the insulating film 30, Ga acts as an impurity. The higher the impurity concentration in the insulating film 30, the smaller the magnitude of the electric field that causes dielectric breakdown in the insulating film 30, making dielectric breakdown more likely to occur. The Ga concentration of the insulating film 30 is reduced by increasing the deposition rate of the insulating film 30 and not performing heat treatment, thereby improving resistance to dielectric breakdown.

[0035] In the figure, three film formation conditions are shown: 2A, 2B, and 2C. Ga concentration profiles under these three film formation conditions will be described later with reference to FIG. 4A.

[0036] 3 shows an example of the carbon (C) concentration of the insulating film 30. In the case where the insulating film 30 is formed by plasma CVD and monosilane is used as the Si source gas, the C concentration according to the depth of the insulating film 30 and the BG (Background) level that the insulating film 30 has as a background are shown.

[0037] When the insulating film 30 is formed by the CVD method, the Si source gas is a gas having the chemical formula Si(OC 2 H 5 Tetraethoxysilane (TEOS), a type of ethyl orthosilicate, is sometimes used. TEOS gas contains carbon as an element, so when TEOS is used as a source gas, carbon is incorporated as an impurity into the insulating film.

[0038] In the nitride semiconductor device 100, a gas that does not contain carbon, such as monosilane or disilane, is used as the Si source gas in the plasma CVD, which makes it possible to reduce the C concentration in SiO2.

[0039] In this example, a profile using monosilane as a source gas is shown. The C concentration of the insulating film 30 in this example can be kept within the order of the BG level except in the vicinity of the interface.

[0040] FIG. 4A shows the relationship between the depth of the insulating film 30 and the Ga concentration. In this example, the horizontal axis is the length taken from the surface of the insulating film 30 toward the interface with the nitride semiconductor layer 20. The vertical axis corresponds to the Ga concentration in the insulating film 30. In each curve, the depth having the maximum Ga concentration is made to coincide. Note that the depth of the maximum Ga concentration roughly corresponds to the interface between the insulating film 30 and the nitride semiconductor layer 20. The three curves in the figure correspond to the Ga concentration profile under the film formation conditions corresponding to the three points 2A, 2B, and 2C shown in FIG. 2.

[0041] In the Ga concentration profile, a region 30 nm from the surface in the insulating film 30 may show a value larger than the actual Ga concentration due to the influence of adsorbates such as Ga or C. At depths of 30 nm or more, the influence of the Ga concentration profile from the surface becomes small, and the Ga concentration profile becomes flat. Similarly, at depths of 30 nm or more from the interface between the insulating film 30 and the nitride semiconductor layer 20 toward the insulating film 30 side, the influence of Ga diffusing from the nitride semiconductor layer 20 becomes small, and the Ga concentration profile becomes flat.

[0042] FIG. 4B shows the relationship between the Ga concentration in the insulating film 30 and the fixed potential of the insulating film 30. cargo density The relationship between the concentration of Ga and the insulating film 30 is shown in FIG. cargo density The relationship between them can be approximated by a straight line.

[0043] 4C shows the relationship between the Ga concentration in the insulating film 30 and the fixed charge density / thickness of the insulating film 30. In FIG. 4C, the average fixed charge density in the insulating film 30 is obtained by dividing the fixed charge density Neff on the vertical axis by the thickness of the insulating film 30.

[0044] The average fixed charge density on the vertical axis indicates a value of approximately 30% relative to the Ga concentration on the horizontal axis. This means that the fixed charges in the insulating film 30 are largely derived from Ga. That is, it is presumed that in the insulating film 30, Ga taken in from the nitride semiconductor layer 20 becomes positively ionized in the insulating film 30 and contributes to the main cause of the fixed charges.

[0045] 5 shows an example of the configuration of a nitride semiconductor device 200 according to the second embodiment. The nitride semiconductor device 200 constitutes a field effect transistor having a MOS (metal oxide semiconductor) gate structure, i.e., a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) device. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high concentration N-type region 26, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48. When the nitride semiconductor device 200 functions as a FET, it may be used as a power semiconductor element such as a power supply circuit or an inverter.

[0046] The nitride semiconductor substrate layer 10 includes GaN. The GaN included in the nitride semiconductor substrate layer 10 may be Ga-plane GaN, N-plane GaN, a-plane GaN, or m-plane GaN.

[0047] The nitride semiconductor layer 20 of this example includes an N-type nitride semiconductor layer 22 and a P-type nitride semiconductor layer 24. Either of the nitride semiconductor layers 20 can be provided by forming the nitride semiconductor substrate layer 10 by epitaxial growth.

[0048] The N-type nitride semiconductor layer 22 may be a layer formed by epitaxial growth on the nitride semiconductor substrate layer 10. As an example, the N-type nitride semiconductor layer 22 is Nd-doped N-type GaN. The Nd doping concentration in the N-type nitride semiconductor layer 22 is +5E15 cm -3 More than +5E16cm -3 For example, the Nd concentration of the N-type nitride semiconductor layer 22 may be +1E16 cm -3 is set to.

[0049] The P-type nitride semiconductor layer 24 may be a layer formed by epitaxial growth on the N-type nitride semiconductor layer 22. As an example, the P-type nitride semiconductor layer 24 is Mg-doped P-type GaN. The Mg concentration doped in the P-type nitride semiconductor layer 24 is +1E16 cm -3 More than +1E18cm -3may be less than or equal to +1E16cm -3 More than +5E17cm -3 For example, the Mg concentration of the P-type nitride semiconductor layer 24 may be +1E17 cm -3 is set to.

[0050] The high-concentration N-type region 26 is an N-type semiconductor region having a higher doping concentration than the N-type nitride semiconductor layer 22. As an example, the high-concentration N-type region is obtained by adding Si and performing a heat treatment.

[0051] The insulating film 30 is formed above the P-type nitride semiconductor layer 24. The insulating film 30 may contain an oxide containing Si, or may contain an oxynitride. The insulating film 30 corresponds to a gate insulating film of a MOSFET device. As an example, the film thickness of the insulating film 30 is set to 100 nm.

[0052] The source electrode 44 corresponds to a source electrode of a MOSFET device. The source electrode 44 is formed above the high concentration N-type region 26. The high concentration N-type region 26 provided below the source electrode 44 corresponds to a source region of the MOSFET device.

[0053] The drain electrode 46 corresponds to the drain electrode of a MOSFET device. The high concentration N-type region 26 provided below the drain electrode 46 corresponds to the drain region of the MOSFET device. The nitride semiconductor device 200 of this example constitutes a planar type FET. In this example, the roles of the source electrode 44 and the drain electrode 46 can be interchanged by exchanging the voltages applied to them.

[0054] The gate electrode 48 corresponds to the gate electrode of a MOSFET device. When a gate voltage is applied to the gate electrode 48, an N-type channel is formed in the P-type nitride semiconductor layer 24, and the source region and the drain region are connected by the N-type channel. This allows the nitride semiconductor device 200 to operate as a FET. The FET may have a threshold voltage Vth(V) of 3V or more.

[0055] 6 shows a method for manufacturing the nitride semiconductor device 200 according to the second embodiment. The method for manufacturing the nitride semiconductor device 200 includes steps S100 to S108.

[0056] In S100, an N-type nitride semiconductor layer 22 is provided. The N-type nitride semiconductor layer 22 may be formed as Nd-doped N-type GaN by epitaxial growth on the nitride semiconductor substrate layer 10 by MOCVD (Metal Organic Chemical Vapor Deposition).

[0057] Furthermore, a P-type nitride semiconductor layer 24 may be formed as Mg-doped P-type GaN by epitaxially growing it above the N-type nitride semiconductor layer 22. The semiconductor device may be subjected to a heat treatment to activate the P-type nitride semiconductor layer 24.

[0058] In step S102, a high-concentration N-type region 26 is provided in the P-type nitride semiconductor layer 24. The step of providing the high-concentration N-type region 26 is performed by implanting N+ type ions into a portion of the P-type nitride semiconductor layer 24. As an example, the ions implanted are Si ions. However, a different N-type dopant, such as Ge ions, may also be implanted. Further, a heat treatment step is performed to activate the Si dopant.

[0059] In S104, an insulating film 30 is provided on the upper surface of the P-type nitride semiconductor layer 24. The insulating film may be provided by a plasma CVD method. In the plasma CVD method, monosilane or disilane may be used as a Si raw material gas, and oxygen gas, water, or oxygen radicals may be used as an oxygen raw material gas. As an example, the insulating film 30 is provided across the P-type nitride semiconductor layer 24 and the high-concentration N-type region 26. The insulating film 30 provided in areas other than the desired area is removed by etching such as wet etching. When providing the insulating film, the temperature of the nitride semiconductor layer may be set to 350° C. or less.

[0060] In step S106, the gate electrode 48 is provided above the insulating film 30. As an example, the gate electrode 48 is provided by aluminum deposition using a metal mask.

[0061] In step S108, the source electrode 44 and the drain electrode 46 are provided above a portion of the high concentration N-type region 26. As an example, the source electrode 44 and the drain electrode 46 are provided by aluminum deposition using a metal mask, similar to the gate electrode 48, but may be provided by a different conductor, and the method of providing the electrodes is not limited to aluminum deposition.

[0062] Furthermore, the order of steps S106 and S108 may be reversed. Through the above steps, the nitride semiconductor device 200 is manufactured.

[0063] FIG. 7 shows the fixed potential of the insulating film 30. cargo density degree N eff The vertical axis shows the threshold voltage Vth (V) of the MOS gate, and the horizontal axis shows the fixed current of the MOSFET device. cargo density degree N eff (cm -2 In this example, a MOSFET device according to the nitride semiconductor device 200 will be used for explanation.

[0064] When the MOSFET device of this example is used as a power MOSFET device, it is preferable to realize a normally-off operation for the safety of the power MOSFET device. In this case, the threshold voltage Vth, which is the on / off boundary, may be set to +3V or more to realize the reliability of the operation, and may be set to 10V or less to realize the controllability of the voltage. However, the range of Vth is not limited to a value between +3V and 10V.

[0065] Threshold voltage Vth and fixed voltage of MOSFET device cargo density degree N eff There is a linear relationship between the fixed voltage Vth and the threshold voltage Vth. cargo density degree Neff The conditions are: If the fixed charge is positive, N eff <9.8E11 ( / cm 2 )

[0066] Here, the threshold voltage Vth and the flat band voltage Vfb have the following relationship: Vth = Vfb + 2φb + √(2ε s qNa(2φb)) / Cox N eff =-Cox(Vfb-Vfb(ideal)) where ε s is the relative dielectric constant of the semiconductor. Also, the acceptor concentration Na=1E17cm -3 , the thickness d of the insulating film 30 ox = 100 nm, flat band voltage Vfb (ideal) = -3 V, and barrier height φb = 1.53 V. In this case, (2ε s qNa(2φb)) / Cox=8.3(V), and Vth+N eff / Cox=8.4(V). Also, from Figure 7, Vth+N eff / Cox is approximately 8.1 (V).

[0067] d ox For other than 100 nm, Cox=εox / d ox Therefore, the threshold voltage Vth is within the predetermined range only when the fixed voltage of the insulating film 30 is cargo density degree N eff and the thickness d of the insulating film 30 ox The product of this is If the fixed charge is positive, then 1E 7 ( / cm) or less.

[0068] In addition, the average fixed charge density in the film, N eff / d ox Regarding (N eff / d ox )< 1E 17 ( / cm 3 ) and the Ga concentration is 4E17cm -3In particular, in the region above 30 nm from the interface where the influence of surface adsorption Ga or diffused Ga is small, the Ga concentration is 4E17 cm -3 It may be the following:

[0069] FIG. 8A shows the relationship between the thickness d of the insulating film 30 and the thickness of the SiO2 film when the film formation rate is changed. ox and the fixed charge surface density N eff The horizontal axis represents the thickness d ox (nm), the vertical axis is the fixed charge density N eff (cm -2 ) A diagram of the scale is shown.

[0070] As described above, the higher the deposition rate, the shorter the time during which the nitride semiconductor layer 20 is exposed to plasma, and the smaller the amount of Ga taken into the insulating film. density can be derived from the film thickness dependency of the fixed charge on the insulating film 30, Figure 8A This is the intercept on the vertical axis.

[0071] 8B shows the relationship between the interface fixed charge density of the insulating film 30 and the maximum value μmax of the field effect mobility μ. ( / cm -2 ), and the vertical axis is the field effect mobility μ (cm -2 A graph showing the maximum value of Vs is shown.

[0072] Field effect mobility μ(cm -2 / Vs) indicates the mobility of carriers in a channel region formed in the nitride semiconductor layer 20 near the interface with the insulating film 30. In a power MOSFET device, the larger the value of the field effect mobility μ, the larger the control output, so it is preferable for the field effect mobility μ to be a large value. As an example, the field effect mobility μ (cm 2 / Vs) is 50(cm 2 / Vs) or more, but 100 (cm 2 / Vs) or higher.

[0073] When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side in the P-type nitride semiconductor layer 24. Meanwhile, in the vicinity of the boundary between the P-type nitride semiconductor layer 24 and the insulating film 30, roughness scattering due to the roughness of the boundary surface and scattering due to electromagnetic interactions such as Coulomb scattering due to Coulomb interactions occurring between carriers and charges at the interface in the insulating film 30 occur. These scatterings make the carrier mobility in the vicinity of the boundary smaller than the carrier mobility in the bulk of the semiconductor substrate.

[0074] In addition to the Coulomb interaction between the carriers and the fixed charges at the interface, when an electrostatic potential exists at the interface, the interaction caused by the electrostatic potential also contributes to the scattering due to the electromagnetic interaction at the interface. Here, the interface state density D it For example, when the P-type nitride semiconductor layer 24 is made of GaN and the insulating film 30 is made of SiO 2 In the case of GaN / SiO 2 The interface state density D it is 1E10(cm -2 / eV) or less. In this case, the interface state density D it The contribution of the charge scattering to the electrons is smaller than that of the Coulomb scattering caused by the fixed charges at the interface.

[0075] The contribution of Coulomb scattering is reduced by reducing the interface fixed charge density. Therefore, by reducing the interface fixed charge density, the effect of scattering due to electromagnetic interactions at the interface is reduced, and the field effect mobility μ(cm 2 / Vs) can be increased.

[0076] In the experimental results, the field effect mobility μ (cm 2 / Vs) to 50(cm 2 / Vs), the interface fixed charge density must be 、1 E11 ( / cm 2 ) below And Was .

[0077] The positive or negative charge on the interface affects whether the Coulomb interaction is attractive or repulsive, but in terms of the contribution to carrier mobility due to Coulomb scattering, it is preferable that either interaction is small. Therefore, by reducing the absolute value of the interface fixed charge density, it is possible to obtain the desired field effect mobility μ (cm 2 In the insulating film 30 of this example, the interface fixed charge density is When the fixed charge is positive 1E11 ( / cm 2 ) or less, more preferably 7E10 ( / cm 2 ) or less.

[0078] 9 shows an example of the configuration of a nitride semiconductor device 300 according to the third embodiment. The nitride semiconductor device 300 of this example constitutes a vertical MOSFET. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high-concentration N-type region 26, an N-type well region 28, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48.

[0079] The nitride semiconductor layer 20 includes an N-type nitride semiconductor layer 22 and a P-type nitride semiconductor layer 24. As an example, the N-type nitride semiconductor layer 22 is an N-type GaN layer epitaxially grown on a GaN semiconductor substrate layer. In another example, the N-type nitride semiconductor layer 22 may be an N-type semiconductor substrate layer, and may include both an N-type semiconductor substrate and an N-type semiconductor layer epitaxially grown on the N-type semiconductor substrate. The P-type nitride semiconductor layer 24 may be formed by epitaxially growing the N-type nitride semiconductor layer 22.

[0080] In this example, each of the high concentration N-type regions 26 corresponds to a source region of a MOSFET device. A source electrode 44 is formed above a portion of the high concentration N-type region 26. The high concentration N-type region 26 may be doped with Si or Ge.

[0081] The N-type well region 28 is provided by adding an N-type dopant to a part of the P-type nitride semiconductor layer 25. The N-type well region 28 may be doped with Si or O.

[0082] The drain electrode 46 is provided below the N-type nitride semiconductor layer 22. The drain electrode 46 functions as a drain electrode of the MOSFET device.

[0083] When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side of the P-type nitride semiconductor layer between the high-concentration N-type region 26 and the N-type well region 28. As a result, carriers flow between the high-concentration N-type region 26 and the N-type well region 28, and the carrier path through the N-type well region 28 and the N-type nitride semiconductor layer 22 becomes conductive. As a result, the nitride semiconductor device 300 operates as a MOSFET device.

[0084] Unlike the nitride semiconductor device 200, the nitride semiconductor device 300 has a conductive carrier path from the upper surface 21 to the drain electrode 46 below in the depth direction of the nitride semiconductor layer 20. Therefore, the nitride semiconductor device 300 can improve the breakdown voltage of the MOSFET device compared to the nitride semiconductor device 200.

[0085] 10 shows an example of the configuration of a nitride semiconductor device 400 according to the fourth embodiment. The nitride semiconductor device 400 of this example constitutes a trench-gate type device. The nitride semiconductor device 400 of this example constitutes a trench-gate type MOSFET. The nitride semiconductor device 200 includes a nitride semiconductor substrate layer 10, a nitride semiconductor layer 20, a high-concentration N-type region 26, an N-type well region 28, an insulating film 30, a source electrode 44, a drain electrode 46, and a gate electrode 48. The following mainly describes the differences from the nitride semiconductor device 300.

[0086] In this example, after the high concentration N-type region 26 is provided above the P-type nitride semiconductor layer 24, the substrate is etched to provide a trench. An insulating film 30 and a gate electrode 48 are provided in the trench.

[0087] The gate electrode 48 may be made of metal or polysilicon. When a gate voltage is applied to the gate electrode 48, an N-type channel is formed on the insulating film 30 side in the P-type nitride semiconductor layer 24 between the high-concentration N-type region 26 and the N-type nitride semiconductor layer 22. This allows a carrier path from the source electrode 44 to the drain electrode 46 to be conductive through the high-concentration N-type region 26, the N-type channel, and the N-type nitride semiconductor layer 22. Therefore, the nitride semiconductor device 400 operates as a MOSFET device.

[0088] In the nitride semiconductor device 400, it is easier to provide a larger number of gate electrodes 48 than in the nitride semiconductor device 300. This increases the ratio of the region in the nitride semiconductor layer 20 that can be used as a channel, improving the operating efficiency of the semiconductor device.

[0089] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0090] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0091] 10 nitride semiconductor substrate layer, 11 lower surface, 20 nitride semiconductor layer, 21 upper surface, 22 N-type nitride semiconductor layer, 24 P-type nitride semiconductor layer, 26 high concentration N-type region, 28 N-type well region, 30 insulating film, 40 upper electrode, 42 lower electrode, 44 source electrode, 46 drain electrode, 48 gate electrode, 100 nitride semiconductor device, 200 nitride semiconductor device, 300 nitride semiconductor device, 400 nitride semiconductor device

Claims

1. a nitride semiconductor layer containing Ga; an insulating film laminated on an upper surface of the nitride semiconductor layer; an electrode provided above the insulating film; Equipped with the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( / cm) or less when the fixed charge is positive; The interface fixed charge density in the insulating film is 1E11 ( / cm) when the fixed charge is positive. ２ ) is less than or equal to Nitride semiconductor devices.

2. The Ga concentration of the insulating film is +4E17 cm in a region 30 nm above the interface with the nitride semiconductor layer. －３ Below is the The nitride semiconductor device according to claim 1 .

3. The insulating film includes an oxide containing Si.

3. The nitride semiconductor device according to claim 1 or 2.

4. The insulating film includes an oxynitride. The nitride semiconductor device according to claim 1 .

5. The insulating film has a thickness of 30 nm or more and 100 nm or less. The nitride semiconductor device according to claim 1 .

6. The nitride semiconductor layer includes GaN. The nitride semiconductor device according to claim 1 .

7. The nitride semiconductor layer includes Mg-doped P-type GaN. The nitride semiconductor device according to claim 1 .

8. The Mg concentration of the nitride semiconductor layer is +1E16 cm －３ Above, +1E18cm －３ Below is the The nitride semiconductor device according to claim 7 .

9. the nitride semiconductor layer, the insulating film, and the electrode constitute a field effect transistor having a MOS gate structure; The nitride semiconductor device according to claim 1 .

10. The field effect transistor has a threshold voltage of +3V or more. The nitride semiconductor device according to claim 9 .

11. The C impurity concentration of the insulating film is +4E17 cm －３ Below is the The nitride semiconductor device according to claim 1 .

12. providing a Ga-containing nitride semiconductor layer; providing an insulating film stacked on an upper surface of the nitride semiconductor layer; providing an electrode above the insulating film; the product of the fixed charge density in the insulating film and the thickness of the insulating film is within a range of 1E7 ( / cm) or less when the fixed charge is positive; The interface fixed charge density in the insulating film is 1E11 ( / cm) when the fixed charge is positive. ２ ) is less than or equal to A method for manufacturing a nitride semiconductor device.

13. The step of providing the insulating film is performed by plasma CVD. The method for manufacturing a nitride semiconductor device according to claim 12 .

14. The source gas in the plasma CVD includes monosilane or disilane. The method for manufacturing a nitride semiconductor device according to claim 13 .

15. The raw material gas in the plasma CVD contains oxygen gas, water, or oxygen radicals; The method for manufacturing a nitride semiconductor device according to claim 13 or 14.

16. In the step of providing the insulating film, The insulating film is formed at a deposition rate of 25 nm / min or more. The method for manufacturing a nitride semiconductor device according to claim 12 .

17. In the step of providing the insulating film, the temperature of the nitride semiconductor layer is set to 350° C. or less. The method for manufacturing a nitride semiconductor device according to claim 12 .

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